OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [spi_top.v] - Blame information for rev 101

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  spi_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the SPI IP core project                ////
6
////  http://www.opencores.org/projects/spi/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Simon Srot (simons@opencores.org)                     ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2002 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
 
41
 
42
`include "spi_defines.v"
43
`include "timescale.v"
44
 
45
module spi_flash_top
46
  (
47
   // Wishbone signals
48
   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
49
   wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
50
   // SPI signals
51
   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
52
   );
53
 
54
   parameter divider_len = 2;
55
   parameter divider = 0;
56
 
57
   parameter Tp = 1;
58
 
59
   // Wishbone signals
60
   input                            wb_clk_i;         // master clock input
61
   input                            wb_rst_i;         // synchronous active high reset
62
   input [4:2]                      wb_adr_i;         // lower address bits
63
   input [31:0]              wb_dat_i;         // databus input
64
   output [31:0]                     wb_dat_o;         // databus output
65
   input [3:0]                       wb_sel_i;         // byte select inputs
66
   input                            wb_we_i;          // write enable input
67
   input                            wb_stb_i;         // stobe/core select signal
68
   input                            wb_cyc_i;         // valid bus cycle input
69
   output                           wb_ack_o;         // bus cycle acknowledge output
70
 
71
   // SPI signals                                     
72
   output [`SPI_SS_NB-1:0]           ss_pad_o;         // slave select
73
   output                           sclk_pad_o;       // serial clock
74
   output                           mosi_pad_o;       // master out slave in
75
   input                            miso_pad_i;       // master in slave out
76
 
77
   reg [31:0]                        wb_dat_o;
78
   reg                              wb_ack_o;
79
 
80
   // Internal signals
81
   //  reg       [`SPI_DIVIDER_LEN-1:0] divider;          // Divider register
82
   wire [`SPI_CTRL_BIT_NB-1:0]       ctrl;             // Control and status register
83
   reg [`SPI_SS_NB-1:0]      ss;               // Slave select register
84
   wire [`SPI_MAX_CHAR-1:0]          rx;               // Rx register
85
 
86
   wire [5:0]                        char_len;
87
   reg                              char_len_ctrl;    // char len
88
   reg                              go;               // go
89
 
90
   wire                             spi_ctrl_sel;     // ctrl register select
91
   wire                             spi_tx_sel;       // tx_l register select
92
   wire                             spi_ss_sel;       // ss register select
93
   wire                             tip;              // transfer in progress
94
   wire                             pos_edge;         // recognize posedge of sclk
95
   wire                             neg_edge;         // recognize negedge of sclk
96
   wire                             last_bit;         // marks last character bit
97
 
98
  wire                             rx_negedge;       // miso is sampled on negative edge
99
  wire                             tx_negedge;       // mosi is driven on negative edge
100
  wire                             lsb;              // lsb first on line
101
  wire                             ass;              // automatic slave select
102
 
103
   // Address decoder
104
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
105
   assign spi_tx_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
106
   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
107
 
108
   // Read from registers
109
   // Wb data out
110
   always @(posedge wb_clk_i or posedge wb_rst_i)
111
  begin
112
     if (wb_rst_i)
113
       wb_dat_o <= #Tp 32'b0;
114
     else
115
       case (wb_adr_i[`SPI_OFS_BITS])
116
         `SPI_RX_0:    wb_dat_o <= rx;
117
         `SPI_CTRL:    wb_dat_o <= {18'd0, ctrl};
118
         `SPI_DEVIDE:  wb_dat_o <= divider;
119
         `SPI_SS:      wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss};
120
        default:      wb_dat_o  <= rx;
121
       endcase
122
  end
123
 
124
   // Wb acknowledge
125
   always @(posedge wb_clk_i or posedge wb_rst_i)
126
     begin
127
        if (wb_rst_i)
128
          wb_ack_o <= #Tp 1'b0;
129
    else
130
      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
131
     end
132
 
133
   // Ctrl register
134
   always @(posedge wb_clk_i or posedge wb_rst_i)
135
     begin
136
        if (wb_rst_i)
137
          {go,char_len_ctrl} <= #Tp 2'b01;
138
        else if(spi_ctrl_sel && wb_we_i && !tip)
139
          begin
140
             if (wb_sel_i[0])
141
               char_len_ctrl <= #Tp wb_dat_i[5];
142
             if (wb_sel_i[1])
143
               go <= #Tp wb_dat_i[8];
144
          end
145
        else if(tip && last_bit && pos_edge)
146
          go <= #Tp 1'b0;
147
     end
148
 
149
   assign char_len = char_len_ctrl ? 6'd32 : 6'd8;
150
`ifdef SPI_CTRL_ASS
151
   assign ass = 1'b1;
152
`else
153
   assign ass = 1'b0;
154
`endif
155
`ifdef SPI_CTRL_LSB
156
   assign lsb = 1'b1;
157
`else
158
   assign lsb = 1'b0;
159
`endif
160
`ifdef SPI_CTRL_RX_NEGEDGE
161
   assign rx_negedge = 1'b1;
162
`else
163
   assign rx_negedge = 1'b0;
164
`endif
165
`ifdef SPI_CTRL_TX_NEGEDGE
166
   assign tx_negedge = 1'b1;
167
`else
168 12 rfajardo
   assign tx_negedge = 1'b0;
169 2 rfajardo
`endif
170
 
171
   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
172
 
173
   // Slave select register
174
   always @(posedge wb_clk_i or posedge wb_rst_i)
175
     if (wb_rst_i)
176
       ss <= #Tp {`SPI_SS_NB{1'b0}};
177
     else if(spi_ss_sel && wb_we_i && !tip)
178
       if (wb_sel_i[0])
179
         ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
180
 
181
   assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
182
 
183
   spi_flash_clgen
184
     #
185
     (
186
      .divider_len(divider_len),
187
      .divider(divider)
188
      )
189
     clgen
190
       (
191
        .clk_in(wb_clk_i),
192
        .rst(wb_rst_i),
193
        .go(go),
194
        .enable(tip),
195
        .last_clk(last_bit),
196
        .clk_out(sclk_pad_o),
197
        .pos_edge(pos_edge),
198
        .neg_edge(neg_edge)
199
        );
200
 
201
   spi_flash_shift  shift
202
     (
203
      .clk(wb_clk_i),
204
      .rst(wb_rst_i),
205
      .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
206
      .latch(spi_tx_sel & wb_we_i),
207
      .byte_sel(wb_sel_i),
208
      .go(go),
209
      .pos_edge(pos_edge),
210
      .neg_edge(neg_edge),
211
      .lsb(lsb),
212
      .rx_negedge(rx_negedge),
213
      .tx_negedge(tx_negedge),
214
      .tip(tip),
215
      .last(last_bit),
216
      .p_in(wb_dat_i),
217
      .p_out(rx),
218
      .s_clk(sclk_pad_o),
219
      .s_in(miso_pad_i),
220
      .s_out(mosi_pad_o)
221
      );
222
 
223
endmodule
224
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.