OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [support/] [except.S] - Blame information for rev 145

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 53 ConX.
#include "or1200.h"
2 2 rfajardo
 
3
// Linked from 0x200, so subtract 0x200 from each .org
4
.section .vectors, "ax"
5
 
6
/*
7 53 ConX.
   .org 0x100
8 50 rfajardo
 
9 53 ConX.
   _reset:
10
   l.nop
11
   l.j    _reset_except
12
   l.nop
13
 */
14
 
15 50 rfajardo
/*  This cannot be a regular function because it would waste the return register r9 of the interrupted procedure. */
16
/*  Furthermore, if this would be a function and l.j handler would be outside of this, the return register set here would be use upon return of this function. */
17
/*  However, the desired behavior is to finish the handler and let the return of the service routine simply restore the registers and return to the interrupted procedure.  */
18
#define intr_handler(handler)   \
19 74 rfajardo
        l.nop                   ;\
20 53 ConX.
l.addi  r1,r1,-244          /*free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1)*/;\
21
/*plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) */;\
22
l.sw    0x18(r1),r9         /*save register r9(return addr) to stack*/;\
23
l.jal   store_regs          /*save registers r3-r31 (except r9) to stack (r9 is changed here)*/;\
24
l.nop                       ;\
25
;\
26
l.movhi r9,hi(end_except)   /*set return addr to end_except instruction*/;\
27
l.ori   r9,r9,lo(end_except)/*set return addr to end_except instruction*/;\
28 74 rfajardo
l.j    CLABEL(handler)      ;\
29 53 ConX.
l.nop
30 50 rfajardo
 
31 2 rfajardo
.org 0x000
32
_except_200:
33 53 ConX.
intr_handler(buserr_except)
34 2 rfajardo
 
35 53 ConX.
        .org 0x100
36
        _except_300:
37
intr_handler(dpf_except)
38 2 rfajardo
 
39 53 ConX.
        .org 0x200
40
        _except_400:
41
intr_handler(ipf_except)
42 2 rfajardo
 
43 53 ConX.
        .org 0x300
44
        _except_500:
45
intr_handler(tick_except)
46 2 rfajardo
 
47 53 ConX.
        .org 0x400
48
        _except_600:
49
intr_handler(align_except)
50 2 rfajardo
 
51 53 ConX.
        .org 0x500
52
        _except_700:
53
intr_handler(illegal_except)
54 2 rfajardo
 
55 53 ConX.
        .org 0x600
56
        _except_800:
57
intr_handler(ext_except)
58 2 rfajardo
 
59 53 ConX.
        .org 0x700
60
        _except_900:
61
intr_handler(dtlbmiss_except)
62 2 rfajardo
 
63 53 ConX.
        .org 0x800
64
        _except_a00:
65
intr_handler(itlbmiss_except)
66 2 rfajardo
 
67 53 ConX.
        .org 0x900
68
        _except_b00:
69
intr_handler(range_except)
70 2 rfajardo
 
71 53 ConX.
        .org 0xa00
72
        _except_c00:
73
intr_handler(syscall_except)
74 2 rfajardo
 
75 53 ConX.
        .org 0xb00
76
        _except_d00:
77
intr_handler(res1_except)
78 2 rfajardo
 
79 53 ConX.
        .org 0xc00
80
        _except_e00:
81
intr_handler(trap_except)
82 2 rfajardo
 
83 53 ConX.
        .org 0xd00
84
        _except_f00:
85
intr_handler(res2_except)
86 2 rfajardo
 
87 53 ConX.
        store_regs:        //save registers r3-r31 (except r9) to stack
88
        l.sw    0x00(r1),r3
89
        l.sw    0x04(r1),r4
90
        l.sw    0x08(r1),r5
91
        l.sw    0x0c(r1),r6
92
        l.sw    0x10(r1),r7
93
        l.sw    0x14(r1),r8
94
        l.sw    0x1c(r1),r10
95
        l.sw    0x20(r1),r11
96
        l.sw    0x24(r1),r12
97
        l.sw    0x28(r1),r13
98
        l.sw    0x2c(r1),r14
99
        l.sw    0x30(r1),r15
100
        l.sw    0x34(r1),r16
101
        l.sw    0x38(r1),r17
102
        l.sw    0x3c(r1),r18
103
        l.sw    0x40(r1),r19
104
        l.sw    0x44(r1),r20
105
        l.sw    0x48(r1),r21
106
        l.sw    0x4c(r1),r22
107
        l.sw    0x50(r1),r23
108
        l.sw    0x54(r1),r24
109
        l.sw    0x58(r1),r25
110
        l.sw    0x5c(r1),r26
111
        l.sw    0x60(r1),r27
112
        l.sw    0x64(r1),r28
113
        l.sw    0x68(r1),r29
114
        l.sw    0x6c(r1),r30
115
        l.sw    0x70(r1),r31
116
        l.jr    r9
117
        l.nop
118 2 rfajardo
 
119 53 ConX.
        end_except:        //load back registers from stack r3-r31
120
        l.lwz   r3,0x00(r1)
121
        l.lwz   r4,0x04(r1)
122
        l.lwz   r5,0x08(r1)
123
        l.lwz   r6,0x0c(r1)
124
        l.lwz   r7,0x10(r1)
125
        l.lwz   r8,0x14(r1)
126
        l.lwz   r9,0x18(r1)
127
        l.lwz   r10,0x1c(r1)
128
        l.lwz   r11,0x20(r1)
129
        l.lwz   r12,0x24(r1)
130
        l.lwz   r13,0x28(r1)
131
        l.lwz   r14,0x2c(r1)
132
        l.lwz   r15,0x30(r1)
133
        l.lwz   r16,0x34(r1)
134
        l.lwz   r17,0x38(r1)
135
        l.lwz   r18,0x3c(r1)
136
        l.lwz   r19,0x40(r1)
137
        l.lwz   r20,0x44(r1)
138
        l.lwz   r21,0x48(r1)
139
        l.lwz   r22,0x4c(r1)
140
        l.lwz   r23,0x50(r1)
141
        l.lwz   r24,0x54(r1)
142
        l.lwz   r25,0x58(r1)
143
        l.lwz   r26,0x5c(r1)
144
        l.lwz   r27,0x60(r1)
145
        l.lwz   r28,0x64(r1)
146
        l.lwz   r29,0x68(r1)
147
        l.lwz   r30,0x6c(r1)
148
l.lwz   r31,0x70(r1)
149
        l.addi  r1,r1,244                //free stack places
150
        l.rfe                            //recover SR register and prior PC (jumps back to program)
151
        l.nop
152 2 rfajardo
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.