URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [utils/] [setup/] [configure.sh] - Blame information for rev 157
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
115 |
rfajardo |
. ${SCRIPT_DIR}/beautify.sh
|
| 2 |
110 |
rfajardo |
|
| 3 |
|
|
#Configuring MinSoC
|
| 4 |
|
|
cecho "\nConfiguring MinSoC"
|
| 5 |
|
|
execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std"
|
| 6 |
|
|
execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure"
|
| 7 |
|
|
execcmd "cd ${DIR_TO_INSTALL}"
|
| 8 |
|
|
|
| 9 |
|
|
|
| 10 |
|
|
#Configuring Advanced Debug System to work with MinSoC
|
| 11 |
|
|
cecho "\nConfiguring Advanced Debug System to work with MinSoC"
|
| 12 |
|
|
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog"
|
| 13 |
112 |
rfajardo |
execcmd "Turning off Advanced Debug System's JSP" "sed 's%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%' adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v"
|
| 14 |
110 |
rfajardo |
|
| 15 |
|
|
#Compiling and moving adv_jtag_bridge debug modules for simulation
|
| 16 |
|
|
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus"
|
| 17 |
112 |
rfajardo |
execcmd "Compiling VPI interface to connect GDB with simulation" "make"
|
| 18 |
110 |
rfajardo |
execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi"
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.