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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [CPU_Ctr.v] - Blame information for rev 2

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1 2 jjf 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    19:12:22 12/29/2016
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// Design Name:
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// Module Name:    CPU_Ctr
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "macros.v"
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module CPU_Ctr(
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input wire [31:0]       instruction,
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output wire             regdst_flag,
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output wire [1:0]       jump_flag,
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output wire [1:0]       branch_flag,
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output wire             memread_flag,
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output wire             memtoReg_flag,
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output wire [1:0]       ALUOp,
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output wire             memwrite_flag,
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output wire             ALUSrc_flag,
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output wire             regwrite_flag
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    );
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        wire [5:0]         opcode;
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        assign opcode = instruction[31:26];
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        /* RegDst */
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        assign regdst_flag = (opcode == `OPCODE_R) ? 1'b1 : 1'b0;
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        /* Jump */
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        assign jump_flag = JUMP( instruction );
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        function [1:0] JUMP;
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        input [31:0]       instruction;
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        begin
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           if( instruction[31:26] == `OPCODE_J_JUMP )
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               JUMP = `JUMP_J;
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           else if( instruction[31:26] == `OPCODE_JAL_JUMP )
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               JUMP = `JUMP_JAL;
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           else if( (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) )
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               JUMP = `JUMP_JR;
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           else
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               JUMP = 2'b00;
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        end
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        endfunction
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        /* Branch */
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        assign branch_flag = BRANCH( opcode );
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        function [1:0]   BRANCH;
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                input [5:0] opcode;
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                begin
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                        case( opcode )
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                        `OPCODE_I_BEQ: BRANCH = `BRANCH_OP_BEQ;
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                        `OPCODE_I_BNE: BRANCH = `BRANCH_OP_BNE;
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                        default:                BRANCH = 2'b00;
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                        endcase
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                end
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        endfunction
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        /* MemRead */
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        assign memread_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
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        /* MemToReg */
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        assign memtoReg_flag = (opcode == `OPCODE_I_LW) ? 1'b1 : 1'b0;
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        /* MemWrite */
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        assign memwrite_flag = (opcode == `OPCODE_I_SW) ? 1'b1 : 1'b0;
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        /* ALUSrc */
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        assign ALUSrc_flag = ALUSRC( opcode );
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        function ALUSRC;
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                input [5:0] opcode;
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                begin
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                        if( opcode[5:3] == `OPCODE_I_MASK)
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                                ALUSRC = 1'b1;
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                        else
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                                case( opcode )
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                                `OPCODE_I_LW:   ALUSRC = 1'b1;
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                                `OPCODE_I_SW:   ALUSRC = 1'b1;
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                                default:                ALUSRC = 1'b0;
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                                endcase
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                end
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        endfunction
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        /* RegWrite */
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        assign regwrite_flag = REGWRITE( opcode, instruction );
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        function REGWRITE;
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                input [5:0]      opcode;
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                input [31:0] instruction;
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                begin
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                    if( instruction == `NOP )
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                         REGWRITE = 1'b0;
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                    else if( opcode == `OPCODE_JAL_JUMP )
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                         REGWRITE = 1'b1;
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                        else if( opcode[5:3] == `OPCODE_I_MASK)
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                                REGWRITE = 1'b1;
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                        else if( opcode == `OPCODE_I_LW)
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                             REGWRITE = 1'b1;
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                        else if( opcode == `OPCODE_R )
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                        begin
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                             if( instruction[5:0] == `R_FUNC_JR)
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                                 REGWRITE = 1'b0;
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                             else
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                                 REGWRITE = 1'b1;
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                        end
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                        else
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                             REGWRITE = 1'b0;
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                end
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        endfunction
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        /* ALUOp */
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        assign ALUOp = OP( opcode );
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        function [1:0]   OP;
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                input [5:0]      opcode;
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                begin
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                        if( opcode[5:3] == `OPCODE_I_MASK)
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                                OP = 2'b11;
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                        else
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                                case( opcode )
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                                `OPCODE_I_SW:  OP = 2'b00;
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                                `OPCODE_I_LW:  OP = 2'b00;
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                                `OPCODE_I_BEQ: OP = 2'b01;
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                                `OPCODE_I_BNE: OP = 2'b01;
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                                `OPCODE_R:         OP = 2'b10;
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                                default:           OP = 2'b00;
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                                endcase
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                end
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        endfunction
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endmodule

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