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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [allocate.v] - Blame information for rev 2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/02/11 22:02:43
// Design Name: 
// Module Name: allocate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
 
 
module allocate(
input wire          clk,
input wire          rst,
input wire [31:0]   CPU_addr,
input wire [31:0]   main_mem_dout,
output reg [12:0]   main_mem_addr,
output reg [8:0]    cache_data_addr,
output wire [31:0]   cache_data_din,
output reg          cache_data_we,
input wire          start,
output reg          done
    );
 
    reg [1:0]       current_state, next_state;
    reg [2:0]       counter;
    wire [5:0]      CPU_addr_index;
 
    assign CPU_addr_index = CPU_addr[10:5];
 
    localparam  IDLE = 2'd0, TRANSFER = 2'd1, DONE = 2'd2;
 
    assign cache_data_din = main_mem_dout;
    /* first stage */
    always @(posedge clk)
    begin
        if( rst )
            current_state <= IDLE;
        else
            current_state <= next_state;
    end
 
    /* second stage */
    always @(*)
    begin
        next_state = IDLE;
        case( current_state )
        IDLE:   begin
                    if( start )
                        next_state =  TRANSFER;
                    else
                        next_state = IDLE;
                end
        TRANSFER:   begin
                        if( counter == 3'b111)
                            next_state = DONE;
                        else
                            next_state = TRANSFER;
                    end
        DONE: next_state = IDLE;
        default: next_state = IDLE;
        endcase
    end
 
    /* third stage */
    always @(posedge clk)
    begin
        if( rst )
        begin
            counter <= 0;
            done <= 0;
            cache_data_addr <= 0;
            cache_data_we <= 0;
            main_mem_addr <= 0;
        end
        else
        begin
            case( current_state )
            IDLE:   begin
                        counter <= 0;
                        done <= 0;
                        cache_data_addr <= 0;
                        cache_data_we <= 0;
                        main_mem_addr <= (CPU_addr[31:5] << 3);
                    end
            TRANSFER:   begin
                            counter <= counter + 1;
                            main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;
                            cache_data_we <= 1;
                            cache_data_addr <= (CPU_addr_index << 3) + counter;
                        end
            DONE:     begin
                        cache_data_we <= 0;
                        done <= 1'b1;
                     end
            endcase
        end
    end
 
endmodule

Line No.	Rev	Author	Line
1	2	jjf	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 2017/02/11 22:02:43`
7			`// Design Name:`
8			`// Module Name: allocate`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool Versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22
23			`module allocate(`
24			`input wire clk,`
25			`input wire rst,`
26			`input wire [31:0] CPU_addr,`
27			`input wire [31:0] main_mem_dout,`
28			`output reg [12:0] main_mem_addr,`
29			`output reg [8:0] cache_data_addr,`
30			`output wire [31:0] cache_data_din,`
31			`output reg cache_data_we,`
32			`input wire start,`
33			`output reg done`
34			`);`
35
36			`reg [1:0] current_state, next_state;`
37			`reg [2:0] counter;`
38			`wire [5:0] CPU_addr_index;`
39
40			`assign CPU_addr_index = CPU_addr[10:5];`
41
42			`localparam IDLE = 2'd0, TRANSFER = 2'd1, DONE = 2'd2;`
43
44			`assign cache_data_din = main_mem_dout;`
45			`/* first stage */`
46			`always @(posedge clk)`
47			`begin`
48			`if( rst )`
49			`current_state <= IDLE;`
50			`else`
51			`current_state <= next_state;`
52			`end`
53
54			`/* second stage */`
55			`always @(*)`
56			`begin`
57			`next_state = IDLE;`
58			`case( current_state )`
59			`IDLE: begin`
60			`if( start )`
61			`next_state = TRANSFER;`
62			`else`
63			`next_state = IDLE;`
64			`end`
65			`TRANSFER: begin`
66			`if( counter == 3'b111)`
67			`next_state = DONE;`
68			`else`
69			`next_state = TRANSFER;`
70			`end`
71			`DONE: next_state = IDLE;`
72			`default: next_state = IDLE;`
73			`endcase`
74			`end`
75
76			`/* third stage */`
77			`always @(posedge clk)`
78			`begin`
79			`if( rst )`
80			`begin`
81			`counter <= 0;`
82			`done <= 0;`
83			`cache_data_addr <= 0;`
84			`cache_data_we <= 0;`
85			`main_mem_addr <= 0;`
86			`end`
87			`else`
88			`begin`
89			`case( current_state )`
90			`IDLE: begin`
91			`counter <= 0;`
92			`done <= 0;`
93			`cache_data_addr <= 0;`
94			`cache_data_we <= 0;`
95			`main_mem_addr <= (CPU_addr[31:5] << 3);`
96			`end`
97			`TRANSFER: begin`
98			`counter <= counter + 1;`
99			`main_mem_addr <= (CPU_addr[31:5] << 3) + counter + 1;`
100			`cache_data_we <= 1;`
101			`cache_data_addr <= (CPU_addr_index << 3) + counter;`
102			`end`
103			`DONE: begin`
104			`cache_data_we <= 0;`
105			`done <= 1'b1;`
106			`end`
107			`endcase`
108			`end`
109			`end`
110
111			`endmodule`

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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [allocate.v] - Blame information for rev 2