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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [decode.v] - Blame information for rev 2

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1 2 jjf 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    17:00:52 12/29/2016
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// Design Name:
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// Module Name:    registers
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "macros.v"
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module decode(
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input wire                                              clk,
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input wire                                              rst,
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input wire [31:0]               pc,
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input wire [31:0]               instruction,
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input wire                                              regwrite_flag,
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input wire [4:0]                write_reg,
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input wire [31:0]               write_data,
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input wire                      isFlush,
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input wire                      isCacheStall,
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output reg [31:0]               reg1_data,
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output reg [31:0]               reg2_data,
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output reg signed [31:0]        reg_immediate,
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output reg [31:0]               reg_instruction,
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output reg [4:0]                reg_rt,
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output reg [4:0]                reg_rd,
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output reg [31:0]               reg_pc,
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output reg [3:0]                reg_ctr_ex,
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output reg [5:0]                reg_ctr_m,
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output reg [1:0]                reg_ctr_wb,
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output wire                     isHazard,
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/* bypass interface */
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input wire [4:0]                ex_write_reg,
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input wire                      ex_regwrite_flag,
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input wire [4:0]                mem_write_reg,
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input wire                      mem_regwrite_flag,
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output reg [1:0]                reg_forward_a,
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output reg [1:0]                reg_forward_b,
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output reg [3:0]                reg_ALUcmd,
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input wire [1:0]                bht_token,
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output reg [1:0]                reg_bht_token
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    );
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         /* define 32 32-bit width register */
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         reg    [31:0]                           registers[31:0];
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         /* the CPU control signals */
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         wire                    c_regdst_flag;
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     wire [1:0]              c_jump_flag;
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     wire [1:0]              c_branch_flag;
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     wire                    c_memread_flag;
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     wire                    c_memtoReg_flag;
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     wire [1:0]              c_ALUOp;
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     wire                    c_memwrite_flag;
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     wire                    c_ALUSrc_flag;
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     wire                    c_regwrite_flag;
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         /* the register indes */
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         wire [4:0]                rs;
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         wire [4:0]                rt;
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         wire [4:0]                rd;
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         integer                   index;
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         assign rs = instruction[25:21];
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         assign rt = instruction[20:16];
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         assign rd = instruction[15:11];
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         /* detech the Hazard of LW instruction */
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         assign isHazard = (reg_ctr_m[1] == 1'b1) && ( (reg_rt == rs) || (reg_rt == rt));
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         wire [1:0]                    forward_a;
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         wire [1:0]                    forward_b;
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          /* instantiate of the bypass control unit */
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      bypath_ctr bypath_ctr_inst(
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        .id_ex_rs(                  rs                          ),
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        .id_ex_rt(                  rt                          ),
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        .ex_mem_rd(                 ex_write_reg                ),
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        .mem_wb_rd(                 mem_write_reg             ),
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        .ex_mem_regwrite_flag(      ex_regwrite_flag               ),
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        .mem_wb_regwrite_flag(      mem_regwrite_flag           ),
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        .forward_a(                 forward_a                   ),
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        .forward_b(                 forward_b                   )
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      );
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      /* save the registers to the next stage */
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      always @(posedge clk)
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      begin
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        if( rst )
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        begin
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            reg_forward_a <= 0;
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            reg_forward_b <= 0;
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            reg_rt <= 0;
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            reg_rd <= 0;
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            reg_pc <= 0;
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            reg_instruction <= 0;
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            reg_immediate <= 0;
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            reg1_data <= 0;
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            reg2_data <= 0;
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        end
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        else
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        begin
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            if( isFlush )
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            begin
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                reg_forward_a <= 0;
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                reg_forward_b <= 0;
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                reg_rt <= 0;
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                reg_rd <= 0;
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                reg_pc <= 0;
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                reg_instruction <= 0;
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                reg_immediate <= 0;
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                reg1_data <= 0;
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                reg2_data <= 0;
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            end
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            else if( isCacheStall || isHazard )
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            begin
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                reg_forward_a <= reg_forward_a;
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                reg_forward_b <= reg_forward_b;
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                reg_rt <= reg_rt;
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                reg_rd <= reg_rd;
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                reg_pc <= reg_pc;
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                reg_instruction <= reg_instruction;
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                reg_immediate <= reg_immediate;
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                reg1_data <= reg1_data;
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                reg2_data <= reg2_data;
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            end
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            else
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            begin
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                reg_forward_a <= forward_a;
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                reg_forward_b <= forward_b;
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                reg_rd <= rd;
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                if( c_jump_flag == `JUMP_JAL)
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                    reg_rt <= 5'd31;
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                else
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                    reg_rt <= rt;
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                reg_pc <= pc;
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                reg_instruction <= instruction;
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                reg_immediate <= instruction[15] ? {16'hFFFF, instruction[15:0]} : {16'h0, instruction[15:0]};
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                /* create a bypath for reg1_data */
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                if( regwrite_flag && write_reg == rs)
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                    reg1_data <= write_data;
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                else
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                    reg1_data <= registers[rs];
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                /* create a bypath for reg2_data */
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                if(regwrite_flag && write_reg == rt)
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                    reg2_data <= write_data;
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                else
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                    reg2_data <= registers[rt];
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            end
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        end
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      end
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         /* write the register */
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         always @(posedge clk)
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         begin
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                if( rst )
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                        begin
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                                for( index = 0; index < 32; index = index + 1)
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                                begin
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                                        registers[ index ] <= 0;
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                                end
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                        end
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                else
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                        begin
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                                if( regwrite_flag )
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                                        registers[ write_reg ] <= write_data;
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                        end
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         end
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         // Instantiate of the ALU_ctr
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         wire [5:0]    opcode;
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         wire [5:0]    funct;
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         wire [3:0]    ALUcmd;
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         assign opcode = instruction[31:26];
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         assign funct = instruction[5:0];
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     ALU_Ctr ALU_Ctr_inst (
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         .opcode(       opcode        ),
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         .funct(        funct         ),
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         .ALUOp(        c_ALUOp       ),
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         .cmd(          ALUcmd        )
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     );
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         /* generate the CPU control signals in the decode stage */
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         CPU_Ctr CPU_Ctr_inst (
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         .instruction(        instruction         ),
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         .regdst_flag(        c_regdst_flag        ),
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         .jump_flag(          c_jump_flag        ),
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         .branch_flag(        c_branch_flag        ),
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         .memread_flag(       c_memread_flag    ),
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         .memtoReg_flag(      c_memtoReg_flag    ),
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         .ALUOp(              c_ALUOp            ),
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         .memwrite_flag(      c_memwrite_flag    ),
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         .ALUSrc_flag(        c_ALUSrc_flag        ),
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         .regwrite_flag(      c_regwrite_flag    )
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         );
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         /* combine and save the control signals */
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         always @(posedge clk)
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         begin
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           if( rst )
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           begin
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               reg_ctr_wb <= 0;
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               reg_ctr_m <= 0;
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               reg_ctr_ex <= 0;
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               reg_bht_token <= 0;
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               reg_ALUcmd <= 0;
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           end
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           else
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           begin
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               if( isCacheStall )
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               begin
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                   reg_ctr_ex <= reg_ctr_ex;
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                   reg_ctr_m <= reg_ctr_m;
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                   reg_ctr_wb <= reg_ctr_wb;
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                   reg_ALUcmd <= reg_ALUcmd;
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                   reg_bht_token <= reg_bht_token;
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               end
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               /* clear the control signals when found the Hazard or Flush  */
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               else if( isHazard || isFlush )
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               begin
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                   reg_ctr_ex <= 0;
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                   reg_ctr_m <= 0;
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                   reg_ctr_wb <= 0;
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                   reg_ALUcmd <= 0;
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                   reg_bht_token <= 0;
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               end
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               else
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               begin
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                   reg_ALUcmd <= ALUcmd;
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                   /* control signals for EX stage */
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                   reg_ctr_ex[0] <= c_ALUSrc_flag;
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                   reg_ctr_ex[2:1] <= c_ALUOp;
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                   reg_ctr_ex[3] <= c_regdst_flag;
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                   /* control signals for M stage */
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                   reg_ctr_m[0] <= c_memwrite_flag;
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                   reg_ctr_m[1] <= c_memread_flag;
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                   reg_ctr_m[3:2] <= c_branch_flag;
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                   reg_ctr_m[5:4] <= c_jump_flag;
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                   /* control signals for WB stage */
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                   reg_ctr_wb[0] <= c_memtoReg_flag;
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                   reg_ctr_wb[1] <= c_regwrite_flag;
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                   /* the bht_token */
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                   reg_bht_token <= bht_token;
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               end
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           end
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         end
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endmodule

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