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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [fetch.v] - Blame information for rev 2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:41:57 12/29/2016 
// Design Name: 
// Module Name:    pc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "macros.v"
module fetch(
input wire                                                      clk,
input wire                                                      rst,
input wire [31:0]                   instruction,
input wire [31:0]                   pc_branch,
input wire [31:0]                   pc_jump,
input wire [31:0]                   pc_next,
input wire                          real_token,
input wire                          jump_token,
input wire                          isHazard,
input wire                          isFlush,
input wire                          isCacheStall,
output reg [31:0]                   reg_pc,
output reg [31:0]                   reg_instruction,
/* the BHT interface */
output reg [1:0]                    reg_bht_token,
input wire [9:0]                    bht_write_addr,
input wire                          bht_we,
input wire [33:0]                   bht_din
    );
 
        wire [31:0]                pc_inc;
        wire [31:0]                pc;
        wire                       pre_jump_flag;
        wire                       jump_j_flag;
        wire                       jump_jal_flag;
        wire                       jump_jr_flag;
        /* the BHT related signals */
    wire                        if_branch_flag;
 
        /* pre-decode the jump flag for J/JAL */
        assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1'b1 : 1'b0;
        assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1'b1 : 1'b0;
        assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1'b1 : 1'b0;
        /* set the pre-jump signal */
    assign pre_jump_flag = (jump_j_flag | jump_jal_flag) | jump_jr_flag;
    /* check the branch and jump instruction at the FETCH stage */
    assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) | (instruction[31:26] == `OPCODE_I_BNE) | pre_jump_flag;
 
        /* calculate the output PC */
        assign pc_inc = reg_pc + 3'd4;
        assign pc = BRANCH_RES(isFlush, jump_token, real_token, pc_branch, pc_jump, pc_next, pc_inc);
        function [31:0] BRANCH_RES;
                input         isFlush;
                input         jump_token;
                input         real_token;
                input [31:0]  pc_branch;
                input [31:0]  pc_jump;
                input [31:0]  pc_next;
                input [31:0]  pc_inc;
                begin
                  if( isFlush )
                  begin
                      if( real_token )
                          BRANCH_RES = pc_branch;
                      else if( jump_token )
                          BRANCH_RES = pc_jump;
                      else
                          BRANCH_RES = pc_next;
                  end
                  else
                      BRANCH_RES = pc_inc;
                end
        endfunction
 
 
        wire [9:0]     bht_read_addr;
        wire [33:0]    bht_dout;
        wire [1:0]     bht_predict_isBranch;
        wire [31:0]    bht_predict_pc;
 
        /* bht read port */
        assign bht_read_addr = reg_pc[11:2];
        assign bht_predict_isBranch = bht_dout[33:32];
        assign bht_predict_pc = bht_dout[31:0];
        /* instantiate of the BHT */
        bht bht_inst(
           .a( bht_write_addr ),
           .d( bht_din ),
           .dpra( bht_read_addr ),
           .clk( clk ),
           .we( bht_we ),
           .dpo( bht_dout )
        );
 
        /* deal with other ocasions */
        always@(posedge clk)
        begin
                if( rst )
                  begin
                        reg_pc <= 0;
                        reg_instruction <= 0;
                        reg_bht_token <= 0;
                  end
                else
                        begin
                                /* set the instruction as NOP when found the FLUSH signal */
                if( isFlush )
                 begin
                    reg_pc <= pc;
                    reg_instruction <= `NOP;
                    reg_bht_token <= 0;
                 end
                 /* stall when found the Hazard signal */
                            else if( isHazard || isCacheStall )
                             begin
                                reg_pc <= reg_pc;
                    reg_instruction <= reg_instruction;
                    reg_bht_token <= reg_bht_token;
                                 end
                                 /* the branch predict */
                                 else if( if_branch_flag && bht_predict_isBranch[1] )
                                 begin
                                    reg_pc <= bht_predict_pc;
                                    reg_instruction <= instruction;
                                    reg_bht_token <= bht_predict_isBranch;
                                 end
                                else
                                 begin
                                    reg_pc <= pc;
                                    reg_instruction <= instruction;
                                    reg_bht_token <= bht_predict_isBranch;;
                                 end
                        end
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	jjf	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 16:41:57 12/29/2016`
7			`// Design Name:`
8			`// Module Name: pc`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`include "macros.v"
22			`module fetch(`
23			`input wire clk,`
24			`input wire rst,`
25			`input wire [31:0] instruction,`
26			`input wire [31:0] pc_branch,`
27			`input wire [31:0] pc_jump,`
28			`input wire [31:0] pc_next,`
29			`input wire real_token,`
30			`input wire jump_token,`
31			`input wire isHazard,`
32			`input wire isFlush,`
33			`input wire isCacheStall,`
34			`output reg [31:0] reg_pc,`
35			`output reg [31:0] reg_instruction,`
36			`/* the BHT interface */`
37			`output reg [1:0] reg_bht_token,`
38			`input wire [9:0] bht_write_addr,`
39			`input wire bht_we,`
40			`input wire [33:0] bht_din`
41			`);`
42
43			`wire [31:0] pc_inc;`
44			`wire [31:0] pc;`
45			`wire pre_jump_flag;`
46			`wire jump_j_flag;`
47			`wire jump_jal_flag;`
48			`wire jump_jr_flag;`
49			`/* the BHT related signals */`
50			`wire if_branch_flag;`
51
52			`/* pre-decode the jump flag for J/JAL */`
53			assign jump_j_flag = (instruction[31:26] == `OPCODE_J_JUMP) ? 1'b1 : 1'b0;
54			assign jump_jal_flag = (instruction[31:26] == `OPCODE_JAL_JUMP) ? 1'b1 : 1'b0;
55			assign jump_jr_flag = (instruction[31:26] == `OPCODE_R && instruction[5:0] == `R_FUNC_JR) ? 1'b1 : 1'b0;
56			`/* set the pre-jump signal */`
57			`assign pre_jump_flag = (jump_j_flag \| jump_jal_flag) \| jump_jr_flag;`
58			`/* check the branch and jump instruction at the FETCH stage */`
59			assign if_branch_flag = (instruction[31:26] == `OPCODE_I_BEQ) \| (instruction[31:26] == `OPCODE_I_BNE) \| pre_jump_flag;
60
61			`/* calculate the output PC */`
62			`assign pc_inc = reg_pc + 3'd4;`
63			`assign pc = BRANCH_RES(isFlush, jump_token, real_token, pc_branch, pc_jump, pc_next, pc_inc);`
64			`function [31:0] BRANCH_RES;`
65			`input isFlush;`
66			`input jump_token;`
67			`input real_token;`
68			`input [31:0] pc_branch;`
69			`input [31:0] pc_jump;`
70			`input [31:0] pc_next;`
71			`input [31:0] pc_inc;`
72			`begin`
73			`if( isFlush )`
74			`begin`
75			`if( real_token )`
76			`BRANCH_RES = pc_branch;`
77			`else if( jump_token )`
78			`BRANCH_RES = pc_jump;`
79			`else`
80			`BRANCH_RES = pc_next;`
81			`end`
82			`else`
83			`BRANCH_RES = pc_inc;`
84			`end`
85			`endfunction`
86
87
88			`wire [9:0] bht_read_addr;`
89			`wire [33:0] bht_dout;`
90			`wire [1:0] bht_predict_isBranch;`
91			`wire [31:0] bht_predict_pc;`
92
93			`/* bht read port */`
94			`assign bht_read_addr = reg_pc[11:2];`
95			`assign bht_predict_isBranch = bht_dout[33:32];`
96			`assign bht_predict_pc = bht_dout[31:0];`
97			`/* instantiate of the BHT */`
98			`bht bht_inst(`
99			`.a( bht_write_addr ),`
100			`.d( bht_din ),`
101			`.dpra( bht_read_addr ),`
102			`.clk( clk ),`
103			`.we( bht_we ),`
104			`.dpo( bht_dout )`
105			`);`
106
107			`/* deal with other ocasions */`
108			`always@(posedge clk)`
109			`begin`
110			`if( rst )`
111			`begin`
112			`reg_pc <= 0;`
113			`reg_instruction <= 0;`
114			`reg_bht_token <= 0;`
115			`end`
116			`else`
117			`begin`
118			`/* set the instruction as NOP when found the FLUSH signal */`
119			`if( isFlush )`
120			`begin`
121			`reg_pc <= pc;`
122			reg_instruction <= `NOP;
123			`reg_bht_token <= 0;`
124			`end`
125			`/* stall when found the Hazard signal */`
126			`else if( isHazard \|\| isCacheStall )`
127			`begin`
128			`reg_pc <= reg_pc;`
129			`reg_instruction <= reg_instruction;`
130			`reg_bht_token <= reg_bht_token;`
131			`end`
132			`/* the branch predict */`
133			`else if( if_branch_flag && bht_predict_isBranch[1] )`
134			`begin`
135			`reg_pc <= bht_predict_pc;`
136			`reg_instruction <= instruction;`
137			`reg_bht_token <= bht_predict_isBranch;`
138			`end`
139			`else`
140			`begin`
141			`reg_pc <= pc;`
142			`reg_instruction <= instruction;`
143			`reg_bht_token <= bht_predict_isBranch;;`
144			`end`
145			`end`
146			`end`
147
148			`endmodule`

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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [fetch.v] - Blame information for rev 2