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[/] [mips32/] [trunk/] [Classic-MIPS/] [source/] [src/] [mem.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 jjf 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2017/01/11 16:52:30
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// Design Name:
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// Module Name: mem
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "macros.v"
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module mem(
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input wire                      clk,
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input wire                      rst,
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input wire [5:0]                ctr_m,
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input wire [1:0]                ctr_wb,
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input wire [31:0]               ALU_out,
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input wire [31:0]               reg2_data,
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input wire [4:0]                write_reg,
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output reg [31:0]               reg_mem_out,
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output reg [31:0]               reg_ALU_out,
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output reg [4:0]                reg_write_reg,
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output reg [1:0]                reg_ctr_wb,
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output wire                     isFlush,
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output wire                     isCacheStall,
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input wire [31:0]               pc,
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input wire signed [31:0]        pc_branch,
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input wire signed [31:0]        pc_jump,
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output wire                     real_token,
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output wire                     jump_token,
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input wire [1:0]                bht_token,
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/* the bht interface */
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output wire [9:0]               bht_write_addr,
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output wire                     bht_we,
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output wire [33:0]              bht_din,
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/* user ram interface */
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input wire [12:0]                         user_addr,
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input wire                      user_we,
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input wire [31:0]               user_din,
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output wire [31:0]                    user_dout
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    );
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    wire [1:0]                  branch_flag;
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    wire                        memread_flag;
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    wire                        memwrite_flag;
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    reg signed [31:0]           reg_pc;
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    wire [31:0]                 mem_out;
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    wire [1:0]                  next_token;
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    /* the MEM operation related signals */
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    assign memread_flag = ctr_m[1];
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    assign memwrite_flag = ctr_m[0];
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    assign branch_flag = ctr_m[3:2];
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    assign jump_token = |ctr_m[5:4];
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    /* check the real branch and jump situation */
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    assign real_token =  ((branch_flag == `BRANCH_OP_BEQ) && (ALU_out == 32'h0)) ||
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          ( (branch_flag == `BRANCH_OP_BNE) && (ALU_out != 32'h0) );
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    /* set the flush signal when the real_token != bht_token */
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    assign isFlush = ISFLUSH( real_token, jump_token, bht_token, pc, pc_branch, pc_jump );
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    function ISFLUSH;
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    input           real_token;
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    input           jump_token;
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    input [1:0]     bht_token;
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    input [31:0]    pc;
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    input [31:0]    pc_branch;
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    input [31:0]    pc_jump;
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        if( (real_token | jump_token) != bht_token[1] )
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            ISFLUSH = 1;
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        /* check whether the branch_pc is equal to the predict pc, it not equal, Flush and JUMP to the branch_pc */
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        else if( (real_token == 1'b1) && (bht_token[1] == 1'b1) && ( pc != pc_branch))
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            ISFLUSH = 1;
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        /* check the jump */
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        else if( (jump_token == 1'b1) && (bht_token[1] == 1'b1) && ( pc != pc_jump))
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            ISFLUSH = 1;
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        else
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            ISFLUSH = 0;
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    endfunction
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    /* set the bht interface */
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    assign bht_write_addr = reg_pc[11:2];
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    assign bht_we = (branch_flag == `BRANCH_OP_BEQ) | (branch_flag == `BRANCH_OP_BNE) | jump_token;
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    assign next_token = NEXT_TOKEN(bht_token, (real_token | jump_token) );
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    assign bht_din = real_token ? {next_token, pc_branch} : {next_token, pc_jump};
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`ifdef __BHT_DEBUG__
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    /* debug the predict accuracy */
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    reg [31:0]     total_cnt;
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    reg [31:0]     right_cnt;
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    always @(posedge clk)
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    begin
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        if( rst )
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        begin
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            total_cnt <= 0;
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            right_cnt <= 0;
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        end
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        else
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        begin
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            if( bht_we )
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            begin
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                total_cnt <= total_cnt + 1'd1;
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                if( isFlush )
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                begin
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                    $display("%x predict wrong(%d|%d)", bht_write_addr, right_cnt, total_cnt);
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                end
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                else
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                begin
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                    right_cnt <= right_cnt + 1'b1;
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                    $display("%x predict right(%d|%d)", bht_write_addr, right_cnt, total_cnt);
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                end
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            end
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        end
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    end
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`endif
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    /* calculate the next state */
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    function [1:0] NEXT_TOKEN;
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    input [1:0] bht_token;
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    input       all_real_token;
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    case( bht_token )
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    2'b00:  begin
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                if( all_real_token )
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                    NEXT_TOKEN = 2'b01;
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                else
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                    NEXT_TOKEN = 2'b00;
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            end
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    2'b01:  begin
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                if( all_real_token )
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                    NEXT_TOKEN = 2'b10;
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                else
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                    NEXT_TOKEN = 2'b00;
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            end
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    2'b10:  begin
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                if( all_real_token )
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                    NEXT_TOKEN = 2'b11;
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                else
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                    NEXT_TOKEN = 2'b01;
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            end
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    2'b11:  begin
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                if( all_real_token )
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                    NEXT_TOKEN = 2'b11;
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                else
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                    NEXT_TOKEN = 2'b10;
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            end
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    endcase
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    endfunction
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    //Instantiate of the SimpleCache
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    SimpleCache SimpleCache_i(
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        .clk(               clk             ),
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        .rst(               rst             ),
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        .CPU_read_en(       memread_flag    ),
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        .CPU_read_dout(     mem_out     ),
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        .CPU_write_en(      memwrite_flag   ),
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        .CPU_write_din(     reg2_data       ),
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        .CPU_addr(          ALU_out         ),
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        .isCacheStall(       isCacheStall     ),
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        .mem_b_we(          user_we         ),
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        .mem_b_addr(        user_addr       ),
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        .mem_b_din(         user_din        ),
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        .mem_b_dout(        user_dout       )
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    );
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    /* register data to the next stage */
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    always @(posedge clk)
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    begin
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        if( rst )
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        begin
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            reg_ALU_out <= 0;
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            reg_write_reg <= 0;
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            reg_ctr_wb <= 0;
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            reg_mem_out <= 0;
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            reg_pc <= 0;
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        end
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        else
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        begin
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            if( ~isCacheStall )
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            begin
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                if( ctr_m[5:4] == `JUMP_JAL)
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                    reg_ALU_out <= reg_pc + 3'd4;
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                else
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                    reg_ALU_out <= ALU_out;
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                reg_write_reg <= write_reg;
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                reg_ctr_wb <= ctr_wb;
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                reg_mem_out <= mem_out;
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                reg_pc <= pc;
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            end
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        end
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    end
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endmodule

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