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[/] [mips32r1/] [trunk/] [Hardware/] [MIPS32_Standalone/] [Compare.v] - Blame information for rev 12

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Line No. Rev Author Line
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`timescale 1ns / 1ps
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/*
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 * File         : Compare.v
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 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   15-Jun-2011  GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   Compares two 32-bit values and outputs the following information about them:
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 *      EQ  : A and B are equal
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 *      GZ  : A is greater than zero
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 *      LZ  : A is less than zero
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 *      GEZ : A is greater than or equal to zero
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 *      LEZ : A is less than or equal to zero
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 */
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module Compare(
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    input  [31:0] A,
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    input  [31:0] B,
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    output EQ,
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    output GZ,
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    output LZ,
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    output GEZ,
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    output LEZ
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    );
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    wire   ZeroA = (A == 32'b0);
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    assign EQ  = ( A == B);
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    assign GZ  = (~A[31] & ~ZeroA);
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    assign LZ  =   A[31];
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    assign GEZ =  ~A[31];
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    assign LEZ = ( A[31] |  ZeroA);
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endmodule
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