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`timescale 1ns / 1ps
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/*
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* File : Control.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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* Modification History:
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* Rev Date Initials Description of Change
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* 1.0 7-Jun-2011 GEA Initial design.
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* 2.0 26-May-2012 GEA Release version with CP0.
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*
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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*
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* Description:
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* The Datapath Controller. This module sets the datapath control
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* bits for an incoming instruction. These control bits follow the
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* instruction through each pipeline stage as needed, and constitute
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* the effective operation of the processor through each pipeline stage.
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*/
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module Control(
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input ID_Stall,
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input [5:0] OpCode,
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input [5:0] Funct,
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input [4:0] Rs, // used to differentiate mfc0 and mtc0
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input [4:0] Rt, // used to differentiate bgez,bgezal,bltz,bltzal,teqi,tgei,tgeiu,tlti,tltiu,tnei
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input Cmp_EQ,
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input Cmp_GZ,
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input Cmp_GEZ,
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input Cmp_LZ,
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input Cmp_LEZ,
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//------------
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output IF_Flush,
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output reg [7:0] DP_Hazards,
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output [1:0] PCSrc,
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output SignExtend,
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output Link,
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output Movn,
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output Movz,
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output Mfc0,
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output Mtc0,
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output CP1,
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output CP2,
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output CP3,
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output Eret,
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output Trap,
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output TrapCond,
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output EXC_Sys,
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output EXC_Bp,
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output EXC_RI,
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output ID_CanErr,
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output EX_CanErr,
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output M_CanErr,
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output NextIsDelay,
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output RegDst,
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output ALUSrcImm,
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output reg [4:0] ALUOp,
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output LLSC,
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output MemWrite,
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output MemRead,
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output MemByte,
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output MemHalf,
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output MemSignExtend,
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output Left,
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output Right,
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output RegWrite,
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output MemtoReg
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);
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`include "MIPS_Parameters.v"
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2 |
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wire Movc;
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wire Branch, Branch_EQ, Branch_GTZ, Branch_LEZ, Branch_NEQ, Branch_GEZ, Branch_LTZ;
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wire Unaligned_Mem;
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reg [15:0] Datapath;
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assign PCSrc[0] = Datapath[14];
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assign Link = Datapath[13];
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assign ALUSrcImm = Datapath[12];
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assign Movc = Datapath[11];
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assign Trap = Datapath[10];
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assign TrapCond = Datapath[9];
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assign RegDst = Datapath[8];
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assign LLSC = Datapath[7];
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assign MemRead = Datapath[6];
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assign MemWrite = Datapath[5];
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assign MemHalf = Datapath[4];
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assign MemByte = Datapath[3];
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assign MemSignExtend = Datapath[2];
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assign RegWrite = Datapath[1];
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assign MemtoReg = Datapath[0];
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reg [2:0] DP_Exceptions;
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assign ID_CanErr = DP_Exceptions[2];
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assign EX_CanErr = DP_Exceptions[1];
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assign M_CanErr = DP_Exceptions[0];
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3 |
ayersg |
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// Set the main datapath control signals based on the Op Code
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always @(*) begin
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if (ID_Stall)
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Datapath <= DP_None;
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else begin
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case (OpCode)
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// R-Type
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Op_Type_R :
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begin
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case (Funct)
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Funct_Add : Datapath <= DP_Add;
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Funct_Addu : Datapath <= DP_Addu;
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Funct_And : Datapath <= DP_And;
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Funct_Break : Datapath <= DP_Break;
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Funct_Div : Datapath <= DP_Div;
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Funct_Divu : Datapath <= DP_Divu;
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Funct_Jalr : Datapath <= DP_Jalr;
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Funct_Jr : Datapath <= DP_Jr;
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Funct_Mfhi : Datapath <= DP_Mfhi;
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Funct_Mflo : Datapath <= DP_Mflo;
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Funct_Movn : Datapath <= DP_Movn;
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Funct_Movz : Datapath <= DP_Movz;
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Funct_Mthi : Datapath <= DP_Mthi;
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Funct_Mtlo : Datapath <= DP_Mtlo;
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Funct_Mult : Datapath <= DP_Mult;
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Funct_Multu : Datapath <= DP_Multu;
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Funct_Nor : Datapath <= DP_Nor;
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Funct_Or : Datapath <= DP_Or;
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Funct_Sll : Datapath <= DP_Sll;
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Funct_Sllv : Datapath <= DP_Sllv;
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Funct_Slt : Datapath <= DP_Slt;
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Funct_Sltu : Datapath <= DP_Sltu;
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Funct_Sra : Datapath <= DP_Sra;
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Funct_Srav : Datapath <= DP_Srav;
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Funct_Srl : Datapath <= DP_Srl;
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Funct_Srlv : Datapath <= DP_Srlv;
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Funct_Sub : Datapath <= DP_Sub;
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Funct_Subu : Datapath <= DP_Subu;
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Funct_Syscall : Datapath <= DP_Syscall;
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Funct_Teq : Datapath <= DP_Teq;
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Funct_Tge : Datapath <= DP_Tge;
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Funct_Tgeu : Datapath <= DP_Tgeu;
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Funct_Tlt : Datapath <= DP_Tlt;
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Funct_Tltu : Datapath <= DP_Tltu;
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Funct_Tne : Datapath <= DP_Tne;
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Funct_Xor : Datapath <= DP_Xor;
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default : Datapath <= DP_None;
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endcase
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end
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// R2-Type
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Op_Type_R2 :
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begin
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case (Funct)
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Funct_Clo : Datapath <= DP_Clo;
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Funct_Clz : Datapath <= DP_Clz;
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Funct_Madd : Datapath <= DP_Madd;
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Funct_Maddu : Datapath <= DP_Maddu;
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Funct_Msub : Datapath <= DP_Msub;
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Funct_Msubu : Datapath <= DP_Msubu;
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Funct_Mul : Datapath <= DP_Mul;
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default : Datapath <= DP_None;
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endcase
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end
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// I-Type
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Op_Addi : Datapath <= DP_Addi;
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Op_Addiu : Datapath <= DP_Addiu;
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Op_Andi : Datapath <= DP_Andi;
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Op_Ori : Datapath <= DP_Ori;
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Op_Pref : Datapath <= DP_Pref;
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Op_Slti : Datapath <= DP_Slti;
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Op_Sltiu : Datapath <= DP_Sltiu;
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Op_Xori : Datapath <= DP_Xori;
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// Jumps (using immediates)
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Op_J : Datapath <= DP_J;
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Op_Jal : Datapath <= DP_Jal;
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// Branches and Traps
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Op_Type_BI :
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begin
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case (Rt)
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OpRt_Bgez : Datapath <= DP_Bgez;
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OpRt_Bgezal : Datapath <= DP_Bgezal;
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OpRt_Bltz : Datapath <= DP_Bltz;
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OpRt_Bltzal : Datapath <= DP_Bltzal;
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OpRt_Teqi : Datapath <= DP_Teqi;
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OpRt_Tgei : Datapath <= DP_Tgei;
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OpRt_Tgeiu : Datapath <= DP_Tgeiu;
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OpRt_Tlti : Datapath <= DP_Tlti;
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OpRt_Tltiu : Datapath <= DP_Tltiu;
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OpRt_Tnei : Datapath <= DP_Tnei;
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default : Datapath <= DP_None;
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endcase
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end
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Op_Beq : Datapath <= DP_Beq;
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Op_Bgtz : Datapath <= DP_Bgtz;
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Op_Blez : Datapath <= DP_Blez;
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Op_Bne : Datapath <= DP_Bne;
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// Coprocessor 0
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Op_Type_CP0 :
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begin
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case (Rs)
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OpRs_MF : Datapath <= DP_Mfc0;
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OpRs_MT : Datapath <= DP_Mtc0;
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OpRs_ERET : Datapath <= (Funct == Funct_ERET) ? DP_Eret : DP_None;
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default : Datapath <= DP_None;
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endcase
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end
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// Memory
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Op_Lb : Datapath <= DP_Lb;
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Op_Lbu : Datapath <= DP_Lbu;
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Op_Lh : Datapath <= DP_Lh;
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Op_Lhu : Datapath <= DP_Lhu;
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Op_Ll : Datapath <= DP_Ll;
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Op_Lui : Datapath <= DP_Lui;
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Op_Lw : Datapath <= DP_Lw;
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Op_Lwl : Datapath <= DP_Lwl;
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Op_Lwr : Datapath <= DP_Lwr;
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Op_Sb : Datapath <= DP_Sb;
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Op_Sc : Datapath <= DP_Sc;
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Op_Sh : Datapath <= DP_Sh;
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Op_Sw : Datapath <= DP_Sw;
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Op_Swl : Datapath <= DP_Swl;
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Op_Swr : Datapath <= DP_Swr;
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default : Datapath <= DP_None;
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endcase
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end
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end
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2 |
ayersg |
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3 |
ayersg |
// Set the Hazard Control Signals and Exception Indicators based on the Op Code
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always @(*) begin
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case (OpCode)
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// R-Type
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Op_Type_R :
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begin
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case (Funct)
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Funct_Add : begin DP_Hazards <= HAZ_Add; DP_Exceptions <= EXC_Add; end
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Funct_Addu : begin DP_Hazards <= HAZ_Addu; DP_Exceptions <= EXC_Addu; end
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Funct_And : begin DP_Hazards <= HAZ_And; DP_Exceptions <= EXC_And; end
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Funct_Break : begin DP_Hazards <= HAZ_Break; DP_Exceptions <= EXC_Break; end
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Funct_Div : begin DP_Hazards <= HAZ_Div; DP_Exceptions <= EXC_Div; end
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Funct_Divu : begin DP_Hazards <= HAZ_Divu; DP_Exceptions <= EXC_Divu; end
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Funct_Jalr : begin DP_Hazards <= HAZ_Jalr; DP_Exceptions <= EXC_Jalr; end
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Funct_Jr : begin DP_Hazards <= HAZ_Jr; DP_Exceptions <= EXC_Jr; end
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Funct_Mfhi : begin DP_Hazards <= HAZ_Mfhi; DP_Exceptions <= EXC_Mfhi; end
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Funct_Mflo : begin DP_Hazards <= HAZ_Mflo; DP_Exceptions <= EXC_Mflo; end
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Funct_Movn : begin DP_Hazards <= HAZ_Movn; DP_Exceptions <= EXC_Movn; end
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Funct_Movz : begin DP_Hazards <= HAZ_Movz; DP_Exceptions <= EXC_Movz; end
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Funct_Mthi : begin DP_Hazards <= HAZ_Mthi; DP_Exceptions <= EXC_Mthi; end
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Funct_Mtlo : begin DP_Hazards <= HAZ_Mtlo; DP_Exceptions <= EXC_Mtlo; end
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Funct_Mult : begin DP_Hazards <= HAZ_Mult; DP_Exceptions <= EXC_Mult; end
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Funct_Multu : begin DP_Hazards <= HAZ_Multu; DP_Exceptions <= EXC_Multu; end
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Funct_Nor : begin DP_Hazards <= HAZ_Nor; DP_Exceptions <= EXC_Nor; end
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Funct_Or : begin DP_Hazards <= HAZ_Or; DP_Exceptions <= EXC_Or; end
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Funct_Sll : begin DP_Hazards <= HAZ_Sll; DP_Exceptions <= EXC_Sll; end
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Funct_Sllv : begin DP_Hazards <= HAZ_Sllv; DP_Exceptions <= EXC_Sllv; end
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Funct_Slt : begin DP_Hazards <= HAZ_Slt; DP_Exceptions <= EXC_Slt; end
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Funct_Sltu : begin DP_Hazards <= HAZ_Sltu; DP_Exceptions <= EXC_Sltu; end
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Funct_Sra : begin DP_Hazards <= HAZ_Sra; DP_Exceptions <= EXC_Sra; end
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Funct_Srav : begin DP_Hazards <= HAZ_Srav; DP_Exceptions <= EXC_Srav; end
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Funct_Srl : begin DP_Hazards <= HAZ_Srl; DP_Exceptions <= EXC_Srl; end
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Funct_Srlv : begin DP_Hazards <= HAZ_Srlv; DP_Exceptions <= EXC_Srlv; end
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Funct_Sub : begin DP_Hazards <= HAZ_Sub; DP_Exceptions <= EXC_Sub; end
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Funct_Subu : begin DP_Hazards <= HAZ_Subu; DP_Exceptions <= EXC_Subu; end
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Funct_Syscall : begin DP_Hazards <= HAZ_Syscall; DP_Exceptions <= EXC_Syscall; end
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Funct_Teq : begin DP_Hazards <= HAZ_Teq; DP_Exceptions <= EXC_Teq; end
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Funct_Tge : begin DP_Hazards <= HAZ_Tge; DP_Exceptions <= EXC_Tge; end
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Funct_Tgeu : begin DP_Hazards <= HAZ_Tgeu; DP_Exceptions <= EXC_Tgeu; end
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Funct_Tlt : begin DP_Hazards <= HAZ_Tlt; DP_Exceptions <= EXC_Tlt; end
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Funct_Tltu : begin DP_Hazards <= HAZ_Tltu; DP_Exceptions <= EXC_Tltu; end
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Funct_Tne : begin DP_Hazards <= HAZ_Tne; DP_Exceptions <= EXC_Tne; end
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Funct_Xor : begin DP_Hazards <= HAZ_Xor; DP_Exceptions <= EXC_Xor; end
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default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
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endcase
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end
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// R2-Type
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Op_Type_R2 :
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begin
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case (Funct)
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Funct_Clo : begin DP_Hazards <= HAZ_Clo; DP_Exceptions <= EXC_Clo; end
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Funct_Clz : begin DP_Hazards <= HAZ_Clz; DP_Exceptions <= EXC_Clz; end
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Funct_Madd : begin DP_Hazards <= HAZ_Madd; DP_Exceptions <= EXC_Madd; end
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Funct_Maddu : begin DP_Hazards <= HAZ_Maddu; DP_Exceptions <= EXC_Maddu; end
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Funct_Msub : begin DP_Hazards <= HAZ_Msub; DP_Exceptions <= EXC_Msub; end
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Funct_Msubu : begin DP_Hazards <= HAZ_Msubu; DP_Exceptions <= EXC_Msubu; end
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Funct_Mul : begin DP_Hazards <= HAZ_Mul; DP_Exceptions <= EXC_Mul; end
|
| 282 |
|
|
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
|
| 283 |
|
|
endcase
|
| 284 |
|
|
end
|
| 285 |
|
|
// I-Type
|
| 286 |
|
|
Op_Addi : begin DP_Hazards <= HAZ_Addi; DP_Exceptions <= EXC_Addi; end
|
| 287 |
|
|
Op_Addiu : begin DP_Hazards <= HAZ_Addiu; DP_Exceptions <= EXC_Addiu; end
|
| 288 |
|
|
Op_Andi : begin DP_Hazards <= HAZ_Andi; DP_Exceptions <= EXC_Andi; end
|
| 289 |
|
|
Op_Ori : begin DP_Hazards <= HAZ_Ori; DP_Exceptions <= EXC_Ori; end
|
| 290 |
|
|
Op_Pref : begin DP_Hazards <= HAZ_Pref; DP_Exceptions <= EXC_Pref; end
|
| 291 |
|
|
Op_Slti : begin DP_Hazards <= HAZ_Slti; DP_Exceptions <= EXC_Slti; end
|
| 292 |
|
|
Op_Sltiu : begin DP_Hazards <= HAZ_Sltiu; DP_Exceptions <= EXC_Sltiu; end
|
| 293 |
|
|
Op_Xori : begin DP_Hazards <= HAZ_Xori; DP_Exceptions <= EXC_Xori; end
|
| 294 |
|
|
// Jumps
|
| 295 |
|
|
Op_J : begin DP_Hazards <= HAZ_J; DP_Exceptions <= EXC_J; end
|
| 296 |
|
|
Op_Jal : begin DP_Hazards <= HAZ_Jal; DP_Exceptions <= EXC_Jal; end
|
| 297 |
|
|
// Branches and Traps
|
| 298 |
|
|
Op_Type_BI :
|
| 299 |
|
|
begin
|
| 300 |
|
|
case (Rt)
|
| 301 |
|
|
OpRt_Bgez : begin DP_Hazards <= HAZ_Bgez; DP_Exceptions <= EXC_Bgez; end
|
| 302 |
|
|
OpRt_Bgezal : begin DP_Hazards <= HAZ_Bgezal; DP_Exceptions <= EXC_Bgezal; end
|
| 303 |
|
|
OpRt_Bltz : begin DP_Hazards <= HAZ_Bltz; DP_Exceptions <= EXC_Bltz; end
|
| 304 |
|
|
OpRt_Bltzal : begin DP_Hazards <= HAZ_Bltzal; DP_Exceptions <= EXC_Bltzal; end
|
| 305 |
|
|
OpRt_Teqi : begin DP_Hazards <= HAZ_Teqi; DP_Exceptions <= EXC_Teqi; end
|
| 306 |
|
|
OpRt_Tgei : begin DP_Hazards <= HAZ_Tgei; DP_Exceptions <= EXC_Tgei; end
|
| 307 |
|
|
OpRt_Tgeiu : begin DP_Hazards <= HAZ_Tgeiu; DP_Exceptions <= EXC_Tgeiu; end
|
| 308 |
|
|
OpRt_Tlti : begin DP_Hazards <= HAZ_Tlti; DP_Exceptions <= EXC_Tlti; end
|
| 309 |
|
|
OpRt_Tltiu : begin DP_Hazards <= HAZ_Tltiu; DP_Exceptions <= EXC_Tltiu; end
|
| 310 |
|
|
OpRt_Tnei : begin DP_Hazards <= HAZ_Tnei; DP_Exceptions <= EXC_Tnei; end
|
| 311 |
|
|
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
|
| 312 |
|
|
endcase
|
| 313 |
|
|
end
|
| 314 |
|
|
Op_Beq : begin DP_Hazards <= HAZ_Beq; DP_Exceptions <= EXC_Beq; end
|
| 315 |
|
|
Op_Bgtz : begin DP_Hazards <= HAZ_Bgtz; DP_Exceptions <= EXC_Bgtz; end
|
| 316 |
|
|
Op_Blez : begin DP_Hazards <= HAZ_Blez; DP_Exceptions <= EXC_Blez; end
|
| 317 |
|
|
Op_Bne : begin DP_Hazards <= HAZ_Bne; DP_Exceptions <= EXC_Bne; end
|
| 318 |
|
|
// Coprocessor 0
|
| 319 |
|
|
Op_Type_CP0 :
|
| 320 |
|
|
begin
|
| 321 |
|
|
case (Rs)
|
| 322 |
|
|
OpRs_MF : begin DP_Hazards <= HAZ_Mfc0; DP_Exceptions <= EXC_Mfc0; end
|
| 323 |
|
|
OpRs_MT : begin DP_Hazards <= HAZ_Mtc0; DP_Exceptions <= EXC_Mtc0; end
|
| 324 |
2 |
ayersg |
OpRs_ERET : begin DP_Hazards <= (Funct == Funct_ERET) ? DP_Eret : 8'hxx; DP_Exceptions <= EXC_Eret; end
|
| 325 |
3 |
ayersg |
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
|
| 326 |
|
|
endcase
|
| 327 |
|
|
end
|
| 328 |
|
|
// Memory
|
| 329 |
|
|
Op_Lb : begin DP_Hazards <= HAZ_Lb; DP_Exceptions <= EXC_Lb; end
|
| 330 |
|
|
Op_Lbu : begin DP_Hazards <= HAZ_Lbu; DP_Exceptions <= EXC_Lbu; end
|
| 331 |
|
|
Op_Lh : begin DP_Hazards <= HAZ_Lh; DP_Exceptions <= EXC_Lh; end
|
| 332 |
|
|
Op_Lhu : begin DP_Hazards <= HAZ_Lhu; DP_Exceptions <= EXC_Lhu; end
|
| 333 |
|
|
Op_Ll : begin DP_Hazards <= HAZ_Ll; DP_Exceptions <= EXC_Ll; end
|
| 334 |
|
|
Op_Lui : begin DP_Hazards <= HAZ_Lui; DP_Exceptions <= EXC_Lui; end
|
| 335 |
|
|
Op_Lw : begin DP_Hazards <= HAZ_Lw; DP_Exceptions <= EXC_Lw; end
|
| 336 |
|
|
Op_Lwl : begin DP_Hazards <= HAZ_Lwl; DP_Exceptions <= EXC_Lwl; end
|
| 337 |
|
|
Op_Lwr : begin DP_Hazards <= HAZ_Lwr; DP_Exceptions <= EXC_Lwr; end
|
| 338 |
|
|
Op_Sb : begin DP_Hazards <= HAZ_Sb; DP_Exceptions <= EXC_Sb; end
|
| 339 |
|
|
Op_Sc : begin DP_Hazards <= HAZ_Sc; DP_Exceptions <= EXC_Sc; end
|
| 340 |
|
|
Op_Sh : begin DP_Hazards <= HAZ_Sh; DP_Exceptions <= EXC_Sh; end
|
| 341 |
|
|
Op_Sw : begin DP_Hazards <= HAZ_Sw; DP_Exceptions <= EXC_Sw; end
|
| 342 |
|
|
Op_Swl : begin DP_Hazards <= HAZ_Swl; DP_Exceptions <= EXC_Swl; end
|
| 343 |
|
|
Op_Swr : begin DP_Hazards <= HAZ_Swr; DP_Exceptions <= EXC_Swr; end
|
| 344 |
|
|
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
|
| 345 |
|
|
endcase
|
| 346 |
|
|
end
|
| 347 |
2 |
ayersg |
|
| 348 |
3 |
ayersg |
// ALU Assignment
|
| 349 |
|
|
always @(*) begin
|
| 350 |
|
|
if (ID_Stall)
|
| 351 |
|
|
ALUOp <= AluOp_Addu; // Any Op that doesn't write HILO or cause exceptions
|
| 352 |
|
|
else begin
|
| 353 |
|
|
case (OpCode)
|
| 354 |
|
|
Op_Type_R :
|
| 355 |
|
|
begin
|
| 356 |
|
|
case (Funct)
|
| 357 |
|
|
Funct_Add : ALUOp <= AluOp_Add;
|
| 358 |
|
|
Funct_Addu : ALUOp <= AluOp_Addu;
|
| 359 |
|
|
Funct_And : ALUOp <= AluOp_And;
|
| 360 |
|
|
Funct_Div : ALUOp <= AluOp_Div;
|
| 361 |
|
|
Funct_Divu : ALUOp <= AluOp_Divu;
|
| 362 |
|
|
Funct_Jalr : ALUOp <= AluOp_Addu;
|
| 363 |
|
|
Funct_Mfhi : ALUOp <= AluOp_Mfhi;
|
| 364 |
|
|
Funct_Mflo : ALUOp <= AluOp_Mflo;
|
| 365 |
|
|
Funct_Movn : ALUOp <= AluOp_Addu;
|
| 366 |
|
|
Funct_Movz : ALUOp <= AluOp_Addu;
|
| 367 |
|
|
Funct_Mthi : ALUOp <= AluOp_Mthi;
|
| 368 |
|
|
Funct_Mtlo : ALUOp <= AluOp_Mtlo;
|
| 369 |
|
|
Funct_Mult : ALUOp <= AluOp_Mult;
|
| 370 |
|
|
Funct_Multu : ALUOp <= AluOp_Multu;
|
| 371 |
|
|
Funct_Nor : ALUOp <= AluOp_Nor;
|
| 372 |
|
|
Funct_Or : ALUOp <= AluOp_Or;
|
| 373 |
|
|
Funct_Sll : ALUOp <= AluOp_Sll;
|
| 374 |
|
|
Funct_Sllv : ALUOp <= AluOp_Sllv;
|
| 375 |
|
|
Funct_Slt : ALUOp <= AluOp_Slt;
|
| 376 |
|
|
Funct_Sltu : ALUOp <= AluOp_Sltu;
|
| 377 |
|
|
Funct_Sra : ALUOp <= AluOp_Sra;
|
| 378 |
|
|
Funct_Srav : ALUOp <= AluOp_Srav;
|
| 379 |
|
|
Funct_Srl : ALUOp <= AluOp_Srl;
|
| 380 |
|
|
Funct_Srlv : ALUOp <= AluOp_Srlv;
|
| 381 |
|
|
Funct_Sub : ALUOp <= AluOp_Sub;
|
| 382 |
|
|
Funct_Subu : ALUOp <= AluOp_Subu;
|
| 383 |
2 |
ayersg |
Funct_Syscall : ALUOp <= AluOp_Addu;
|
| 384 |
|
|
Funct_Teq : ALUOp <= AluOp_Subu;
|
| 385 |
3 |
ayersg |
Funct_Tge : ALUOp <= AluOp_Slt;
|
| 386 |
|
|
Funct_Tgeu : ALUOp <= AluOp_Sltu;
|
| 387 |
|
|
Funct_Tlt : ALUOp <= AluOp_Slt;
|
| 388 |
|
|
Funct_Tltu : ALUOp <= AluOp_Sltu;
|
| 389 |
|
|
Funct_Tne : ALUOp <= AluOp_Subu;
|
| 390 |
|
|
Funct_Xor : ALUOp <= AluOp_Xor;
|
| 391 |
|
|
default : ALUOp <= AluOp_Addu;
|
| 392 |
|
|
endcase
|
| 393 |
|
|
end
|
| 394 |
|
|
Op_Type_R2 :
|
| 395 |
|
|
begin
|
| 396 |
|
|
case (Funct)
|
| 397 |
|
|
Funct_Clo : ALUOp <= AluOp_Clo;
|
| 398 |
|
|
Funct_Clz : ALUOp <= AluOp_Clz;
|
| 399 |
|
|
Funct_Madd : ALUOp <= AluOp_Madd;
|
| 400 |
|
|
Funct_Maddu : ALUOp <= AluOp_Maddu;
|
| 401 |
|
|
Funct_Msub : ALUOp <= AluOp_Msub;
|
| 402 |
|
|
Funct_Msubu : ALUOp <= AluOp_Msubu;
|
| 403 |
|
|
Funct_Mul : ALUOp <= AluOp_Mul;
|
| 404 |
|
|
default : ALUOp <= AluOp_Addu;
|
| 405 |
|
|
endcase
|
| 406 |
|
|
end
|
| 407 |
2 |
ayersg |
Op_Type_BI :
|
| 408 |
|
|
begin
|
| 409 |
|
|
case (Rt)
|
| 410 |
3 |
ayersg |
OpRt_Teqi : ALUOp <= AluOp_Subu;
|
| 411 |
|
|
OpRt_Tgei : ALUOp <= AluOp_Slt;
|
| 412 |
|
|
OpRt_Tgeiu : ALUOp <= AluOp_Sltu;
|
| 413 |
|
|
OpRt_Tlti : ALUOp <= AluOp_Slt;
|
| 414 |
|
|
OpRt_Tltiu : ALUOp <= AluOp_Sltu;
|
| 415 |
|
|
OpRt_Tnei : ALUOp <= AluOp_Subu;
|
| 416 |
|
|
default : ALUOp <= AluOp_Addu; // Branches don't matter.
|
| 417 |
|
|
endcase
|
| 418 |
2 |
ayersg |
end
|
| 419 |
|
|
Op_Type_CP0 : ALUOp <= AluOp_Addu;
|
| 420 |
3 |
ayersg |
Op_Addi : ALUOp <= AluOp_Add;
|
| 421 |
|
|
Op_Addiu : ALUOp <= AluOp_Addu;
|
| 422 |
|
|
Op_Andi : ALUOp <= AluOp_And;
|
| 423 |
|
|
Op_Jal : ALUOp <= AluOp_Addu;
|
| 424 |
|
|
Op_Lb : ALUOp <= AluOp_Addu;
|
| 425 |
|
|
Op_Lbu : ALUOp <= AluOp_Addu;
|
| 426 |
|
|
Op_Lh : ALUOp <= AluOp_Addu;
|
| 427 |
|
|
Op_Lhu : ALUOp <= AluOp_Addu;
|
| 428 |
|
|
Op_Ll : ALUOp <= AluOp_Addu;
|
| 429 |
|
|
Op_Lui : ALUOp <= AluOp_Sllc;
|
| 430 |
|
|
Op_Lw : ALUOp <= AluOp_Addu;
|
| 431 |
|
|
Op_Lwl : ALUOp <= AluOp_Addu;
|
| 432 |
|
|
Op_Lwr : ALUOp <= AluOp_Addu;
|
| 433 |
|
|
Op_Ori : ALUOp <= AluOp_Or;
|
| 434 |
|
|
Op_Sb : ALUOp <= AluOp_Addu;
|
| 435 |
|
|
Op_Sc : ALUOp <= AluOp_Addu; // XXX Needs HW implement
|
| 436 |
|
|
Op_Sh : ALUOp <= AluOp_Addu;
|
| 437 |
|
|
Op_Slti : ALUOp <= AluOp_Slt;
|
| 438 |
|
|
Op_Sltiu : ALUOp <= AluOp_Sltu;
|
| 439 |
|
|
Op_Sw : ALUOp <= AluOp_Addu;
|
| 440 |
|
|
Op_Swl : ALUOp <= AluOp_Addu;
|
| 441 |
|
|
Op_Swr : ALUOp <= AluOp_Addu;
|
| 442 |
|
|
Op_Xori : ALUOp <= AluOp_Xor;
|
| 443 |
|
|
default : ALUOp <= AluOp_Addu;
|
| 444 |
|
|
endcase
|
| 445 |
|
|
end
|
| 446 |
|
|
end
|
| 447 |
2 |
ayersg |
|
| 448 |
|
|
/***
|
| 449 |
|
|
These remaining options cover portions of the datapath that are not
|
| 450 |
|
|
controlled directly by the datapath bits. Note that some refer to bits of
|
| 451 |
|
|
the opcode or other fields, which breaks the otherwise fully-abstracted view
|
| 452 |
|
|
of instruction encodings. Make sure when adding custom instructions that
|
| 453 |
|
|
no false positives/negatives are generated here.
|
| 454 |
|
|
***/
|
| 455 |
|
|
|
| 456 |
|
|
// Branch Detection: Options are mutually exclusive.
|
| 457 |
|
|
assign Branch_EQ = OpCode[2] & ~OpCode[1] & ~OpCode[0] & Cmp_EQ;
|
| 458 |
|
|
assign Branch_GTZ = OpCode[2] & OpCode[1] & OpCode[0] & Cmp_GZ;
|
| 459 |
|
|
assign Branch_LEZ = OpCode[2] & OpCode[1] & ~OpCode[0] & Cmp_LEZ;
|
| 460 |
|
|
assign Branch_NEQ = OpCode[2] & ~OpCode[1] & OpCode[0] & ~Cmp_EQ;
|
| 461 |
|
|
assign Branch_GEZ = ~OpCode[2] & Rt[0] & Cmp_GEZ;
|
| 462 |
|
|
assign Branch_LTZ = ~OpCode[2] & ~Rt[0] & Cmp_LZ;
|
| 463 |
|
|
|
| 464 |
|
|
assign Branch = Branch_EQ | Branch_GTZ | Branch_LEZ | Branch_NEQ | Branch_GEZ | Branch_LTZ;
|
| 465 |
|
|
assign PCSrc[1] = (Datapath[15] & ~Datapath[14]) ? Branch : Datapath[15];
|
| 466 |
|
|
|
| 467 |
|
|
/* In MIPS32, all Branch and Jump operations execute the Branch Delay Slot,
|
| 468 |
3 |
ayersg |
* or next instruction, regardless if the branch is taken or not. The exception
|
| 469 |
|
|
* is the "Branch Likely" instruction group. These are deprecated, however, and not
|
| 470 |
|
|
* implemented here. "IF_Flush" is defined to allow for the cancelation of a
|
| 471 |
|
|
* Branch Delay Slot should these be implemented later.
|
| 472 |
|
|
*/
|
| 473 |
|
|
assign IF_Flush = 0;
|
| 474 |
2 |
ayersg |
|
| 475 |
3 |
ayersg |
// Indicator that next instruction is a Branch Delay Slot.
|
| 476 |
|
|
assign NextIsDelay = Datapath[15] | Datapath[14];
|
| 477 |
2 |
ayersg |
|
| 478 |
|
|
// Sign- or Zero-Extension Control. The only ops that require zero-extension are
|
| 479 |
|
|
// Andi, Ori, and Xori. The following also zero-extends 'lui', however it does not alter the effect of lui.
|
| 480 |
|
|
assign SignExtend = (OpCode[5:2] != 4'b0011);
|
| 481 |
|
|
|
| 482 |
|
|
// Move Conditional
|
| 483 |
|
|
assign Movn = Movc & Funct[0];
|
| 484 |
|
|
assign Movz = Movc & ~Funct[0];
|
| 485 |
3 |
ayersg |
|
| 486 |
|
|
// Coprocessor 0 (Mfc0, Mtc0) control signals.
|
| 487 |
2 |
ayersg |
assign Mfc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MF));
|
| 488 |
3 |
ayersg |
assign Mtc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MT));
|
| 489 |
2 |
ayersg |
assign Eret = ((OpCode == Op_Type_CP0) && (Rs == OpRs_ERET) && (Funct == Funct_ERET));
|
| 490 |
|
|
|
| 491 |
|
|
// Coprocessor 1,2,3 accesses (not implemented)
|
| 492 |
|
|
assign CP1 = (OpCode == Op_Type_CP1);
|
| 493 |
|
|
assign CP2 = (OpCode == Op_Type_CP2);
|
| 494 |
|
|
assign CP3 = (OpCode == Op_Type_CP3);
|
| 495 |
|
|
|
| 496 |
|
|
// Exceptions found in ID
|
| 497 |
|
|
assign EXC_Sys = ((OpCode == Op_Type_R) && (Funct == Funct_Syscall));
|
| 498 |
|
|
assign EXC_Bp = ((OpCode == Op_Type_R) && (Funct == Funct_Break));
|
| 499 |
|
|
|
| 500 |
|
|
// Unaligned Memory Accesses (lwl, lwr, swl, swr)
|
| 501 |
|
|
assign Unaligned_Mem = OpCode[5] & ~OpCode[4] & OpCode[1] & ~OpCode[0];
|
| 502 |
|
|
assign Left = Unaligned_Mem & ~OpCode[2];
|
| 503 |
|
|
assign Right = Unaligned_Mem & OpCode[2];
|
| 504 |
|
|
|
| 505 |
|
|
// TODO: Reserved Instruction Exception must still be implemented
|
| 506 |
|
|
assign EXC_RI = 0;
|
| 507 |
|
|
|
| 508 |
|
|
endmodule
|
| 509 |
3 |
ayersg |
|
