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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [Common/] [FIFO_Clear.v] - Blame information for rev 3

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`timescale 1ns / 1ps
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/*
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 * File         : FIFO_Clear.v
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 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   4-Apr-2010   GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   A synchronous FIFO of variable data width and depth. 'enQ' is ignored when
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 *   the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and
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 *   'deQ' are asserted simultaneously, the FIFO is unchanged and the output data
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 *   is the same as the input data.
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 *
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 *   This FIFO is "First word fall-through" meaning data can be read without
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 *   asserting 'deQ' by merely supplying an address. However, when 'deQ' is
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 *   asserted, the data is "removed" from the FIFO and one location is freed.
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 *   If the FIFO is empty and 'enQ' and 'deQ' are not asserted simultaneously,
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 *   the output data will be 0s.
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 *
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 * Variation:
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 *   - Input 'clear' empties the FIFO exactly like 'reset' does.
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 */
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module FIFO_Clear(clock, reset, clear, enQ, deQ, data_in, data_out, empty, full);
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   parameter DATA_WIDTH = 8;
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   parameter ADDR_WIDTH = 8;
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   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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   input clock;
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   input reset;
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   input clear;
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   input enQ;
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   input deQ;
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   input [(DATA_WIDTH-1):0] data_in;
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   output [(DATA_WIDTH-1):0] data_out;
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   output empty;
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   output full;
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   reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr;     // Addresses for reading from and writing to internal memory
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   reg [(ADDR_WIDTH):0] count;                  // How many elements are in the FIFO (0->256)
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   assign empty = (count == 0);
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   assign full = (count == (1 << ADDR_WIDTH));
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   wire [(DATA_WIDTH-1):0] w_data_out;
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   assign data_out = (empty) ? ((enQ & deQ) ? data_in : 0) : w_data_out;
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   wire w_enQ = (full) ? 0 : enQ;   // Mask 'enQ' when the FIFO is full
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   wire w_deQ = (empty) ? 0 : deQ;  // Mask 'deQ' when the FIFO is empty
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   always @(posedge clock) begin
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      if (reset | clear) begin
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         enQ_ptr <= 0;
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         deQ_ptr <= 0;
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         count <= 0;
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      end
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      else begin
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         enQ_ptr <= (w_enQ) ? enQ_ptr +1 : enQ_ptr;
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         deQ_ptr <= (w_deQ) ? deQ_ptr +1 : deQ_ptr;
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         count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count +1 : count -1);
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      end
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   end
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   SRAM #(
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      .DATA_WIDTH (DATA_WIDTH),
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      .ADDR_WIDTH (ADDR_WIDTH),
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      .RAM_DEPTH  (RAM_DEPTH))
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      RAM(
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      .clock   (clock),
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      .wEn     (w_enQ),
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      .rAddr   (deQ_ptr),
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      .wAddr   (enQ_ptr),
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      .dIn     (data_in),
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      .dOut    (w_data_out)
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   );
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endmodule
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