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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [Common/] [SRAM.v] - Blame information for rev 3

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1 2 ayersg
`timescale 1ns / 1ps
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/*
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 * File         : SRAM.v
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 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   4-Apr-2010   GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   A simple memory of varying width and depth. Reads are asynchronous,
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 *   writes are synchronous. Defaults to 8-bit width and 8-bit depth for
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 *   a total of 8-bit * 256 entry or 256 bytes of storage.
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 */
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module SRAM(clock, wEn, rAddr, wAddr, dIn, dOut);
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    parameter DATA_WIDTH = 8;
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    parameter ADDR_WIDTH = 8;
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    parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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    input clock;
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    input wEn;
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    input [(ADDR_WIDTH-1):0] rAddr;
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    input [(ADDR_WIDTH-1):0] wAddr;
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    input [(DATA_WIDTH-1):0] dIn;
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    output [(DATA_WIDTH-1):0] dOut;
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    reg [(DATA_WIDTH-1):0] mem [0:(RAM_DEPTH-1)];
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    assign dOut = mem[rAddr];
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    always @(posedge clock) begin
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        if (wEn) mem[wAddr] <= dIn;
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    end
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endmodule
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