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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [LCD/] [LCD.v] - Blame information for rev 2

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1 2 ayersg 
`timescale 1ns / 1ps
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/*
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 * File         : LCD.v
4 
 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   16-Jun-2012  GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   The top-level LCD controller. This module bridges the underlying 16x2 LCD
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 *   hardware controller and the data memory bus. It caches 32 bytes of data which
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 *   each correspond to a location on the LCD screen. The LCD screen is continuously
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 *   updated with these 32 bytes as quickly as possible.
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 */
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module LCD(
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    input  clock_100MHz,
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    input  clock_Mem,
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    input  reset,
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    input  [2:0] address,
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    input  [31:0] data,
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    input  [3:0] writeEnable,
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    output reg ack,
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    output [6:0] LCD
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    );
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    localparam [5:0]    INIT_1=1, INIT_2=2, INIT_3=3, INIT_4=4, LOC_0=5, LOC_1=6, LOC_2=7,
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                        LOC_3=8, LOC_4=9, LOC_5=10, LOC_6=11, LOC_7=12, LOC_8=13, LOC_9=14, LOC_10=15,
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                        LOC_11=16, LOC_12=17, LOC_13=18, LOC_14=19, LOC_15=20, LOC_16=21, LOC_17=22,
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                        LOC_18=23, LOC_19=24, LOC_20=25, LOC_21=26, LOC_22=27, LOC_23=28, LOC_24=29,
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                        LOC_25=30, LOC_26=31, LOC_27=32, LOC_28=33, LOC_29=34, LOC_30=35, LOC_31=36,
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                        LINE_2=37, HOME=38;
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    wire clock = clock_100MHz;
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    reg [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
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    reg [5:0] state;
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    wire bell;
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    // LCD driver signals
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    reg  [8:0] lcd_command;
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    reg  lcd_write;
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    wire lcd_ack;
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    assign bell = ~(lcd_write | lcd_ack);
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    always @(posedge clock_Mem) begin
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        ack <= (reset) ? 0 : (writeEnable != 4'b0000);
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    end
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    /* 32 bytes of LCD memory held on the FPGA fabric. The following is BIG ENDIAN */
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    always @(posedge clock_Mem) begin
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        a0[31:24] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[3]) ? data[31:24] : a0[31:24]);
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        a0[23:16] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[2]) ? data[23:16] : a0[23:16]);
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        a0[15:8]  <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[1]) ? data[15:8]  : a0[15:8]);
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        a0[7:0]   <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[0]) ? data[7:0]   : a0[7:0]);
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        a1[31:24] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[3]) ? data[31:24] : a1[31:24]);
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        a1[23:16] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[2]) ? data[23:16] : a1[23:16]);
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        a1[15:8]  <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[1]) ? data[15:8]  : a1[15:8]);
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        a1[7:0]   <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[0]) ? data[7:0]   : a1[7:0]);
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        a2[31:24] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[3]) ? data[31:24] : a2[31:24]);
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        a2[23:16] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[2]) ? data[23:16] : a2[23:16]);
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        a2[15:8]  <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[1]) ? data[15:8]  : a2[15:8]);
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        a2[7:0]   <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[0]) ? data[7:0]   : a2[7:0]);
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        a3[31:24] <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[3]) ? data[31:24] : a3[31:24]);
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        a3[23:16] <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[2]) ? data[23:16] : a3[23:16]);
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        a3[15:8]  <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[1]) ? data[15:8]  : a3[15:8]);
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        a3[7:0]   <= (reset) ? 8'h21 : (((address == 3'd3) & writeEnable[0]) ? data[7:0]   : a3[7:0]);
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        a4[31:24] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[3]) ? data[31:24] : a4[31:24]);
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        a4[23:16] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[2]) ? data[23:16] : a4[23:16]);
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        a4[15:8]  <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[1]) ? data[15:8]  : a4[15:8]);
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        a4[7:0]   <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[0]) ? data[7:0]   : a4[7:0]);
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        a5[31:24] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[3]) ? data[31:24] : a5[31:24]);
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        a5[23:16] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[2]) ? data[23:16] : a5[23:16]);
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        a5[15:8]  <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[1]) ? data[15:8]  : a5[15:8]);
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        a5[7:0]   <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[0]) ? data[7:0]   : a5[7:0]);
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        a6[31:24] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[3]) ? data[31:24] : a6[31:24]);
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        a6[23:16] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[2]) ? data[23:16] : a6[23:16]);
83 
        a6[15:8]  <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[1]) ? data[15:8]  : a6[15:8]);
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        a6[7:0]   <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[0]) ? data[7:0]   : a6[7:0]);
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        a7[31:24] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[3]) ? data[31:24] : a7[31:24]);
86 
        a7[23:16] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[2]) ? data[23:16] : a7[23:16]);
87 
        a7[15:8]  <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[1]) ? data[15:8]  : a7[15:8]);
88 
        a7[7:0]   <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[0]) ? data[7:0]   : a7[7:0]);
89 
    end
90 
 
91 
    /* The LCD continuously writes the memory locations as fast as possible */
92 
    always @(posedge clock) begin
93 
        lcd_write <= (reset) ? 1 : ~lcd_ack;
94 
    end
95 
 
96 
    /* LCD commands for initialization and looping through 32 locations */
97 
    always @(*) begin
98 
        case (state)
99 
            INIT_1  : lcd_command <= 9'b000101000;      // 0x28 'Function Set' Not sure what this means
100 
            INIT_2  : lcd_command <= 9'b000000110;      // Entry mode: set auto increment and no shifting
101 
            INIT_3  : lcd_command <= 9'b000001100;      // Turn LCD on, disable cursor/blinking
102 
            INIT_4  : lcd_command <= 9'b000000001;      // Clear display
103 
            LOC_0   : lcd_command <= {1'b1, a0[31:24]};
104 
            LOC_1   : lcd_command <= {1'b1, a0[23:16]};
105 
            LOC_2   : lcd_command <= {1'b1, a0[15:8]};
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            LOC_3   : lcd_command <= {1'b1, a0[7:0]};
107 
            LOC_4   : lcd_command <= {1'b1, a1[31:24]};
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            LOC_5   : lcd_command <= {1'b1, a1[23:16]};
109 
            LOC_6   : lcd_command <= {1'b1, a1[15:8]};
110 
            LOC_7   : lcd_command <= {1'b1, a1[7:0]};
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            LOC_8   : lcd_command <= {1'b1, a2[31:24]};
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            LOC_9   : lcd_command <= {1'b1, a2[23:16]};
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            LOC_10  : lcd_command <= {1'b1, a2[15:8]};
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            LOC_11  : lcd_command <= {1'b1, a2[7:0]};
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            LOC_12  : lcd_command <= {1'b1, a3[31:24]};
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            LOC_13  : lcd_command <= {1'b1, a3[23:16]};
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            LOC_14  : lcd_command <= {1'b1, a3[15:8]};
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            LOC_15  : lcd_command <= {1'b1, a3[7:0]};
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            LINE_2  : lcd_command <= 9'b011000000;
120 
            LOC_16  : lcd_command <= {1'b1, a4[31:24]};
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            LOC_17  : lcd_command <= {1'b1, a4[23:16]};
122 
            LOC_18  : lcd_command <= {1'b1, a4[15:8]};
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            LOC_19  : lcd_command <= {1'b1, a4[7:0]};
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            LOC_20  : lcd_command <= {1'b1, a5[31:24]};
125 
            LOC_21  : lcd_command <= {1'b1, a5[23:16]};
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            LOC_22  : lcd_command <= {1'b1, a5[15:8]};
127 
            LOC_23  : lcd_command <= {1'b1, a5[7:0]};
128 
            LOC_24  : lcd_command <= {1'b1, a6[31:24]};
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            LOC_25  : lcd_command <= {1'b1, a6[23:16]};
130 
            LOC_26  : lcd_command <= {1'b1, a6[15:8]};
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            LOC_27  : lcd_command <= {1'b1, a6[7:0]};
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            LOC_28  : lcd_command <= {1'b1, a7[31:24]};
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            LOC_29  : lcd_command <= {1'b1, a7[23:16]};
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            LOC_30  : lcd_command <= {1'b1, a7[15:8]};
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            LOC_31  : lcd_command <= {1'b1, a7[7:0]};
136 
            HOME    : lcd_command <= 9'b010000000;
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            default : lcd_command <= 9'bx_xxxx_xxxx;
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        endcase
139 
    end
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141 
    /* Main state machine */
142 
    always @(posedge clock) begin
143 
        if (reset) begin
144 
            state <= INIT_1;
145 
        end
146 
        else begin
147 
            case (state)
148 
                INIT_1  : state <= (bell) ? INIT_2 : INIT_1;
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                INIT_2  : state <= (bell) ? INIT_3 : INIT_2;
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                INIT_3  : state <= (bell) ? INIT_4 : INIT_3;
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                INIT_4  : state <= (bell) ? LOC_0  : INIT_4;
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                LOC_0   : state <= (bell) ? LOC_1  : LOC_0;
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                LOC_1   : state <= (bell) ? LOC_2  : LOC_1;
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                LOC_2   : state <= (bell) ? LOC_3  : LOC_2;
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                LOC_3   : state <= (bell) ? LOC_4  : LOC_3;
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                LOC_4   : state <= (bell) ? LOC_5  : LOC_4;
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                LOC_5   : state <= (bell) ? LOC_6  : LOC_5;
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                LOC_6   : state <= (bell) ? LOC_7  : LOC_6;
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                LOC_7   : state <= (bell) ? LOC_8  : LOC_7;
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                LOC_8   : state <= (bell) ? LOC_9  : LOC_8;
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                LOC_9   : state <= (bell) ? LOC_10 : LOC_9;
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                LOC_10  : state <= (bell) ? LOC_11 : LOC_10;
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                LOC_11  : state <= (bell) ? LOC_12 : LOC_11;
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                LOC_12  : state <= (bell) ? LOC_13 : LOC_12;
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                LOC_13  : state <= (bell) ? LOC_14 : LOC_13;
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                LOC_14  : state <= (bell) ? LOC_15 : LOC_14;
167 
                LOC_15  : state <= (bell) ? LINE_2 : LOC_15;
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                LINE_2  : state <= (bell) ? LOC_16 : LINE_2;
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                LOC_16  : state <= (bell) ? LOC_17 : LOC_16;
170 
                LOC_17  : state <= (bell) ? LOC_18 : LOC_17;
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                LOC_18  : state <= (bell) ? LOC_19 : LOC_18;
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                LOC_19  : state <= (bell) ? LOC_20 : LOC_19;
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                LOC_20  : state <= (bell) ? LOC_21 : LOC_20;
174 
                LOC_21  : state <= (bell) ? LOC_22 : LOC_21;
175 
                LOC_22  : state <= (bell) ? LOC_23 : LOC_22;
176 
                LOC_23  : state <= (bell) ? LOC_24 : LOC_23;
177 
                LOC_24  : state <= (bell) ? LOC_25 : LOC_24;
178 
                LOC_25  : state <= (bell) ? LOC_26 : LOC_25;
179 
                LOC_26  : state <= (bell) ? LOC_27 : LOC_26;
180 
                LOC_27  : state <= (bell) ? LOC_28 : LOC_27;
181 
                LOC_28  : state <= (bell) ? LOC_29 : LOC_28;
182 
                LOC_29  : state <= (bell) ? LOC_30 : LOC_29;
183 
                LOC_30  : state <= (bell) ? LOC_31 : LOC_30;
184 
                LOC_31  : state <= (bell) ? HOME   : LOC_31;
185 
                HOME    : state <= (bell) ? LOC_0  : HOME;
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                default : state <= 6'bxxxxxx;
187 
            endcase
188 
        end
189 
    end
190 
 
191 
    lcd_ctrl LCD_Driver (
192 
        .clock    (clock),
193 
        .reset    (reset),
194 
        .command  (lcd_command),
195 
        .write    (lcd_write),
196 
        .ack      (lcd_ack),
197 
        .LCD_D    (LCD[6:3]),
198 
        .LCD_E    (LCD[2]),
199 
        .LCD_RS   (LCD[1]),
200 
        .LCD_RW   (LCD[0])
201 
    );
202 
 
203 
endmodule

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