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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [LCD/] [lcd_ctrl.v] - Blame information for rev 2

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1 2 ayersg 
`timescale 1ns / 1ps
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/*
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 * File         : lcd_ctrl.v
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 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   16-Jun-2011  GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   A controller for the common 16x2-character LCD screen based on the
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 *   Sitronix ST7066U, Samsung S6A0069X / KS0066U, Hitachi HD44780, SMOS SED1278,
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 *   or other compatible device. This controller uses a 4-bit data bus, is write-only,
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 *   and requires a total of 7 output pins to the LCD. The timing must be adjusted for
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 *   different input clock frequencies where noted. The primary version is based on a
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 *   100 MHz clock.
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 */
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module lcd_ctrl(
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    input  clock,
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    input  reset,
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    input  [8:0] command,
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    input  write,
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    output reg ack,
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    //---------------------------------
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    output reg [3:0] LCD_D, // 4-bit LCD data bus
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    output reg LCD_E,       // Enable
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    output LCD_RS,          // Register Select (0->Register; 1->Data)
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    output LCD_RW           // Read/Write (0->Write; 1->Read)
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    );
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    localparam [4:0]    INIT_1=1, INIT_2=2, INIT_3=3, INIT_4=4, INIT_5=5, INIT_6=6, INIT_7=7, INIT_8=8,
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                        CMD_WAIT=9, NOP=10, U_SETUP=11, U_ENAB=12, U_HOLD=13, UL_WAIT=14, L_SETUP=15,
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                        L_ENAB=16, L_HOLD=17;
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    reg  [18:0] count;
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    reg  [18:0] compare;
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    reg  [4:0] state;
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    wire bell;
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    wire long_instr;
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    assign LCD_RW = 0;                  // There is no reason to read from the LCD screen.
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    assign LCD_RS = command[8];
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    assign bell = (count == compare);
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    assign long_instr = ((command == 9'b0_0000_0001) || (command[8:1] == 8'b0_0000_001));
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    /* The count register increments until it equals 'compare' */
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    always @(posedge clock) begin
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        count <= (reset | bell) ? 19'b0 : count + 1;
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    end
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    /* Time delays for various states */
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    always @(*) begin
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        case (state)
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            INIT_1   : compare <= 19'd410000;  // 15ms (4.1ms OK due to power-up delay)
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            INIT_2   : compare <= 19'd24;      // 240 ns
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            INIT_3   : compare <= 19'd410000;  // 4.1 ms
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            INIT_4   : compare <= 19'd24;      // 240 ns
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            INIT_5   : compare <= 19'd10000;   // 100 us or longer
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            INIT_6   : compare <= 19'd24;      // 240 ns
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            INIT_7   : compare <= 19'd4000;    // 40  us or longer
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            INIT_8   : compare <= 19'd24;      // 240 ns
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            CMD_WAIT : compare <= (long_instr) ? 19'd164000 : 19'd4000;   // 40 us or 1.64 ms
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            NOP      : compare <= 19'hxxxxx;
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            U_SETUP  : compare <= 19'd4;       // 40  ns
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            U_ENAB   : compare <= 19'd23;      // 230 ns
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            U_HOLD   : compare <= 19'd1;       // 10  ns
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            UL_WAIT  : compare <= 19'd100;     // 1   us
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            L_SETUP  : compare <= 19'd4;       // 40  ns
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            L_ENAB   : compare <= 19'd23;      // 230 ns
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            L_HOLD   : compare <= 19'd1;       // 10  ns
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            default  : compare <= 19'hxxxxx;
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        endcase
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    end
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    /* The main state machine */
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    always @(posedge clock) begin
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        if (reset) begin
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            state <= INIT_1;
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        end
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        else begin
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            case (state)
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                INIT_1   : state <= (bell)  ? INIT_2   : INIT_1;
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                INIT_2   : state <= (bell)  ? INIT_3   : INIT_2;
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                INIT_3   : state <= (bell)  ? INIT_4   : INIT_3;
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                INIT_4   : state <= (bell)  ? INIT_5   : INIT_4;
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                INIT_5   : state <= (bell)  ? INIT_6   : INIT_5;
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                INIT_6   : state <= (bell)  ? INIT_7   : INIT_6;
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                INIT_7   : state <= (bell)  ? INIT_8   : INIT_7;
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                INIT_8   : state <= (bell)  ? CMD_WAIT : INIT_8;
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                CMD_WAIT : state <= (bell)  ? NOP      : CMD_WAIT;
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                NOP      : state <= (write & ~ack) ? U_SETUP  : NOP;
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                U_SETUP  : state <= (bell)  ? U_ENAB   : U_SETUP;
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                U_ENAB   : state <= (bell)  ? U_HOLD   : U_ENAB;
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                U_HOLD   : state <= (bell)  ? UL_WAIT  : U_HOLD;
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                UL_WAIT  : state <= (bell)  ? L_SETUP  : UL_WAIT;
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                L_SETUP  : state <= (bell)  ? L_ENAB   : L_SETUP;
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                L_ENAB   : state <= (bell)  ? L_HOLD   : L_ENAB;
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                L_HOLD   : state <= (bell)  ? CMD_WAIT : L_HOLD;
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                default  : state <= 5'bxxxxx;
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            endcase
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        end
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    end
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    /* Combinatorial enable and data assignments */
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    always @(*) begin
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        case (state)
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            INIT_1   : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            INIT_2   : begin LCD_E <= 0; LCD_D <= 4'b0011; end
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            INIT_3   : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            INIT_4   : begin LCD_E <= 1; LCD_D <= 4'b0011; end
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            INIT_5   : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            INIT_6   : begin LCD_E <= 1; LCD_D <= 4'b0011; end
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            INIT_7   : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            INIT_8   : begin LCD_E <= 1; LCD_D <= 4'b0010; end
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            CMD_WAIT : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            NOP      : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            U_SETUP  : begin LCD_E <= 0; LCD_D <= command[7:4]; end
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            U_ENAB   : begin LCD_E <= 1; LCD_D <= command[7:4]; end
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            U_HOLD   : begin LCD_E <= 0; LCD_D <= command[7:4]; end
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            UL_WAIT  : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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            L_SETUP  : begin LCD_E <= 0; LCD_D <= command[3:0]; end
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            L_ENAB   : begin LCD_E <= 1; LCD_D <= command[3:0]; end
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            L_HOLD   : begin LCD_E <= 0; LCD_D <= command[3:0]; end
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            default  : begin LCD_E <= 0; LCD_D <= 4'b0000; end
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        endcase
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    end
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    /* Full 4-way Handshake */
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    always @(posedge clock) begin
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        ack <= (reset | ~write) ? 0 : (((state == L_HOLD) && (bell == 1'b1)) ? 1 : ack);
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    end
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endmodule

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