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`timescale 1ns / 1ps
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/*
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* File : IDEX_Stage.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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* Modification History:
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* Rev Date Initials Description of Change
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* 1.0 9-Jun-2011 GEA Initial design.
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* 2.0 26-Jul-2012 GEA Many updates have been made.
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*
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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*
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* Description:
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* The Pipeline Register to bridge the Instruction Decode
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* and Execute stages.
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*/
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module IDEX_Stage(
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input clock,
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input reset,
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input ID_Flush,
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input ID_Stall,
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input EX_Stall,
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// Control Signals
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input ID_Link,
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input ID_RegDst,
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input ID_ALUSrcImm,
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input [4:0] ID_ALUOp,
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input ID_Movn,
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input ID_Movz,
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input ID_LLSC,
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input ID_MemRead,
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input ID_MemWrite,
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input ID_MemByte,
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input ID_MemHalf,
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input ID_MemSignExtend,
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input ID_Left,
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input ID_Right,
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input ID_RegWrite,
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input ID_MemtoReg,
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input ID_ReverseEndian,
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// Hazard & Forwarding
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input [4:0] ID_Rs,
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input [4:0] ID_Rt,
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input ID_WantRsByEX,
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input ID_NeedRsByEX,
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input ID_WantRtByEX,
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input ID_NeedRtByEX,
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// Exception Control/Info
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input ID_KernelMode,
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input [31:0] ID_RestartPC,
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input ID_IsBDS,
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input ID_Trap,
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input ID_TrapCond,
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input ID_EX_CanErr,
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input ID_M_CanErr,
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// Data Signals
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input [31:0] ID_ReadData1,
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input [31:0] ID_ReadData2,
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input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here
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// ----------------
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output reg EX_Link,
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output [1:0] EX_LinkRegDst,
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output reg EX_ALUSrcImm,
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output reg [4:0] EX_ALUOp,
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output reg EX_Movn,
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output reg EX_Movz,
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output reg EX_LLSC,
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output reg EX_MemRead,
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output reg EX_MemWrite,
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output reg EX_MemByte,
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output reg EX_MemHalf,
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output reg EX_MemSignExtend,
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output reg EX_Left,
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output reg EX_Right,
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output reg EX_RegWrite,
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output reg EX_MemtoReg,
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output reg EX_ReverseEndian,
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output reg [4:0] EX_Rs,
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output reg [4:0] EX_Rt,
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output reg EX_WantRsByEX,
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output reg EX_NeedRsByEX,
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output reg EX_WantRtByEX,
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output reg EX_NeedRtByEX,
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output reg EX_KernelMode,
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output reg [31:0] EX_RestartPC,
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output reg EX_IsBDS,
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output reg EX_Trap,
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output reg EX_TrapCond,
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output reg EX_EX_CanErr,
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output reg EX_M_CanErr,
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output reg [31:0] EX_ReadData1,
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output reg [31:0] EX_ReadData2,
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output [31:0] EX_SignExtImm,
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output [4:0] EX_Rd,
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output [4:0] EX_Shamt
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);
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/***
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The purpose of a pipeline register is to capture data from one pipeline stage
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and provide it to the next pipeline stage. This creates at least one clock cycle
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of delay, but reduces the combinatorial path length of signals which allows for
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higher clock speeds.
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All pipeline registers update unless the forward stage is stalled. When this occurs
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or when the current stage is being flushed, the forward stage will receive data that
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is effectively a NOP and causes nothing to happen throughout the remaining pipeline
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traversal. In other words:
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A stall masks all control signals to forward stages. A flush permanently clears
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control signals to forward stages (but not certain data for exception purposes).
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***/
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reg [16:0] EX_SignExtImm_pre;
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reg EX_RegDst;
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assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00);
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assign EX_Rd = EX_SignExtImm[15:11];
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assign EX_Shamt = EX_SignExtImm[10:6];
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assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]};
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always @(posedge clock) begin
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EX_Link <= (reset) ? 0 : ((EX_Stall) ? EX_Link : ID_Link);
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EX_RegDst <= (reset) ? 0 : ((EX_Stall) ? EX_RegDst : ID_RegDst);
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EX_ALUSrcImm <= (reset) ? 0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm);
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EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp));
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EX_Movn <= (reset) ? 0 : ((EX_Stall) ? EX_Movn : ID_Movn);
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EX_Movz <= (reset) ? 0 : ((EX_Stall) ? EX_Movz : ID_Movz);
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EX_LLSC <= (reset) ? 0 : ((EX_Stall) ? EX_LLSC : ID_LLSC);
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EX_MemRead <= (reset) ? 0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 0 : ID_MemRead));
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EX_MemWrite <= (reset) ? 0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 0 : ID_MemWrite));
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EX_MemByte <= (reset) ? 0 : ((EX_Stall) ? EX_MemByte : ID_MemByte);
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EX_MemHalf <= (reset) ? 0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf);
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EX_MemSignExtend <= (reset) ? 0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend);
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EX_Left <= (reset) ? 0 : ((EX_Stall) ? EX_Left : ID_Left);
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EX_Right <= (reset) ? 0 : ((EX_Stall) ? EX_Right : ID_Right);
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EX_RegWrite <= (reset) ? 0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 0 : ID_RegWrite));
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EX_MemtoReg <= (reset) ? 0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg);
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EX_ReverseEndian <= (reset) ? 0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian);
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EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC);
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EX_IsBDS <= (reset) ? 0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS);
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EX_Trap <= (reset) ? 0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 0 : ID_Trap));
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EX_TrapCond <= (reset) ? 0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond);
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EX_EX_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_EX_CanErr));
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EX_M_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_M_CanErr));
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EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1);
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EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2);
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EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm);
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EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs);
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EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt);
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EX_WantRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRsByEX));
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EX_NeedRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRsByEX));
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EX_WantRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRtByEX));
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EX_NeedRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRtByEX));
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EX_KernelMode <= (reset) ? 0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode);
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end
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endmodule
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