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`timescale 1ns / 1ps
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/*
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* File : Processor.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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* Modification History:
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* Rev Date Initials Description of Change
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* 1.0 23-Jul-2011 GEA Initial design.
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* 2.0 26-May-2012 GEA Release version with CP0.
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*
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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*
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* Description:
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* The top-level MIPS32 Processor. This file is mostly the instantiation
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* and wiring of the building blocks of the processor according to the
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* hardware design diagram. It contains very little logic itself.
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*/
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module Processor(
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input clock,
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input reset,
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input [4:0] Interrupts, // 5 general-purpose hardware interrupts
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input NMI, // Non-maskable interrupt
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// Data Memory Interface
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input [31:0] DataMem_In,
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input DataMem_Ready,
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output DataMem_Read,
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output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word.
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output [29:0] DataMem_Address, // Addresses are words, not bytes.
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output [31:0] DataMem_Out,
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// Instruction Memory Interface
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input [31:0] InstMem_In,
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output [29:0] InstMem_Address, // Addresses are words, not bytes.
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input InstMem_Ready,
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output InstMem_Read,
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output [7:0] IP // Pending interrupts (diagnostic)
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);
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`include "MIPS_Parameters.v"
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/*** MIPS Instruction and Components (ID Stage) ***/
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wire [31:0] Instruction;
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wire [5:0] OpCode = Instruction[31:26];
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wire [4:0] Rs = Instruction[25:21];
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wire [4:0] Rt = Instruction[20:16];
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wire [4:0] Rd = Instruction[15:11];
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wire [5:0] Funct = Instruction[5:0];
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wire [15:0] Immediate = Instruction[15:0];
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wire [25:0] JumpAddress = Instruction[25:0];
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wire [2:0] Cp0_Sel = Instruction[2:0];
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/*** IF (Instruction Fetch) Signals ***/
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wire IF_Stall, IF_Flush;
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wire IF_EXC_AdIF;
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wire IF_Exception_Stall;
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wire IF_Exception_Flush;
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wire IF_IsBDS;
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wire [31:0] IF_PCAdd4, IF_PC_PreExc, IF_PCIn, IF_PCOut, IF_Instruction;
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/*** ID (Instruction Decode) Signals ***/
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wire ID_Stall;
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wire [1:0] ID_PCSrc;
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wire [1:0] ID_RsFwdSel, ID_RtFwdSel;
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wire ID_Link, ID_Movn, ID_Movz;
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wire ID_SignExtend;
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wire ID_LLSC;
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wire ID_RegDst, ID_ALUSrcImm, ID_MemWrite, ID_MemRead, ID_MemByte, ID_MemHalf, ID_MemSignExtend, ID_RegWrite, ID_MemtoReg;
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wire [4:0] ID_ALUOp;
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wire ID_Mfc0, ID_Mtc0, ID_Eret;
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wire ID_NextIsDelay;
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wire ID_CanErr, ID_ID_CanErr, ID_EX_CanErr, ID_M_CanErr;
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wire ID_KernelMode;
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wire ID_ReverseEndian;
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wire ID_Trap, ID_TrapCond;
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wire ID_EXC_Sys, ID_EXC_Bp, ID_EXC_RI;
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wire ID_Exception_Stall;
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wire ID_Exception_Flush;
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wire ID_PCSrc_Exc;
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wire [31:0] ID_ExceptionPC;
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wire ID_CP1, ID_CP2, ID_CP3;
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wire [31:0] ID_PCAdd4;
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wire [31:0] ID_ReadData1_RF, ID_ReadData1_End;
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wire [31:0] ID_ReadData2_RF, ID_ReadData2_End;
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wire [31:0] CP0_RegOut;
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wire ID_CmpEQ, ID_CmpGZ, ID_CmpLZ, ID_CmpGEZ, ID_CmpLEZ;
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wire [29:0] ID_SignExtImm = (ID_SignExtend & Immediate[15]) ? {14'h3FFF, Immediate} : {14'h0000, Immediate};
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wire [31:0] ID_ImmLeftShift2 = {ID_SignExtImm[29:0], 2'b00};
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wire [31:0] ID_JumpAddress = {ID_PCAdd4[31:28], JumpAddress[25:0], 2'b00};
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wire [31:0] ID_BranchAddress;
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wire [31:0] ID_RestartPC;
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wire ID_IsBDS;
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wire ID_Left, ID_Right;
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wire ID_IsFlushed;
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/*** EX (Execute) Signals ***/
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wire EX_Stall;
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wire [1:0] EX_RsFwdSel, EX_RtFwdSel;
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wire EX_Link;
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wire [1:0] EX_LinkRegDst;
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wire EX_ALUSrcImm;
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wire [4:0] EX_ALUOp;
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wire EX_Movn, EX_Movz;
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wire EX_LLSC;
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wire EX_MemRead, EX_MemWrite, EX_MemByte, EX_MemHalf, EX_MemSignExtend, EX_RegWrite, EX_MemtoReg;
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wire [4:0] EX_Rs, EX_Rt;
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wire EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX;
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wire EX_Trap, EX_TrapCond;
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wire EX_CanErr, EX_EX_CanErr, EX_M_CanErr;
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wire EX_KernelMode;
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wire EX_ReverseEndian;
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wire EX_Exception_Stall;
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wire EX_Exception_Flush;
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wire [31:0] EX_ReadData1_PR, EX_ReadData1_Fwd, EX_ReadData2_PR, EX_ReadData2_Fwd, EX_ReadData2_Imm;
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wire [31:0] EX_SignExtImm;
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wire [4:0] EX_Rd, EX_RtRd, EX_Shamt;
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wire [31:0] EX_ALUResult;
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wire EX_BZero;
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wire EX_EXC_Ov;
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wire [31:0] EX_RestartPC;
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wire EX_IsBDS;
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wire EX_Left, EX_Right;
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/*** MEM (Memory) Signals ***/
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wire M_Stall, M_Stall_Controller;
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wire M_LLSC;
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wire M_MemRead, M_MemWrite, M_MemByte, M_MemHalf, M_MemSignExtend;
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wire M_RegWrite, M_MemtoReg;
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wire M_WriteDataFwdSel;
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wire M_EXC_AdEL, M_EXC_AdES;
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wire M_M_CanErr;
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wire M_KernelMode;
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wire M_ReverseEndian;
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wire M_Trap, M_TrapCond;
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wire M_EXC_Tr;
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wire M_Exception_Flush;
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wire [31:0] M_ALUResult, M_ReadData2_PR;
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wire [4:0] M_RtRd;
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wire [31:0] M_MemReadData;
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wire [31:0] M_RestartPC;
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wire M_IsBDS;
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wire [31:0] M_WriteData_Pre;
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wire M_Left, M_Right;
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wire M_Exception_Stall;
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/*** WB (Writeback) Signals ***/
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wire WB_Stall, WB_RegWrite;
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wire [31:0] WB_ReadData, WB_ALUResult;
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wire [4:0] WB_RtRd;
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wire [31:0] WB_WriteData;
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/*** Other Signals ***/
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wire [7:0] ID_DP_Hazards, HAZ_DP_Hazards;
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/*** Assignments ***/
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assign IF_Instruction = (IF_Stall) ? 32'h00000000 : InstMem_In;
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assign IF_IsBDS = ID_NextIsDelay;
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assign HAZ_DP_Hazards = {ID_DP_Hazards[7:4], EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX};
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assign IF_EXC_AdIF = IF_PCOut[1] | IF_PCOut[0];
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assign ID_CanErr = ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr;
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assign EX_CanErr = EX_EX_CanErr | EX_M_CanErr;
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assign M_CanErr = M_M_CanErr;
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// External Memory Interface
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reg IRead, IReadMask;
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assign InstMem_Address = IF_PCOut[31:2];
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assign DataMem_Address = M_ALUResult[31:2];
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always @(posedge clock) begin
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IRead <= (reset) ? 1 : ~InstMem_Ready;
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IReadMask <= (reset) ? 0 : ((IRead & InstMem_Ready) ? 1 : ((~IF_Stall) ? 0 : IReadMask));
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end
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assign InstMem_Read = IRead & ~IReadMask;
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/*** Datapath Controller ***/
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Control Controller (
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.ID_Stall (ID_Stall),
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.OpCode (OpCode),
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.Funct (Funct),
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.Rs (Rs),
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.Rt (Rt),
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.Cmp_EQ (ID_CmpEQ),
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.Cmp_GZ (ID_CmpGZ),
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.Cmp_GEZ (ID_CmpGEZ),
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.Cmp_LZ (ID_CmpLZ),
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.Cmp_LEZ (ID_CmpLEZ),
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.IF_Flush (IF_Flush),
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.DP_Hazards (ID_DP_Hazards),
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.PCSrc (ID_PCSrc),
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.SignExtend (ID_SignExtend),
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.Link (ID_Link),
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.Movn (ID_Movn),
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.Movz (ID_Movz),
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.Mfc0 (ID_Mfc0),
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.Mtc0 (ID_Mtc0),
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.CP1 (ID_CP1),
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.CP2 (ID_CP2),
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.CP3 (ID_CP3),
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.Eret (ID_Eret),
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.Trap (ID_Trap),
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.TrapCond (ID_TrapCond),
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.EXC_Sys (ID_EXC_Sys),
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.EXC_Bp (ID_EXC_Bp),
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.EXC_RI (ID_EXC_RI),
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.ID_CanErr (ID_ID_CanErr),
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.EX_CanErr (ID_EX_CanErr),
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.M_CanErr (ID_M_CanErr),
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.NextIsDelay (ID_NextIsDelay),
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.RegDst (ID_RegDst),
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.ALUSrcImm (ID_ALUSrcImm),
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.ALUOp (ID_ALUOp),
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.LLSC (ID_LLSC),
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.MemWrite (ID_MemWrite),
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.MemRead (ID_MemRead),
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.MemByte (ID_MemByte),
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.MemHalf (ID_MemHalf),
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.MemSignExtend (ID_MemSignExtend),
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.Left (ID_Left),
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.Right (ID_Right),
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.RegWrite (ID_RegWrite),
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.MemtoReg (ID_MemtoReg)
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);
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/*** Hazard and Forward Control Unit ***/
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Hazard_Detection HazardControl (
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.DP_Hazards (HAZ_DP_Hazards),
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.ID_Rs (Rs),
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.ID_Rt (Rt),
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.EX_Rs (EX_Rs),
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.EX_Rt (EX_Rt),
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.EX_RtRd (EX_RtRd),
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.MEM_RtRd (M_RtRd),
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.WB_RtRd (WB_RtRd),
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.ID_Link (ID_Link),
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.EX_Link (EX_Link),
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.EX_RegWrite (EX_RegWrite),
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.MEM_RegWrite (M_RegWrite),
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.WB_RegWrite (WB_RegWrite),
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.MEM_MemRead (M_MemRead),
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.MEM_MemWrite (M_MemWrite),
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.InstMem_Read (InstMem_Read),
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.InstMem_Ready (InstMem_Ready),
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.Mfc0 (ID_Mfc0),
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.IF_Exception_Stall (IF_Exception_Stall),
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.ID_Exception_Stall (ID_Exception_Stall),
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.EX_Exception_Stall (EX_Exception_Stall),
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.M_Stall_Controller (M_Stall_Controller),
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.IF_Stall (IF_Stall),
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.ID_Stall (ID_Stall),
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.EX_Stall (EX_Stall),
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.M_Stall (M_Stall),
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.WB_Stall (WB_Stall),
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.ID_RsFwdSel (ID_RsFwdSel),
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.ID_RtFwdSel (ID_RtFwdSel),
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.EX_RsFwdSel (EX_RsFwdSel),
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.EX_RtFwdSel (EX_RtFwdSel),
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.M_WriteDataFwdSel (M_WriteDataFwdSel)
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);
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/*** Coprocessor 0: Exceptions and Interrupts ***/
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CPZero CP0 (
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.clock (clock),
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.Mfc0 (ID_Mfc0),
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.Mtc0 (ID_Mtc0),
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.IF_Stall (IF_Stall),
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.ID_Stall (ID_Stall),
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.COP1 (ID_CP1),
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.COP2 (ID_CP2),
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.COP3 (ID_CP3),
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.ERET (ID_Eret),
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.Rd (Rd),
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.Sel (Cp0_Sel),
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.Reg_In (ID_ReadData2_End),
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.Reg_Out (CP0_RegOut),
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.KernelMode (ID_KernelMode),
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.ReverseEndian (ID_ReverseEndian),
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.Int (Interrupts),
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.reset (reset),
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.EXC_NMI (NMI),
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.EXC_AdIF (IF_EXC_AdIF),
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.EXC_AdEL (M_EXC_AdEL),
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.EXC_AdES (M_EXC_AdES),
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.EXC_Ov (EX_EXC_Ov),
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.EXC_Tr (M_EXC_Tr),
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.EXC_Sys (ID_EXC_Sys),
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.EXC_Bp (ID_EXC_Bp),
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.EXC_RI (ID_EXC_RI),
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.ID_RestartPC (ID_RestartPC),
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.EX_RestartPC (EX_RestartPC),
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.M_RestartPC (M_RestartPC),
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.ID_IsFlushed (ID_IsFlushed),
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.IF_IsBD (IF_IsBDS),
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.ID_IsBD (ID_IsBDS),
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.EX_IsBD (EX_IsBDS),
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|
.M_IsBD (M_IsBDS),
|
| 297 |
|
|
.BadAddr_M (M_ALUResult),
|
| 298 |
|
|
.BadAddr_IF (IF_PCOut),
|
| 299 |
|
|
.ID_CanErr (ID_CanErr),
|
| 300 |
|
|
.EX_CanErr (EX_CanErr),
|
| 301 |
|
|
.M_CanErr (M_CanErr),
|
| 302 |
|
|
.IF_Exception_Stall (IF_Exception_Stall),
|
| 303 |
|
|
.ID_Exception_Stall (ID_Exception_Stall),
|
| 304 |
|
|
.EX_Exception_Stall (EX_Exception_Stall),
|
| 305 |
|
|
.M_Exception_Stall (M_Exception_Stall),
|
| 306 |
|
|
.IF_Exception_Flush (IF_Exception_Flush),
|
| 307 |
|
|
.ID_Exception_Flush (ID_Exception_Flush),
|
| 308 |
|
|
.EX_Exception_Flush (EX_Exception_Flush),
|
| 309 |
|
|
.M_Exception_Flush (M_Exception_Flush),
|
| 310 |
|
|
.Exc_PC_Sel (ID_PCSrc_Exc),
|
| 311 |
|
|
.Exc_PC_Out (ID_ExceptionPC),
|
| 312 |
|
|
.IP (IP)
|
| 313 |
|
|
);
|
| 314 |
|
|
|
| 315 |
|
|
/*** PC Source Non-Exception Mux ***/
|
| 316 |
|
|
Mux4 #(.WIDTH(32)) PCSrcStd_Mux (
|
| 317 |
|
|
.sel (ID_PCSrc),
|
| 318 |
|
|
.in0 (IF_PCAdd4),
|
| 319 |
|
|
.in1 (ID_JumpAddress),
|
| 320 |
|
|
.in2 (ID_BranchAddress),
|
| 321 |
|
|
.in3 (ID_ReadData1_End),
|
| 322 |
|
|
.out (IF_PC_PreExc)
|
| 323 |
|
|
);
|
| 324 |
|
|
|
| 325 |
|
|
/*** PC Source Exception Mux ***/
|
| 326 |
|
|
Mux2 #(.WIDTH(32)) PCSrcExc_Mux (
|
| 327 |
|
|
.sel (ID_PCSrc_Exc),
|
| 328 |
|
|
.in0 (IF_PC_PreExc),
|
| 329 |
|
|
.in1 (ID_ExceptionPC),
|
| 330 |
|
|
.out (IF_PCIn)
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
/*** Program Counter (MIPS spec is 0xBFC00000 starting address) ***/
|
| 334 |
|
|
Register #(.WIDTH(32), .INIT(EXC_Vector_Base_Reset)) PC (
|
| 335 |
|
|
.clock (clock),
|
| 336 |
|
|
.reset (reset),
|
| 337 |
|
|
//.enable (~IF_Stall), // XXX verify. HERE. Was 1 but on stall latches PC+4, ad nauseum.
|
| 338 |
|
|
.enable (~(IF_Stall | ID_Stall)),
|
| 339 |
|
|
.D (IF_PCIn),
|
| 340 |
|
|
.Q (IF_PCOut)
|
| 341 |
|
|
);
|
| 342 |
|
|
|
| 343 |
|
|
/*** PC +4 Adder ***/
|
| 344 |
|
|
Add PC_Add4 (
|
| 345 |
|
|
.A (IF_PCOut),
|
| 346 |
|
|
.B (32'h00000004),
|
| 347 |
|
|
.C (IF_PCAdd4)
|
| 348 |
|
|
);
|
| 349 |
|
|
|
| 350 |
|
|
/*** Instruction Fetch -> Instruction Decode Stage Register ***/
|
| 351 |
|
|
IFID_Stage IFID (
|
| 352 |
|
|
.clock (clock),
|
| 353 |
|
|
.reset (reset),
|
| 354 |
|
|
.IF_Flush (IF_Exception_Flush | IF_Flush),
|
| 355 |
|
|
.IF_Stall (IF_Stall),
|
| 356 |
|
|
.ID_Stall (ID_Stall),
|
| 357 |
|
|
.IF_Instruction (IF_Instruction),
|
| 358 |
|
|
.IF_PCAdd4 (IF_PCAdd4),
|
| 359 |
|
|
.IF_PC (IF_PCOut),
|
| 360 |
|
|
.IF_IsBDS (IF_IsBDS),
|
| 361 |
|
|
.ID_Instruction (Instruction),
|
| 362 |
|
|
.ID_PCAdd4 (ID_PCAdd4),
|
| 363 |
|
|
.ID_RestartPC (ID_RestartPC),
|
| 364 |
|
|
.ID_IsBDS (ID_IsBDS),
|
| 365 |
|
|
.ID_IsFlushed (ID_IsFlushed)
|
| 366 |
|
|
);
|
| 367 |
|
|
|
| 368 |
|
|
/*** Register File ***/
|
| 369 |
|
|
RegisterFile RegisterFile (
|
| 370 |
|
|
.clock (clock),
|
| 371 |
|
|
.reset (reset),
|
| 372 |
|
|
.ReadReg1 (Rs),
|
| 373 |
|
|
.ReadReg2 (Rt),
|
| 374 |
|
|
.WriteReg (WB_RtRd),
|
| 375 |
|
|
.WriteData (WB_WriteData),
|
| 376 |
|
|
.RegWrite (WB_RegWrite),
|
| 377 |
|
|
.ReadData1 (ID_ReadData1_RF),
|
| 378 |
|
|
.ReadData2 (ID_ReadData2_RF)
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
/*** ID Rs Forwarding/Link Mux ***/
|
| 382 |
|
|
Mux4 #(.WIDTH(32)) IDRsFwd_Mux (
|
| 383 |
|
|
.sel (ID_RsFwdSel),
|
| 384 |
|
|
.in0 (ID_ReadData1_RF),
|
| 385 |
|
|
.in1 (M_ALUResult),
|
| 386 |
|
|
.in2 (WB_WriteData),
|
| 387 |
|
|
.in3 (ID_PCAdd4),
|
| 388 |
|
|
.out (ID_ReadData1_End)
|
| 389 |
|
|
);
|
| 390 |
|
|
|
| 391 |
|
|
/*** ID Rt Forwarding/CP0 Mfc0 Mux ***/
|
| 392 |
|
|
Mux4 #(.WIDTH(32)) IDRtFwd_Mux (
|
| 393 |
|
|
.sel (ID_RtFwdSel),
|
| 394 |
|
|
.in0 (ID_ReadData2_RF),
|
| 395 |
|
|
.in1 (M_ALUResult),
|
| 396 |
|
|
.in2 (WB_WriteData),
|
| 397 |
|
|
.in3 (CP0_RegOut),
|
| 398 |
|
|
.out (ID_ReadData2_End)
|
| 399 |
|
|
);
|
| 400 |
|
|
|
| 401 |
|
|
/*** Condition Compare Unit ***/
|
| 402 |
|
|
Compare Compare (
|
| 403 |
|
|
.A (ID_ReadData1_End),
|
| 404 |
|
|
.B (ID_ReadData2_End),
|
| 405 |
|
|
.EQ (ID_CmpEQ),
|
| 406 |
|
|
.GZ (ID_CmpGZ),
|
| 407 |
|
|
.LZ (ID_CmpLZ),
|
| 408 |
|
|
.GEZ (ID_CmpGEZ),
|
| 409 |
|
|
.LEZ (ID_CmpLEZ)
|
| 410 |
|
|
);
|
| 411 |
|
|
|
| 412 |
|
|
/*** Branch Address Adder ***/
|
| 413 |
|
|
Add BranchAddress_Add (
|
| 414 |
|
|
.A (ID_PCAdd4),
|
| 415 |
|
|
.B (ID_ImmLeftShift2),
|
| 416 |
|
|
.C (ID_BranchAddress)
|
| 417 |
|
|
);
|
| 418 |
|
|
|
| 419 |
|
|
/*** Instruction Decode -> Execute Pipeline Stage ***/
|
| 420 |
|
|
IDEX_Stage IDEX (
|
| 421 |
|
|
.clock (clock),
|
| 422 |
|
|
.reset (reset),
|
| 423 |
|
|
.ID_Flush (ID_Exception_Flush),
|
| 424 |
|
|
.ID_Stall (ID_Stall),
|
| 425 |
|
|
.EX_Stall (EX_Stall),
|
| 426 |
|
|
.ID_Link (ID_Link),
|
| 427 |
|
|
.ID_RegDst (ID_RegDst),
|
| 428 |
|
|
.ID_ALUSrcImm (ID_ALUSrcImm),
|
| 429 |
|
|
.ID_ALUOp (ID_ALUOp),
|
| 430 |
|
|
.ID_Movn (ID_Movn),
|
| 431 |
|
|
.ID_Movz (ID_Movz),
|
| 432 |
|
|
.ID_LLSC (ID_LLSC),
|
| 433 |
|
|
.ID_MemRead (ID_MemRead),
|
| 434 |
|
|
.ID_MemWrite (ID_MemWrite),
|
| 435 |
|
|
.ID_MemByte (ID_MemByte),
|
| 436 |
|
|
.ID_MemHalf (ID_MemHalf),
|
| 437 |
|
|
.ID_MemSignExtend (ID_MemSignExtend),
|
| 438 |
|
|
.ID_Left (ID_Left),
|
| 439 |
|
|
.ID_Right (ID_Right),
|
| 440 |
|
|
.ID_RegWrite (ID_RegWrite),
|
| 441 |
|
|
.ID_MemtoReg (ID_MemtoReg),
|
| 442 |
|
|
.ID_ReverseEndian (ID_ReverseEndian),
|
| 443 |
|
|
.ID_Rs (Rs),
|
| 444 |
|
|
.ID_Rt (Rt),
|
| 445 |
|
|
.ID_WantRsByEX (ID_DP_Hazards[3]),
|
| 446 |
|
|
.ID_NeedRsByEX (ID_DP_Hazards[2]),
|
| 447 |
|
|
.ID_WantRtByEX (ID_DP_Hazards[1]),
|
| 448 |
|
|
.ID_NeedRtByEX (ID_DP_Hazards[0]),
|
| 449 |
|
|
.ID_KernelMode (ID_KernelMode),
|
| 450 |
|
|
.ID_RestartPC (ID_RestartPC),
|
| 451 |
|
|
.ID_IsBDS (ID_IsBDS),
|
| 452 |
|
|
.ID_Trap (ID_Trap),
|
| 453 |
|
|
.ID_TrapCond (ID_TrapCond),
|
| 454 |
|
|
.ID_EX_CanErr (ID_EX_CanErr),
|
| 455 |
|
|
.ID_M_CanErr (ID_M_CanErr),
|
| 456 |
|
|
.ID_ReadData1 (ID_ReadData1_End),
|
| 457 |
|
|
.ID_ReadData2 (ID_ReadData2_End),
|
| 458 |
|
|
.ID_SignExtImm (ID_SignExtImm[16:0]),
|
| 459 |
|
|
.EX_Link (EX_Link),
|
| 460 |
|
|
.EX_LinkRegDst (EX_LinkRegDst),
|
| 461 |
|
|
.EX_ALUSrcImm (EX_ALUSrcImm),
|
| 462 |
|
|
.EX_ALUOp (EX_ALUOp),
|
| 463 |
|
|
.EX_Movn (EX_Movn),
|
| 464 |
|
|
.EX_Movz (EX_Movz),
|
| 465 |
|
|
.EX_LLSC (EX_LLSC),
|
| 466 |
|
|
.EX_MemRead (EX_MemRead),
|
| 467 |
|
|
.EX_MemWrite (EX_MemWrite),
|
| 468 |
|
|
.EX_MemByte (EX_MemByte),
|
| 469 |
|
|
.EX_MemHalf (EX_MemHalf),
|
| 470 |
|
|
.EX_MemSignExtend (EX_MemSignExtend),
|
| 471 |
|
|
.EX_Left (EX_Left),
|
| 472 |
|
|
.EX_Right (EX_Right),
|
| 473 |
|
|
.EX_RegWrite (EX_RegWrite),
|
| 474 |
|
|
.EX_MemtoReg (EX_MemtoReg),
|
| 475 |
|
|
.EX_ReverseEndian (EX_ReverseEndian),
|
| 476 |
|
|
.EX_Rs (EX_Rs),
|
| 477 |
|
|
.EX_Rt (EX_Rt),
|
| 478 |
|
|
.EX_WantRsByEX (EX_WantRsByEX),
|
| 479 |
|
|
.EX_NeedRsByEX (EX_NeedRsByEX),
|
| 480 |
|
|
.EX_WantRtByEX (EX_WantRtByEX),
|
| 481 |
|
|
.EX_NeedRtByEX (EX_NeedRtByEX),
|
| 482 |
|
|
.EX_KernelMode (EX_KernelMode),
|
| 483 |
|
|
.EX_RestartPC (EX_RestartPC),
|
| 484 |
|
|
.EX_IsBDS (EX_IsBDS),
|
| 485 |
|
|
.EX_Trap (EX_Trap),
|
| 486 |
|
|
.EX_TrapCond (EX_TrapCond),
|
| 487 |
|
|
.EX_EX_CanErr (EX_EX_CanErr),
|
| 488 |
|
|
.EX_M_CanErr (EX_M_CanErr),
|
| 489 |
|
|
.EX_ReadData1 (EX_ReadData1_PR),
|
| 490 |
|
|
.EX_ReadData2 (EX_ReadData2_PR),
|
| 491 |
|
|
.EX_SignExtImm (EX_SignExtImm),
|
| 492 |
|
|
.EX_Rd (EX_Rd),
|
| 493 |
|
|
.EX_Shamt (EX_Shamt)
|
| 494 |
|
|
);
|
| 495 |
|
|
|
| 496 |
|
|
/*** EX Rs Forwarding Mux ***/
|
| 497 |
|
|
Mux4 #(.WIDTH(32)) EXRsFwd_Mux (
|
| 498 |
|
|
.sel (EX_RsFwdSel),
|
| 499 |
|
|
.in0 (EX_ReadData1_PR),
|
| 500 |
|
|
.in1 (M_ALUResult),
|
| 501 |
|
|
.in2 (WB_WriteData),
|
| 502 |
|
|
.in3 (32'hxxxxxxxx),
|
| 503 |
|
|
.out (EX_ReadData1_Fwd)
|
| 504 |
|
|
);
|
| 505 |
|
|
|
| 506 |
|
|
/*** EX Rt Forwarding / Link Mux ***/
|
| 507 |
|
|
Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux (
|
| 508 |
|
|
.sel (EX_RtFwdSel),
|
| 509 |
|
|
.in0 (EX_ReadData2_PR),
|
| 510 |
|
|
.in1 (M_ALUResult),
|
| 511 |
|
|
.in2 (WB_WriteData),
|
| 512 |
|
|
.in3 (32'h00000004),
|
| 513 |
|
|
.out (EX_ReadData2_Fwd)
|
| 514 |
|
|
);
|
| 515 |
|
|
|
| 516 |
|
|
/*** EX ALU Immediate Mux ***/
|
| 517 |
|
|
Mux2 #(.WIDTH(32)) EXALUImm_Mux (
|
| 518 |
|
|
.sel (EX_ALUSrcImm),
|
| 519 |
|
|
.in0 (EX_ReadData2_Fwd),
|
| 520 |
|
|
.in1 (EX_SignExtImm),
|
| 521 |
|
|
.out (EX_ReadData2_Imm)
|
| 522 |
|
|
);
|
| 523 |
|
|
|
| 524 |
|
|
/*** EX RtRd / Link Mux ***/
|
| 525 |
|
|
Mux4 #(.WIDTH(5)) EXRtRdLnk_Mux (
|
| 526 |
|
|
.sel (EX_LinkRegDst),
|
| 527 |
|
|
.in0 (EX_Rt),
|
| 528 |
|
|
.in1 (EX_Rd),
|
| 529 |
|
|
.in2 (5'b11111),
|
| 530 |
|
|
.in3 (5'bxxxxx),
|
| 531 |
|
|
.out (EX_RtRd)
|
| 532 |
|
|
);
|
| 533 |
|
|
|
| 534 |
|
|
/*** Arithmetic Logic Unit ***/
|
| 535 |
|
|
ALU ALU (
|
| 536 |
|
|
.clock (clock),
|
| 537 |
|
|
.reset (reset),
|
| 538 |
|
|
.EX_Stall (EX_Stall),
|
| 539 |
|
|
.EX_Flush (EX_Exception_Flush),
|
| 540 |
|
|
.A (EX_ReadData1_Fwd),
|
| 541 |
|
|
.B (EX_ReadData2_Imm),
|
| 542 |
|
|
.Operation (EX_ALUOp),
|
| 543 |
|
|
.Shamt (EX_Shamt),
|
| 544 |
|
|
.Result (EX_ALUResult),
|
| 545 |
|
|
.BZero (EX_BZero),
|
| 546 |
|
|
.EXC_Ov (EX_EXC_Ov)
|
| 547 |
|
|
);
|
| 548 |
|
|
|
| 549 |
|
|
/*** Execute -> Memory Pipeline Stage ***/
|
| 550 |
|
|
EXMEM_Stage EXMEM (
|
| 551 |
|
|
.clock (clock),
|
| 552 |
|
|
.reset (reset),
|
| 553 |
|
|
.EX_Flush (EX_Exception_Flush),
|
| 554 |
|
|
.EX_Stall (EX_Stall),
|
| 555 |
|
|
.M_Stall (M_Stall),
|
| 556 |
|
|
.EX_Movn (EX_Movn),
|
| 557 |
|
|
.EX_Movz (EX_Movz),
|
| 558 |
|
|
.EX_BZero (EX_BZero),
|
| 559 |
|
|
.EX_RegWrite (EX_RegWrite),
|
| 560 |
|
|
.EX_MemtoReg (EX_MemtoReg),
|
| 561 |
|
|
.EX_ReverseEndian (EX_ReverseEndian),
|
| 562 |
|
|
.EX_LLSC (EX_LLSC),
|
| 563 |
|
|
.EX_MemRead (EX_MemRead),
|
| 564 |
|
|
.EX_MemWrite (EX_MemWrite),
|
| 565 |
|
|
.EX_MemByte (EX_MemByte),
|
| 566 |
|
|
.EX_MemHalf (EX_MemHalf),
|
| 567 |
|
|
.EX_MemSignExtend (EX_MemSignExtend),
|
| 568 |
|
|
.EX_Left (EX_Left),
|
| 569 |
|
|
.EX_Right (EX_Right),
|
| 570 |
|
|
.EX_KernelMode (EX_KernelMode),
|
| 571 |
|
|
.EX_RestartPC (EX_RestartPC),
|
| 572 |
|
|
.EX_IsBDS (EX_IsBDS),
|
| 573 |
|
|
.EX_Trap (EX_Trap),
|
| 574 |
|
|
.EX_TrapCond (EX_TrapCond),
|
| 575 |
|
|
.EX_M_CanErr (EX_M_CanErr),
|
| 576 |
|
|
.EX_ALU_Result (EX_ALUResult),
|
| 577 |
|
|
.EX_ReadData2 (EX_ReadData2_Fwd),
|
| 578 |
|
|
.EX_RtRd (EX_RtRd),
|
| 579 |
|
|
.M_RegWrite (M_RegWrite),
|
| 580 |
|
|
.M_MemtoReg (M_MemtoReg),
|
| 581 |
|
|
.M_ReverseEndian (M_ReverseEndian),
|
| 582 |
|
|
.M_LLSC (M_LLSC),
|
| 583 |
|
|
.M_MemRead (M_MemRead),
|
| 584 |
|
|
.M_MemWrite (M_MemWrite),
|
| 585 |
|
|
.M_MemByte (M_MemByte),
|
| 586 |
|
|
.M_MemHalf (M_MemHalf),
|
| 587 |
|
|
.M_MemSignExtend (M_MemSignExtend),
|
| 588 |
|
|
.M_Left (M_Left),
|
| 589 |
|
|
.M_Right (M_Right),
|
| 590 |
|
|
.M_KernelMode (M_KernelMode),
|
| 591 |
|
|
.M_RestartPC (M_RestartPC),
|
| 592 |
|
|
.M_IsBDS (M_IsBDS),
|
| 593 |
|
|
.M_Trap (M_Trap),
|
| 594 |
|
|
.M_TrapCond (M_TrapCond),
|
| 595 |
|
|
.M_M_CanErr (M_M_CanErr),
|
| 596 |
|
|
.M_ALU_Result (M_ALUResult),
|
| 597 |
|
|
.M_ReadData2 (M_ReadData2_PR),
|
| 598 |
|
|
.M_RtRd (M_RtRd)
|
| 599 |
|
|
);
|
| 600 |
|
|
|
| 601 |
|
|
/*** Trap Detection Unit ***/
|
| 602 |
|
|
TrapDetect TrapDetect (
|
| 603 |
|
|
.Trap (M_Trap),
|
| 604 |
|
|
.TrapCond (M_TrapCond),
|
| 605 |
|
|
.ALUResult (M_ALUResult),
|
| 606 |
|
|
.EXC_Tr (M_EXC_Tr)
|
| 607 |
|
|
);
|
| 608 |
|
|
|
| 609 |
|
|
/*** MEM Write Data Mux ***/
|
| 610 |
|
|
Mux2 #(.WIDTH(32)) MWriteData_Mux (
|
| 611 |
|
|
.sel (M_WriteDataFwdSel),
|
| 612 |
|
|
.in0 (M_ReadData2_PR),
|
| 613 |
|
|
.in1 (WB_WriteData),
|
| 614 |
|
|
.out (M_WriteData_Pre)
|
| 615 |
|
|
);
|
| 616 |
|
|
|
| 617 |
|
|
/*** Data Memory Controller ***/
|
| 618 |
|
|
MemControl DataMem_Controller (
|
| 619 |
|
|
.clock (clock),
|
| 620 |
|
|
.reset (reset),
|
| 621 |
|
|
.DataIn (M_WriteData_Pre),
|
| 622 |
|
|
.Address (M_ALUResult),
|
| 623 |
|
|
.MReadData (DataMem_In),
|
| 624 |
|
|
.MemRead (M_MemRead),
|
| 625 |
|
|
.MemWrite (M_MemWrite),
|
| 626 |
|
|
.DataMem_Ready (DataMem_Ready),
|
| 627 |
|
|
.Byte (M_MemByte),
|
| 628 |
|
|
.Half (M_MemHalf),
|
| 629 |
|
|
.SignExtend (M_MemSignExtend),
|
| 630 |
|
|
.KernelMode (M_KernelMode),
|
| 631 |
|
|
.ReverseEndian (M_ReverseEndian),
|
| 632 |
|
|
.LLSC (M_LLSC),
|
| 633 |
|
|
.ERET (ID_Eret),
|
| 634 |
|
|
.Left (M_Left),
|
| 635 |
|
|
.Right (M_Right),
|
| 636 |
|
|
.M_Exception_Stall (M_Exception_Stall),
|
| 637 |
|
|
|
| 638 |
|
|
.IF_Stall (IF_Stall),
|
| 639 |
|
|
|
| 640 |
|
|
.DataOut (M_MemReadData),
|
| 641 |
|
|
.MWriteData (DataMem_Out),
|
| 642 |
|
|
.WriteEnable (DataMem_Write),
|
| 643 |
|
|
.ReadEnable (DataMem_Read),
|
| 644 |
|
|
.M_Stall (M_Stall_Controller),
|
| 645 |
|
|
.EXC_AdEL (M_EXC_AdEL),
|
| 646 |
|
|
.EXC_AdES (M_EXC_AdES)
|
| 647 |
|
|
);
|
| 648 |
|
|
|
| 649 |
|
|
/*** Memory -> Writeback Pipeline Stage ***/
|
| 650 |
|
|
MEMWB_Stage MEMWB (
|
| 651 |
|
|
.clock (clock),
|
| 652 |
|
|
.reset (reset),
|
| 653 |
|
|
.M_Flush (M_Exception_Flush),
|
| 654 |
|
|
.M_Stall (M_Stall),
|
| 655 |
|
|
.WB_Stall (WB_Stall),
|
| 656 |
|
|
.M_RegWrite (M_RegWrite),
|
| 657 |
|
|
.M_MemtoReg (M_MemtoReg),
|
| 658 |
|
|
.M_ReadData (M_MemReadData),
|
| 659 |
|
|
.M_ALU_Result (M_ALUResult),
|
| 660 |
|
|
.M_RtRd (M_RtRd),
|
| 661 |
|
|
.WB_RegWrite (WB_RegWrite),
|
| 662 |
|
|
.WB_MemtoReg (WB_MemtoReg),
|
| 663 |
|
|
.WB_ReadData (WB_ReadData),
|
| 664 |
|
|
.WB_ALU_Result (WB_ALUResult),
|
| 665 |
|
|
.WB_RtRd (WB_RtRd)
|
| 666 |
|
|
);
|
| 667 |
|
|
|
| 668 |
|
|
/*** WB MemtoReg Mux ***/
|
| 669 |
|
|
Mux2 #(.WIDTH(32)) WBMemtoReg_Mux (
|
| 670 |
|
|
.sel (WB_MemtoReg),
|
| 671 |
|
|
.in0 (WB_ALUResult),
|
| 672 |
|
|
.in1 (WB_ReadData),
|
| 673 |
|
|
.out (WB_WriteData)
|
| 674 |
|
|
);
|
| 675 |
|
|
|
| 676 |
|
|
endmodule
|
| 677 |
3 |
ayersg |
|
