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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [UART/] [uart_bootloader_v1.v] - Blame information for rev 2

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1 2 ayersg 
               `timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Grant Ayers (ayers@cs.utah.edu)
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//
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// Create Date:    09:59:05 05/24/2010
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// Design Name:
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// Module Name:    uart_bootloader
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//       Implements the XUM bootloader protocol over a serial port (115200 8N1).
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//       The protocol is as follows:
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//
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//       1. Programmer sends 'XUM' ascii bytes
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//       2. Programmer sends a number indicating how many 32-bit data words it
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//          has to send, minus 1. (For example, if it has one 32-bit data word,
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//          this number will be 0.) The size of this number is 18 bits.
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//          This means the minimum transmission size is 1 word (32 bits), and
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//          the maximum transmission size is 262144 words (exactly 1MB).
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//          This 18-bit number is sent in three bytes, and the six most
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//          significant bits of the first byte must be 0.
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//       3. The FPGA sends back the third size byte from the programmer, allowing
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//          the programmer to determine if the FPGA is listening and conforming
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//          to the XUM boot protocol.
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//       4. The programmer sends another 18-bit number indicating the starting
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//          offset in memory where the data should be placed. Normally this will
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//          be 0. This number is also sent in three bytes, and the six most
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//          significant bits of the first byte are ignored.
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//       5. The programmer sends the data. A copy of each byte that it sends will
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//          be sent back to the programmer from the FPGA, allowing the programmer
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//          to determine if all of the data was transmitted successfully.
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module uart_bootloader(
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   input clock,                  // 100Mhz
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   input reset,                  // System-wide global reset
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   input RxD,                    // UART data from computer
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   output TxD,                   // UART data to computer
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   output resetCPU,              // Reset CPUs' PCs to start execution at 0x0
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   output reg writeMem = 0,      // Write command to instruction memory
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   output reg [17:0] addrMem = 0, // address to instruction memory
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   output reg [31:0] dataMem = 0 // 32-bit data words of instruction memory
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   );
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   localparam [3:0]  HEAD_1=0, HEAD_2=1, HEAD_3=2, SIZE_1=3, SIZE_2=4, SIZE_3=5, OFST_1=6, OFST_2=7,
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                     OFST_3=8, ADDRSET=9, DATA_1=10, DATA_2=11, DATA_3=12, DATA_4=13, ADDRINC=14;
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   /* UART Signals */
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   reg uart_write = 0;
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   reg uart_read = 0;
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   wire [7:0] uart_rx_data;
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   wire [7:0] uart_tx_data = uart_rx_data;
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   wire uart_rx_data_ready;
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   reg [17:0] size = 0;       // Number of 32-bit words to expect
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   reg [17:0] offset = 0;     // Starting address to store words
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   reg [17:0] rx_count = 0;   // Number of 32-bit words received so far
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   reg [3:0] state = HEAD_1;
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   // The CPU(s) is continuously reset while memory is being replaced.
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   assign resetCPU = ((state!=HEAD_1) && (state!=HEAD_2) && (state!=HEAD_3) && (state!=SIZE_1));
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   always @(posedge clock) begin
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      if (reset) begin
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         state <= HEAD_1;
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         uart_read <= 0;
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         uart_write <= 0;
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         writeMem <= 0;
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         rx_count <= 0;
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      end
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      else begin
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         uart_read <= uart_rx_data_ready & ((state!=ADDRSET) && (state!=ADDRINC));
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         uart_write <= uart_rx_data_ready & ((state==SIZE_3) || (state==DATA_1) || (state==DATA_2) || (state==DATA_3) || (state==DATA_4));
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         writeMem <= uart_rx_data_ready & (state == DATA_4);
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         rx_count <= (state == HEAD_1) ? 0 : ((state == ADDRINC) ? rx_count + 1 : rx_count);
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         case (state)
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            HEAD_1:  begin
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                        if (uart_rx_data_ready) begin
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                           state <= (uart_rx_data == 8'h58) ? HEAD_2 : HEAD_1;   // 'X'
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                        end
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                        else begin
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                           state <= HEAD_1;
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                        end
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                     end
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            HEAD_2:  begin
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                        if (uart_rx_data_ready) begin
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                           state <= (uart_rx_data == 8'h55) ? HEAD_3 : HEAD_1;   // 'U'
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                        end
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                        else begin
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                           state <= HEAD_2;
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                        end
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                     end
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            HEAD_3:  begin
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                        if (uart_rx_data_ready) begin
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                           state <= (uart_rx_data == 8'h4D) ? SIZE_1 : HEAD_1;   // 'M'
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                        end
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                        else begin
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                           state <= HEAD_3;
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                        end
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                     end
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            SIZE_1:  begin
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                        if (uart_rx_data_ready) begin
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                           state <= (uart_rx_data[7:2] == 6'b000000) ? SIZE_2 : HEAD_1;   // 6 leading 0s
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                           size[17:16] <= uart_rx_data[1:0];
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                        end
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                        else begin
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                           state <= SIZE_1;
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                        end
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                     end
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            SIZE_2:  begin
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                        state <= (uart_rx_data_ready) ? SIZE_3 : SIZE_2;
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                        size[15:8] <= (uart_rx_data_ready) ? uart_rx_data : size[15:8];
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                     end
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            SIZE_3:  begin
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                        state <= (uart_rx_data_ready) ? OFST_1 : SIZE_3;
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                        size[7:0] <= (uart_rx_data_ready) ? uart_rx_data : size[7:0];
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                     end
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            OFST_1:  begin
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                        state <= (uart_rx_data_ready) ? OFST_2 : OFST_1;
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                        offset[17:16] <= (uart_rx_data_ready) ? uart_rx_data[1:0] : offset[17:16];
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                     end
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            OFST_2:  begin
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                        state <= (uart_rx_data_ready) ? OFST_3 : OFST_2;
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                        offset[15:8] <= (uart_rx_data_ready) ? uart_rx_data : offset[15:8];
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                     end
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            OFST_3:  begin
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                        state <= (uart_rx_data_ready) ? ADDRSET : OFST_3;
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                        offset[7:0] <= (uart_rx_data_ready) ? uart_rx_data : offset[7:0];
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                     end
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            ADDRSET: begin
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                        state <= DATA_1;
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                        addrMem <= offset;
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                     end
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            DATA_1:  begin
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                        state <= (uart_rx_data_ready) ? DATA_2 : DATA_1;
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                        dataMem[31:24] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[31:24];
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                     end
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            DATA_2:  begin
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                        state <= (uart_rx_data_ready) ? DATA_3 : DATA_2;
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                        dataMem[23:16] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[23:16];
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                     end
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            DATA_3:  begin
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                        state <= (uart_rx_data_ready) ? DATA_4 : DATA_3;
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                        dataMem[15:8] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[15:8];
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                     end
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            DATA_4:  begin
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                        state <= (uart_rx_data_ready) ? ADDRINC : DATA_4;
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                        dataMem[7:0] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[7:0];
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                     end
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            ADDRINC:   begin
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                        addrMem <= addrMem + 1;
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                        state <= (rx_count == size) ? HEAD_1 : DATA_1;
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                     end
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            default: state <= HEAD_1;
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         endcase
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      end
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   end
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   uart_min uart (
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      .clock      (clock),
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      .reset      (reset),
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      .write      (uart_write),
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      .data_in    (uart_tx_data),
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      .read       (uart_read),
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      .data_out   (uart_rx_data),
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      .data_ready (uart_rx_data_ready),
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      .RxD        (RxD),
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      .TxD        (TxD)
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   );
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endmodule

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