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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [UART/] [uart_tx.v] - Blame information for rev 2

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1 2 ayersg 
`timescale 1ns / 1ps
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/*
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 * File         : uart_tx.v
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 * Project      : University of Utah, XUM Project MIPS32 core
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 * Creator(s)   : Grant Ayers (ayers@cs.utah.edu)
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 *
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 * Modification History:
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 *   Rev   Date         Initials  Description of Change
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 *   1.0   25-Mar-2010  GEA       Initial design.
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 *
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 * Standards/Formatting:
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 *   Verilog 2001, 4 soft tab, wide column.
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 *
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 * Description:
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 *   Transmits bytes of data from the serial port. Capable of back-to-back
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 *   transmission of data for maximum bandwidth utilization.
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 *   'TxD_start' must only pulse with a 'uart_tick' pulse. 8N1.
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 */
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module uart_tx (
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    input clock,
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    input reset,
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    input uart_tick,
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    input [7:0] TxD_data,
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    input TxD_start,    // Must happen with a uart_tick
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    output ready,
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    output reg TxD
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    );
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    localparam [3:0] IDLE=0, START=1, BIT_0=2, BIT_1=3, BIT_2=4, BIT_3=5,
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                     BIT_4=6, BIT_5=7, BIT_6=8, BIT_7=9, STOP=10;
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    reg [3:0] tx_state = IDLE;
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    reg [7:0] TxD_data_r = 8'h00;    // Registered input data so it doesn't need to be held
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    assign ready = (tx_state == IDLE) || (tx_state == STOP);
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    always @(posedge clock) begin
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        TxD_data_r <= (ready & TxD_start) ? TxD_data : TxD_data_r;
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    end
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    always @(posedge clock) begin
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        if (reset) tx_state <= IDLE;
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        else begin
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            case (tx_state)
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                IDLE:   if (TxD_start) tx_state <= START;
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                START:  if (uart_tick) tx_state <= BIT_0;
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                BIT_0:  if (uart_tick) tx_state <= BIT_1;
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                BIT_1:  if (uart_tick) tx_state <= BIT_2;
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                BIT_2:  if (uart_tick) tx_state <= BIT_3;
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                BIT_3:  if (uart_tick) tx_state <= BIT_4;
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                BIT_4:  if (uart_tick) tx_state <= BIT_5;
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                BIT_5:  if (uart_tick) tx_state <= BIT_6;
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                BIT_6:  if (uart_tick) tx_state <= BIT_7;
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                BIT_7:  if (uart_tick) tx_state <= STOP;
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                STOP:   if (uart_tick) tx_state <= (TxD_start) ? START : IDLE;
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                default: tx_state <= 4'bxxxx;
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            endcase
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        end
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    end
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    always @(tx_state, TxD_data_r) begin
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        case (tx_state)
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            IDLE:   TxD <= 1;
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            START:  TxD <= 0;
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            BIT_0:  TxD <= TxD_data_r[0];
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            BIT_1:  TxD <= TxD_data_r[1];
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            BIT_2:  TxD <= TxD_data_r[2];
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            BIT_3:  TxD <= TxD_data_r[3];
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            BIT_4:  TxD <= TxD_data_r[4];
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            BIT_5:  TxD <= TxD_data_r[5];
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            BIT_6:  TxD <= TxD_data_r[6];
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            BIT_7:  TxD <= TxD_data_r[7];
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            STOP:   TxD <= 1;
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            default: TxD <= 1'bx;
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        endcase
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    end
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endmodule

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