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[/] [mips32r1/] [trunk/] [Software/] [demos/] [XD2_Timer/] [src/] [os/] [exceptions.asm] - Blame information for rev 2

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1 2 ayersg 
###############################################################################
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# TITLE: Exception Vectors
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# AUTHOR: Grant Ayers (ayers@cs.utah.edu)
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# DATE: 23 May 2012
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# FILENAME: exceptions.asm
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# PROJECT: University of Utah XUM Single Core
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# DESCRIPTION:
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#   Provides the exception vectors which jump to
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#   exception-handling routines.
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#
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###############################################################################
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        .text
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        .balign 4
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        .set    noreorder
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        .set    noat
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exc_save:
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        # Save all registers except k0 k1 sp ra
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        addiu   $sp, $sp, -112
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        sw      $1,    0($sp)
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        sw      $2,    4($sp)
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        sw      $3,    8($sp)
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        sw      $4,   12($sp)
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        sw      $5,   16($sp)
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        sw      $6,   20($sp)
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        sw      $7,   24($sp)
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        sw      $8,   28($sp)
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        sw      $9,   32($sp)
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        sw      $10,  36($sp)
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        sw      $11,  40($sp)
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        sw      $12,  44($sp)
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        sw      $13,  48($sp)
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        sw      $14,  52($sp)
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        sw      $15,  56($sp)
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        sw      $16,  60($sp)
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        sw      $17,  64($sp)
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        sw      $18,  68($sp)
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        sw      $19,  72($sp)
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        sw      $20,  76($sp)
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        sw      $21,  80($sp)
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        sw      $22,  84($sp)
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        sw      $23,  88($sp)
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        sw      $24,  92($sp)
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        sw      $25,  96($sp)
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        sw      $28, 100($sp)
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        jr      $ra
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        sw      $30, 104($sp)
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exc_restore:
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        # Restore all registers except k0 k1 sp ra
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        lw      $1,    0($sp)
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        lw      $2,    4($sp)
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        lw      $3,    8($sp)
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        lw      $4,   12($sp)
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        lw      $5,   16($sp)
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        lw      $6,   20($sp)
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        lw      $7,   24($sp)
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        lw      $8,   28($sp)
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        lw      $9,   32($sp)
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        lw      $10,  36($sp)
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        lw      $11,  40($sp)
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        lw      $12,  44($sp)
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        lw      $13,  48($sp)
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        lw      $14,  52($sp)
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        lw      $15,  56($sp)
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        lw      $16,  60($sp)
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        lw      $17,  64($sp)
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        lw      $18,  68($sp)
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        lw      $19,  72($sp)
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        lw      $20,  76($sp)
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        lw      $21,  80($sp)
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        lw      $22,  84($sp)
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        lw      $23,  88($sp)
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        lw      $24,  92($sp)
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        lw      $25,  96($sp)
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        lw      $28, 100($sp)
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        lw      $30, 104($sp)
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        jr      $ra
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        addiu   $sp, $sp, 112
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        .global mips32_general_exception
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        .ent    mips32_general_exception
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mips32_general_exception:
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        or      $26, $0, $ra
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        jal     exc_save
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        nop
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        mfc0    $27, $13, 0             # Read Cause which has ExcCode bits
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        srl     $27, $27, 2             # Extract exception code to $k1
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        andi    $27, $27, 0x001f
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        la      $ra, $end_exception     # Jump to the appropriate handler
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        addiu   $t0, $0, 4
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        addiu   $t1, $0, 5
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        addiu   $t2, $0, 8
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        addiu   $t3, $0, 9
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        beq     $t0, $27, mips32_handler_AdEL
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        addiu   $t0, $0, 10
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        beq     $t1, $27, mips32_handler_AdES
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        addiu   $t1, $0, 11
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        beq     $t2, $27, mips32_handler_Sys
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        addiu   $t2, $0, 12
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        beq     $t3, $27, mips32_handler_Bp
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        addiu   $t3, $0, 13
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        beq     $t0, $27, mips32_handler_RI
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        nop
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        beq     $t1, $27, mips32_handler_CpU
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        nop
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        beq     $t2, $27, mips32_handler_Ov
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        nop
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        beq     $t3, $27, mips32_handler_Tr
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        nop
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$end_exception:
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        jal     exc_restore
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        xor     $27, $0, $0
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        or      $ra, $0, $26
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        xor     $26, $0, $0
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        eret
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        .end    mips32_general_exception
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### "Special" Interrupt Vector: Cause_IV must be set.
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        .ent    mips32_interrupt_exception
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        .global mips32_interrupt_exception
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mips32_interrupt_exception:
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        mfc0    $26, $12, 0             # Status register for IM bits
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        mfc0    $27, $13, 0             # Cause register for IP bits
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        and     $26, $26, $27           # Extract pending, unmasked interrupts
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        srl     $26, $26, 8
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        andi    $26, $26, 0x00ff
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        addu    $27, $0, $ra
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        jal     exc_save
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        clz     $26, $26
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        la      $ra, $end_interrupt     # All C functions will return here
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        addiu   $t0, $0, 24
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        addiu   $t1, $0, 25
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        addiu   $t2, $0, 26
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        beq     $26, $t0, mips32_handler_HwInt5
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        addiu   $t0, $0, 27
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        beq     $26, $t1, mips32_handler_HwInt4
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        addiu   $t1, $0, 28
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        beq     $26, $t2, mips32_handler_HwInt3
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        addiu   $t2, $0, 29
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        beq     $26, $t0, mips32_handler_HwInt2
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        addiu   $t0, $0, 30
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        beq     $26, $t1, mips32_handler_HwInt1
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        addiu   $t1, $0, 31
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        beq     $26, $t2, mips32_handler_HwInt0
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        nop
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        beq     $26, $t0, mips32_handler_SwInt1
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        nop
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        beq     $26, $t1, mips32_handler_SwInt0
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        nop
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$end_interrupt:
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        jal     exc_restore
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        mfc0    $26, $9, 0              # Clear HwInt5 if applicable
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        or      $ra, $0, $27
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        eret
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        .end    mips32_interrupt_exception
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