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[/] [mips789/] [branches/] [avendor/] [CTool/] [gensim.c] - Blame information for rev 51

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1 35 mcupro 
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via,      *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
13 
 
14 10 mcupro 
#include "stdio.h"
15 
#include "stdlib.h"
16 
 
17 35 mcupro 
#define MAX_LEN (1024*2)
18 10 mcupro 
 
19 35 mcupro 
int print_module(FILE * ft){
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    if (ft==NULL)return 0;
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fprintf(ft,"//This file is only used for simulation.\nmodule sim_mem_array \n");
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fprintf(ft,"    ( \n");
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fprintf(ft,"        input clk, \n");
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fprintf(ft,"        input [31:0] pc_i, \n");
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fprintf(ft,"        output [31:0] ins_o, \n");
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fprintf(ft,"        input [3:0] wren, \n");
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fprintf(ft,"        input [31:0]din, \n");
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fprintf(ft,"        input [31:0]data_addr_i, \n");
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fprintf(ft,"        output [31:0]dout \n");
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fprintf(ft,"    ); \n\n");
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fprintf(ft,"    wire [29:0] data_addr,pc; \n");
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fprintf(ft,"    wire [31:0]dout_w; \n");
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fprintf(ft,"    assign dout = dout_w; \n");
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fprintf(ft,"    assign data_addr=data_addr_i[31:2]; \n");
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fprintf(ft,"    assign pc= pc_i[31:2]; \n\n");
36 10 mcupro 
 
37 35 mcupro 
 
38 
fprintf(ft,"    sim_syn_ram3 ram3 ( \n");
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fprintf(ft,"                     .data(din[31:24]), \n");
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fprintf(ft,"                     .wraddress(data_addr), \n");
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fprintf(ft,"                     .rdaddress_a(pc), \n");
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fprintf(ft,"                     .rdaddress_b(data_addr), \n");
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fprintf(ft,"                     .wren(wren[3]), \n");
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fprintf(ft,"                     .clock(clk), \n");
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fprintf(ft,"                     .qa(ins_o[31:24]), \n");
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fprintf(ft,"                     .qb(dout_w[31:24]) \n");
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fprintf(ft,"                 ); \n");
48 
 
49 
fprintf(ft,"    sim_syn_ram2 ram2( \n");
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fprintf(ft,"                     .data(din[23:16]), \n");
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fprintf(ft,"                     .wraddress(data_addr), \n");
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fprintf(ft,"                     .rdaddress_a(pc), \n");
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fprintf(ft,"                     .rdaddress_b(data_addr), \n");
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fprintf(ft,"                     .wren(wren[2]), \n");
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fprintf(ft,"                     .clock(clk), \n");
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fprintf(ft,"                     .qa(ins_o[23:16]), \n");
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fprintf(ft,"                     .qb(dout_w[23:16]) \n");
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fprintf(ft,"                 ); \n");
59 
 
60 
fprintf(ft,"    sim_syn_ram1 ram1( \n");
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fprintf(ft,"                     .data(din[15:8]), \n");
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fprintf(ft,"                     .wraddress(data_addr), \n");
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fprintf(ft,"                     .rdaddress_a(pc), \n");
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fprintf(ft,"                     .rdaddress_b(data_addr), \n");
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fprintf(ft,"                     .wren(wren[1]), \n");
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fprintf(ft,"                     .clock(clk), \n");
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fprintf(ft,"                     .qa(ins_o[15:8]), \n");
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fprintf(ft,"                     .qb(dout_w[15:8]) \n");
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fprintf(ft,"                 ); \n");
70 
 
71 
fprintf(ft,"    sim_syn_ram0 ram0( \n");
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fprintf(ft,"                     .data(din[7:0]), \n");
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fprintf(ft,"                     .wraddress(data_addr), \n");
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fprintf(ft,"                     .rdaddress_a(pc), \n");
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fprintf(ft,"                     .rdaddress_b(data_addr), \n");
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fprintf(ft,"                     .wren(wren[0]), \n");
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fprintf(ft,"                     .clock(clk), \n");
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fprintf(ft,"                     .qa(ins_o[7:0]), \n");
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fprintf(ft,"                     .qb(dout_w[7:0]) \n");
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fprintf(ft,"                 ); \n");
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fprintf(ft,"endmodule \n\n\n");
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return 1;
83 
    }
84 
 
85 15 mcupro 
/*Liwei 2007-8-29*/
86 10 mcupro 
 char HEX[]="0123456789ABCDEF" ;
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 char hex[]="0123456789abcdef" ;
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unsigned char hex2byte( char hex_char)
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{
90 
    unsigned char i ;
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    for(i=0;i<16;++i)if(HEX[i]==hex_char)return i ;
92 
    for(i=0;i<16;++i)if(hex[i]==hex_char)return i ;
93 
    return 0 ;
94 
}
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unsigned int par2u32(char*par)
96 
{
97 
    unsigned int i,ret=0 ;
98 
    if(par==NULL)return ;
99 
    if((0==strncmp(par,"0x",2))||(0==strncmp(par,"0X",2)))
100 35 mcupro 
    for(i=2;;++i)    {if(par[i]=='\0')return ret ;if(par[i]==' ')return ret ; ret=ret*16+hex2byte(par[i]);}
101 10 mcupro 
    else
102 35 mcupro 
    for(i=0;;++i)    {if(par[i]=='\0')return ret ;if(par[i]==' ')return ret ; ret=ret*10+hex2byte(par[i]);}
103 10 mcupro 
    return 0 ;
104 
}
105 
 
106 
main(int argc,char*argv[])
107 
{
108 
    int j=4,i=0,ii=0 ;
109 
    int cntr=0,base=0 ;
110 
 
111 
    char str1[100],str2[111];
112 15 mcupro 
 
113 10 mcupro 
    FILE*ff=fopen("code.txt","r");
114 
    FILE*ft=fopen("sim_ram.v","w");
115 
 
116 
    if(NULL!=argv[1])
117 
    base=par2u32(argv[1])/4;
118 35 mcupro 
    print_module(ft);
119 10 mcupro 
    for(j=0;j<4;++j)
120 
    {
121 
        cntr=-10 ;
122 
        fprintf(ft,"module sim_syn_ram%d(\n",j);
123 35 mcupro 
        fprintf(ft,"    input   [7:0]  data,\n");
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        fprintf(ft,"    input   [10:0]  wraddress,\n");
125 
        fprintf(ft,"    input   [10:0]  rdaddress_a,\n");
126 
        fprintf(ft,"    input   [10:0]  rdaddress_b,\n");
127 
        fprintf(ft,"    input     wren,\n");
128 
        fprintf(ft,"    input     clock,\n");
129 
        fprintf(ft,"    output  [7:0]  qa,\n");
130 
        fprintf(ft,"    output  [7:0]  qb\n");
131 
        fprintf(ft,"    );\n\n");
132 
 
133 10 mcupro 
        fprintf(ft,"    reg [7:0]  r_data;\n");
134 
        fprintf(ft,"    reg [10:0]  r_wraddress;\n");
135 
        fprintf(ft,"    reg [10:0]  r_rdaddress_a;\n");
136 
        fprintf(ft,"    reg [10:0]  r_rdaddress_b;\n");
137 
        fprintf(ft,"    reg   r_wren;\n");
138 35 mcupro 
 
139 10 mcupro 
        fprintf(ft,"    reg [7:0] mem_bank  [0:2047]  ;\n");
140 
        if(base!=0)
141 35 mcupro 
        fprintf(ft,"    \ninteger i;\n    initial begin\n        for(i=0;i<%d;i=1+i)\n         mem_bank[i] = 'h00;\n       ",base);
142 10 mcupro 
        else
143 35 mcupro 
        fprintf(ft,"    \ninitial begin   \n       ");
144 10 mcupro 
 
145 
        rewind(ff);
146 
        cntr=-10 ;
147 
        i=-1 ;
148 
 
149 
        while(fgets(str2,100,ff))
150 
        {
151 
            ++i ;
152 
            if(3==j)
153 
            {
154 
                str2[2]=0 ;
155 
                fprintf(ft,"mem_bank[%d] = 'h%s ; ",base+i,&str2[0]);
156 
                ++cntr ;
157 
                if(!(cntr%10))
158 
                {
159 
                    cntr=0 ;
160 
                    fprintf(ft,"\n       ");
161 
                }
162 
            }
163 
            else
164 
            if(2==j)
165 
            {
166 
                str2[4]=0 ;
167 
 
168 
                fprintf(ft,"mem_bank[%d] = 'h%s ; ",base+i,&str2[2]);
169 
 
170 
                ++cntr ;
171 
                if(!(cntr%10))
172 
                {
173 
                    cntr=0 ;
174 
                    fprintf(ft,"\n       ");
175 
                }
176 
            }
177 
            else
178 
            if(1==j)
179 
            {
180 
                str2[6]=0 ;
181 
                fprintf(ft,"mem_bank[%d] = 'h%s ; ",base+i,&str2[4]);
182 
 
183 
                ++cntr ;
184 
                if(!(cntr%10))
185 
                {
186 
                    cntr=0 ;
187 
                    fprintf(ft,"\n       ");
188 
                }
189 
            }
190 
            else
191 
            if(0==j)
192 
            {
193 
                str2[8]=0 ;
194 
                fprintf(ft,"mem_bank[%d] = 'h%s ; ",base+i,&str2[6]);
195 
 
196 
                ++cntr ;
197 
                if(!(cntr%10))
198 
                {
199 
                    cntr=0 ;
200 
                    fprintf(ft,"\n       ");
201 
                }
202 
            }
203 
        }
204 
        fprintf(ft,"    \n       end\n");
205 
        fprintf(ft,"    always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;\n");
206 
        fprintf(ft,"    always @ (posedge clock)\n");
207 
        fprintf(ft,"    begin\n");
208 
        fprintf(ft,"        r_data<=data;\n");
209 
        fprintf(ft,"        r_wraddress<=wraddress;\n");
210 
        fprintf(ft,"        r_rdaddress_a<=rdaddress_a;\n");
211 
        fprintf(ft,"        r_rdaddress_b<=rdaddress_b;\n");
212 
        fprintf(ft,"        r_wren<=wren;\n");
213 
        fprintf(ft,"    end\n");
214 35 mcupro 
        fprintf(ft,"    assign qa =(r_rdaddress_a>%d)?0:mem_bank[r_rdaddress_a];\n",base+i);
215 
        fprintf(ft,"    assign qb =(r_rdaddress_b>%d)?0:mem_bank[r_rdaddress_b];\n",base+i);
216 10 mcupro 
        fprintf(ft,"endmodule\n\n\n\n");
217 35 mcupro 
    }fclose(ft);
218 10 mcupro 
}

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