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[/] [mips789/] [branches/] [avendor/] [bench/] [MODELSIM/] [fifo.v] - Blame information for rev 53

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1 33 mcupro
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via       *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
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`include "mips789_defs.v"
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module sim_fifo512_cyclone ( //just uesd for simulation in EDA tools
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        data,
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        wrreq,
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        rdreq,
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        clock,
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        q,
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        full,
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        empty,
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        rst);
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    input       [7:0]  data;
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    input         rst;
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    input     wrreq;
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    input         rdreq;
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    input         clock;
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    output      [7:0]  q;
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    output        full;
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    output        empty;
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    fifo fifo_ff
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         (
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             .clk_i(clock),
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             .rst_i(rst),
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             .clear_i(1'b0),
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             .data_i(data),
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             .wen_i(wrreq),
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             .ren_i(rdreq),
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             .data_o(q),
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             .almost_full_o(),
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             .full_o(full),
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             .almost_empty_o(),
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             .empty_o(empty),
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             .cnt_o()
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         );
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endmodule
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//created by zhangfeifei
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//modifined only for simulating by liwei
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module fifo
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    (
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        clk_i,
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        rst_i,
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        clear_i,
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        data_i,
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        wen_i,
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        ren_i,
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        data_o,
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        almost_full_o,
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        full_o,
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        almost_empty_o,
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        empty_o,
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        cnt_o
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    );
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    parameter DATA_WIDTH    = 8;
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    parameter DEPTH         = 512;
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    parameter CNT_WIDTH     = 12;
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    input  clk_i;
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    input  rst_i;
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    input  clear_i;
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    input  wen_i;
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    input  [DATA_WIDTH-1:0] data_i;
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    input  ren_i;
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    output reg[DATA_WIDTH-1:0] data_o;
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    output almost_full_o;
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    output full_o;
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    output almost_empty_o;
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    output empty_o;
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    output [CNT_WIDTH-1:0] cnt_o;
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    reg    [DATA_WIDTH-1:0] mem[0:DEPTH-1];
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    reg    [CNT_WIDTH-1:0] cnt;
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    reg    [CNT_WIDTH-2:0] read_pointer;
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    reg    [CNT_WIDTH-2:0] write_pointer;
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    assign cnt_o = cnt;
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    integer i;
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    initial
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    begin
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        for(i=0;i<DEPTH;i=i+1)
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            mem[i] =0;
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    end
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    always @(posedge clk_i)
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    begin
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        if(~rst_i)
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            cnt <=  0;
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        else if(clear_i)
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            cnt <=  {{(CNT_WIDTH-1){1'b0}},ren_i^wen_i};
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        else if(ren_i ^ wen_i)
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        begin
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            if(ren_i & ~empty_o)
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                cnt <= cnt - 1'b1;
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            else if( wen_i & ~full_o)
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                cnt <= cnt + 1'b1;
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        end
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    end
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    always @(posedge clk_i)
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    begin
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        if(~rst_i)
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            read_pointer <= 0;
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        else if(clear_i)
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            read_pointer <= { {(CNT_WIDTH-2){1'b0}}, ren_i};
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        else if(ren_i & ~empty_o)
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            read_pointer <= read_pointer + 1'b1;
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    end
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    always @ (posedge clk_i )
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    begin
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        if(~rst_i)
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            write_pointer <= 0;
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        else if(clear_i)
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            write_pointer <= { {(CNT_WIDTH-2){1'b0}}, wen_i};
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        else if(wen_i & ~full_o)
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            write_pointer <= write_pointer + 1'b1;
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    end
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    assign empty_o = ~(|cnt);
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    assign almost_empty_o = cnt == 1;
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    assign full_o  = cnt == DEPTH;
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    assign almost_full_o  = &cnt[CNT_WIDTH-2:0];
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    always @ (posedge clk_i)
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    begin
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        if(wen_i & clear_i)
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            mem[0] <= data_i;
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        else if(wen_i & ~full_o)
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            mem[write_pointer] <= data_i;
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    end
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    always @ (posedge clk_i)
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        data_o <= clear_i ? mem[0] : mem[read_pointer];
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endmodule
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