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--N1_txd is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd at LC_X16_Y3_N2
--operation mode is normal
 
N1_txd_lut_out = N1_txd_1_a & N1_txd # !N1_txd_1_a & N1_txd_8 # !sys_rst;
N1_txd = DFFEAS(N1_txd_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--H1_N_62_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_62_i at LC_X34_Y14_N6
--operation mode is normal
 
F1_seg7data[7]_qfbk = F1_seg7data[7];
H1_N_62_i = F1_seg7data[7]_qfbk # F1_seg7data[6] & !F1_seg7data[4] # !F1_seg7data[5] # !F1_seg7data[6] & F1_seg7data[5];
 
--F1_seg7data[7] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[7] at LC_X34_Y14_N6
--operation mode is normal
 
F1_seg7data[7] = DFFEAS(H1_N_62_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_7, , !sys_rst, VCC);
 
 
--H1_N_60_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_60_i at LC_X34_Y14_N9
--operation mode is normal
 
F1_seg7data[6]_qfbk = F1_seg7data[6];
H1_N_60_i = F1_seg7data[7] & F1_seg7data[5] # !F1_seg7data[6]_qfbk # !F1_seg7data[7] & F1_seg7data[5] & F1_seg7data[6]_qfbk & !F1_seg7data[4] # !F1_seg7data[5] & F1_seg7data[6]_qfbk # !F1_seg7data[4];
 
--F1_seg7data[6] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[6] at LC_X34_Y14_N9
--operation mode is normal
 
F1_seg7data[6] = DFFEAS(H1_N_60_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_6, , !sys_rst, VCC);
 
 
--H1_N_58_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_58_i at LC_X34_Y14_N8
--operation mode is normal
 
F1_seg7data[5]_qfbk = F1_seg7data[5];
H1_N_58_i = F1_seg7data[5]_qfbk & F1_seg7data[7] # !F1_seg7data[4] # !F1_seg7data[5]_qfbk & F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[4];
 
--F1_seg7data[5] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[5] at LC_X34_Y14_N8
--operation mode is normal
 
F1_seg7data[5] = DFFEAS(H1_N_58_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_5, , !sys_rst, VCC);
 
 
--H1_m18_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18_0 at LC_X34_Y14_N5
--operation mode is normal
 
F1_seg7data[4]_qfbk = F1_seg7data[4];
H1_m18_0 = F1_seg7data[4]_qfbk & F1_seg7data[6] $ F1_seg7data[5] # !F1_seg7data[4]_qfbk & F1_seg7data[6] & F1_seg7data[5] # F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[7] # !F1_seg7data[5];
 
--F1_seg7data[4] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[4] at LC_X34_Y14_N5
--operation mode is normal
 
F1_seg7data[4] = DFFEAS(H1_m18_0, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_4, , !sys_rst, VCC);
 
 
--H1_m15_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15_0 at LC_X34_Y14_N4
--operation mode is normal
 
H1_m15_0 = F1_seg7data[6] & F1_seg7data[4] & !F1_seg7data[5] # !F1_seg7data[7] # !F1_seg7data[6] & F1_seg7data[4] # F1_seg7data[7] # !F1_seg7data[5];
 
 
--H1_m11_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11_0 at LC_X34_Y14_N7
--operation mode is normal
 
H1_m11_0 = F1_seg7data[5] & F1_seg7data[4] & !F1_seg7data[7] # !F1_seg7data[4] & !F1_seg7data[6] # !F1_seg7data[5] & F1_seg7data[4] $ !F1_seg7data[7] # !F1_seg7data[6];
 
 
--H1_N_44_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_44_i at LC_X34_Y14_N2
--operation mode is normal
 
H1_N_44_i = F1_seg7data[6] & F1_seg7data[7] & F1_seg7data[5] # !F1_seg7data[7] & F1_seg7data[4] # !F1_seg7data[6] & F1_seg7data[5] $ F1_seg7data[7] # !F1_seg7data[4];
 
 
--H1_N_31_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_31_i at LC_X34_Y13_N0
--operation mode is normal
 
F1_seg7data[3]_qfbk = F1_seg7data[3];
H1_N_31_i = F1_seg7data[3]_qfbk # F1_seg7data[2] & !F1_seg7data[0] # !F1_seg7data[1] # !F1_seg7data[2] & F1_seg7data[1];
 
--F1_seg7data[3] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[3] at LC_X34_Y13_N0
--operation mode is normal
 
F1_seg7data[3] = DFFEAS(H1_N_31_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_3, , !sys_rst, VCC);
 
 
--H1_N_29_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_29_i at LC_X34_Y13_N9
--operation mode is normal
 
F1_seg7data[2]_qfbk = F1_seg7data[2];
H1_N_29_i = F1_seg7data[1] & F1_seg7data[3] # !F1_seg7data[0] & F1_seg7data[2]_qfbk # !F1_seg7data[1] & F1_seg7data[2]_qfbk & !F1_seg7data[3] # !F1_seg7data[2]_qfbk & F1_seg7data[3] # !F1_seg7data[0];
 
--F1_seg7data[2] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[2] at LC_X34_Y13_N9
--operation mode is normal
 
F1_seg7data[2] = DFFEAS(H1_N_29_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_2, , !sys_rst, VCC);
 
 
--H1_N_27_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_27_i at LC_X34_Y13_N3
--operation mode is normal
 
F1_seg7data[1]_qfbk = F1_seg7data[1];
H1_N_27_i = F1_seg7data[1]_qfbk & F1_seg7data[3] # !F1_seg7data[0] # !F1_seg7data[1]_qfbk & F1_seg7data[2] & F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[0];
 
--F1_seg7data[1] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[1] at LC_X34_Y13_N3
--operation mode is normal
 
F1_seg7data[1] = DFFEAS(H1_N_27_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_1, , !sys_rst, VCC);
 
 
--H1_m18 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18 at LC_X34_Y13_N8
--operation mode is normal
 
F1_seg7data[0]_qfbk = F1_seg7data[0];
H1_m18 = F1_seg7data[0]_qfbk & F1_seg7data[2] $ F1_seg7data[1] # !F1_seg7data[0]_qfbk & F1_seg7data[2] & F1_seg7data[1] # F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[3] # !F1_seg7data[1];
 
--F1_seg7data[0] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[0] at LC_X34_Y13_N8
--operation mode is normal
 
F1_seg7data[0] = DFFEAS(H1_m18, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_0, , !sys_rst, VCC);
 
 
--H1_m15 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15 at LC_X34_Y13_N6
--operation mode is normal
 
H1_m15 = F1_seg7data[2] & !F1_seg7data[1] & F1_seg7data[0] # !F1_seg7data[3] # !F1_seg7data[2] & F1_seg7data[0] # F1_seg7data[3] # !F1_seg7data[1];
 
 
--H1_m11 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11 at LC_X34_Y13_N4
--operation mode is normal
 
H1_m11 = F1_seg7data[1] & F1_seg7data[0] & !F1_seg7data[3] # !F1_seg7data[0] & !F1_seg7data[2] # !F1_seg7data[1] & F1_seg7data[0] $ !F1_seg7data[3] # !F1_seg7data[2];
 
 
--H1_N_13_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_13_i at LC_X34_Y13_N2
--operation mode is normal
 
H1_N_13_i = F1_seg7data[2] & F1_seg7data[3] & F1_seg7data[1] # !F1_seg7data[3] & F1_seg7data[0] # !F1_seg7data[2] & F1_seg7data[1] $ F1_seg7data[3] # !F1_seg7data[0];
 
 
--F1_lcd_data_7 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_7 at LC_X34_Y7_N4
--operation mode is normal
 
F1_lcd_data_7_lut_out = CB1_r32_o_7;
F1_lcd_data_7 = DFFEAS(F1_lcd_data_7_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_6 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_6 at LC_X34_Y7_N7
--operation mode is normal
 
F1_lcd_data_6_lut_out = CB1_r32_o_6;
F1_lcd_data_6 = DFFEAS(F1_lcd_data_6_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_5 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_5 at LC_X34_Y7_N3
--operation mode is normal
 
F1_lcd_data_5_lut_out = CB1_r32_o_5;
F1_lcd_data_5 = DFFEAS(F1_lcd_data_5_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_4 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_4 at LC_X34_Y7_N8
--operation mode is normal
 
F1_lcd_data_4_lut_out = GND;
F1_lcd_data_4 = DFFEAS(F1_lcd_data_4_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, CB1_r32_o_4, , , VCC);
 
 
--F1_lcd_data_3 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_3 at LC_X34_Y7_N2
--operation mode is normal
 
F1_lcd_data_3_lut_out = CB1_r32_o_3;
F1_lcd_data_3 = DFFEAS(F1_lcd_data_3_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_2 at LC_X34_Y7_N5
--operation mode is normal
 
F1_lcd_data_2_lut_out = CB1_r32_o_2;
F1_lcd_data_2 = DFFEAS(F1_lcd_data_2_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_1 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_1 at LC_X34_Y7_N6
--operation mode is normal
 
F1_lcd_data_1_lut_out = CB1_r32_o_1;
F1_lcd_data_1 = DFFEAS(F1_lcd_data_1_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );
 
 
--F1_lcd_data_0 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0 at LC_X34_Y7_N1
--operation mode is normal
 
F1_lcd_data_0_lut_out = GND;
F1_lcd_data_0 = DFFEAS(F1_lcd_data_0_lut_out, GLOBAL(E1__clk0), VCC, , F1_lcd_data_0_sqmuxa_0_a2, CB1_r32_o_0, , , VCC);
 
 
--F1_cmd_4 is mips_sys:isys|mips_dvc:imips_dvc|cmd_4 at LC_X34_Y6_N2
--operation mode is normal
 
F1_cmd_4_lut_out = CB1_r32_o_4;
F1_cmd_4 = DFFEAS(F1_cmd_4_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd_5 is mips_sys:isys|mips_dvc:imips_dvc|cmd_5 at LC_X31_Y8_N6
--operation mode is normal
 
F1_cmd_5_lut_out = CB1_r32_o_5;
F1_cmd_5 = DFFEAS(F1_cmd_5_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd_6 is mips_sys:isys|mips_dvc:imips_dvc|cmd_6 at LC_X34_Y6_N8
--operation mode is normal
 
F1_cmd_6_lut_out = CB1_r32_o_6;
F1_cmd_6 = DFFEAS(F1_cmd_6_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--E1__clk0 is pll50:Ipll|altpll:altpll_component|_clk0 at PLL_1
E1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
 
 
--N1_txd_8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_8 at LC_X16_Y3_N6
--operation mode is normal
 
N1_txd_8 = N1_ua_state[2] & N1_tx_sr[0] # !N1_ua_state[2] & !N1_ua_state[1] # !N1_clk_ctr_equ15_0_a2;
 
 
--N1_txd_1_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_1_a at LC_X16_Y3_N3
--operation mode is normal
 
N1_txd_1_a = N1_ua_state_i[0] & !N1_bit_ctr23_i_0_o2 & !N1_ua_state[1] # !N1_clk_ctr_equ15_0_a2;
 
 
--CB1_dout_2_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_7 at LC_X15_Y4_N6
--operation mode is normal
 
CB1_dout_2_7 = ND1_dout7 & FD1_wb_o_7 # !ND1_dout7 & !ND1_dout_2_a_7;
 
--CB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_7 at LC_X15_Y4_N6
--operation mode is normal
 
CB1_r32_o_7 = DFFEAS(CB1_dout_2_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_lcd_data_0_sqmuxa_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2 at LC_X33_Y9_N0
--operation mode is normal
 
F1_lcd_data_0_sqmuxa_0_a2 = F1_wr_cmd_0_a2_0 & !AB1_r32_o_2 & AB1_r32_o_3 & F1_lcd_data_0_sqmuxa_0_a2_a;
 
 
--CB1_dout_2_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_6 at LC_X20_Y5_N6
--operation mode is normal
 
CB1_dout_2_6 = ND1_dout7 & FD1_wb_o_6 # !ND1_dout7 & !ND1_dout_2_a_6;
 
--CB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_6 at LC_X20_Y5_N6
--operation mode is normal
 
CB1_r32_o_6 = DFFEAS(CB1_dout_2_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_5 at LC_X29_Y14_N4
--operation mode is normal
 
CB1_dout_2_5 = ND1_dout7 & FD1_wb_o_5 # !ND1_dout7 & !ND1_dout_2_a_5;
 
--CB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_5 at LC_X29_Y14_N4
--operation mode is normal
 
CB1_r32_o_5 = DFFEAS(CB1_dout_2_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_4 at LC_X16_Y6_N5
--operation mode is normal
 
CB1_dout_2_4 = ND1_dout7 & FD1_wb_o_4 # !ND1_dout7 & !ND1_dout_2_a_4;
 
--CB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_4 at LC_X16_Y6_N5
--operation mode is normal
 
CB1_r32_o_4 = DFFEAS(CB1_dout_2_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_3 at LC_X16_Y6_N8
--operation mode is normal
 
CB1_dout_2_3 = ND1_dout7 & FD1_wb_o_3 # !ND1_dout7 & !ND1_dout_2_a_3;
 
--CB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_3 at LC_X16_Y6_N8
--operation mode is normal
 
CB1_r32_o_3 = DFFEAS(CB1_dout_2_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_2 at LC_X15_Y10_N2
--operation mode is normal
 
CB1_dout_2_2 = ND1_dout7 & FD1_wb_o_2 # !ND1_dout7 & !ND1_dout_2_a_2;
 
--CB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_2 at LC_X15_Y10_N2
--operation mode is normal
 
CB1_r32_o_2 = DFFEAS(CB1_dout_2_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_1 at LC_X25_Y2_N5
--operation mode is normal
 
CB1_dout_2_1 = ND1_dout7 & FD1_wb_o_1 # !ND1_dout7 & !ND1_dout_2_a_1;
 
--CB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_1 at LC_X25_Y2_N5
--operation mode is normal
 
CB1_r32_o_1 = DFFEAS(CB1_dout_2_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_0 at LC_X15_Y10_N4
--operation mode is normal
 
CB1_dout_2_0 = ND1_dout7 & FD1_wb_o_0 # !ND1_dout7 & !ND1_dout_2_a_0;
 
--CB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_0 at LC_X15_Y10_N4
--operation mode is normal
 
CB1_r32_o_0 = DFFEAS(CB1_dout_2_0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--C1_G_602 is mips_sys:isys|G_602 at LC_X33_Y9_N4
--operation mode is normal
 
C1_G_602 = F1_wr_cmd_0_a2_0 & F1_wr_tmr_data_0_a2_0 & !AB1_r32_o_3 # !sys_rst;
 
 
--r_rst is r_rst at LC_X33_Y13_N8
--operation mode is normal
 
r_rst_lut_out = GND;
r_rst = DFFEAS(r_rst_lut_out, GLOBAL(E1__clk0), VCC, , , rst, , , VCC);
 
 
--N1_ua_state[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[1] at LC_X16_Y3_N0
--operation mode is normal
 
N1_ua_state[1]_lut_out = U1_b_non_empty & !N1_clk_ctr_equ15_0_a2 & N1_ua_state[1] # !N1_ua_state_i[0] # !U1_b_non_empty & !N1_clk_ctr_equ15_0_a2 & N1_ua_state[1];
N1_ua_state[1] = DFFEAS(N1_ua_state[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--N1_ua_state[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[2] at LC_X16_Y3_N5
--operation mode is normal
 
N1_ua_state[2]_lut_out = N1_clk_ctr_equ15_0_a2 & N1_ua_state[1] # N1_ua_state_ns_0_a[2] & N1_ua_state[2] # !N1_clk_ctr_equ15_0_a2 & N1_ua_state[2];
N1_ua_state[2] = DFFEAS(N1_ua_state[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--N1_tx_sr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[0] at LC_X16_Y2_N9
--operation mode is normal
 
N1_tx_sr[0]_lut_out = N1_read_request_ff & Y1_q_b[0] # !N1_read_request_ff & N1_tx_sr[1];
N1_tx_sr[0] = DFFEAS(N1_tx_sr[0]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_clk_ctr_equ15_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2 at LC_X15_Y3_N0
--operation mode is normal
 
N1_clk_ctr_equ15_0_a2 = N1_clk_ctr_equ15_0_a2_7 & N1_clk_ctr26_i_0_a2;
 
 
--N1_ua_state_i[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_i[0] at LC_X16_Y3_N8
--operation mode is normal
 
N1_ua_state_i[0]_lut_out = !N1_ua_state[7] & U1_b_non_empty # N1_ua_state_i[0];
N1_ua_state_i[0] = DFFEAS(N1_ua_state_i[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--N1_bit_ctr23_i_0_o2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_0_o2 at LC_X16_Y3_N9
--operation mode is normal
 
N1_bit_ctr23_i_0_o2 = N1_ua_state[3] # N1_ua_state[2];
 
 
--C1_G_594 is mips_sys:isys|G_594 at LC_X33_Y9_N5
--operation mode is normal
 
C1_G_594 = !AB1_r32_o_3 & C1_G_594_a & F1_wr_cmd_0_a2_0 # !sys_rst;
 
 
--FD1_wb_o_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_7 at LC_X30_Y8_N6
--operation mode is normal
 
FD1_wb_o_7 = TC1_wb_mux_ctl_o_0 & F1_dout_7 # DB1_r32_o_7 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_7;
 
--FD1_r_data_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_7 at LC_X30_Y8_N6
--operation mode is normal
 
FD1_r_data_7 = DFFEAS(FD1_wb_o_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_7 at LC_X15_Y4_N5
--operation mode is normal
 
ND1_dout_2_a_7 = XD1_mux_fw_1 & !AB1_r32_o_5 # !XD1_mux_fw_1 & !QB1_r32_o_7;
 
 
--ND1_dout7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7 at LC_X21_Y12_N8
--operation mode is normal
 
ND1_dout7 = !WD1_un30_mux_fw & MC1_wb_we_o_0 & !XD1_mux_fw_1 & !XD1_un17_mux_fw_NE;
 
 
--AB1_c_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_2 at LC_X16_Y16_N6
--operation mode is normal
 
AB1_c_2 = MD1_c_1_4 # UD1_shift_out_4 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add4;
 
--AB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_2 at LC_X16_Y16_N6
--operation mode is normal
 
AB1_r32_o_2 = DFFEAS(AB1_c_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_3 at LC_X13_Y11_N4
--operation mode is normal
 
AB1_c_3 = MD1_c_2_5 # UD1_shift_out_5 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add5;
 
--AB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_3 at LC_X13_Y11_N4
--operation mode is normal
 
AB1_r32_o_3 = DFFEAS(AB1_c_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_lcd_data_0_sqmuxa_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2_a at LC_X33_Y9_N3
--operation mode is normal
 
F1_lcd_data_0_sqmuxa_0_a2_a = sys_rst & !AB1_r32_o_1 & !JC1_dmem_ctl_o_2 & AB1_r32_o_0;
 
 
--F1_wr_cmd_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_cmd_0_a2_0 at LC_X33_Y9_N8
--operation mode is normal
 
JC1_dmem_ctl_o_0_qfbk = JC1_dmem_ctl_o_0;
F1_wr_cmd_0_a2_0 = !JC1_dmem_ctl_o_1 & JC1_dmem_ctl_o_0_qfbk & F1_rd_uartdata_0_a2_0;
 
--JC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_0 at LC_X33_Y9_N8
--operation mode is normal
 
JC1_dmem_ctl_o_0 = DFFEAS(F1_wr_cmd_0_a2_0, GLOBAL(E1__clk0), VCC, , , QC1_dmem_ctl_o_0, , , VCC);
 
 
--FD1_wb_o_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_6 at LC_X32_Y7_N8
--operation mode is normal
 
FD1_wb_o_6 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_6 # F1_dout_6 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_6;
 
--FD1_r_data_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_6 at LC_X32_Y7_N8
--operation mode is normal
 
FD1_r_data_6 = DFFEAS(FD1_wb_o_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_6 at LC_X20_Y5_N0
--operation mode is normal
 
ND1_dout_2_a_6 = XD1_mux_fw_1 & !AB1_r32_o_4 # !XD1_mux_fw_1 & !QB1_r32_o_6;
 
 
--FD1_wb_o_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_5 at LC_X29_Y14_N5
--operation mode is normal
 
FD1_wb_o_5 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_5 # F1_dout_5 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_5;
 
--FD1_r_data_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_5 at LC_X29_Y14_N5
--operation mode is normal
 
FD1_r_data_5 = DFFEAS(FD1_wb_o_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_5 at LC_X29_Y14_N3
--operation mode is normal
 
ND1_dout_2_a_5 = XD1_mux_fw_1 & !AB1_r32_o_3 # !XD1_mux_fw_1 & !QB1_r32_o_5;
 
 
--FD1_wb_o_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_4 at LC_X30_Y14_N7
--operation mode is normal
 
FD1_wb_o_4 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_4 # F1_dout_4 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_4;
 
--FD1_r_data_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_4 at LC_X30_Y14_N7
--operation mode is normal
 
FD1_r_data_4 = DFFEAS(FD1_wb_o_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_4 at LC_X16_Y6_N3
--operation mode is normal
 
ND1_dout_2_a_4 = XD1_mux_fw_1 & !AB1_r32_o_2 # !XD1_mux_fw_1 & !QB1_r32_o_4;
 
 
--FD1_wb_o_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_3 at LC_X31_Y6_N2
--operation mode is normal
 
FD1_wb_o_3 = TC1_wb_mux_ctl_o_0 & F1_dout_3 # DB1_r32_o_3 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_3;
 
--FD1_r_data_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_3 at LC_X31_Y6_N2
--operation mode is normal
 
FD1_r_data_3 = DFFEAS(FD1_wb_o_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_3 at LC_X16_Y6_N2
--operation mode is normal
 
ND1_dout_2_a_3 = XD1_mux_fw_1 & !AB1_r32_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_3;
 
 
--FD1_wb_o_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_2 at LC_X33_Y7_N8
--operation mode is normal
 
FD1_wb_o_2 = TC1_wb_mux_ctl_o_0 & F1_dout_2 # DB1_r32_o_2 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_2;
 
--FD1_r_data_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_2 at LC_X33_Y7_N8
--operation mode is normal
 
FD1_r_data_2 = DFFEAS(FD1_wb_o_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_2 at LC_X15_Y10_N5
--operation mode is normal
 
ND1_dout_2_a_2 = XD1_mux_fw_1 & !AB1_r32_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_2;
 
 
--FD1_wb_o_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_1 at LC_X20_Y9_N6
--operation mode is normal
 
FD1_wb_o_1 = TC1_wb_mux_ctl_o_0 & F1_dout_1 # DB1_r32_o_1 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_1;
 
--FD1_r_data_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_1 at LC_X20_Y9_N6
--operation mode is normal
 
FD1_r_data_1 = DFFEAS(FD1_wb_o_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_1 at LC_X25_Y2_N4
--operation mode is normal
 
ND1_dout_2_a_1 = XD1_mux_fw_1 & !RB1_byte_addr_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_1;
 
 
--FD1_wb_o_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_0 at LC_X31_Y7_N2
--operation mode is normal
 
FD1_wb_o_0 = TC1_wb_mux_ctl_o_0 & F1_dout_0 # DB1_r32_o_0 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_0;
 
--FD1_r_data_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_0 at LC_X31_Y7_N2
--operation mode is normal
 
FD1_r_data_0 = DFFEAS(FD1_wb_o_0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_0 at LC_X15_Y10_N3
--operation mode is normal
 
ND1_dout_2_a_0 = XD1_mux_fw_1 & !RB1_byte_addr_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_0;
 
 
--F1_wr_tmr_data_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2_0 at LC_X33_Y9_N7
--operation mode is normal
 
JC1_dmem_ctl_o_2_qfbk = JC1_dmem_ctl_o_2;
F1_wr_tmr_data_0_a2_0 = AB1_r32_o_0 & AB1_r32_o_2 & JC1_dmem_ctl_o_2_qfbk & !AB1_r32_o_1;
 
--JC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_2 at LC_X33_Y9_N7
--operation mode is normal
 
JC1_dmem_ctl_o_2 = DFFEAS(F1_wr_tmr_data_0_a2_0, GLOBAL(E1__clk0), VCC, , , QC1_dmem_ctl_o_2, , , VCC);
 
 
--U1_b_non_empty is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty at LC_X22_Y2_N3
--operation mode is normal
 
U1_b_non_empty_lut_out = U1_b_full # F1_wr_uartdata_0_a2 # U1L9 & U1_b_non_empty;
U1_b_non_empty = DFFEAS(U1_b_non_empty_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--N1_ua_state_ns_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_ns_0_a[2] at LC_X15_Y3_N6
--operation mode is normal
 
N1_ua_state_ns_0_a[2] = !N1_bit_ctr[0] # !N1_bit_ctr[1] # !N1_bit_ctr[2];
 
 
--Y1_q_b[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[0] at M4K_X17_Y2
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 512, Port B Width: 8
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[0] = Y1_q_b[0]_PORT_B_data_out[0];
 
--Y1_q_b[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[7] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[7] = Y1_q_b[0]_PORT_B_data_out[7];
 
--Y1_q_b[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[6] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[6] = Y1_q_b[0]_PORT_B_data_out[6];
 
--Y1_q_b[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[5] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[5] = Y1_q_b[0]_PORT_B_data_out[5];
 
--Y1_q_b[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[4] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[4] = Y1_q_b[0]_PORT_B_data_out[4];
 
--Y1_q_b[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[3] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[3] = Y1_q_b[0]_PORT_B_data_out[3];
 
--Y1_q_b[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[2] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[2] = Y1_q_b[0]_PORT_B_data_out[2];
 
--Y1_q_b[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[1] at M4K_X17_Y2
Y1_q_b[0]_PORT_A_data_in = BUS(CB1_r32_o_0, CB1_r32_o_1, CB1_r32_o_2, CB1_r32_o_3, CB1_r32_o_4, CB1_r32_o_5, CB1_r32_o_6, CB1_r32_o_7);
Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);
Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);
Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;
Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );
Y1_q_b[0]_PORT_B_read_enable = VCC;
Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);
Y1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_1 = GLOBAL(E1__clk0);
Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;
Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );
Y1_q_b[1] = Y1_q_b[0]_PORT_B_data_out[1];
 
 
--N1_tx_sr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[1] at LC_X16_Y2_N3
--operation mode is normal
 
N1_tx_sr[1]_lut_out = N1_read_request_ff & Y1_q_b[1] # !N1_read_request_ff & N1_tx_sr[2];
N1_tx_sr[1] = DFFEAS(N1_tx_sr[1]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_read_request_ff is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|read_request_ff at LC_X16_Y2_N6
--operation mode is normal
 
N1_read_request_ff_lut_out = U1_b_non_empty & !N1_ua_state_i[0];
N1_read_request_ff = DFFEAS(N1_read_request_ff_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--C1_G_586 is mips_sys:isys|G_586 at LC_X16_Y2_N7
--operation mode is normal
 
C1_G_586 = N1_read_request_ff # N1_bit_ctr23_i_0_o2 & N1_clk_ctr_equ15_0_a2 # !sys_rst;
 
 
--N1_clk_ctr26_i_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a2 at LC_X15_Y1_N9
--operation mode is normal
 
N1_clk_ctr26_i_0_a2 = N1_clk_ctr[0] & N1_clk_ctr26_i_0_a2_a & !N1_clk_ctr[15] & !N1_clk_ctr[6];
 
 
--N1_clk_ctr_equ15_0_a2_7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_7 at LC_X15_Y3_N4
--operation mode is normal
 
N1_clk_ctr_equ15_0_a2_7 = N1_clk_ctr[4] & N1_clk_ctr_equ15_0_a2_4 & N1_clk_ctr_equ15_0_a2_7_a & !N1_clk_ctr[5];
 
 
--N1_ua_state[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[7] at LC_X16_Y3_N1
--operation mode is normal
 
N1_ua_state[7]_lut_out = N1_ua_state[6] & N1_clk_ctr_equ15_0_a2;
N1_ua_state[7] = DFFEAS(N1_ua_state[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--N1_ua_state[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[3] at LC_X16_Y3_N4
--operation mode is normal
 
N1_ua_state[3]_lut_out = N1_ua_state[3] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state[3] & !N1_ua_state_ns_0_a[2] & N1_clk_ctr_equ15_0_a2 & N1_ua_state[2];
N1_ua_state[3] = DFFEAS(N1_ua_state[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--C1_G_594_a is mips_sys:isys|G_594_a at LC_X33_Y9_N9
--operation mode is normal
 
C1_G_594_a = !JC1_dmem_ctl_o_2 & AB1_r32_o_2 & AB1_r32_o_1 & AB1_r32_o_0;
 
 
--F1_dout_7 is mips_sys:isys|mips_dvc:imips_dvc|dout_7 at LC_X30_Y8_N0
--operation mode is normal
 
F1_dout_7_lut_out = K1_cntr_7 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[7];
F1_dout_7 = DFFEAS(F1_dout_7_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_7 at LC_X30_Y8_N3
--operation mode is normal
 
BB1_r32_o_7_lut_out = GND;
BB1_r32_o_7 = DFFEAS(BB1_r32_o_7_lut_out, GLOBAL(E1__clk0), VCC, , , AB1_r32_o_5, , , VCC);
 
 
--TC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18|wb_mux_ctl_o_0 at LC_X29_Y7_N7
--operation mode is normal
 
TC1_wb_mux_ctl_o_0_lut_out = WC1_wb_mux_ctl_o_0;
TC1_wb_mux_ctl_o_0 = DFFEAS(TC1_wb_mux_ctl_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_7 at LC_X23_Y5_N9
--operation mode is normal
 
QB1_dout_iv_7 = GD1_dout_iv_1_7 # GD1_dout7_0_a2 & FD1_wb_o_7;
 
--QB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_7 at LC_X23_Y5_N9
--operation mode is normal
 
QB1_r32_o_7 = DFFEAS(QB1_dout_iv_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_5 at LC_X15_Y12_N1
--operation mode is normal
 
AB1_c_5 = MD1_c_0_6 # UD1_shift_out_sn_m31_i & !MD1_c_a_7 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_6;
 
--AB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_5 at LC_X15_Y12_N1
--operation mode is normal
 
AB1_r32_o_5 = DFFEAS(AB1_c_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--XD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1 at LC_X21_Y12_N4
--operation mode is normal
 
XD1_mux_fw_1 = !XD1_un1_mux_fw_NE_2 & !XD1_mux_fw_1_a & !XD1_un1_mux_fw_NE_1 & !WD1_un14_mux_fw;
 
 
--MC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12|wb_we_o_0 at LC_X27_Y12_N8
--operation mode is normal
 
MC1_wb_we_o_0_lut_out = VC1_wb_we_o_0 # XC1_wb_we_o_0;
MC1_wb_we_o_0 = DFFEAS(MC1_wb_we_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--WD1_un30_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un30_mux_fw at LC_X25_Y9_N6
--operation mode is normal
 
NB1_r5_o_3_qfbk = NB1_r5_o_3;
WD1_un30_mux_fw = !NB1_r5_o_0 & !NB1_r5_o_1 & !NB1_r5_o_3_qfbk & WD1_un30_mux_fw_a;
 
--NB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_3 at LC_X25_Y9_N6
--operation mode is normal
 
NB1_r5_o_3 = DFFEAS(WD1_un30_mux_fw, GLOBAL(E1__clk0), VCC, , , MB1_r5_o_3, , , VCC);
 
 
--XD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE at LC_X21_Y12_N0
--operation mode is normal
 
XD1_un17_mux_fw_NE = XD1_un17_mux_fw_NE_1 # XD1_un17_mux_fw_NE_a # NB1_r5_o_4 $ BE1_q_4;
 
 
--TD1_alu_out_sn_m14_0_0_a4_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4_0 at LC_X13_Y15_N2
--operation mode is normal
 
RC1_alu_func_o_4_qfbk = RC1_alu_func_o_4;
TD1_alu_out_sn_m14_0_0_a4_0 = !RC1_alu_func_o_4_qfbk & !TD1_alu_out_sn_m14_0_0_a4_0_a & RC1_alu_func_o_1 # !RC1_alu_func_o_0;
 
--RC1_alu_func_o_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_4 at LC_X13_Y15_N2
--operation mode is normal
 
RC1_alu_func_o_4 = DFFEAS(TD1_alu_out_sn_m14_0_0_a4_0, GLOBAL(E1__clk0), VCC, , , ZC1_alu_func_o_4, , !AD1_NET1640_i, VCC);
 
 
--MD1_c_1_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_4 at LC_X8_Y12_N9
--operation mode is normal
 
MD1_c_1_4 = MD1_c_0_Z[4] # TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0_m2_1;
 
 
--TD1_un1_a_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add4 at LC_X12_Y10_N9
--operation mode is arithmetic
 
TD1_un1_a_add4_carry_eqn = (!TD1_un1_a_add0_start_cout & TD1_un1_a_carry_3) # (TD1_un1_a_add0_start_cout & TD1L815);
TD1_un1_a_add4 = PD1_a_o_4 $ TD1_un1_b_1_combout[4] $ !TD1_un1_a_add4_carry_eqn;
 
--TD1_un1_a_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_4 at LC_X12_Y10_N9
--operation mode is arithmetic
 
TD1_un1_a_carry_4 = CARRY(PD1_a_o_4 & TD1_un1_b_1_combout[4] # !TD1L815 # !PD1_a_o_4 & TD1_un1_b_1_combout[4] & !TD1L815);
 
 
--UD1_shift_out_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_4 at LC_X16_Y16_N5
--operation mode is normal
 
UD1_shift_out_4 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[4] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[4];
 
 
--MD1_c_2_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_5 at LC_X13_Y11_N5
--operation mode is normal
 
MD1_c_2_5 = MD1_c_0_Z[5] # TD1_alu_out_sn_m14_0_0 & MD1_c_2_a[5] # TD1_alu_out_7_0_0_m2_2;
 
 
--TD1_un1_a_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add5 at LC_X12_Y9_N0
--operation mode is arithmetic
 
TD1_un1_a_add5_carry_eqn = TD1_un1_a_carry_4;
TD1_un1_a_add5 = PD1_a_o_5 $ TD1_un1_b_1_combout[5] $ TD1_un1_a_add5_carry_eqn;
 
--TD1_un1_a_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_5 at LC_X12_Y9_N0
--operation mode is arithmetic
 
TD1_un1_a_carry_5_cout_0 = PD1_a_o_5 & !TD1_un1_b_1_combout[5] & !TD1_un1_a_carry_4 # !PD1_a_o_5 & !TD1_un1_a_carry_4 # !TD1_un1_b_1_combout[5];
TD1_un1_a_carry_5 = CARRY(TD1_un1_a_carry_5_cout_0);
 
--TD1L125 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_5~COUT1_1 at LC_X12_Y9_N0
--operation mode is arithmetic
 
TD1L125_cout_1 = PD1_a_o_5 & !TD1_un1_b_1_combout[5] & !TD1_un1_a_carry_4 # !PD1_a_o_5 & !TD1_un1_a_carry_4 # !TD1_un1_b_1_combout[5];
TD1L125 = CARRY(TD1L125_cout_1);
 
 
--UD1_shift_out_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_5 at LC_X13_Y11_N3
--operation mode is normal
 
UD1_shift_out_5 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[5] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[5];
 
 
--AB1_c_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_0 at LC_X19_Y17_N8
--operation mode is normal
 
AB1_c_0 = MD1_c_0_1 # UD1_shift_out_sn_m31_i & !MD1_c_a_2 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_1;
 
--AB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_0 at LC_X19_Y17_N8
--operation mode is normal
 
AB1_r32_o_0 = DFFEAS(AB1_c_0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_1 at LC_X15_Y15_N5
--operation mode is normal
 
AB1_c_1 = UD1_shift_out_3 # MD1_c_1_3 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add3;
 
--AB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_1 at LC_X15_Y15_N5
--operation mode is normal
 
AB1_r32_o_1 = DFFEAS(AB1_c_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_rd_uartdata_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|rd_uartdata_0_a2_0 at LC_X28_Y6_N7
--operation mode is normal
 
F1_rd_uartdata_0_a2_0 = F1_dout_0_0_a3_6_5_9[0] & F1_dout_0_0_a3_6_5_12[0] & F1_rd_status_29_0_a2_0_8 & F1_rd_uartdata_0_a2_0_a;
 
 
--F1_dout_6 is mips_sys:isys|mips_dvc:imips_dvc|dout_6 at LC_X32_Y7_N2
--operation mode is normal
 
F1_dout_6_lut_out = K1_cntr_6 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[6];
F1_dout_6 = DFFEAS(F1_dout_6_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_6 at LC_X32_Y7_N5
--operation mode is normal
 
BB1_r32_o_6_lut_out = AB1_r32_o_4;
BB1_r32_o_6 = DFFEAS(BB1_r32_o_6_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_6 at LC_X24_Y7_N8
--operation mode is normal
 
QB1_dout_iv_6 = GD1_dout_iv_1_6 # FD1_wb_o_6 & GD1_dout7_0_a2;
 
--QB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_6 at LC_X24_Y7_N8
--operation mode is normal
 
QB1_r32_o_6 = DFFEAS(QB1_dout_iv_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_4 at LC_X19_Y15_N6
--operation mode is normal
 
AB1_c_4 = UD1_shift_out_sn_m31_i & UD1_shift_out_92_0 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_5 # !MD1_c_a_6;
 
--AB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_4 at LC_X19_Y15_N6
--operation mode is normal
 
AB1_r32_o_4 = DFFEAS(AB1_c_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_5 is mips_sys:isys|mips_dvc:imips_dvc|dout_5 at LC_X29_Y14_N2
--operation mode is normal
 
F1_dout_5_lut_out = K1_cntr_5 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[5];
F1_dout_5 = DFFEAS(F1_dout_5_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_5 at LC_X29_Y14_N6
--operation mode is normal
 
BB1_r32_o_5_lut_out = GND;
BB1_r32_o_5 = DFFEAS(BB1_r32_o_5_lut_out, GLOBAL(E1__clk0), VCC, , , AB1_r32_o_3, , , VCC);
 
 
--QB1_dout_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_5 at LC_X20_Y7_N7
--operation mode is normal
 
QB1_dout_iv_5 = GD1_dout_iv_1_5 # GD1_dout7_0_a2 & FD1_wb_o_5;
 
--QB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_5 at LC_X20_Y7_N7
--operation mode is normal
 
QB1_r32_o_5 = DFFEAS(QB1_dout_iv_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_4 is mips_sys:isys|mips_dvc:imips_dvc|dout_4 at LC_X30_Y14_N3
--operation mode is normal
 
F1_dout_4_lut_out = K1_cntr_4 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[4];
F1_dout_4 = DFFEAS(F1_dout_4_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_4 at LC_X30_Y14_N9
--operation mode is normal
 
BB1_r32_o_4_lut_out = AB1_r32_o_2;
BB1_r32_o_4 = DFFEAS(BB1_r32_o_4_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_4 at LC_X21_Y7_N3
--operation mode is normal
 
QB1_dout_iv_4 = GD1_dout_iv_1_4 # FD1_wb_o_4 & GD1_dout7_0_a2;
 
--QB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_4 at LC_X21_Y7_N3
--operation mode is normal
 
QB1_r32_o_4 = DFFEAS(QB1_dout_iv_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_3 is mips_sys:isys|mips_dvc:imips_dvc|dout_3 at LC_X31_Y6_N1
--operation mode is normal
 
F1_dout_3_lut_out = F1_dout_0_0_a3_0[3] # K1_cntr_3 & F1_dout_0_0_a3_4[0] # !L1_dout_0_0_a_0;
F1_dout_3 = DFFEAS(F1_dout_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_3 at LC_X31_Y6_N0
--operation mode is normal
 
BB1_r32_o_3_lut_out = AB1_r32_o_1;
BB1_r32_o_3 = DFFEAS(BB1_r32_o_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_3 at LC_X26_Y7_N6
--operation mode is normal
 
QB1_dout_iv_3 = GD1_dout_iv_1_3 # FD1_wb_o_3 & GD1_dout7_0_a2;
 
--QB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_3 at LC_X26_Y7_N6
--operation mode is normal
 
QB1_r32_o_3 = DFFEAS(QB1_dout_iv_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_2 is mips_sys:isys|mips_dvc:imips_dvc|dout_2 at LC_X33_Y7_N6
--operation mode is normal
 
F1_dout_2_lut_out = F1_dout_0_0_a3_0[2] # F1_dout_0_0_a3_4[0] & K1_cntr_2 # !F1_dout_0_0_a[2];
F1_dout_2 = DFFEAS(F1_dout_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_2 at LC_X33_Y7_N2
--operation mode is normal
 
BB1_r32_o_2_lut_out = AB1_r32_o_0;
BB1_r32_o_2 = DFFEAS(BB1_r32_o_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_2 at LC_X21_Y8_N3
--operation mode is normal
 
QB1_dout_iv_2 = GD1_dout_iv_1_2 # FD1_wb_o_2 & GD1_dout7_0_a2;
 
--QB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_2 at LC_X21_Y8_N3
--operation mode is normal
 
QB1_r32_o_2 = DFFEAS(QB1_dout_iv_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_1 is mips_sys:isys|mips_dvc:imips_dvc|dout_1 at LC_X33_Y6_N8
--operation mode is normal
 
F1_dout_1_lut_out = F1_dout_0_0_a3_0[1] # F1_dout_0_0_a3_4[0] & K1_cntr_1 # !F1_dout_0_0_a[1];
F1_dout_1 = DFFEAS(F1_dout_1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_1 at LC_X20_Y9_N7
--operation mode is normal
 
BB1_r32_o_1_lut_out = RB1_byte_addr_o_1;
BB1_r32_o_1 = DFFEAS(BB1_r32_o_1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_1 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_1 at LC_X25_Y7_N9
--operation mode is normal
 
QB1_dout_iv_1 = GD1_dout_iv_1_1 # FD1_wb_o_1 & GD1_dout7_0_a2;
 
--QB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_1 at LC_X25_Y7_N9
--operation mode is normal
 
QB1_r32_o_1 = DFFEAS(QB1_dout_iv_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RB1_c_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_1 at LC_X13_Y9_N1
--operation mode is normal
 
RB1_c_1 = MD1_c_0_0 # UD1_shift_out_sn_m31_i & !MD1_c_a_1 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_0;
 
--RB1_byte_addr_o_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|byte_addr_o_1 at LC_X13_Y9_N1
--operation mode is normal
 
RB1_byte_addr_o_1 = DFFEAS(RB1_c_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_0 is mips_sys:isys|mips_dvc:imips_dvc|dout_0 at LC_X31_Y7_N9
--operation mode is normal
 
F1_dout_0_lut_out = F1_dout_0_0_a3_0[0] # K1_cntr_0 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[0];
F1_dout_0 = DFFEAS(F1_dout_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_0 at LC_X31_Y7_N7
--operation mode is normal
 
BB1_r32_o_0_lut_out = RB1_byte_addr_o_0;
BB1_r32_o_0 = DFFEAS(BB1_r32_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_0 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_0 at LC_X25_Y7_N4
--operation mode is normal
 
QB1_dout_iv_0 = GD1_dout_iv_1_0 # GD1_dout7_0_a2 & FD1_wb_o_0;
 
--QB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_0 at LC_X25_Y7_N4
--operation mode is normal
 
QB1_r32_o_0 = DFFEAS(QB1_dout_iv_0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RB1_c_0_d0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_0_d0 at LC_X14_Y9_N3
--operation mode is normal
 
RB1_c_0_d0 = MD1_c_2_0 # UD1_shift_out_0 # TD1_alu_out_9_a2_0 # !MD1_c_a_0;
 
--RB1_byte_addr_o_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|byte_addr_o_0 at LC_X14_Y9_N3
--operation mode is normal
 
RB1_byte_addr_o_0 = DFFEAS(RB1_c_0_d0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_wr_uartdata_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2 at LC_X22_Y2_N7
--operation mode is normal
 
F1_wr_uartdata_0_a2 = F1_rd_uartdata_0_a2_0 & F1_wr_uartdata_0_a2_1 & F1_wr_uartdata_0_a2_a & AB1_r32_o_3;
 
 
--U1_b_full is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full at LC_X22_Y2_N4
--operation mode is normal
 
U1_b_full_lut_out = !N1_ua_state_ns_0_a2_0[1] & U1_b_full # U1L3 & U1_b_non_empty;
U1_b_full = DFFEAS(U1_b_full_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--X1_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[1] at LC_X21_Y2_N1
--operation mode is arithmetic
 
X1_safe_q[1]_lut_out = X1_safe_q[1] $ X1L2;
X1_safe_q[1] = DFFEAS(X1_safe_q[1]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella1~COUT at LC_X21_Y2_N1
--operation mode is arithmetic
 
X1L5_cout_0 = T1_valid_wreq $ X1_safe_q[1] # !X1L2;
X1L5 = CARRY(X1L5_cout_0);
 
--X1L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella1~COUTCOUT1_1 at LC_X21_Y2_N1
--operation mode is arithmetic
 
X1L6_cout_1 = T1_valid_wreq $ X1_safe_q[1] # !X1L3;
X1L6 = CARRY(X1L6_cout_1);
 
 
--X1_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[8] at LC_X21_Y2_N8
--operation mode is normal
 
X1_safe_q[8]_carry_eqn = (!X1L41 & X1L42) # (X1L41 & X1L52);
X1_safe_q[8]_lut_out = X1_safe_q[8] $ !X1_safe_q[8]_carry_eqn;
X1_safe_q[8] = DFFEAS(X1_safe_q[8]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
 
--X1_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[7] at LC_X21_Y2_N7
--operation mode is arithmetic
 
X1_safe_q[7]_carry_eqn = (!X1L41 & X1L12) # (X1L41 & X1L22);
X1_safe_q[7]_lut_out = X1_safe_q[7] $ (X1_safe_q[7]_carry_eqn);
X1_safe_q[7] = DFFEAS(X1_safe_q[7]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L42 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella7~COUT at LC_X21_Y2_N7
--operation mode is arithmetic
 
X1L42_cout_0 = X1_safe_q[7] $ T1_valid_wreq # !X1L12;
X1L42 = CARRY(X1L42_cout_0);
 
--X1L52 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella7~COUTCOUT1_1 at LC_X21_Y2_N7
--operation mode is arithmetic
 
X1L52_cout_1 = X1_safe_q[7] $ T1_valid_wreq # !X1L22;
X1L52 = CARRY(X1L52_cout_1);
 
 
--X1_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[6] at LC_X21_Y2_N6
--operation mode is arithmetic
 
X1_safe_q[6]_carry_eqn = (!X1L41 & X1L81) # (X1L41 & X1L91);
X1_safe_q[6]_lut_out = X1_safe_q[6] $ !X1_safe_q[6]_carry_eqn;
X1_safe_q[6] = DFFEAS(X1_safe_q[6]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L12 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella6~COUT at LC_X21_Y2_N6
--operation mode is arithmetic
 
X1L12_cout_0 = !X1L81 & T1_valid_wreq $ !X1_safe_q[6];
X1L12 = CARRY(X1L12_cout_0);
 
--X1L22 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella6~COUTCOUT1_1 at LC_X21_Y2_N6
--operation mode is arithmetic
 
X1L22_cout_1 = !X1L91 & T1_valid_wreq $ !X1_safe_q[6];
X1L22 = CARRY(X1L22_cout_1);
 
 
--N1_ua_state_ns_0_a2_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_ns_0_a2_0[1] at LC_X22_Y2_N2
--operation mode is normal
 
N1_ua_state_ns_0_a2_0[1] = !N1_ua_state_i[0] & U1_b_non_empty;
 
 
--U1L7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~112 at LC_X22_Y2_N0
--operation mode is normal
 
U1L7 = X1_safe_q[7] # X1_safe_q[8] # X1_safe_q[6] # !N1_ua_state_ns_0_a2_0[1];
 
 
--X1_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[5] at LC_X21_Y2_N5
--operation mode is arithmetic
 
X1_safe_q[5]_carry_eqn = (!X1L41 & GND) # (X1L41 & VCC);
X1_safe_q[5]_lut_out = X1_safe_q[5] $ X1_safe_q[5]_carry_eqn;
X1_safe_q[5] = DFFEAS(X1_safe_q[5]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L81 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella5~COUT at LC_X21_Y2_N5
--operation mode is arithmetic
 
X1L81_cout_0 = T1_valid_wreq $ X1_safe_q[5] # !X1L41;
X1L81 = CARRY(X1L81_cout_0);
 
--X1L91 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella5~COUTCOUT1_1 at LC_X21_Y2_N5
--operation mode is arithmetic
 
X1L91_cout_1 = T1_valid_wreq $ X1_safe_q[5] # !X1L41;
X1L91 = CARRY(X1L91_cout_1);
 
 
--X1_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[4] at LC_X21_Y2_N4
--operation mode is arithmetic
 
X1_safe_q[4]_lut_out = X1_safe_q[4] $ !X1L11;
X1_safe_q[4] = DFFEAS(X1_safe_q[4]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella4~COUT at LC_X21_Y2_N4
--operation mode is arithmetic
 
X1L41 = X1L51;
 
 
--X1_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[3] at LC_X21_Y2_N3
--operation mode is arithmetic
 
X1_safe_q[3]_lut_out = X1_safe_q[3] $ X1L8;
X1_safe_q[3] = DFFEAS(X1_safe_q[3]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L11 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella3~COUT at LC_X21_Y2_N3
--operation mode is arithmetic
 
X1L11_cout_0 = T1_valid_wreq $ X1_safe_q[3] # !X1L8;
X1L11 = CARRY(X1L11_cout_0);
 
--X1L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella3~COUTCOUT1 at LC_X21_Y2_N3
--operation mode is arithmetic
 
X1L21_cout_1 = T1_valid_wreq $ X1_safe_q[3] # !X1L9;
X1L21 = CARRY(X1L21_cout_1);
 
 
--X1_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[2] at LC_X21_Y2_N2
--operation mode is arithmetic
 
X1_safe_q[2]_lut_out = X1_safe_q[2] $ !X1L5;
X1_safe_q[2] = DFFEAS(X1_safe_q[2]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella2~COUT at LC_X21_Y2_N2
--operation mode is arithmetic
 
X1L8_cout_0 = !X1L5 & T1_valid_wreq $ !X1_safe_q[2];
X1L8 = CARRY(X1L8_cout_0);
 
--X1L9 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella2~COUTCOUT1_1 at LC_X21_Y2_N2
--operation mode is arithmetic
 
X1L9_cout_1 = !X1L6 & T1_valid_wreq $ !X1_safe_q[2];
X1L9 = CARRY(X1L9_cout_1);
 
 
--U1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~113 at LC_X21_Y1_N4
--operation mode is normal
 
U1L8 = X1_safe_q[3] # X1_safe_q[4] # X1_safe_q[5] # X1_safe_q[2];
 
 
--X1_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|safe_q[0] at LC_X21_Y2_N0
--operation mode is arithmetic
 
X1_safe_q[0]_lut_out = !X1_safe_q[0];
X1_safe_q[0] = DFFEAS(X1_safe_q[0]_lut_out, GLOBAL(E1__clk0), VCC, , U1L1, , , , );
 
--X1L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella0~COUT at LC_X21_Y2_N0
--operation mode is arithmetic
 
X1L2_cout_0 = T1_valid_wreq $ !X1_safe_q[0];
X1L2 = CARRY(X1L2_cout_0);
 
--X1L3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw|counter_cella0~COUTCOUT1_1 at LC_X21_Y2_N0
--operation mode is arithmetic
 
X1L3_cout_1 = T1_valid_wreq $ !X1_safe_q[0];
X1L3 = CARRY(X1L3_cout_1);
 
 
--U1L9 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty~114 at LC_X22_Y2_N1
--operation mode is normal
 
U1L9 = X1_safe_q[1] # U1L7 # U1L8 # !X1_safe_q[0];
 
 
--N1_bit_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[1] at LC_X15_Y3_N2
--operation mode is arithmetic
 
N1_bit_ctr[1]_lut_out = N1_bit_ctr[1] $ (N1_bit_ctr_cout_0[0]);
N1_bit_ctr[1] = DFFEAS(N1_bit_ctr[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_bit_ctr23_i_i, );
 
--N1_bit_ctr_cout_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[1] at LC_X15_Y3_N2
--operation mode is arithmetic
 
N1_bit_ctr_cout_0[1]_cout_0 = !N1_bit_ctr_cout_0[0] # !N1_bit_ctr[1];
N1_bit_ctr_cout_0[1] = CARRY(N1_bit_ctr_cout_0[1]_cout_0);
 
--N1L61 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[1]~COUT1_1 at LC_X15_Y3_N2
--operation mode is arithmetic
 
N1L61_cout_1 = !N1L41 # !N1_bit_ctr[1];
N1L61 = CARRY(N1L61_cout_1);
 
 
--N1_bit_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[2] at LC_X15_Y3_N3
--operation mode is normal
 
N1_bit_ctr[2]_lut_out = N1_bit_ctr_cout_0[1] $ !N1_bit_ctr[2];
N1_bit_ctr[2] = DFFEAS(N1_bit_ctr[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_bit_ctr23_i_i, );
 
 
--N1_bit_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr[0] at LC_X15_Y3_N1
--operation mode is arithmetic
 
N1_bit_ctr[0]_lut_out = N1_bit_ctr[0] $ N1_clk_ctr_equ15_0_a2;
N1_bit_ctr[0] = DFFEAS(N1_bit_ctr[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_bit_ctr23_i_i, );
 
--N1_bit_ctr_cout_0[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[0] at LC_X15_Y3_N1
--operation mode is arithmetic
 
N1_bit_ctr_cout_0[0]_cout_0 = N1_bit_ctr[0] & N1_clk_ctr_equ15_0_a2;
N1_bit_ctr_cout_0[0] = CARRY(N1_bit_ctr_cout_0[0]_cout_0);
 
--N1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr_cout_0[0]~COUT1 at LC_X15_Y3_N1
--operation mode is arithmetic
 
N1L41_cout_1 = N1_bit_ctr[0] & N1_clk_ctr_equ15_0_a2;
N1L41 = CARRY(N1L41_cout_1);
 
 
--T1_valid_wreq is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_wreq at LC_X22_Y2_N8
--operation mode is normal
 
T1_valid_wreq = !U1_b_full & F1_wr_uartdata_0_a2;
 
 
--T1_valid_rreq is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_rreq at LC_X22_Y2_N9
--operation mode is normal
 
T1_valid_rreq = N1_ua_state_ns_0_a2_0[1] & U1_b_non_empty;
 
 
--W2_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[0] at LC_X19_Y2_N0
--operation mode is arithmetic
 
W2_safe_q[0]_lut_out = T1_valid_wreq $ W2_safe_q[0];
W2_safe_q[0] = DFFEAS(W2_safe_q[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella0~COUT at LC_X19_Y2_N0
--operation mode is arithmetic
 
W2L2_cout_0 = W2_safe_q[0];
W2L2 = CARRY(W2L2_cout_0);
 
--W2L3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella0~COUTCOUT1_1 at LC_X19_Y2_N0
--operation mode is arithmetic
 
W2L3_cout_1 = W2_safe_q[0];
W2L3 = CARRY(W2L3_cout_1);
 
 
--W2_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[1] at LC_X19_Y2_N1
--operation mode is arithmetic
 
W2_safe_q[1]_lut_out = W2_safe_q[1] $ (T1_valid_wreq & W2L2);
W2_safe_q[1] = DFFEAS(W2_safe_q[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella1~COUT at LC_X19_Y2_N1
--operation mode is arithmetic
 
W2L5_cout_0 = !W2L2 # !W2_safe_q[1];
W2L5 = CARRY(W2L5_cout_0);
 
--W2L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella1~COUTCOUT1_1 at LC_X19_Y2_N1
--operation mode is arithmetic
 
W2L6_cout_1 = !W2L3 # !W2_safe_q[1];
W2L6 = CARRY(W2L6_cout_1);
 
 
--W2_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[2] at LC_X19_Y2_N2
--operation mode is arithmetic
 
W2_safe_q[2]_lut_out = W2_safe_q[2] $ (T1_valid_wreq & !W2L5);
W2_safe_q[2] = DFFEAS(W2_safe_q[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella2~COUT at LC_X19_Y2_N2
--operation mode is arithmetic
 
W2L8_cout_0 = W2_safe_q[2] & !W2L5;
W2L8 = CARRY(W2L8_cout_0);
 
--W2L9 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella2~COUTCOUT1_1 at LC_X19_Y2_N2
--operation mode is arithmetic
 
W2L9_cout_1 = W2_safe_q[2] & !W2L6;
W2L9 = CARRY(W2L9_cout_1);
 
 
--W2_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[3] at LC_X19_Y2_N3
--operation mode is arithmetic
 
W2_safe_q[3]_lut_out = W2_safe_q[3] $ (T1_valid_wreq & W2L8);
W2_safe_q[3] = DFFEAS(W2_safe_q[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L11 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella3~COUT at LC_X19_Y2_N3
--operation mode is arithmetic
 
W2L11_cout_0 = !W2L8 # !W2_safe_q[3];
W2L11 = CARRY(W2L11_cout_0);
 
--W2L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella3~COUTCOUT1 at LC_X19_Y2_N3
--operation mode is arithmetic
 
W2L21_cout_1 = !W2L9 # !W2_safe_q[3];
W2L21 = CARRY(W2L21_cout_1);
 
 
--W2_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[4] at LC_X19_Y2_N4
--operation mode is arithmetic
 
W2_safe_q[4]_lut_out = W2_safe_q[4] $ (T1_valid_wreq & !W2L11);
W2_safe_q[4] = DFFEAS(W2_safe_q[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella4~COUT at LC_X19_Y2_N4
--operation mode is arithmetic
 
W2L41 = W2L51;
 
 
--W2_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[5] at LC_X19_Y2_N5
--operation mode is arithmetic
 
W2_safe_q[5]_carry_eqn = (!W2L41 & GND) # (W2L41 & VCC);
W2_safe_q[5]_lut_out = W2_safe_q[5] $ (T1_valid_wreq & W2_safe_q[5]_carry_eqn);
W2_safe_q[5] = DFFEAS(W2_safe_q[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L81 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella5~COUT at LC_X19_Y2_N5
--operation mode is arithmetic
 
W2L81_cout_0 = !W2L41 # !W2_safe_q[5];
W2L81 = CARRY(W2L81_cout_0);
 
--W2L91 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella5~COUTCOUT1_1 at LC_X19_Y2_N5
--operation mode is arithmetic
 
W2L91_cout_1 = !W2L41 # !W2_safe_q[5];
W2L91 = CARRY(W2L91_cout_1);
 
 
--W2_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[6] at LC_X19_Y2_N6
--operation mode is arithmetic
 
W2_safe_q[6]_carry_eqn = (!W2L41 & W2L81) # (W2L41 & W2L91);
W2_safe_q[6]_lut_out = W2_safe_q[6] $ (T1_valid_wreq & !W2_safe_q[6]_carry_eqn);
W2_safe_q[6] = DFFEAS(W2_safe_q[6]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L12 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella6~COUT at LC_X19_Y2_N6
--operation mode is arithmetic
 
W2L12_cout_0 = W2_safe_q[6] & !W2L81;
W2L12 = CARRY(W2L12_cout_0);
 
--W2L22 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella6~COUTCOUT1_1 at LC_X19_Y2_N6
--operation mode is arithmetic
 
W2L22_cout_1 = W2_safe_q[6] & !W2L91;
W2L22 = CARRY(W2L22_cout_1);
 
 
--W2_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[7] at LC_X19_Y2_N7
--operation mode is arithmetic
 
W2_safe_q[7]_carry_eqn = (!W2L41 & W2L12) # (W2L41 & W2L22);
W2_safe_q[7]_lut_out = W2_safe_q[7] $ (T1_valid_wreq & W2_safe_q[7]_carry_eqn);
W2_safe_q[7] = DFFEAS(W2_safe_q[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W2L42 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella7~COUT at LC_X19_Y2_N7
--operation mode is arithmetic
 
W2L42_cout_0 = !W2L12 # !W2_safe_q[7];
W2L42 = CARRY(W2L42_cout_0);
 
--W2L52 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|counter_cella7~COUTCOUT1_1 at LC_X19_Y2_N7
--operation mode is arithmetic
 
W2L52_cout_1 = !W2L22 # !W2_safe_q[7];
W2L52 = CARRY(W2L52_cout_1);
 
 
--W2_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr|safe_q[8] at LC_X19_Y2_N8
--operation mode is normal
 
W2_safe_q[8]_carry_eqn = (!W2L41 & W2L42) # (W2L41 & W2L52);
W2_safe_q[8]_lut_out = W2_safe_q[8] $ (T1_valid_wreq & !W2_safe_q[8]_carry_eqn);
W2_safe_q[8] = DFFEAS(W2_safe_q[8]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--W1_safe_q[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[0] at LC_X20_Y2_N0
--operation mode is arithmetic
 
W1_safe_q[0]_lut_out = W1_safe_q[0] $ T1_valid_rreq;
W1_safe_q[0] = DFFEAS(W1_safe_q[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella0~COUT at LC_X20_Y2_N0
--operation mode is arithmetic
 
W1L2_cout_0 = W1_safe_q[0];
W1L2 = CARRY(W1L2_cout_0);
 
--W1L3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella0~COUTCOUT1_1 at LC_X20_Y2_N0
--operation mode is arithmetic
 
W1L3_cout_1 = W1_safe_q[0];
W1L3 = CARRY(W1L3_cout_1);
 
 
--W1_safe_q[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[1] at LC_X20_Y2_N1
--operation mode is arithmetic
 
W1_safe_q[1]_lut_out = W1_safe_q[1] $ (T1_valid_rreq & W1L2);
W1_safe_q[1] = DFFEAS(W1_safe_q[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella1~COUT at LC_X20_Y2_N1
--operation mode is arithmetic
 
W1L5_cout_0 = !W1L2 # !W1_safe_q[1];
W1L5 = CARRY(W1L5_cout_0);
 
--W1L6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella1~COUTCOUT1_1 at LC_X20_Y2_N1
--operation mode is arithmetic
 
W1L6_cout_1 = !W1L3 # !W1_safe_q[1];
W1L6 = CARRY(W1L6_cout_1);
 
 
--W1_safe_q[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[2] at LC_X20_Y2_N2
--operation mode is arithmetic
 
W1_safe_q[2]_lut_out = W1_safe_q[2] $ (T1_valid_rreq & !W1L5);
W1_safe_q[2] = DFFEAS(W1_safe_q[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella2~COUT at LC_X20_Y2_N2
--operation mode is arithmetic
 
W1L8_cout_0 = W1_safe_q[2] & !W1L5;
W1L8 = CARRY(W1L8_cout_0);
 
--W1L9 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella2~COUTCOUT1_1 at LC_X20_Y2_N2
--operation mode is arithmetic
 
W1L9_cout_1 = W1_safe_q[2] & !W1L6;
W1L9 = CARRY(W1L9_cout_1);
 
 
--W1_safe_q[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[3] at LC_X20_Y2_N3
--operation mode is arithmetic
 
W1_safe_q[3]_lut_out = W1_safe_q[3] $ (T1_valid_rreq & W1L8);
W1_safe_q[3] = DFFEAS(W1_safe_q[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L11 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella3~COUT at LC_X20_Y2_N3
--operation mode is arithmetic
 
W1L11_cout_0 = !W1L8 # !W1_safe_q[3];
W1L11 = CARRY(W1L11_cout_0);
 
--W1L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella3~COUTCOUT1 at LC_X20_Y2_N3
--operation mode is arithmetic
 
W1L21_cout_1 = !W1L9 # !W1_safe_q[3];
W1L21 = CARRY(W1L21_cout_1);
 
 
--W1_safe_q[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[4] at LC_X20_Y2_N4
--operation mode is arithmetic
 
W1_safe_q[4]_lut_out = W1_safe_q[4] $ (T1_valid_rreq & !W1L11);
W1_safe_q[4] = DFFEAS(W1_safe_q[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella4~COUT at LC_X20_Y2_N4
--operation mode is arithmetic
 
W1L41 = W1L51;
 
 
--W1_safe_q[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[5] at LC_X20_Y2_N5
--operation mode is arithmetic
 
W1_safe_q[5]_carry_eqn = (!W1L41 & GND) # (W1L41 & VCC);
W1_safe_q[5]_lut_out = W1_safe_q[5] $ (T1_valid_rreq & W1_safe_q[5]_carry_eqn);
W1_safe_q[5] = DFFEAS(W1_safe_q[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L81 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella5~COUT at LC_X20_Y2_N5
--operation mode is arithmetic
 
W1L81_cout_0 = !W1L41 # !W1_safe_q[5];
W1L81 = CARRY(W1L81_cout_0);
 
--W1L91 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella5~COUTCOUT1_1 at LC_X20_Y2_N5
--operation mode is arithmetic
 
W1L91_cout_1 = !W1L41 # !W1_safe_q[5];
W1L91 = CARRY(W1L91_cout_1);
 
 
--W1_safe_q[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[6] at LC_X20_Y2_N6
--operation mode is arithmetic
 
W1_safe_q[6]_carry_eqn = (!W1L41 & W1L81) # (W1L41 & W1L91);
W1_safe_q[6]_lut_out = W1_safe_q[6] $ (T1_valid_rreq & !W1_safe_q[6]_carry_eqn);
W1_safe_q[6] = DFFEAS(W1_safe_q[6]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L12 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella6~COUT at LC_X20_Y2_N6
--operation mode is arithmetic
 
W1L12_cout_0 = W1_safe_q[6] & !W1L81;
W1L12 = CARRY(W1L12_cout_0);
 
--W1L22 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella6~COUTCOUT1_1 at LC_X20_Y2_N6
--operation mode is arithmetic
 
W1L22_cout_1 = W1_safe_q[6] & !W1L91;
W1L22 = CARRY(W1L22_cout_1);
 
 
--W1_safe_q[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[7] at LC_X20_Y2_N7
--operation mode is arithmetic
 
W1_safe_q[7]_carry_eqn = (!W1L41 & W1L12) # (W1L41 & W1L22);
W1_safe_q[7]_lut_out = W1_safe_q[7] $ (T1_valid_rreq & W1_safe_q[7]_carry_eqn);
W1_safe_q[7] = DFFEAS(W1_safe_q[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--W1L42 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella7~COUT at LC_X20_Y2_N7
--operation mode is arithmetic
 
W1L42_cout_0 = !W1L12 # !W1_safe_q[7];
W1L42 = CARRY(W1L42_cout_0);
 
--W1L52 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|counter_cella7~COUTCOUT1_1 at LC_X20_Y2_N7
--operation mode is arithmetic
 
W1L52_cout_1 = !W1L22 # !W1_safe_q[7];
W1L52 = CARRY(W1L52_cout_1);
 
 
--W1_safe_q[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count|safe_q[8] at LC_X20_Y2_N8
--operation mode is normal
 
W1_safe_q[8]_carry_eqn = (!W1L41 & W1L42) # (W1L41 & W1L52);
W1_safe_q[8]_lut_out = W1_safe_q[8] $ (T1_valid_rreq & !W1_safe_q[8]_carry_eqn);
W1_safe_q[8] = DFFEAS(W1_safe_q[8]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--N1_tx_sr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[2] at LC_X16_Y2_N1
--operation mode is normal
 
N1_tx_sr[2]_lut_out = N1_read_request_ff & Y1_q_b[2] # !N1_read_request_ff & N1_tx_sr[3];
N1_tx_sr[2] = DFFEAS(N1_tx_sr[2]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_clk_ctr[15] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[15] at LC_X15_Y1_N7
--operation mode is normal
 
N1_clk_ctr[15]_carry_eqn = (!N1_clk_ctr_cout_0[12] & N1_clk_ctr_cout_0[14]) # (N1_clk_ctr_cout_0[12] & N1L39);
N1_clk_ctr[15]_lut_out = N1_clk_ctr[15] $ (N1_clk_ctr[15]_carry_eqn);
N1_clk_ctr[15] = DFFEAS(N1_clk_ctr[15]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
 
--N1_clk_ctr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[6] at LC_X15_Y2_N8
--operation mode is arithmetic
 
N1_clk_ctr[6]_carry_eqn = (!N1_clk_ctr_cout_0[2] & N1_clk_ctr_cout_0[5]) # (N1_clk_ctr_cout_0[2] & N1L77);
N1_clk_ctr[6]_lut_out = N1_clk_ctr[6] $ !N1_clk_ctr[6]_carry_eqn;
N1_clk_ctr[6] = DFFEAS(N1_clk_ctr[6]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[6] at LC_X15_Y2_N8
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[6]_cout_0 = N1_clk_ctr[6] & !N1_clk_ctr_cout_0[5];
N1_clk_ctr_cout_0[6] = CARRY(N1_clk_ctr_cout_0[6]_cout_0);
 
--N1L97 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[6]~COUT1_6 at LC_X15_Y2_N8
--operation mode is arithmetic
 
N1L97_cout_1 = N1_clk_ctr[6] & !N1L77;
N1L97 = CARRY(N1L97_cout_1);
 
 
--N1_clk_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[0] at LC_X15_Y2_N2
--operation mode is arithmetic
 
N1_clk_ctr[0]_lut_out = !N1_clk_ctr[0];
N1_clk_ctr[0] = DFFEAS(N1_clk_ctr[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[0] at LC_X15_Y2_N2
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[0]_cout_0 = N1_clk_ctr[0];
N1_clk_ctr_cout_0[0] = CARRY(N1_clk_ctr_cout_0[0]_cout_0);
 
--N1L86 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[0]~COUT1_1 at LC_X15_Y2_N2
--operation mode is arithmetic
 
N1L86_cout_1 = N1_clk_ctr[0];
N1L86 = CARRY(N1L86_cout_1);
 
 
--N1_clk_ctr26_i_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a2_a at LC_X15_Y1_N8
--operation mode is normal
 
N1_clk_ctr26_i_0_a2_a = !N1_clk_ctr[14] & !N1_clk_ctr[7] & !N1_clk_ctr[12] & !N1_clk_ctr[13];
 
 
--N1_clk_ctr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[5] at LC_X15_Y2_N7
--operation mode is arithmetic
 
N1_clk_ctr[5]_carry_eqn = (!N1_clk_ctr_cout_0[2] & N1_clk_ctr_cout_0[4]) # (N1_clk_ctr_cout_0[2] & N1L57);
N1_clk_ctr[5]_lut_out = N1_clk_ctr[5] $ (N1_clk_ctr[5]_carry_eqn);
N1_clk_ctr[5] = DFFEAS(N1_clk_ctr[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[5] at LC_X15_Y2_N7
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[5]_cout_0 = !N1_clk_ctr_cout_0[4] # !N1_clk_ctr[5];
N1_clk_ctr_cout_0[5] = CARRY(N1_clk_ctr_cout_0[5]_cout_0);
 
--N1L77 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[5]~COUT1_5 at LC_X15_Y2_N7
--operation mode is arithmetic
 
N1L77_cout_1 = !N1L57 # !N1_clk_ctr[5];
N1L77 = CARRY(N1L77_cout_1);
 
 
--N1_clk_ctr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[4] at LC_X15_Y2_N6
--operation mode is arithmetic
 
N1_clk_ctr[4]_carry_eqn = (!N1_clk_ctr_cout_0[2] & N1_clk_ctr_cout_0[3]) # (N1_clk_ctr_cout_0[2] & N1L37);
N1_clk_ctr[4]_lut_out = N1_clk_ctr[4] $ (!N1_clk_ctr[4]_carry_eqn);
N1_clk_ctr[4] = DFFEAS(N1_clk_ctr[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[4] at LC_X15_Y2_N6
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[4]_cout_0 = N1_clk_ctr[4] & !N1_clk_ctr_cout_0[3];
N1_clk_ctr_cout_0[4] = CARRY(N1_clk_ctr_cout_0[4]_cout_0);
 
--N1L57 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[4]~COUT1_4 at LC_X15_Y2_N6
--operation mode is arithmetic
 
N1L57_cout_1 = N1_clk_ctr[4] & !N1L37;
N1L57 = CARRY(N1L57_cout_1);
 
 
--N1_clk_ctr_equ15_0_a2_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_4 at LC_X15_Y3_N5
--operation mode is normal
 
N1_clk_ctr_equ15_0_a2_4 = N1_clk_ctr[10] & N1_clk_ctr[8] & N1_clk_ctr[2];
 
 
--N1_clk_ctr_equ15_0_a2_7_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_7_a at LC_X15_Y2_N0
--operation mode is normal
 
N1_clk_ctr_equ15_0_a2_7_a = !N1_clk_ctr[11] & !N1_clk_ctr[3] & !N1_clk_ctr[9] & !N1_clk_ctr[1];
 
 
--K1_cntr_7 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_7 at LC_X31_Y5_N1
--operation mode is arithmetic
 
K1_cntr_7_carry_eqn = (!K1_cntr_cout[5] & K1_cntr_cout[6]) # (K1_cntr_cout[5] & K1L011);
K1_cntr_7_lut_out = K1_cntr_7 $ (!K1_cntr_7_carry_eqn);
K1_cntr_7 = DFFEAS(K1_cntr_7_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[7], , , !K1_un1_ld_1);
 
--K1_cntr_cout[7] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[7] at LC_X31_Y5_N1
--operation mode is arithmetic
 
K1_cntr_cout[7]_cout_0 = !K1_cntr_7 & !K1_cntr_cout[6];
K1_cntr_cout[7] = CARRY(K1_cntr_cout[7]_cout_0);
 
--K1L211 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[7]~COUT1_6 at LC_X31_Y5_N1
--operation mode is arithmetic
 
K1L211_cout_1 = !K1_cntr_7 & !K1L011;
K1L211 = CARRY(K1L211_cout_1);
 
 
--F1_dout_0_0_a3_4[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_4[0] at LC_X32_Y9_N1
--operation mode is normal
 
F1_dout_0_0_a3_4[0] = F1_rd_cmd_0_a2_2 & F1_rd_uartdata_0_a2_0 & sys_rst & AB1_r32_o_3;
 
 
--F1_dout_0_0_a[7] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[7] at LC_X33_Y8_N4
--operation mode is normal
 
F1_cmd[7]_qfbk = F1_cmd[7];
F1_dout_0_0_a[7] = F1_dout_0_0_a3_3[0] & !F1_cmd[7]_qfbk & !M1_buffer_reg_7 # !F1_dout_0_0_a3_5_x[0] # !F1_dout_0_0_a3_3[0] & !M1_buffer_reg_7 # !F1_dout_0_0_a3_5_x[0];
 
--F1_cmd[7] is mips_sys:isys|mips_dvc:imips_dvc|cmd[7] at LC_X33_Y8_N4
--operation mode is normal
 
F1_cmd[7] = DFFEAS(F1_dout_0_0_a[7], GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_7, , !sys_rst, VCC);
 
 
--WC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21|wb_mux_ctl_o_0 at LC_X29_Y7_N1
--operation mode is normal
 
WC1_wb_mux_ctl_o_0_lut_out = NC1_wb_mux_ctl_o_0;
WC1_wb_mux_ctl_o_0 = DFFEAS(WC1_wb_mux_ctl_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_7 at LC_X21_Y5_N5
--operation mode is normal
 
GD1_dout_iv_1_7 = FD1_N_20_i_0_s3 & LD1_q_b[7] # !GD1_dout_iv_1_a[7];
 
 
--GD1_dout7_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout7_0_a2 at LC_X26_Y10_N4
--operation mode is normal
 
GD1_dout7_0_a2 = !WD1_un30_mux_fw & MC1_wb_we_o_0 & !ZD1_mux_fw_1 & !ZD1_un17_mux_fw_NE;
 
 
--UD1_shift_out_89_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_6 at LC_X10_Y15_N9
--operation mode is normal
 
UD1_shift_out_89_6 = UD1_shift_out586 & !UD1_shift_out_89_a[7] # !UD1_shift_out586 & UD1_shift_out_87[7];
 
 
--UD1_shift_out_sn_m31_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i at LC_X14_Y8_N4
--operation mode is normal
 
UD1_shift_out_sn_m31_i = !PD1_a_o_2 & !PD1_a_o_1 & !PD1_a_o_0 # !UD1_shift_out_sn_m31_i_a;
 
 
--MD1_c_a_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_7 at LC_X15_Y12_N2
--operation mode is normal
 
MD1_c_a_7 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_7 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_7;
 
 
--MD1_c_0_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_6 at LC_X9_Y11_N7
--operation mode is normal
 
MD1_c_0_6 = RC1_alu_func_o_4 & !TD1_m11 # !RC1_alu_func_o_4 & TD1_m1 # !MD1_c_0_a[7];
 
 
--XD1_mux_fw_1_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1_a at LC_X25_Y14_N8
--operation mode is normal
 
BE1_q_4_qfbk = BE1_q_4;
XD1_mux_fw_1_a = MB1_r5_o_4 $ BE1_q_4_qfbk # !XC1_wb_we_o_0;
 
--BE1_q_4 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_4 at LC_X25_Y14_N8
--operation mode is normal
 
BE1_q_4 = DFFEAS(XD1_mux_fw_1_a, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_20, , , VCC);
 
 
--XD1_un1_mux_fw_NE_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un1_mux_fw_NE_2 at LC_X25_Y12_N8
--operation mode is normal
 
BE1_q_3_qfbk = BE1_q_3;
XD1_un1_mux_fw_NE_2 = MB1_r5_o_2 & MB1_r5_o_3 $ BE1_q_3_qfbk # !BE1_q_2 # !MB1_r5_o_2 & BE1_q_2 # MB1_r5_o_3 $ BE1_q_3_qfbk;
 
--BE1_q_3 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_3 at LC_X25_Y12_N8
--operation mode is normal
 
BE1_q_3 = DFFEAS(XD1_un1_mux_fw_NE_2, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_19, , , VCC);
 
 
--XD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un1_mux_fw_NE_1 at LC_X27_Y9_N5
--operation mode is normal
 
MB1_r5_o_0_qfbk = MB1_r5_o_0;
XD1_un1_mux_fw_NE_1 = BE1_q_0 & BE1_q_1 $ MB1_r5_o_1 # !MB1_r5_o_0_qfbk # !BE1_q_0 & MB1_r5_o_0_qfbk # BE1_q_1 $ MB1_r5_o_1;
 
--MB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_0 at LC_X27_Y9_N5
--operation mode is normal
 
MB1_r5_o_0 = DFFEAS(XD1_un1_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , , LB1_r5_o_0, , , VCC);
 
 
--WD1_un14_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw at LC_X26_Y10_N9
--operation mode is normal
 
MB1_r5_o_3_qfbk = MB1_r5_o_3;
WD1_un14_mux_fw = !MB1_r5_o_2 & !MB1_r5_o_0 & !MB1_r5_o_3_qfbk & WD1_un14_mux_fw_a;
 
--MB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_3 at LC_X26_Y10_N9
--operation mode is normal
 
MB1_r5_o_3 = DFFEAS(WD1_un14_mux_fw, GLOBAL(E1__clk0), VCC, , , LB1_r5_o_3, , , VCC);
 
 
--VC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20|wb_we_o_0 at LC_X27_Y12_N2
--operation mode is normal
 
VC1_wb_we_o_0_lut_out = UC1_wb_we_o_0;
VC1_wb_we_o_0 = DFFEAS(VC1_wb_we_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--NB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_0 at LC_X25_Y9_N9
--operation mode is normal
 
NB1_r5_o_0_lut_out = MB1_r5_o_0;
NB1_r5_o_0 = DFFEAS(NB1_r5_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--NB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_1 at LC_X25_Y9_N0
--operation mode is normal
 
NB1_r5_o_1_lut_out = GND;
NB1_r5_o_1 = DFFEAS(NB1_r5_o_1_lut_out, GLOBAL(E1__clk0), VCC, , , MB1_r5_o_1, , , VCC);
 
 
--WD1_un30_mux_fw_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un30_mux_fw_a at LC_X25_Y9_N3
--operation mode is normal
 
NB1_r5_o_2_qfbk = NB1_r5_o_2;
WD1_un30_mux_fw_a = !NB1_r5_o_2_qfbk & !NB1_r5_o_4;
 
--NB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_2 at LC_X25_Y9_N3
--operation mode is normal
 
NB1_r5_o_2 = DFFEAS(WD1_un30_mux_fw_a, GLOBAL(E1__clk0), VCC, , , MB1_r5_o_2, , , VCC);
 
 
--XD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE_1 at LC_X27_Y9_N4
--operation mode is normal
 
BE1_q_1_qfbk = BE1_q_1;
XD1_un17_mux_fw_NE_1 = BE1_q_0 & NB1_r5_o_1 $ BE1_q_1_qfbk # !NB1_r5_o_0 # !BE1_q_0 & NB1_r5_o_0 # NB1_r5_o_1 $ BE1_q_1_qfbk;
 
--BE1_q_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_1 at LC_X27_Y9_N4
--operation mode is normal
 
BE1_q_1 = DFFEAS(XD1_un17_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_17, , , VCC);
 
 
--XD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE_a at LC_X25_Y12_N5
--operation mode is normal
 
BE1_q_2_qfbk = BE1_q_2;
XD1_un17_mux_fw_NE_a = NB1_r5_o_2 & BE1_q_3 $ NB1_r5_o_3 # !BE1_q_2_qfbk # !NB1_r5_o_2 & BE1_q_2_qfbk # BE1_q_3 $ NB1_r5_o_3;
 
--BE1_q_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_2 at LC_X25_Y12_N5
--operation mode is normal
 
BE1_q_2 = DFFEAS(XD1_un17_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_18, , , VCC);
 
 
--TD1_alu_out_sn_m14_0_0_a4_0_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4_0_a at LC_X13_Y15_N1
--operation mode is normal
 
RC1_alu_func_o_3_qfbk = RC1_alu_func_o_3;
TD1_alu_out_sn_m14_0_0_a4_0_a = !RC1_alu_func_o_2 # !RC1_alu_func_o_3_qfbk;
 
--RC1_alu_func_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_3 at LC_X13_Y15_N1
--operation mode is normal
 
RC1_alu_func_o_3 = DFFEAS(TD1_alu_out_sn_m14_0_0_a4_0_a, GLOBAL(E1__clk0), VCC, , , ZC1_alu_func_o_3, , !AD1_NET1640_i, VCC);
 
 
--TD1_alu_out_sn_m14_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0 at LC_X7_Y16_N4
--operation mode is normal
 
TD1_alu_out_sn_m14_0_0 = TD1_alu_out_sn_m14_0_0_a4_0 # TD1_alu_out_sn_m14_0_0_a4 # UD1_shift_out588_0 & RC1_alu_func_o_4;
 
 
--MD1_c_0_Z[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[4] at LC_X8_Y12_N4
--operation mode is normal
 
MD1_c_0_Z[4] = TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_4 # !MD1_c_0_a[4];
 
 
--TD1_alu_out_7_0_0_m2_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_1 at LC_X8_Y12_N8
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_1 = PD1_a_o_4 & !TD1_alu_out_7_0_0_m2_a[4] # !PD1_a_o_4 & TD1_alu_out_7_0_0_m4_0[4];
 
 
--PD1_a_o_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_4 at LC_X16_Y11_N6
--operation mode is normal
 
PD1_a_o_4 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[4] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[4];
 
 
--TD1_un1_b_1_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[4] at LC_X15_Y5_N2
--operation mode is normal
 
TD1_un1_b_1_combout[4] = TD1_sum13_0_a2 $ !VD1_b_o_iv_4;
 
 
--TD1_un1_a_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add3 at LC_X12_Y10_N8
--operation mode is arithmetic
 
TD1_un1_a_add3_carry_eqn = (!TD1_un1_a_add0_start_cout & TD1_un1_a_carry_2) # (TD1_un1_a_add0_start_cout & TD1L615);
TD1_un1_a_add3 = PD1_a_o_3 $ TD1_un1_b_1_combout[3] $ TD1_un1_a_add3_carry_eqn;
 
--TD1_un1_a_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_3 at LC_X12_Y10_N8
--operation mode is arithmetic
 
TD1_un1_a_carry_3_cout_0 = PD1_a_o_3 & !TD1_un1_b_1_combout[3] & !TD1_un1_a_carry_2 # !PD1_a_o_3 & !TD1_un1_a_carry_2 # !TD1_un1_b_1_combout[3];
TD1_un1_a_carry_3 = CARRY(TD1_un1_a_carry_3_cout_0);
 
--TD1L815 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_3~COUT1_1 at LC_X12_Y10_N8
--operation mode is arithmetic
 
TD1L815_cout_1 = PD1_a_o_3 & !TD1_un1_b_1_combout[3] & !TD1L615 # !PD1_a_o_3 & !TD1L615 # !TD1_un1_b_1_combout[3];
TD1L815 = CARRY(TD1L815_cout_1);
 
 
--UD1_shift_out_89[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[4] at LC_X16_Y16_N4
--operation mode is normal
 
UD1_shift_out_89[4] = UD1_shift_out586 & UD1_shift_out_85[4] # !UD1_shift_out586 & UD1_shift_out_87[4];
 
 
--UD1_shift_out_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[4] at LC_X21_Y17_N4
--operation mode is normal
 
UD1_shift_out_a[4] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[4] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[4];
 
 
--MD1_c_0_Z[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[5] at LC_X13_Y11_N6
--operation mode is normal
 
MD1_c_0_Z[5] = VD1_hilo_5 & VD1_un11_res # VD1_hilo_37 & VD1_un24_res # !VD1_hilo_5 & VD1_hilo_37 & VD1_un24_res;
 
 
--MD1_c_2_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[5] at LC_X8_Y14_N5
--operation mode is normal
 
MD1_c_2_a[5] = !TD1_alu_out_7_0_0_o3_0 & RC1_alu_func_o_4 & VD1_b_o_iv_5 & RC1_alu_func_o_0;
 
 
--TD1_alu_out_7_0_0_m2_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_2 at LC_X10_Y13_N2
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_2 = PD1_a_o_5 & !TD1_alu_out_7_0_0_m2_a[5] # !PD1_a_o_5 & TD1_alu_out_7_0_0_m4_0[5];
 
 
--PD1_a_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_5 at LC_X20_Y11_N9
--operation mode is normal
 
PD1_a_o_5 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[5] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[5];
 
 
--TD1_un1_b_1_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[5] at LC_X16_Y4_N6
--operation mode is normal
 
TD1_un1_b_1_combout[5] = VD1_b_o_iv_5 $ (!TD1_sum13_0_a2);
 
 
--UD1_shift_out_89[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[5] at LC_X15_Y19_N6
--operation mode is normal
 
UD1_shift_out_89[5] = UD1_shift_out586 & !UD1_shift_out_89_a[5] # !UD1_shift_out586 & UD1_shift_out_87[5];
 
 
--UD1_shift_out_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[5] at LC_X13_Y11_N2
--operation mode is normal
 
UD1_shift_out_a[5] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[5] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[5];
 
 
--UD1_shift_out_89_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_1 at LC_X11_Y19_N2
--operation mode is normal
 
UD1_shift_out_89_1 = UD1_shift_out586 & !PD1_a_o_2 & UD1_shift_out_89_a[2] # !UD1_shift_out586 & UD1_shift_out_87[2];
 
 
--MD1_c_a_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_2 at LC_X19_Y17_N7
--operation mode is normal
 
MD1_c_a_2 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_2 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_2;
 
 
--MD1_c_0_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_1 at LC_X11_Y9_N4
--operation mode is normal
 
MD1_c_0_1 = RC1_alu_func_o_4 & !TD1_m112 # !RC1_alu_func_o_4 & TD1_m109 # !MD1_c_0_a[2];
 
 
--MD1_c_1_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_3 at LC_X7_Y14_N6
--operation mode is normal
 
MD1_c_1_3 = MD1_c_0_Z[3] # TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0_m2_0;
 
 
--UD1_shift_out_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_3 at LC_X15_Y15_N8
--operation mode is normal
 
UD1_shift_out_3 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[3] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[3];
 
 
--F1_dout_0_0_a3_6_5_9[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_9[0] at LC_X28_Y6_N9
--operation mode is normal
 
F1_dout_0_0_a3_6_5_9[0] = !AB1_r32_o_12 & !AB1_r32_o_13 & !AB1_r32_o_15 & !AB1_r32_o_14;
 
 
--F1_rd_status_29_0_a2_0_8 is mips_sys:isys|mips_dvc:imips_dvc|rd_status_29_0_a2_0_8 at LC_X28_Y9_N4
--operation mode is normal
 
F1_rd_status_29_0_a2_0_8 = AB1_r32_o_29 & !AB1_r32_o_5 & !RB1_byte_addr_o_1 & F1_rd_status_29_0_a2_0_8_a;
 
 
--F1_dout_0_0_a3_6_5_12[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_12[0] at LC_X26_Y3_N2
--operation mode is normal
 
F1_dout_0_0_a3_6_5_12[0] = !AB1_r32_o_19 & !AB1_r32_o_18 & F1_dout_0_0_a3_6_5_2[0] & F1_dout_0_0_a3_6_5_12_a[0];
 
 
--F1_rd_uartdata_0_a2_0_a is mips_sys:isys|mips_dvc:imips_dvc|rd_uartdata_0_a2_0_a at LC_X28_Y6_N3
--operation mode is normal
 
F1_rd_uartdata_0_a2_0_a = !AB1_r32_o_11 & !AB1_r32_o_28 & F1_dout_0_0_a3_6_5_8[0] & JC1_rd_status_29_0_a2_0_7;
 
 
--K1_cntr_6 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_6 at LC_X31_Y5_N0
--operation mode is arithmetic
 
K1_cntr_6_carry_eqn = K1_cntr_cout[5];
K1_cntr_6_lut_out = K1_cntr_6 $ K1_cntr_6_carry_eqn;
K1_cntr_6 = DFFEAS(K1_cntr_6_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[6], , , !K1_un1_ld_1);
 
--K1_cntr_cout[6] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[6] at LC_X31_Y5_N0
--operation mode is arithmetic
 
K1_cntr_cout[6]_cout_0 = K1_cntr_6 # !K1_cntr_cout[5];
K1_cntr_cout[6] = CARRY(K1_cntr_cout[6]_cout_0);
 
--K1L011 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[6]~COUT1_5 at LC_X31_Y5_N0
--operation mode is arithmetic
 
K1L011_cout_1 = K1_cntr_6 # !K1_cntr_cout[5];
K1L011 = CARRY(K1L011_cout_1);
 
 
--F1_dout_0_0_a[6] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[6] at LC_X33_Y8_N8
--operation mode is normal
 
M1_buffer_reg_6_qfbk = M1_buffer_reg_6;
F1_dout_0_0_a[6] = F1_cmd_6 & !F1_dout_0_0_a3_3[0] & !M1_buffer_reg_6_qfbk # !F1_dout_0_0_a3_5_x[0] # !F1_cmd_6 & !M1_buffer_reg_6_qfbk # !F1_dout_0_0_a3_5_x[0];
 
--M1_buffer_reg_6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_6 at LC_X33_Y8_N8
--operation mode is normal
 
M1_buffer_reg_6 = DFFEAS(F1_dout_0_0_a[6], GLOBAL(E1__clk0), VCC, , C1_G_578, M1_rx_sr[6], , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_6 at LC_X24_Y7_N7
--operation mode is normal
 
GD1_dout_iv_1_6 = FD1_N_20_i_0_s3 & LD1_q_b[6] # !GD1_dout_iv_1_a[6];
 
 
--UD1_shift_out_89_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_5 at LC_X19_Y15_N5
--operation mode is normal
 
UD1_shift_out_89_5 = UD1_shift_out586 & !UD1_shift_out_89_a[6] # !UD1_shift_out586 & UD1_shift_out_87[6];
 
 
--MD1_c_a_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_6 at LC_X19_Y15_N1
--operation mode is normal
 
MD1_c_a_6 = !MD1_c_1_Z[6] & !TD1_un1_a_add6 # !TD1_alu_out_sn_m14_0_0_a4_0;
 
 
--UD1_shift_out_92_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_0 at LC_X19_Y15_N4
--operation mode is normal
 
UD1_shift_out_92_0 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[6] # !UD1_shift_out_sn_m25_0 & !UD1_shift_out586 & UD1_shift_out_86[6];
 
 
--K1_cntr_5 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5 at LC_X31_Y6_N9
--operation mode is arithmetic
 
K1_cntr_5_carry_eqn = (!K1_cntr_cout[0] & K1_cntr_cout[4]) # (K1_cntr_cout[0] & K1L701);
K1_cntr_5_lut_out = K1_cntr_5 $ (!K1_cntr_5_carry_eqn);
K1_cntr_5 = DFFEAS(K1_cntr_5_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[5], , , !K1_un1_ld_1);
 
--K1_cntr_cout[5] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[5] at LC_X31_Y6_N9
--operation mode is arithmetic
 
K1_cntr_cout[5] = CARRY(!K1_cntr_5 & !K1L701);
 
 
--F1_dout_0_0_a[5] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[5] at LC_X33_Y8_N5
--operation mode is normal
 
M1_buffer_reg_5_qfbk = M1_buffer_reg_5;
F1_dout_0_0_a[5] = F1_dout_0_0_a3_3[0] & !F1_cmd_5 & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_5_qfbk # !F1_dout_0_0_a3_3[0] & !F1_dout_0_0_a3_5_x[0] # !M1_buffer_reg_5_qfbk;
 
--M1_buffer_reg_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_5 at LC_X33_Y8_N5
--operation mode is normal
 
M1_buffer_reg_5 = DFFEAS(F1_dout_0_0_a[5], GLOBAL(E1__clk0), VCC, , C1_G_578, M1_rx_sr[5], , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_5 at LC_X20_Y7_N5
--operation mode is normal
 
GD1_dout_iv_1_5 = FD1_N_20_i_0_s3 & LD1_q_b[5] # !GD1_dout_iv_1_a[5];
 
 
--K1_cntr_4 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_4 at LC_X31_Y6_N8
--operation mode is arithmetic
 
K1_cntr_4_carry_eqn = (!K1_cntr_cout[0] & K1_cntr_cout[3]) # (K1_cntr_cout[0] & K1L501);
K1_cntr_4_lut_out = K1_cntr_4 $ K1_cntr_4_carry_eqn;
K1_cntr_4 = DFFEAS(K1_cntr_4_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[4], , , !K1_un1_ld_1);
 
--K1_cntr_cout[4] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[4] at LC_X31_Y6_N8
--operation mode is arithmetic
 
K1_cntr_cout[4]_cout_0 = K1_cntr_4 # !K1_cntr_cout[3];
K1_cntr_cout[4] = CARRY(K1_cntr_cout[4]_cout_0);
 
--K1L701 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[4]~COUT1_4 at LC_X31_Y6_N8
--operation mode is arithmetic
 
K1L701_cout_1 = K1_cntr_4 # !K1L501;
K1L701 = CARRY(K1L701_cout_1);
 
 
--F1_dout_0_0_a[4] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[4] at LC_X33_Y8_N6
--operation mode is normal
 
M1_buffer_reg_4_qfbk = M1_buffer_reg_4;
F1_dout_0_0_a[4] = F1_cmd_4 & !F1_dout_0_0_a3_3[0] & !M1_buffer_reg_4_qfbk # !F1_dout_0_0_a3_5_x[0] # !F1_cmd_4 & !M1_buffer_reg_4_qfbk # !F1_dout_0_0_a3_5_x[0];
 
--M1_buffer_reg_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_4 at LC_X33_Y8_N6
--operation mode is normal
 
M1_buffer_reg_4 = DFFEAS(F1_dout_0_0_a[4], GLOBAL(E1__clk0), VCC, , C1_G_578, M1_rx_sr[4], , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_4 at LC_X21_Y7_N1
--operation mode is normal
 
GD1_dout_iv_1_4 = FD1_N_20_i_0_s3 & LD1_q_b[4] # !GD1_dout_iv_1_a[4];
 
 
--K1_cntr_3 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_3 at LC_X31_Y6_N7
--operation mode is arithmetic
 
K1_cntr_3_carry_eqn = (!K1_cntr_cout[0] & K1_cntr_cout[2]) # (K1_cntr_cout[0] & K1L301);
K1_cntr_3_lut_out = K1_cntr_3 $ (!K1_cntr_3_carry_eqn);
K1_cntr_3 = DFFEAS(K1_cntr_3_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[3], , , !K1_un1_ld_1);
 
--K1_cntr_cout[3] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[3] at LC_X31_Y6_N7
--operation mode is arithmetic
 
K1_cntr_cout[3]_cout_0 = !K1_cntr_3 & !K1_cntr_cout[2];
K1_cntr_cout[3] = CARRY(K1_cntr_cout[3]_cout_0);
 
--K1L501 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[3]~COUT1_3 at LC_X31_Y6_N7
--operation mode is arithmetic
 
K1L501_cout_1 = !K1_cntr_3 & !K1L301;
K1L501 = CARRY(K1L501_cout_1);
 
 
--L1_dout_0_0_a_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw|dout_0_0_a_0 at LC_X33_Y6_N5
--operation mode is normal
 
L1_q_Z_qfbk = L1_q_Z;
L1_dout_0_0_a_0 = M1_buffer_reg_3 & !F1_dout_0_0_a3_5_x[0] & !F1_dout_0_0_a3_6[0] # !L1_q_Z_qfbk # !M1_buffer_reg_3 & !F1_dout_0_0_a3_6[0] # !L1_q_Z_qfbk;
 
--L1_q_Z is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw|q_Z at LC_X33_Y6_N5
--operation mode is normal
 
L1_q_Z = DFFEAS(L1_dout_0_0_a_0, GLOBAL(E1__clk0), !F1_cmd[1], , M1_int_req, VCC, , , VCC);
 
 
--F1_dout_0_0_a3_0[3] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[3] at LC_X34_Y13_N5
--operation mode is normal
 
F1_cmd_3_qfbk = F1_cmd_3;
F1_dout_0_0_a3_0[3] = F1_dout_0_0_a3_3[0] & F1_cmd_3_qfbk;
 
--F1_cmd_3 is mips_sys:isys|mips_dvc:imips_dvc|cmd_3 at LC_X34_Y13_N5
--operation mode is normal
 
F1_cmd_3 = DFFEAS(F1_dout_0_0_a3_0[3], GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_3, , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_3 at LC_X26_Y7_N5
--operation mode is normal
 
GD1_dout_iv_1_3 = FD1_N_20_i_0_s3 & LD1_q_b[3] # !GD1_dout_iv_1_a[3];
 
 
--K1_cntr_2 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_2 at LC_X31_Y6_N6
--operation mode is arithmetic
 
K1_cntr_2_carry_eqn = (!K1_cntr_cout[0] & K1_cntr_cout[1]) # (K1_cntr_cout[0] & K1L101);
K1_cntr_2_lut_out = K1_cntr_2 $ (K1_cntr_2_carry_eqn);
K1_cntr_2 = DFFEAS(K1_cntr_2_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[2], , , !K1_un1_ld_1);
 
--K1_cntr_cout[2] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[2] at LC_X31_Y6_N6
--operation mode is arithmetic
 
K1_cntr_cout[2]_cout_0 = K1_cntr_2 # !K1_cntr_cout[1];
K1_cntr_cout[2] = CARRY(K1_cntr_cout[2]_cout_0);
 
--K1L301 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[2]~COUT1_2 at LC_X31_Y6_N6
--operation mode is arithmetic
 
K1L301_cout_1 = K1_cntr_2 # !K1L101;
K1L301 = CARRY(K1L301_cout_1);
 
 
--F1_dout_0_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[2] at LC_X33_Y7_N5
--operation mode is normal
 
M1_buffer_reg_2_qfbk = M1_buffer_reg_2;
F1_dout_0_0_a[2] = F1_dout_0_0_a3_5_x[0] & !M1_buffer_reg_2_qfbk & !U1_b_full # !F1_dout_0_0_a3_6[0] # !F1_dout_0_0_a3_5_x[0] & !U1_b_full # !F1_dout_0_0_a3_6[0];
 
--M1_buffer_reg_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_2 at LC_X33_Y7_N5
--operation mode is normal
 
M1_buffer_reg_2 = DFFEAS(F1_dout_0_0_a[2], GLOBAL(E1__clk0), VCC, , C1_G_578, M1_rx_sr[2], , !sys_rst, VCC);
 
 
--F1_dout_0_0_a3_0[2] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[2] at LC_X34_Y13_N1
--operation mode is normal
 
F1_cmd_2_qfbk = F1_cmd_2;
F1_dout_0_0_a3_0[2] = F1_dout_0_0_a3_3[0] & F1_cmd_2_qfbk;
 
--F1_cmd_2 is mips_sys:isys|mips_dvc:imips_dvc|cmd_2 at LC_X34_Y13_N1
--operation mode is normal
 
F1_cmd_2 = DFFEAS(F1_dout_0_0_a3_0[2], GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_2, , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_2 at LC_X21_Y8_N2
--operation mode is normal
 
GD1_dout_iv_1_2 = FD1_N_20_i_0_s3 & LD1_q_b[2] # !GD1_dout_iv_1_a[2];
 
 
--K1_cntr_1 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_1 at LC_X31_Y6_N5
--operation mode is arithmetic
 
K1_cntr_1_carry_eqn = K1_cntr_cout[0];
K1_cntr_1_lut_out = K1_cntr_1 $ !K1_cntr_1_carry_eqn;
K1_cntr_1 = DFFEAS(K1_cntr_1_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[1], , , !K1_un1_ld_1);
 
--K1_cntr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[1] at LC_X31_Y6_N5
--operation mode is arithmetic
 
K1_cntr_cout[1]_cout_0 = !K1_cntr_1 & !K1_cntr_cout[0];
K1_cntr_cout[1] = CARRY(K1_cntr_cout[1]_cout_0);
 
--K1L101 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[1]~COUT1_1 at LC_X31_Y6_N5
--operation mode is arithmetic
 
K1L101_cout_1 = !K1_cntr_1 & !K1_cntr_cout[0];
K1L101 = CARRY(K1L101_cout_1);
 
 
--F1_dout_0_0_a[1] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[1] at LC_X33_Y6_N4
--operation mode is normal
 
F1_rr_key1_Z_qfbk = F1_rr_key1_Z;
F1_dout_0_0_a[1] = M1_buffer_reg_1 & !F1_dout_0_0_a3_5_x[0] & !F1_dout_0_0_a3_6[0] # !F1_rr_key1_Z_qfbk # !M1_buffer_reg_1 & !F1_dout_0_0_a3_6[0] # !F1_rr_key1_Z_qfbk;
 
--F1_rr_key1_Z is mips_sys:isys|mips_dvc:imips_dvc|rr_key1_Z at LC_X33_Y6_N4
--operation mode is normal
 
F1_rr_key1_Z = DFFEAS(F1_dout_0_0_a[1], GLOBAL(E1__clk0), VCC, , , F1_r_key1, , , VCC);
 
 
--F1_dout_0_0_a3_0[1] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[1] at LC_X34_Y13_N7
--operation mode is normal
 
F1_cmd[1]_qfbk = F1_cmd[1];
F1_dout_0_0_a3_0[1] = F1_dout_0_0_a3_3[0] & F1_cmd[1]_qfbk;
 
--F1_cmd[1] is mips_sys:isys|mips_dvc:imips_dvc|cmd[1] at LC_X34_Y13_N7
--operation mode is normal
 
F1_cmd[1] = DFFEAS(F1_dout_0_0_a3_0[1], GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_1, , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_1 at LC_X26_Y10_N5
--operation mode is normal
 
GD1_dout_iv_1_1 = FD1_N_20_i_0_s3 & LD1_q_b[1] # !GD1_dout_iv_1_a[1];
 
 
--UD1_shift_out_89_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_0 at LC_X16_Y17_N7
--operation mode is normal
 
UD1_shift_out_89_0 = UD1_shift_out586 & !PD1_a_o_1 & UD1_shift_out_89_a[1] # !UD1_shift_out586 & UD1_shift_out_87[1];
 
 
--MD1_c_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_1 at LC_X13_Y9_N0
--operation mode is normal
 
MD1_c_a_1 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91_1 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86_1;
 
 
--MD1_c_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_0 at LC_X13_Y11_N8
--operation mode is normal
 
MD1_c_0_0 = TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0 # !MD1_c_0_a[1];
 
 
--K1_cntr_0 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_0 at LC_X31_Y6_N4
--operation mode is arithmetic
 
K1_cntr_0_lut_out = !K1_cntr_0;
K1_cntr_0 = DFFEAS(K1_cntr_0_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[0], , , !K1_un1_ld_1);
 
--K1_cntr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[0] at LC_X31_Y6_N4
--operation mode is arithmetic
 
K1_cntr_cout[0] = CARRY(K1_cntr_0);
 
 
--F1_dout_0_0_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a[0] at LC_X33_Y6_N6
--operation mode is normal
 
F1_rr_key2_Z_qfbk = F1_rr_key2_Z;
F1_dout_0_0_a[0] = M1_buffer_reg_0 & !F1_dout_0_0_a3_5_x[0] & !F1_dout_0_0_a3_6[0] # !F1_rr_key2_Z_qfbk # !M1_buffer_reg_0 & !F1_dout_0_0_a3_6[0] # !F1_rr_key2_Z_qfbk;
 
--F1_rr_key2_Z is mips_sys:isys|mips_dvc:imips_dvc|rr_key2_Z at LC_X33_Y6_N6
--operation mode is normal
 
F1_rr_key2_Z = DFFEAS(F1_dout_0_0_a[0], GLOBAL(E1__clk0), VCC, , , F1_r_key2, , , VCC);
 
 
--F1_dout_0_0_a3_0[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_0[0] at LC_X31_Y7_N8
--operation mode is normal
 
F1_cmd[0]_qfbk = F1_cmd[0];
F1_dout_0_0_a3_0[0] = F1_cmd[0]_qfbk & F1_dout_0_0_a3_3[0];
 
--F1_cmd[0] is mips_sys:isys|mips_dvc:imips_dvc|cmd[0] at LC_X31_Y7_N8
--operation mode is normal
 
F1_cmd[0] = DFFEAS(F1_dout_0_0_a3_0[0], GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_0, , !sys_rst, VCC);
 
 
--GD1_dout_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_0 at LC_X27_Y5_N4
--operation mode is normal
 
GD1_dout_iv_1_0 = FD1_N_20_i_0_s3 & LD1_q_b[0] # !GD1_dout_iv_1_a[0];
 
 
--MD1_c_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_0 at LC_X9_Y14_N3
--operation mode is normal
 
MD1_c_2_0 = MD1_c_1_Z[0] # !RC1_alu_func_o_1 & UD1_shift_out588_0 & MD1_c_2_a[0];
 
 
--MD1_c_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_0 at LC_X14_Y9_N9
--operation mode is normal
 
MD1_c_a_0 = !TD1_un1_a_add0 # !TD1_alu_out_sn_m14_0_0_a4_0;
 
 
--UD1_shift_out_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_0 at LC_X14_Y9_N8
--operation mode is normal
 
UD1_shift_out_0 = UD1_shift_out_sn_m31_i & UD1_shift_out_sn_m25_0 & UD1_shift_out_91[0] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_a[0] # !UD1_shift_out_sn_m31_i & UD1_shift_out_a[0];
 
 
--TD1_alu_out_9_a2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_0 at LC_X14_Y9_N2
--operation mode is normal
 
TD1_alu_out_9_a2_0 = TD1_alu_out_9_a2_a[0] & RC1_alu_func_o_0 & TD1_sum_add32 # !RC1_alu_func_o_0 & TD1_lt31;
 
 
--F1_wr_uartdata_0_a2_1 is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2_1 at LC_X33_Y8_N7
--operation mode is normal
 
F1_wr_uartdata_0_a2_1 = AB1_r32_o_1 & !AB1_r32_o_0;
 
 
--F1_wr_uartdata_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|wr_uartdata_0_a2_a at LC_X33_Y9_N2
--operation mode is normal
 
F1_wr_uartdata_0_a2_a = !JC1_dmem_ctl_o_2 & !AB1_r32_o_2 & JC1_dmem_ctl_o_0 & !JC1_dmem_ctl_o_1;
 
 
--U1L4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~105 at LC_X21_Y2_N9
--operation mode is normal
 
U1L4 = X1_safe_q[7] & X1_safe_q[5] & X1_safe_q[4] & X1_safe_q[6];
 
 
--U1L5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~106 at LC_X21_Y1_N2
--operation mode is normal
 
U1L5 = X1_safe_q[1] & X1_safe_q[3] & X1_safe_q[0] & X1_safe_q[2];
 
 
--U1L3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_full~103 at LC_X22_Y2_N5
--operation mode is normal
 
U1L3 = F1_wr_uartdata_0_a2 & U1L5 & X1_safe_q[8] & U1L4;
 
 
--U1L1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|_~14 at LC_X22_Y2_N6
--operation mode is normal
 
U1L1 = N1_ua_state_ns_0_a2_0[1] & U1_b_non_empty $ (!U1_b_full & F1_wr_uartdata_0_a2) # !N1_ua_state_ns_0_a2_0[1] & !U1_b_full & F1_wr_uartdata_0_a2;
 
 
--N1_bit_ctr23_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_i at LC_X16_Y3_N7
--operation mode is normal
 
N1_bit_ctr23_i_i = sys_rst & N1_ua_state[3] # N1_ua_state[2];
 
 
--N1_tx_sr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[3] at LC_X16_Y2_N4
--operation mode is normal
 
N1_tx_sr[3]_lut_out = N1_read_request_ff & Y1_q_b[3] # !N1_read_request_ff & N1_tx_sr[4];
N1_tx_sr[3] = DFFEAS(N1_tx_sr[3]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_clk_ctr26_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_i at LC_X15_Y3_N8
--operation mode is normal
 
N1_clk_ctr26_i_i = !N1_clk_ctr26_i_0_0 & !N1_clk_ctr26_i_0_a4_0_5 # !N1_clk_ctr26_i_0_a2 # !N1_clk_ctr26_i_0_a4_0_6;
 
 
--N1_clk_ctr[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[14] at LC_X15_Y1_N6
--operation mode is arithmetic
 
N1_clk_ctr[14]_carry_eqn = (!N1_clk_ctr_cout_0[12] & N1_clk_ctr_cout_0[13]) # (N1_clk_ctr_cout_0[12] & N1L19);
N1_clk_ctr[14]_lut_out = N1_clk_ctr[14] $ (!N1_clk_ctr[14]_carry_eqn);
N1_clk_ctr[14] = DFFEAS(N1_clk_ctr[14]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[14] at LC_X15_Y1_N6
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[14]_cout_0 = N1_clk_ctr[14] & !N1_clk_ctr_cout_0[13];
N1_clk_ctr_cout_0[14] = CARRY(N1_clk_ctr_cout_0[14]_cout_0);
 
--N1L39 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[14]~COUT1_12 at LC_X15_Y1_N6
--operation mode is arithmetic
 
N1L39_cout_1 = N1_clk_ctr[14] & !N1L19;
N1L39 = CARRY(N1L39_cout_1);
 
 
--N1_clk_ctr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[7] at LC_X15_Y2_N9
--operation mode is arithmetic
 
N1_clk_ctr[7]_carry_eqn = (!N1_clk_ctr_cout_0[2] & N1_clk_ctr_cout_0[6]) # (N1_clk_ctr_cout_0[2] & N1L97);
N1_clk_ctr[7]_lut_out = N1_clk_ctr[7] $ (N1_clk_ctr[7]_carry_eqn);
N1_clk_ctr[7] = DFFEAS(N1_clk_ctr[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[7] at LC_X15_Y2_N9
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[7] = CARRY(!N1L97 # !N1_clk_ctr[7]);
 
 
--N1_clk_ctr[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[12] at LC_X15_Y1_N4
--operation mode is arithmetic
 
N1_clk_ctr[12]_carry_eqn = (!N1_clk_ctr_cout_0[7] & N1_clk_ctr_cout_0[11]) # (N1_clk_ctr_cout_0[7] & N1L88);
N1_clk_ctr[12]_lut_out = N1_clk_ctr[12] $ !N1_clk_ctr[12]_carry_eqn;
N1_clk_ctr[12] = DFFEAS(N1_clk_ctr[12]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[12] at LC_X15_Y1_N4
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[12] = CARRY(N1_clk_ctr[12] & !N1L88);
 
 
--N1_clk_ctr[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[13] at LC_X15_Y1_N5
--operation mode is arithmetic
 
N1_clk_ctr[13]_carry_eqn = N1_clk_ctr_cout_0[12];
N1_clk_ctr[13]_lut_out = N1_clk_ctr[13] $ N1_clk_ctr[13]_carry_eqn;
N1_clk_ctr[13] = DFFEAS(N1_clk_ctr[13]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[13] at LC_X15_Y1_N5
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[13]_cout_0 = !N1_clk_ctr_cout_0[12] # !N1_clk_ctr[13];
N1_clk_ctr_cout_0[13] = CARRY(N1_clk_ctr_cout_0[13]_cout_0);
 
--N1L19 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[13]~COUT1_11 at LC_X15_Y1_N5
--operation mode is arithmetic
 
N1L19_cout_1 = !N1_clk_ctr_cout_0[12] # !N1_clk_ctr[13];
N1L19 = CARRY(N1L19_cout_1);
 
 
--N1_clk_ctr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[3] at LC_X15_Y2_N5
--operation mode is arithmetic
 
N1_clk_ctr[3]_carry_eqn = N1_clk_ctr_cout_0[2];
N1_clk_ctr[3]_lut_out = N1_clk_ctr[3] $ N1_clk_ctr[3]_carry_eqn;
N1_clk_ctr[3] = DFFEAS(N1_clk_ctr[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[3] at LC_X15_Y2_N5
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[3]_cout_0 = !N1_clk_ctr_cout_0[2] # !N1_clk_ctr[3];
N1_clk_ctr_cout_0[3] = CARRY(N1_clk_ctr_cout_0[3]_cout_0);
 
--N1L37 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[3]~COUT1_3 at LC_X15_Y2_N5
--operation mode is arithmetic
 
N1L37_cout_1 = !N1_clk_ctr_cout_0[2] # !N1_clk_ctr[3];
N1L37 = CARRY(N1L37_cout_1);
 
 
--N1_clk_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[2] at LC_X15_Y2_N4
--operation mode is arithmetic
 
N1_clk_ctr[2]_lut_out = N1_clk_ctr[2] $ !N1_clk_ctr_cout_0[1];
N1_clk_ctr[2] = DFFEAS(N1_clk_ctr[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[2] at LC_X15_Y2_N4
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[2] = CARRY(N1_clk_ctr[2] & !N1L07);
 
 
--N1_clk_ctr[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[10] at LC_X15_Y1_N2
--operation mode is arithmetic
 
N1_clk_ctr[10]_carry_eqn = (!N1_clk_ctr_cout_0[7] & N1_clk_ctr_cout_0[9]) # (N1_clk_ctr_cout_0[7] & N1L48);
N1_clk_ctr[10]_lut_out = N1_clk_ctr[10] $ (!N1_clk_ctr[10]_carry_eqn);
N1_clk_ctr[10] = DFFEAS(N1_clk_ctr[10]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[10] at LC_X15_Y1_N2
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[10]_cout_0 = N1_clk_ctr[10] & !N1_clk_ctr_cout_0[9];
N1_clk_ctr_cout_0[10] = CARRY(N1_clk_ctr_cout_0[10]_cout_0);
 
--N1L68 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[10]~COUT1_9 at LC_X15_Y1_N2
--operation mode is arithmetic
 
N1L68_cout_1 = N1_clk_ctr[10] & !N1L48;
N1L68 = CARRY(N1L68_cout_1);
 
 
--N1_clk_ctr[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[8] at LC_X15_Y1_N0
--operation mode is arithmetic
 
N1_clk_ctr[8]_carry_eqn = N1_clk_ctr_cout_0[7];
N1_clk_ctr[8]_lut_out = N1_clk_ctr[8] $ !N1_clk_ctr[8]_carry_eqn;
N1_clk_ctr[8] = DFFEAS(N1_clk_ctr[8]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[8] at LC_X15_Y1_N0
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[8]_cout_0 = N1_clk_ctr[8] & !N1_clk_ctr_cout_0[7];
N1_clk_ctr_cout_0[8] = CARRY(N1_clk_ctr_cout_0[8]_cout_0);
 
--N1L28 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[8]~COUT1_7 at LC_X15_Y1_N0
--operation mode is arithmetic
 
N1L28_cout_1 = N1_clk_ctr[8] & !N1_clk_ctr_cout_0[7];
N1L28 = CARRY(N1L28_cout_1);
 
 
--N1_clk_ctr[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[11] at LC_X15_Y1_N3
--operation mode is arithmetic
 
N1_clk_ctr[11]_carry_eqn = (!N1_clk_ctr_cout_0[7] & N1_clk_ctr_cout_0[10]) # (N1_clk_ctr_cout_0[7] & N1L68);
N1_clk_ctr[11]_lut_out = N1_clk_ctr[11] $ N1_clk_ctr[11]_carry_eqn;
N1_clk_ctr[11] = DFFEAS(N1_clk_ctr[11]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[11] at LC_X15_Y1_N3
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[11]_cout_0 = !N1_clk_ctr_cout_0[10] # !N1_clk_ctr[11];
N1_clk_ctr_cout_0[11] = CARRY(N1_clk_ctr_cout_0[11]_cout_0);
 
--N1L88 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[11]~COUT1_10 at LC_X15_Y1_N3
--operation mode is arithmetic
 
N1L88_cout_1 = !N1L68 # !N1_clk_ctr[11];
N1L88 = CARRY(N1L88_cout_1);
 
 
--N1_clk_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[1] at LC_X15_Y2_N3
--operation mode is arithmetic
 
N1_clk_ctr[1]_lut_out = N1_clk_ctr[1] $ N1_clk_ctr_cout_0[0];
N1_clk_ctr[1] = DFFEAS(N1_clk_ctr[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[1] at LC_X15_Y2_N3
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[1]_cout_0 = !N1_clk_ctr_cout_0[0] # !N1_clk_ctr[1];
N1_clk_ctr_cout_0[1] = CARRY(N1_clk_ctr_cout_0[1]_cout_0);
 
--N1L07 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[1]~COUT1_2 at LC_X15_Y2_N3
--operation mode is arithmetic
 
N1L07_cout_1 = !N1L86 # !N1_clk_ctr[1];
N1L07 = CARRY(N1L07_cout_1);
 
 
--N1_clk_ctr[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr[9] at LC_X15_Y1_N1
--operation mode is arithmetic
 
N1_clk_ctr[9]_carry_eqn = (!N1_clk_ctr_cout_0[7] & N1_clk_ctr_cout_0[8]) # (N1_clk_ctr_cout_0[7] & N1L28);
N1_clk_ctr[9]_lut_out = N1_clk_ctr[9] $ (N1_clk_ctr[9]_carry_eqn);
N1_clk_ctr[9] = DFFEAS(N1_clk_ctr[9]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !N1_clk_ctr26_i_i, );
 
--N1_clk_ctr_cout_0[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[9] at LC_X15_Y1_N1
--operation mode is arithmetic
 
N1_clk_ctr_cout_0[9]_cout_0 = !N1_clk_ctr_cout_0[8] # !N1_clk_ctr[9];
N1_clk_ctr_cout_0[9] = CARRY(N1_clk_ctr_cout_0[9]_cout_0);
 
--N1L48 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_cout_0[9]~COUT1_8 at LC_X15_Y1_N1
--operation mode is arithmetic
 
N1L48_cout_1 = !N1L28 # !N1_clk_ctr[9];
N1L48 = CARRY(N1L48_cout_1);
 
 
--N1_ua_state[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[5] at LC_X14_Y2_N2
--operation mode is normal
 
N1_ua_state[5]_lut_out = N1_ua_state[4];
N1_ua_state[5] = DFFEAS(N1_ua_state[5]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_451_x, , , !sys_rst, );
 
 
--C1_G_451_x is mips_sys:isys|G_451_x at LC_X14_Y3_N5
--operation mode is normal
 
C1_G_451_x = N1_clk_ctr_equ15_0_a2 # !sys_rst;
 
 
--K1_cntr_5_0[7] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[7] at LC_X30_Y4_N4
--operation mode is normal
 
K1_s_cntr_7__Z_qfbk = K1_s_cntr_7__Z;
K1_cntr_5_0[7] = F1_wr_tmr_data_0_a2 & CB1_r32_o_7 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_7__Z_qfbk;
 
--K1_s_cntr_7__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_7__Z at LC_X30_Y4_N4
--operation mode is normal
 
K1_s_cntr_7__Z = DFFEAS(K1_cntr_5_0[7], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_7, , , VCC);
 
 
--K1_un1_ld_1 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1 at LC_X31_Y3_N8
--operation mode is normal
 
K1_un1_ld_1 = !F1_wr_tmr_data_0_a2 & K1_un1_ld_1_a # !K1_un2_w_irq_28 # !K1_un2_w_irq_21;
 
 
--K1_cntrlde is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntrlde at LC_X32_Y6_N0
--operation mode is normal
 
F1_cmd[8]_qfbk = F1_cmd[8];
K1_cntrlde = F1_cmd[8]_qfbk # !K1_un1_ld_1;
 
--F1_cmd[8] is mips_sys:isys|mips_dvc:imips_dvc|cmd[8] at LC_X32_Y6_N0
--operation mode is normal
 
F1_cmd[8] = DFFEAS(K1_cntrlde, GLOBAL(E1__clk0), VCC, , C1_G_602, CB1_r32_o_8, , !sys_rst, VCC);
 
 
--F1_rd_cmd_0_a2_2 is mips_sys:isys|mips_dvc:imips_dvc|rd_cmd_0_a2_2 at LC_X33_Y9_N6
--operation mode is normal
 
F1_rd_cmd_0_a2_2 = JC1_dmem_ctl_o_1 & !JC1_dmem_ctl_o_0 & F1_wr_tmr_data_0_a2_0;
 
 
--M1_buffer_reg_7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_7 at LC_X33_Y4_N2
--operation mode is normal
 
M1_buffer_reg_7_lut_out = M1_rx_sr[7];
M1_buffer_reg_7 = DFFEAS(M1_buffer_reg_7_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_578, , , !sys_rst, );
 
 
--F1_dout_0_0_a3_5_x[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_x[0] at LC_X33_Y8_N3
--operation mode is normal
 
F1_dout_0_0_a3_5_x[0] = sys_rst & F1_rd_uartdata_0_a2_0 & F1_dout_0_0_a3_5_3[0];
 
 
--F1_dout_0_0_a3_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_3[0] at LC_X32_Y9_N8
--operation mode is normal
 
F1_dout_0_0_a3_3[0] = F1_rd_cmd_0_a2_2 & F1_rd_uartdata_0_a2_0 & sys_rst & !AB1_r32_o_3;
 
 
--UB1_dout_2_i_i[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[7] at LC_X30_Y8_N7
--operation mode is normal
 
UB1_dout_2_i_i[7] = UB1_dout_2_i_i_0[7] # GE1_q_b[7] & UB1_dout_2_i_i_a3_1[7] # !UB1_dout_2_i_i_a[7];
 
 
--UB1_un1_byte_addr_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_byte_addr_2 at LC_X30_Y8_N9
--operation mode is normal
 
UB1_un1_byte_addr_2 = !RB1_byte_addr_o_0 # !RB1_ctl_o_3;
 
 
--UB1_un1_dout98_i_0_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_dout98_i_0_0 at LC_X31_Y9_N2
--operation mode is normal
 
UB1_un1_dout98_i_0_0 = RB1_ctl_o_0 # RB1_ctl_o_2 & RB1_ctl_o_3 # !RB1_ctl_o_2 & !RB1_ctl_o_3 & !RB1_ctl_o_1;
 
 
--WB21L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_7__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y8_N8
--operation mode is normal
 
WB21L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[7] # !UB1_un1_byte_addr_2 & WB21L1;
 
--DB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_7 at LC_X30_Y8_N8
--operation mode is normal
 
DB1_r32_o_7 = DFFEAS(WB21L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--NC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13|wb_mux_ctl_o_0 at LC_X27_Y12_N5
--operation mode is normal
 
NC1_wb_mux_ctl_o_0_lut_out = KC1_wb_mux_ctl_o_0;
NC1_wb_mux_ctl_o_0 = DFFEAS(NC1_wb_mux_ctl_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , !AD1_NET1640_i, );
 
 
--FD1_N_20_i_0_s3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_20_i_0_s3 at LC_X26_Y10_N2
--operation mode is normal
 
FD1_N_20_i_0_s3 = !FD1_un23_qb_i_0_a2 & ZD1_un32_mux_fw & FD1_un14_qb_NE # !FD1_r_wren;
 
 
--GD1_dout_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[7] at LC_X21_Y5_N6
--operation mode is normal
 
GD1_dout_iv_1_a[7] = AB1_r32_o_5 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_7 # !AB1_r32_o_5 & !FD1_N_16_i_0_s2 # !FD1_r_data_7;
 
 
--LD1_q_b[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[7] at M4K_X17_Y3
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[7] = LD1_q_b[7]_PORT_B_data_out[0];
 
--LD1_q_b[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[24] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[24] = LD1_q_b[7]_PORT_B_data_out[31];
 
--LD1_q_b[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[23] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[23] = LD1_q_b[7]_PORT_B_data_out[30];
 
--LD1_q_b[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[28] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[28] = LD1_q_b[7]_PORT_B_data_out[29];
 
--LD1_q_b[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[16] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[16] = LD1_q_b[7]_PORT_B_data_out[28];
 
--LD1_q_b[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[19] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[19] = LD1_q_b[7]_PORT_B_data_out[27];
 
--LD1_q_b[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[27] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[27] = LD1_q_b[7]_PORT_B_data_out[26];
 
--LD1_q_b[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[15] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[15] = LD1_q_b[7]_PORT_B_data_out[25];
 
--LD1_q_b[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[10] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[10] = LD1_q_b[7]_PORT_B_data_out[24];
 
--LD1_q_b[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[20] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[20] = LD1_q_b[7]_PORT_B_data_out[23];
 
--LD1_q_b[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[18] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[18] = LD1_q_b[7]_PORT_B_data_out[22];
 
--LD1_q_b[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[17] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[17] = LD1_q_b[7]_PORT_B_data_out[21];
 
--LD1_q_b[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[29] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[29] = LD1_q_b[7]_PORT_B_data_out[20];
 
--LD1_q_b[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[26] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[26] = LD1_q_b[7]_PORT_B_data_out[19];
 
--LD1_q_b[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[25] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[25] = LD1_q_b[7]_PORT_B_data_out[18];
 
--LD1_q_b[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[22] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[22] = LD1_q_b[7]_PORT_B_data_out[17];
 
--LD1_q_b[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[21] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[21] = LD1_q_b[7]_PORT_B_data_out[16];
 
--LD1_q_b[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[14] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[14] = LD1_q_b[7]_PORT_B_data_out[15];
 
--LD1_q_b[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[12] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[12] = LD1_q_b[7]_PORT_B_data_out[14];
 
--LD1_q_b[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[13] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[13] = LD1_q_b[7]_PORT_B_data_out[13];
 
--LD1_q_b[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[11] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[11] = LD1_q_b[7]_PORT_B_data_out[12];
 
--LD1_q_b[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[30] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[30] = LD1_q_b[7]_PORT_B_data_out[11];
 
--LD1_q_b[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[31] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[31] = LD1_q_b[7]_PORT_B_data_out[10];
 
--LD1_q_b[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[8] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[8] = LD1_q_b[7]_PORT_B_data_out[9];
 
--LD1_q_b[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[9] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[9] = LD1_q_b[7]_PORT_B_data_out[8];
 
--LD1_q_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[0] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[0] = LD1_q_b[7]_PORT_B_data_out[7];
 
--LD1_q_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[1] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[1] = LD1_q_b[7]_PORT_B_data_out[6];
 
--LD1_q_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[2] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[2] = LD1_q_b[7]_PORT_B_data_out[5];
 
--LD1_q_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[3] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[3] = LD1_q_b[7]_PORT_B_data_out[4];
 
--LD1_q_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[4] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[4] = LD1_q_b[7]_PORT_B_data_out[3];
 
--LD1_q_b[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[5] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[5] = LD1_q_b[7]_PORT_B_data_out[2];
 
--LD1_q_b[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|q_b[6] at M4K_X17_Y3
LD1_q_b[7]_PORT_A_data_in = BUS(FD1_wb_o_7, FD1_wb_o_6, FD1_wb_o_5, FD1_wb_o_4, FD1_wb_o_3, FD1_wb_o_2, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_9, FD1_wb_o_8, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_11, FD1_wb_o_13, FD1_wb_o_12, FD1_wb_o_14, FD1_wb_o_21, FD1_wb_o_22, FD1_wb_o_25, FD1_wb_o_26, FD1_wb_o_29, FD1_wb_o_17, FD1_wb_o_18, FD1_wb_o_20, FD1_wb_o_10, FD1_wb_o_15, FD1_wb_o_27, FD1_wb_o_19, FD1_wb_o_16, FD1_wb_o_28, FD1_wb_o_23, FD1_wb_o_24);
LD1_q_b[7]_PORT_A_data_in_reg = DFFE(LD1_q_b[7]_PORT_A_data_in, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD1_q_b[7]_PORT_A_address_reg = DFFE(LD1_q_b[7]_PORT_A_address, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_address = BUS(FD1_r_rdaddress_b_0_x[0], FD1_r_rdaddress_b_0_x[1], FD1_r_rdaddress_b_0_x[2], FD1_r_rdaddress_b_0_x[3], FD1_r_rdaddress_b_0_x[4]);
LD1_q_b[7]_PORT_B_address_reg = DFFE(LD1_q_b[7]_PORT_B_address, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_PORT_A_write_enable = MC1_wb_we_o_0;
LD1_q_b[7]_PORT_A_write_enable_reg = DFFE(LD1_q_b[7]_PORT_A_write_enable, LD1_q_b[7]_clock_0, , , );
LD1_q_b[7]_PORT_B_read_enable = VCC;
LD1_q_b[7]_PORT_B_read_enable_reg = DFFE(LD1_q_b[7]_PORT_B_read_enable, LD1_q_b[7]_clock_1, , , );
LD1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
LD1_q_b[7]_clock_1 = GLOBAL(E1__clk0);
LD1_q_b[7]_PORT_B_data_out = MEMORY(LD1_q_b[7]_PORT_A_data_in_reg, , LD1_q_b[7]_PORT_A_address_reg, LD1_q_b[7]_PORT_B_address_reg, LD1_q_b[7]_PORT_A_write_enable_reg, LD1_q_b[7]_PORT_B_read_enable_reg, , , LD1_q_b[7]_clock_0, LD1_q_b[7]_clock_1, , , , );
LD1_q_b[6] = LD1_q_b[7]_PORT_B_data_out[1];
 
 
--ZD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE at LC_X26_Y10_N6
--operation mode is normal
 
NB1_r5_o_4_qfbk = NB1_r5_o_4;
ZD1_un17_mux_fw_NE = ZD1_un17_mux_fw_NE_1 # ZD1_un17_mux_fw_NE_a # NB1_r5_o_4_qfbk $ ED1_r32_o_20;
 
--NB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2|r5_o_4 at LC_X26_Y10_N6
--operation mode is normal
 
NB1_r5_o_4 = DFFEAS(ZD1_un17_mux_fw_NE, GLOBAL(E1__clk0), VCC, , , MB1_r5_o_4, , , VCC);
 
 
--ZD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1 at LC_X26_Y10_N7
--operation mode is normal
 
ZD1_mux_fw_1 = !WD1_un14_mux_fw & !ZD1_un1_mux_fw_NE_2 & !ZD1_un1_mux_fw_NE_1 & !ZD1_mux_fw_1_a;
 
 
--UD1_shift_out586 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out586 at LC_X13_Y15_N3
--operation mode is normal
 
UD1_shift_out586 = !RC1_alu_func_o_0 & TD1_alu_out_9_a2_0_1_0 & !RC1_alu_func_o_4 & RC1_alu_func_o_1;
 
 
--UD1_shift_out_87[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[7] at LC_X10_Y15_N2
--operation mode is normal
 
UD1_shift_out_87[7] = PD1_a_o_2 & UD1_shift_out_87_d[7] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[7] # !PD1_a_o_0 & VD1_b_o_iv_9;
 
 
--UD1_shift_out_89_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[7] at LC_X10_Y15_N8
--operation mode is normal
 
UD1_shift_out_89_a[7] = PD1_a_o_2 & !UD1_shift_out_85_d[7] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[7] # !PD1_a_o_1 & !VD1_b_o_iv_6;
 
 
--UD1_shift_out_sn_m31_i_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i_a at LC_X14_Y8_N3
--operation mode is normal
 
UD1_shift_out_sn_m31_i_a = !PD1_a_o_4 & !UD1_shift_out_sn_m25_0_a5_1 & !PD1_a_o_3;
 
 
--PD1_a_o_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_2 at LC_X20_Y10_N7
--operation mode is normal
 
PD1_a_o_2 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[2] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[2];
 
 
--PD1_a_o_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_1 at LC_X20_Y13_N4
--operation mode is normal
 
SC1_muxa_ctl_o_0_qfbk = SC1_muxa_ctl_o_0;
PD1_a_o_1 = SC1_muxa_ctl_o_0_qfbk & !RD1_a_o_a_1 # !SC1_muxa_ctl_o_0_qfbk & PD1_a_o_3_Z[1];
 
--SC1_muxa_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_0 at LC_X20_Y13_N4
--operation mode is normal
 
SC1_muxa_ctl_o_0 = DFFEAS(PD1_a_o_1, GLOBAL(E1__clk0), VCC, , , GC1_muxa_ctl_o_0, , !AD1_NET1640_i, VCC);
 
 
--PD1_a_o_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_0 at LC_X20_Y14_N4
--operation mode is normal
 
PD1_a_o_0 = SC1_muxa_ctl_o_0 & !RD1_a_o_a_0 # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[0];
 
 
--UD1_shift_out_86_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_7 at LC_X15_Y17_N8
--operation mode is normal
 
UD1_shift_out_86_7 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[7] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[7];
 
 
--UD1_shift_out_sn_m25_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0 at LC_X20_Y13_N8
--operation mode is normal
 
UD1_shift_out_sn_m25_0 = UD1_shift_out_sn_m25_0_a5_0 # !UD1_shift_out586 & UD1_shift_out_sn_m17_0_a2 # !UD1_shift_out_sn_m25_0_a;
 
 
--UD1_shift_out_91_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_7 at LC_X15_Y12_N6
--operation mode is normal
 
UD1_shift_out_91_7 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[7] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[7];
 
 
--MD1_c_0_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[7] at LC_X9_Y11_N5
--operation mode is normal
 
MD1_c_0_a[7] = VD1_un24_res & !VD1_hilo_39 # !VD1_un24_res & !VD1_hilo_7 # !VD1_un11_res;
 
 
--TD1_m11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m11 at LC_X9_Y11_N0
--operation mode is normal
 
TD1_m11 = TD1_m11_a & PD1_a_o_7 # !TD1_m4 # !TD1_m11_a & TD1_m7 & !PD1_a_o_7;
 
 
--TD1_m1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m1 at LC_X9_Y11_N9
--operation mode is normal
 
TD1_m1 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add7;
 
 
--BE1_q_0 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt|q_0 at LC_X27_Y9_N2
--operation mode is normal
 
BE1_q_0_lut_out = ED1_r32_o_16;
BE1_q_0 = DFFEAS(BE1_q_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--WD1_un14_mux_fw_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw_a at LC_X26_Y10_N3
--operation mode is normal
 
MB1_r5_o_1_qfbk = MB1_r5_o_1;
WD1_un14_mux_fw_a = !MB1_r5_o_1_qfbk & !MB1_r5_o_4;
 
--MB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_1 at LC_X26_Y10_N3
--operation mode is normal
 
MB1_r5_o_1 = DFFEAS(WD1_un14_mux_fw_a, GLOBAL(E1__clk0), VCC, , , LB1_r5_o_1, , , VCC);
 
 
--UC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19|wb_we_o_0 at LC_X27_Y12_N4
--operation mode is normal
 
UC1_wb_we_o_0_lut_out = LC1_wb_we_o_0;
UC1_wb_we_o_0 = DFFEAS(UC1_wb_we_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , !AD1_NET1640_i, );
 
 
--YC1_alu_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24|alu_we_o_0 at LC_X27_Y12_N6
--operation mode is normal
 
YC1_alu_we_o_0_lut_out = FC1_alu_we_o_0;
YC1_alu_we_o_0 = DFFEAS(YC1_alu_we_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , !AD1_NET1640_i, );
 
 
--AD1_NET1640_i is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|NET1640_i at LC_X27_Y14_N9
--operation mode is normal
 
AD1_NET1640_i = !AD1_CurrState_Sreg0_5 & !AD1_CurrState_Sreg0_2;
 
 
--UD1_shift_out588_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out588_0 at LC_X13_Y15_N6
--operation mode is normal
 
RC1_alu_func_o_2_qfbk = RC1_alu_func_o_2;
UD1_shift_out588_0 = RC1_alu_func_o_2_qfbk & !RC1_alu_func_o_3;
 
--RC1_alu_func_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_2 at LC_X13_Y15_N6
--operation mode is normal
 
RC1_alu_func_o_2 = DFFEAS(UD1_shift_out588_0, GLOBAL(E1__clk0), VCC, , , ZC1_alu_func_o_2, , !AD1_NET1640_i, VCC);
 
 
--TD1_alu_out_sn_m14_0_0_a4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4 at LC_X7_Y16_N3
--operation mode is normal
 
TD1_alu_out_sn_m14_0_0_a4 = !RC1_alu_func_o_3 & TD1_m107;
 
 
--MD1_c_0_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[4] at LC_X8_Y12_N2
--operation mode is normal
 
MD1_c_0_a[4] = VD1_un24_res & !VD1_hilo_36 # !VD1_un24_res & !VD1_hilo_4 # !VD1_un11_res;
 
 
--TD1_alu_out_0_a3_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a3_0_0 at LC_X7_Y14_N8
--operation mode is normal
 
TD1_alu_out_0_a3_0_0 = RC1_alu_func_o_0 & RC1_alu_func_o_4 & !TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_sn_m14_0_0;
 
 
--VD1_b_o_iv_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_4 at LC_X16_Y6_N1
--operation mode is normal
 
VD1_b_o_iv_4 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] & !G1_BUS15471_i_m[4] & AB1_r32_o_2 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[4] at LC_X16_Y6_N1
--operation mode is normal
 
VD1_op2_reged[4] = DFFEAS(VD1_b_o_iv_4, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_alu_out_7_0_0_m4_0[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[4] at LC_X8_Y14_N3
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0[4] = VD1_b_o_iv_4 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_4 & TD1_alu_out_7_0_0_m4_0_a[3];
 
 
--TD1_alu_out_7_0_0_m2_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[4] at LC_X8_Y12_N7
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_a[4] = VD1_b_o_iv_4 & !TD1_m107 # !VD1_b_o_iv_4 & !TD1_alu_out_0_a3[28];
 
 
--PD1_a_o_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[4] at LC_X21_Y4_N2
--operation mode is normal
 
PD1_a_o_a[4] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_4 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_4;
 
 
--PD1_a_o_3_Z[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[4] at LC_X16_Y11_N5
--operation mode is normal
 
SD1_r32_o_4_qfbk = SD1_r32_o_4;
PD1_a_o_3_Z[4] = PD1_a_o_3_s[0] & SD1_r32_o_4_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[4];
 
--SD1_r32_o_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_4 at LC_X16_Y11_N5
--operation mode is normal
 
SD1_r32_o_4 = DFFEAS(PD1_a_o_3_Z[4], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_4, , , VCC);
 
 
--TD1_sum13_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum13_0_a2 at LC_X13_Y15_N8
--operation mode is normal
 
TD1_sum13_0_a2 = !RC1_alu_func_o_1 & TD1_alu_out_sn_m14_0_0_a4_0;
 
 
--PD1_a_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3 at LC_X16_Y13_N6
--operation mode is normal
 
PD1_a_o_3 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[3] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[3];
 
 
--TD1_un1_b_1_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[3] at LC_X10_Y13_N0
--operation mode is normal
 
TD1_un1_b_1_combout[3] = TD1_sum13_0_a2 $ (!VD1_b_o_iv_3);
 
 
--TD1_un1_a_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add2 at LC_X12_Y10_N7
--operation mode is arithmetic
 
TD1_un1_a_add2_carry_eqn = (!TD1_un1_a_add0_start_cout & TD1_un1_a_carry_1) # (TD1_un1_a_add0_start_cout & TD1L415);
TD1_un1_a_add2 = PD1_a_o_2 $ TD1_un1_b_1_combout[2] $ !TD1_un1_a_add2_carry_eqn;
 
--TD1_un1_a_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_2 at LC_X12_Y10_N7
--operation mode is arithmetic
 
TD1_un1_a_carry_2_cout_0 = PD1_a_o_2 & TD1_un1_b_1_combout[2] # !TD1_un1_a_carry_1 # !PD1_a_o_2 & TD1_un1_b_1_combout[2] & !TD1_un1_a_carry_1;
TD1_un1_a_carry_2 = CARRY(TD1_un1_a_carry_2_cout_0);
 
--TD1L615 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_2~COUT1_1 at LC_X12_Y10_N7
--operation mode is arithmetic
 
TD1L615_cout_1 = PD1_a_o_2 & TD1_un1_b_1_combout[2] # !TD1L415 # !PD1_a_o_2 & TD1_un1_b_1_combout[2] & !TD1L415;
TD1L615 = CARRY(TD1L615_cout_1);
 
 
--UD1_shift_out_85[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[4] at LC_X16_Y16_N3
--operation mode is normal
 
UD1_shift_out_85[4] = PD1_a_o_1 & UD1_shift_out_85_d[4] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[4] # !PD1_a_o_2 & VD1_b_o_iv_3;
 
 
--UD1_shift_out_87[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[4] at LC_X16_Y16_N9
--operation mode is normal
 
UD1_shift_out_87[4] = PD1_a_o_2 & UD1_shift_out_87_d[4] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[4] # !PD1_a_o_0 & VD1_b_o_iv_6;
 
 
--UD1_shift_out_91[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[4] at LC_X21_Y17_N8
--operation mode is normal
 
UD1_shift_out_91[4] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[4] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[4];
 
 
--UD1_shift_out_86[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[4] at LC_X21_Y17_N3
--operation mode is normal
 
UD1_shift_out_86[4] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[4] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[4];
 
 
--VD1_hilo_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_5 at LC_X5_Y17_N2
--operation mode is normal
 
VD1_hilo_5_lut_out = VD1_hilo_37_iv_0_0[5] # PD1_a_o_5 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[5];
VD1_hilo_5 = DFFEAS(VD1_hilo_5_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_37 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37 at LC_X6_Y5_N7
--operation mode is normal
 
VD1_hilo_37_lut_out = !VD1_hilo_37_iv_0_a[37] & !VD1_hilo_37_iv_0_5[37] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_0_a2_7[37];
VD1_hilo_37 = DFFEAS(VD1_hilo_37_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_un24_res is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un24_res at LC_X8_Y14_N4
--operation mode is normal
 
VD1_un24_res = !TD1_alu_out_7_0_0_o3_0 & !RC1_alu_func_o_0 & !RC1_alu_func_o_3 & !RC1_alu_func_o_4;
 
 
--VD1_un11_res is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un11_res at LC_X13_Y15_N0
--operation mode is normal
 
VD1_un11_res = RC1_alu_func_o_0 & RC1_alu_func_o_1 & !RC1_alu_func_o_4 & UD1_shift_out588_0;
 
 
--TD1_alu_out_7_0_0_o3_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_o3_0 at LC_X8_Y14_N9
--operation mode is normal
 
TD1_alu_out_7_0_0_o3_0 = !RC1_alu_func_o_2 # !RC1_alu_func_o_1;
 
 
--VD1_b_o_iv_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_5 at LC_X16_Y4_N1
--operation mode is normal
 
VD1_b_o_iv_5 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] & !G1_BUS15471_i_m[5] & AB1_r32_o_3 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[5] at LC_X16_Y4_N1
--operation mode is normal
 
VD1_op2_reged[5] = DFFEAS(VD1_b_o_iv_5, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_alu_out_7_0_0_m4_0[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[5] at LC_X8_Y14_N7
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0[5] = VD1_b_o_iv_5 & TD1_alu_out_0_a3[28] & TD1_alu_out_7_0_0_o3_0 # !VD1_b_o_iv_5 & TD1_alu_out_7_0_0_m4_0_a[3];
 
 
--TD1_alu_out_7_0_0_m2_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[5] at LC_X10_Y13_N1
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_a[5] = VD1_b_o_iv_5 & !TD1_m107 # !VD1_b_o_iv_5 & !TD1_alu_out_0_a3[28];
 
 
--PD1_a_o_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[5] at LC_X23_Y4_N1
--operation mode is normal
 
PD1_a_o_a[5] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_5 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_5;
 
 
--PD1_a_o_3_Z[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[5] at LC_X20_Y11_N4
--operation mode is normal
 
SD1_r32_o_5_qfbk = SD1_r32_o_5;
PD1_a_o_3_Z[5] = PD1_a_o_3_s[0] & SD1_r32_o_5_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[5];
 
--SD1_r32_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_5 at LC_X20_Y11_N4
--operation mode is normal
 
SD1_r32_o_5 = DFFEAS(PD1_a_o_3_Z[5], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_5, , , VCC);
 
 
--UD1_shift_out_87[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[5] at LC_X15_Y19_N9
--operation mode is normal
 
UD1_shift_out_87[5] = PD1_a_o_2 & UD1_shift_out_87_d[5] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[5] # !PD1_a_o_0 & VD1_b_o_iv_7;
 
 
--UD1_shift_out_89_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[5] at LC_X15_Y19_N3
--operation mode is normal
 
UD1_shift_out_89_a[5] = PD1_a_o_2 & !UD1_shift_out_85_d[5] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[5] # !PD1_a_o_1 & !VD1_b_o_iv_4;
 
 
--UD1_shift_out_91[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[5] at LC_X12_Y11_N9
--operation mode is normal
 
UD1_shift_out_91[5] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[5] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[5];
 
 
--UD1_shift_out_86[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[5] at LC_X13_Y11_N9
--operation mode is normal
 
UD1_shift_out_86[5] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[5] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[5];
 
 
--UD1_shift_out_89_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[2] at LC_X11_Y19_N1
--operation mode is normal
 
UD1_shift_out_89_a[2] = PD1_a_o_1 & !PD1_a_o_0 & VD1_b_o_iv_0 # !PD1_a_o_1 & VD1_b_o_iv_1;
 
 
--UD1_shift_out_87[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[2] at LC_X11_Y19_N5
--operation mode is normal
 
UD1_shift_out_87[2] = PD1_a_o_0 & UD1_shift_out_80[2] # !PD1_a_o_0 & UD1_shift_out_82[2];
 
 
--UD1_shift_out_86_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_2 at LC_X19_Y17_N3
--operation mode is normal
 
UD1_shift_out_86_2 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[2] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[2];
 
 
--UD1_shift_out_91_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_2 at LC_X19_Y17_N6
--operation mode is normal
 
UD1_shift_out_91_2 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[2] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[2];
 
 
--MD1_c_0_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[2] at LC_X11_Y9_N7
--operation mode is normal
 
MD1_c_0_a[2] = VD1_un24_res & !VD1_hilo_34 # !VD1_un24_res & !VD1_hilo_2 # !VD1_un11_res;
 
 
--TD1_m112 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m112 at LC_X11_Y9_N5
--operation mode is normal
 
TD1_m112 = VD1_b_o_iv_2 & TD1_m112_a & TD1_m7 # !TD1_m112_a & !TD1_m9 # !VD1_b_o_iv_2 & TD1_m112_a;
 
 
--TD1_m109 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m109 at LC_X11_Y9_N3
--operation mode is normal
 
TD1_m109 = TD1_un1_a_add2 & TD1_alu_out_sn_m14_0_0;
 
 
--MD1_c_0_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[3] at LC_X7_Y14_N5
--operation mode is normal
 
MD1_c_0_Z[3] = TD1_alu_out_0_a3_0_0 & VD1_b_o_iv_3 # !MD1_c_0_a[3];
 
 
--TD1_alu_out_7_0_0_m2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_0 at LC_X7_Y14_N9
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_0 = PD1_a_o_3 & !TD1_alu_out_7_0_0_m2_a[3] # !PD1_a_o_3 & TD1_alu_out_7_0_0_m4_0[3];
 
 
--UD1_shift_out_89[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[3] at LC_X13_Y19_N6
--operation mode is normal
 
UD1_shift_out_89[3] = UD1_shift_out586 & UD1_shift_out_89_a[3] # !UD1_shift_out586 & PD1_a_o_0 & !UD1_shift_out_89_a[3] # !PD1_a_o_0 & UD1_shift_out_82[3];
 
 
--UD1_shift_out_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[3] at LC_X15_Y15_N7
--operation mode is normal
 
UD1_shift_out_a[3] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_91[3] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 # !UD1_shift_out_86[3];
 
 
--AB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_14 at LC_X13_Y12_N7
--operation mode is normal
 
AB1_r32_o_14_lut_out = MD1_c_0_15 # UD1_shift_out_sn_m31_i & !MD1_c_a_16 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_15;
AB1_r32_o_14 = DFFEAS(AB1_r32_o_14_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_15 at LC_X14_Y16_N4
--operation mode is normal
 
AB1_r32_o_15_lut_out = MD1_c_0_16 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_11 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_16;
AB1_r32_o_15 = DFFEAS(AB1_r32_o_15_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_12 at LC_X13_Y12_N9
--operation mode is normal
 
AB1_r32_o_12_lut_out = MD1_c_0_13 # UD1_shift_out_sn_m31_i & !MD1_c_a_14 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_13;
AB1_r32_o_12 = DFFEAS(AB1_r32_o_12_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_13 at LC_X11_Y12_N9
--operation mode is normal
 
AB1_r32_o_13_lut_out = MD1_c_0_14 # UD1_shift_out_sn_m31_i & !MD1_c_a_15 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_14;
AB1_r32_o_13 = DFFEAS(AB1_r32_o_13_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_29 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_29 at LC_X11_Y10_N3
--operation mode is normal
 
AB1_c_29 = MD1_c_0_30 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_25 # !UD1_shift_out_sn_m31_i & !MD1_c_a_31;
 
--AB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_29 at LC_X11_Y10_N3
--operation mode is normal
 
AB1_r32_o_29 = DFFEAS(AB1_c_29, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_rd_status_29_0_a2_0_8_a is mips_sys:isys|mips_dvc:imips_dvc|rd_status_29_0_a2_0_8_a at LC_X28_Y9_N3
--operation mode is normal
 
F1_rd_status_29_0_a2_0_8_a = !AB1_r32_o_7 & !AB1_r32_o_9 & !AB1_r32_o_6 & !AB1_r32_o_8;
 
 
--AB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_19 at LC_X14_Y10_N8
--operation mode is normal
 
AB1_r32_o_19_lut_out = MD1_c_0_20 # UD1_shift_out_sn_m31_i & MD1_c_a_21 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_20;
AB1_r32_o_19 = DFFEAS(AB1_r32_o_19_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_18 at LC_X10_Y14_N0
--operation mode is normal
 
AB1_r32_o_18_lut_out = MD1_c_1_20 # UD1_shift_out_sn_m31_i & MD1_c_a_20 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_19;
AB1_r32_o_18 = DFFEAS(AB1_r32_o_18_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--F1_dout_0_0_a3_6_5_2[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_2[0] at LC_X26_Y3_N4
--operation mode is normal
 
F1_dout_0_0_a3_6_5_2[0] = !AB1_r32_o_16 & !AB1_r32_o_17;
 
 
--F1_dout_0_0_a3_6_5_12_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_12_a[0] at LC_X26_Y3_N1
--operation mode is normal
 
F1_dout_0_0_a3_6_5_12_a[0] = !AB1_r32_o_26 & !AB1_r32_o_27 & !AB1_r32_o_25 & !AB1_r32_o_24;
 
 
--AB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_11 at LC_X14_Y11_N6
--operation mode is normal
 
AB1_r32_o_11_lut_out = MD1_c_0_12 # UD1_shift_out_sn_m31_i & !MD1_c_a_13 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_12;
AB1_r32_o_11 = DFFEAS(AB1_r32_o_11_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_28 at LC_X11_Y13_N3
--operation mode is normal
 
AB1_r32_o_28_lut_out = VD1_un11_res & VD1_hilo_30 # !TD1_m97 # !MD1_c_a_30;
AB1_r32_o_28 = DFFEAS(AB1_r32_o_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--JC1_rd_status_29_0_a2_0_7 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|rd_status_29_0_a2_0_7 at LC_X28_Y6_N5
--operation mode is normal
 
JC1_dmem_ctl_o_3__Z_qfbk = JC1_dmem_ctl_o_3__Z;
JC1_rd_status_29_0_a2_0_7 = !RB1_byte_addr_o_0 & !AB1_r32_o_4 & !JC1_dmem_ctl_o_3__Z_qfbk & !AB1_r32_o_10;
 
--JC1_dmem_ctl_o_3__Z is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_3__Z at LC_X28_Y6_N5
--operation mode is normal
 
JC1_dmem_ctl_o_3__Z = DFFEAS(JC1_rd_status_29_0_a2_0_7, GLOBAL(E1__clk0), VCC, , , QC1_dmem_ctl_o_3, , , VCC);
 
 
--F1_dout_0_0_a3_6_5_8[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_8[0] at LC_X28_Y6_N2
--operation mode is normal
 
F1_dout_0_0_a3_6_5_8[0] = !AB1_r32_o_20 & !AB1_r32_o_22 & !AB1_r32_o_23 & !AB1_r32_o_21;
 
 
--K1_cntr_5_0[6] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[6] at LC_X32_Y5_N2
--operation mode is normal
 
K1_s_cntr_6__Z_qfbk = K1_s_cntr_6__Z;
K1_cntr_5_0[6] = F1_wr_tmr_data_0_a2 & CB1_r32_o_6 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_6__Z_qfbk;
 
--K1_s_cntr_6__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_6__Z at LC_X32_Y5_N2
--operation mode is normal
 
K1_s_cntr_6__Z = DFFEAS(K1_cntr_5_0[6], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_6, , , VCC);
 
 
--UB1_dout_2_i_0[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[6] at LC_X31_Y14_N5
--operation mode is normal
 
UB1_dout_2_i_0[6] = !UB1_dout_2_i_0_a[6] & !UB1_dout_2_i_0_a2_x[6] & JE1_q_b[6] # !UB1_dout_2_i_o2[3];
 
 
--WB11L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_6__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y14_N4
--operation mode is normal
 
WB11L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[6] # !UB1_un1_byte_addr_2 & WB11L1;
 
--DB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_6 at LC_X31_Y14_N4
--operation mode is normal
 
DB1_r32_o_6 = DFFEAS(WB11L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[6] at LC_X24_Y7_N3
--operation mode is normal
 
GD1_dout_iv_1_a[6] = FD1_r_data_6 & !FD1_N_16_i_0_s2 & !AB1_r32_o_4 # !ZD1_mux_fw_1 # !FD1_r_data_6 & !AB1_r32_o_4 # !ZD1_mux_fw_1;
 
 
--UD1_shift_out_87[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[6] at LC_X12_Y15_N4
--operation mode is normal
 
UD1_shift_out_87[6] = PD1_a_o_0 & UD1_shift_out_87_d[6] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[6] # !PD1_a_o_2 & VD1_b_o_iv_8;
 
 
--UD1_shift_out_89_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[6] at LC_X14_Y19_N7
--operation mode is normal
 
UD1_shift_out_89_a[6] = PD1_a_o_1 & !UD1_shift_out_85_d[6] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[6] # !PD1_a_o_2 & !VD1_b_o_iv_5;
 
 
--MD1_c_1_Z[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_Z[6] at LC_X6_Y15_N2
--operation mode is normal
 
MD1_c_1_Z[6] = TD1_alu_out_0_a2_0 # VD1_b_o_iv_6 & TD1_alu_out_0_a3_0_0 # !MD1_c_1_a[6];
 
 
--TD1_un1_a_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add6 at LC_X12_Y9_N1
--operation mode is arithmetic
 
TD1_un1_a_add6_carry_eqn = (!TD1_un1_a_carry_4 & TD1_un1_a_carry_5) # (TD1_un1_a_carry_4 & TD1L125);
TD1_un1_a_add6 = PD1_a_o_6 $ TD1_un1_b_1_combout[6] $ !TD1_un1_a_add6_carry_eqn;
 
--TD1_un1_a_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_6 at LC_X12_Y9_N1
--operation mode is arithmetic
 
TD1_un1_a_carry_6_cout_0 = PD1_a_o_6 & TD1_un1_b_1_combout[6] # !TD1_un1_a_carry_5 # !PD1_a_o_6 & TD1_un1_b_1_combout[6] & !TD1_un1_a_carry_5;
TD1_un1_a_carry_6 = CARRY(TD1_un1_a_carry_6_cout_0);
 
--TD1L325 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_6~COUT1_1 at LC_X12_Y9_N1
--operation mode is arithmetic
 
TD1L325_cout_1 = PD1_a_o_6 & TD1_un1_b_1_combout[6] # !TD1L125 # !PD1_a_o_6 & TD1_un1_b_1_combout[6] & !TD1L125;
TD1L325 = CARRY(TD1L325_cout_1);
 
 
--UD1_shift_out_91[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[6] at LC_X20_Y18_N7
--operation mode is normal
 
UD1_shift_out_91[6] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[6] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[6];
 
 
--UD1_shift_out_86[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[6] at LC_X19_Y15_N3
--operation mode is normal
 
UD1_shift_out_86[6] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[6] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[6];
 
 
--K1_cntr_5_0[5] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[5] at LC_X30_Y4_N2
--operation mode is normal
 
K1_s_cntr_5__Z_qfbk = K1_s_cntr_5__Z;
K1_cntr_5_0[5] = F1_wr_tmr_data_0_a2 & CB1_r32_o_5 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_5__Z_qfbk;
 
--K1_s_cntr_5__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_5__Z at LC_X30_Y4_N2
--operation mode is normal
 
K1_s_cntr_5__Z = DFFEAS(K1_cntr_5_0[5], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_5, , , VCC);
 
 
--UB1_dout_2_i_0[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[5] at LC_X31_Y14_N2
--operation mode is normal
 
UB1_dout_2_i_0[5] = !UB1_dout_2_i_0_a[5] & !UB1_dout_2_i_0_a2_x[5] & JE1_q_b[5] # !UB1_dout_2_i_o2[3];
 
 
--WB01L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_5__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y14_N3
--operation mode is normal
 
WB01L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[5] # !UB1_un1_byte_addr_2 & WB01L1;
 
--DB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_5 at LC_X31_Y14_N3
--operation mode is normal
 
DB1_r32_o_5 = DFFEAS(WB01L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[5] at LC_X20_Y7_N4
--operation mode is normal
 
GD1_dout_iv_1_a[5] = ZD1_mux_fw_1 & !AB1_r32_o_3 & !FD1_N_16_i_0_s2 # !FD1_r_data_5 # !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_5;
 
 
--K1_cntr_5_0[4] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[4] at LC_X30_Y4_N9
--operation mode is normal
 
K1_s_cntr_4__Z_qfbk = K1_s_cntr_4__Z;
K1_cntr_5_0[4] = F1_wr_tmr_data_0_a2 & CB1_r32_o_4 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_4__Z_qfbk;
 
--K1_s_cntr_4__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_4__Z at LC_X30_Y4_N9
--operation mode is normal
 
K1_s_cntr_4__Z = DFFEAS(K1_cntr_5_0[4], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_4, , , VCC);
 
 
--UB1_dout_2_i_0[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[4] at LC_X30_Y14_N6
--operation mode is normal
 
UB1_dout_2_i_0[4] = !UB1_dout_2_i_0_a[4] & !UB1_dout_2_i_0_a2_x[4] & JE1_q_b[4] # !UB1_dout_2_i_o2[3];
 
 
--WB9L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_4__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y14_N2
--operation mode is normal
 
WB9L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[4] # !UB1_un1_byte_addr_2 & WB9L1;
 
--DB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_4 at LC_X30_Y14_N2
--operation mode is normal
 
DB1_r32_o_4 = DFFEAS(WB9L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[4] at LC_X21_Y7_N0
--operation mode is normal
 
GD1_dout_iv_1_a[4] = FD1_r_data_4 & !FD1_N_16_i_0_s2 & !AB1_r32_o_2 # !ZD1_mux_fw_1 # !FD1_r_data_4 & !AB1_r32_o_2 # !ZD1_mux_fw_1;
 
 
--K1_cntr_5_0[3] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[3] at LC_X32_Y5_N5
--operation mode is normal
 
K1_s_cntr_3__Z_qfbk = K1_s_cntr_3__Z;
K1_cntr_5_0[3] = F1_wr_tmr_data_0_a2 & CB1_r32_o_3 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_3__Z_qfbk;
 
--K1_s_cntr_3__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_3__Z at LC_X32_Y5_N5
--operation mode is normal
 
K1_s_cntr_3__Z = DFFEAS(K1_cntr_5_0[3], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_3, , , VCC);
 
 
--M1_buffer_reg_3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_3 at LC_X33_Y5_N7
--operation mode is normal
 
M1_buffer_reg_3_lut_out = M1_rx_sr[3];
M1_buffer_reg_3 = DFFEAS(M1_buffer_reg_3_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_578, , , !sys_rst, );
 
 
--F1_dout_0_0_a3_6[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6[0] at LC_X28_Y6_N8
--operation mode is normal
 
F1_dout_0_0_a3_6[0] = !F1_dout_0_0_a3_6_a[0] & F1_dout_0_0_a3_6_5_12[0] & F1_rd_status_29_0_a2_0_8 & F1_dout_0_0_a3_6_5_14[0];
 
 
--M1_int_req is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|int_req at LC_X33_Y15_N9
--operation mode is normal
 
M1_int_req_lut_out = M1_ua_state[4];
M1_int_req = DFFEAS(M1_int_req_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--UB1_dout_2_i[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i[3] at LC_X31_Y13_N6
--operation mode is normal
 
UB1_dout_2_i[3] = !UB1_dout_2_i_a[3] & !UB1_dout_2_i_a2_x[3] & JE1_q_b[3] # !UB1_dout_2_i_o2[3];
 
 
--WB8L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_3__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y13_N8
--operation mode is normal
 
WB8L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i[3] # !UB1_un1_byte_addr_2 & WB8L1;
 
--DB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_3 at LC_X31_Y13_N8
--operation mode is normal
 
DB1_r32_o_3 = DFFEAS(WB8L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[3] at LC_X27_Y7_N2
--operation mode is normal
 
GD1_dout_iv_1_a[3] = AB1_r32_o_1 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_3 # !AB1_r32_o_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_3;
 
 
--K1_cntr_5_0[2] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[2] at LC_X34_Y7_N9
--operation mode is normal
 
K1_s_cntr_2__Z_qfbk = K1_s_cntr_2__Z;
K1_cntr_5_0[2] = F1_wr_tmr_data_0_a2 & CB1_r32_o_2 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_2__Z_qfbk;
 
--K1_s_cntr_2__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_2__Z at LC_X34_Y7_N9
--operation mode is normal
 
K1_s_cntr_2__Z = DFFEAS(K1_cntr_5_0[2], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_2, , , VCC);
 
 
--UB1_dout_2_i_0[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[2] at LC_X30_Y9_N6
--operation mode is normal
 
UB1_dout_2_i_0[2] = !UB1_dout_2_i_0_a[2] & !UB1_dout_2_i_0_a2_x[2] & JE1_q_b[2] # !UB1_dout_2_i_o2[3];
 
 
--WB7L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_2__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y9_N3
--operation mode is normal
 
WB7L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[2] # !UB1_un1_byte_addr_2 & WB7L1;
 
--DB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_2 at LC_X30_Y9_N3
--operation mode is normal
 
DB1_r32_o_2 = DFFEAS(WB7L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[2] at LC_X21_Y8_N4
--operation mode is normal
 
GD1_dout_iv_1_a[2] = AB1_r32_o_0 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_2 # !AB1_r32_o_0 & !FD1_N_16_i_0_s2 # !FD1_r_data_2;
 
 
--K1_cntr_5_0[1] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[1] at LC_X25_Y2_N2
--operation mode is normal
 
K1_s_cntr_1__Z_qfbk = K1_s_cntr_1__Z;
K1_cntr_5_0[1] = F1_wr_tmr_data_0_a2 & CB1_r32_o_1 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_1__Z_qfbk;
 
--K1_s_cntr_1__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_1__Z at LC_X25_Y2_N2
--operation mode is normal
 
K1_s_cntr_1__Z = DFFEAS(K1_cntr_5_0[1], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_1, , , VCC);
 
 
--M1_buffer_reg_1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_1 at LC_X33_Y5_N1
--operation mode is normal
 
M1_buffer_reg_1_lut_out = M1_rx_sr[1];
M1_buffer_reg_1 = DFFEAS(M1_buffer_reg_1_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_578, , , !sys_rst, );
 
 
--F1_r_key1 is mips_sys:isys|mips_dvc:imips_dvc|r_key1 at LC_X33_Y6_N9
--operation mode is normal
 
F1_r_key1_lut_out = key1;
F1_r_key1 = DFFEAS(F1_r_key1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_0[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[1] at LC_X30_Y13_N5
--operation mode is normal
 
UB1_dout_2_i_0[1] = !UB1_dout_2_i_0_a2_x[1] & !UB1_dout_2_i_0_a[1] & JE1_q_b[1] # !UB1_dout_2_i_o2[3];
 
 
--WB6L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_1__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y13_N6
--operation mode is normal
 
WB6L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[1] # !UB1_un1_byte_addr_2 & WB6L1;
 
--DB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_1 at LC_X30_Y13_N6
--operation mode is normal
 
DB1_r32_o_1 = DFFEAS(WB6L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[1] at LC_X26_Y10_N8
--operation mode is normal
 
GD1_dout_iv_1_a[1] = FD1_r_data_1 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_1 # !FD1_r_data_1 & !ZD1_mux_fw_1 # !RB1_byte_addr_o_1;
 
 
--UD1_shift_out_89_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[1] at LC_X16_Y17_N4
--operation mode is normal
 
UD1_shift_out_89_a[1] = VD1_b_o_iv_0 & !PD1_a_o_2;
 
 
--UD1_shift_out_87[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[1] at LC_X16_Y17_N6
--operation mode is normal
 
UD1_shift_out_87[1] = PD1_a_o_0 & UD1_shift_out_80[1] # !PD1_a_o_0 & UD1_shift_out_82[1];
 
 
--UD1_shift_out_86_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_1 at LC_X14_Y13_N1
--operation mode is normal
 
UD1_shift_out_86_1 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[1] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[1];
 
 
--UD1_shift_out_91_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_1 at LC_X15_Y13_N9
--operation mode is normal
 
UD1_shift_out_91_1 = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[1] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[1];
 
 
--MD1_c_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[1] at LC_X13_Y11_N7
--operation mode is normal
 
MD1_c_0_a[1] = VD1_un24_res & !VD1_hilo_33 # !VD1_un24_res & !VD1_hilo_1 # !VD1_un11_res;
 
 
--TD1_alu_out_7_0_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0 at LC_X12_Y10_N0
--operation mode is normal
 
TD1_alu_out_7_0_0 = TD1_m107 & !TD1_alu_out_7_0_a[1] # !TD1_m107 & TD1_alu_out_6_0[1];
 
 
--K1_cntr_5_0[0] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[0] at LC_X32_Y5_N0
--operation mode is normal
 
K1_s_cntr_0__Z_qfbk = K1_s_cntr_0__Z;
K1_cntr_5_0[0] = F1_wr_tmr_data_0_a2 & CB1_r32_o_0 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_0__Z_qfbk;
 
--K1_s_cntr_0__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_0__Z at LC_X32_Y5_N0
--operation mode is normal
 
K1_s_cntr_0__Z = DFFEAS(K1_cntr_5_0[0], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_0, , , VCC);
 
 
--M1_buffer_reg_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|buffer_reg_0 at LC_X33_Y5_N6
--operation mode is normal
 
M1_buffer_reg_0_lut_out = M1_rx_sr[0];
M1_buffer_reg_0 = DFFEAS(M1_buffer_reg_0_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_578, , , !sys_rst, );
 
 
--F1_r_key2 is mips_sys:isys|mips_dvc:imips_dvc|r_key2 at LC_X33_Y6_N2
--operation mode is normal
 
F1_r_key2_lut_out = key2;
F1_r_key2 = DFFEAS(F1_r_key2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_0[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0[0] at LC_X31_Y7_N6
--operation mode is normal
 
UB1_dout_2_i_0[0] = !UB1_dout_2_i_0_a[0] & !UB1_dout_2_i_0_a2_x[0] & JE1_q_b[0] # !UB1_dout_2_i_o2[3];
 
 
--WB5L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_0__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y7_N4
--operation mode is normal
 
WB5L1 = !UB1_un1_dout98_i_0_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_0[0] # !UB1_un1_byte_addr_2 & WB5L1;
 
--DB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_0 at LC_X31_Y7_N4
--operation mode is normal
 
DB1_r32_o_0 = DFFEAS(WB5L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[0] at LC_X27_Y5_N3
--operation mode is normal
 
GD1_dout_iv_1_a[0] = FD1_r_data_0 & !FD1_N_16_i_0_s2 & !RB1_byte_addr_o_0 # !ZD1_mux_fw_1 # !FD1_r_data_0 & !RB1_byte_addr_o_0 # !ZD1_mux_fw_1;
 
 
--MD1_c_1_Z[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_Z[0] at LC_X9_Y14_N2
--operation mode is normal
 
MD1_c_1_Z[0] = VD1_res_2_0 # !RC1_alu_func_o_3 & TD1_m107 & !MD1_c_1_a[0];
 
 
--MD1_c_2_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[0] at LC_X9_Y14_N7
--operation mode is normal
 
MD1_c_2_a[0] = RC1_alu_func_o_4 & RC1_alu_func_o_0 & !PD1_a_o_0 & !VD1_b_o_iv_0 # !RC1_alu_func_o_0 & PD1_a_o_0 $ VD1_b_o_iv_0;
 
 
--TD1_un1_a_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add0 at LC_X12_Y10_N5
--operation mode is arithmetic
 
TD1_un1_a_add0_carry_eqn = TD1_un1_a_add0_start_cout;
TD1_un1_a_add0 = TD1_un1_b_1_combout[0] $ PD1_a_o_0 $ !TD1_un1_a_add0_carry_eqn;
 
--TD1_un1_a_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_0 at LC_X12_Y10_N5
--operation mode is arithmetic
 
TD1_un1_a_carry_0_cout_0 = TD1_un1_b_1_combout[0] & PD1_a_o_0 # !TD1_un1_a_add0_start_cout # !TD1_un1_b_1_combout[0] & PD1_a_o_0 & !TD1_un1_a_add0_start_cout;
TD1_un1_a_carry_0 = CARRY(TD1_un1_a_carry_0_cout_0);
 
--TD1L215 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_0~COUT1_1 at LC_X12_Y10_N5
--operation mode is arithmetic
 
TD1L215_cout_1 = TD1_un1_b_1_combout[0] & PD1_a_o_0 # !TD1_un1_a_add0_start_cout # !TD1_un1_b_1_combout[0] & PD1_a_o_0 & !TD1_un1_a_add0_start_cout;
TD1L215 = CARRY(TD1L215_cout_1);
 
 
--UD1_shift_out_91[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[0] at LC_X21_Y13_N4
--operation mode is normal
 
UD1_shift_out_91[0] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[0] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[0];
 
 
--UD1_shift_out_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[0] at LC_X14_Y9_N7
--operation mode is normal
 
UD1_shift_out_a[0] = !UD1_shift_out586 & UD1_shift_out_sn_m31_i & UD1_shift_out_86[0] # !UD1_shift_out_sn_m31_i & UD1_shift_out_87[0];
 
 
--TD1_alu_out_9_a2_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_a[0] at LC_X9_Y14_N5
--operation mode is normal
 
TD1_alu_out_9_a2_a[0] = !RC1_alu_func_o_2 & !RC1_alu_func_o_3 & !RC1_alu_func_o_1 & RC1_alu_func_o_4;
 
 
--TD1_lt31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt31 at LC_X16_Y7_N5
--operation mode is normal
 
TD1_lt31_carry_eqn = TD1_lt_30;
TD1_lt31 = VD1_b_o_iv_31 & TD1_lt31_carry_eqn # !PD1_a_o_31 # !VD1_b_o_iv_31 & TD1_lt31_carry_eqn & !PD1_a_o_31;
 
 
--TD1_sum_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_add32 at LC_X15_Y6_N6
--operation mode is normal
 
TD1_sum_add32_carry_eqn = (!TD1_sum_carry_30 & TD1_sum_carry_31) # (TD1_sum_carry_30 & TD1L444);
TD1_sum_add32 = PD1_a_o_31 $ VD1_b_o_iv_31 $ TD1_sum_add32_carry_eqn;
 
 
--N1_tx_sr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[4] at LC_X16_Y2_N2
--operation mode is normal
 
N1_tx_sr[4]_lut_out = N1_read_request_ff & Y1_q_b[4] # !N1_read_request_ff & N1_tx_sr[5];
N1_tx_sr[4] = DFFEAS(N1_tx_sr[4]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_clk_ctr26_i_0_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_0 at LC_X14_Y3_N6
--operation mode is normal
 
N1_ua_state[6]_qfbk = N1_ua_state[6];
N1_clk_ctr26_i_0_0 = N1_clk_ctr26_i_0_0_a & !N1_ua_state[1] & !N1_ua_state[6]_qfbk # !sys_rst;
 
--N1_ua_state[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[6] at LC_X14_Y3_N6
--operation mode is normal
 
N1_ua_state[6] = DFFEAS(N1_clk_ctr26_i_0_0, GLOBAL(E1__clk0), VCC, , C1_G_451_x, N1_ua_state[5], , !sys_rst, VCC);
 
 
--N1_clk_ctr26_i_0_a4_0_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_5 at LC_X15_Y3_N7
--operation mode is normal
 
N1_clk_ctr26_i_0_a4_0_5 = N1_clk_ctr[11] & !N1_clk_ctr[8] & N1_clk_ctr[3] & !N1_clk_ctr[4];
 
 
--N1_clk_ctr26_i_0_a4_0_6 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_6 at LC_X15_Y3_N9
--operation mode is normal
 
N1_clk_ctr26_i_0_a4_0_6 = !N1_clk_ctr[2] & !N1_clk_ctr[10] & !N1_clk_ctr26_i_0_a4_0_6_a & N1_clk_ctr[5];
 
 
--F1_wr_tmr_data_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2 at LC_X33_Y9_N1
--operation mode is normal
 
F1_wr_tmr_data_0_a2 = F1_wr_tmr_data_0_a2_0 & AB1_r32_o_3 & F1_wr_cmd_0_a2_0;
 
 
--K1_un2_w_irq_21 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_21 at LC_X31_Y3_N7
--operation mode is normal
 
K1_un2_w_irq_21 = !K1_cntr_28 & !K1_cntr_31 & !K1_cntr_30 & !K1_cntr_29;
 
 
--K1_un1_ld_1_a is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1_a at LC_X31_Y3_N9
--operation mode is normal
 
K1_un1_ld_1_a = !K1_un2_w_irq_20 # !K1_un2_w_irq_23 # !K1_un2_w_irq_22;
 
 
--K1_un2_w_irq_28 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_28 at LC_X30_Y6_N4
--operation mode is normal
 
K1_un2_w_irq_28 = K1_un2_w_irq_16 & K1_un2_w_irq_17 & K1_un2_w_irq_19 & K1_un2_w_irq_18;
 
 
--M1_rx_sr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[7] at LC_X33_Y4_N5
--operation mode is normal
 
M1_rx_sr[7]_lut_out = M1_rxq1;
M1_rx_sr[7] = DFFEAS(M1_rx_sr[7]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--C1_G_578 is mips_sys:isys|G_578 at LC_X33_Y16_N7
--operation mode is normal
 
C1_G_578 = M1_un1_clk_ctr_equ0_0_a2_0 & M1_un1_clk_ctr_equ0_0_a2 & C1_G_578_a # !sys_rst;
 
 
--F1_dout_0_0_a3_5_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_3[0] at LC_X33_Y8_N2
--operation mode is normal
 
F1_dout_0_0_a3_5_3[0] = AB1_r32_o_3 & !AB1_r32_o_2 & !AB1_r32_o_0 & F1_dout_0_0_a3_5_3_a[0];
 
 
--GE1_q_a[7] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[7] at M4K_X17_Y5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
GE1_q_a[7]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[7]_PORT_A_data_in_reg = DFFE(GE1_q_a[7]_PORT_A_data_in, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_data_in = BUS(CB1_dout_2_7, CB1_dout_2_6);
GE1_q_a[7]_PORT_B_data_in_reg = DFFE(GE1_q_a[7]_PORT_B_data_in, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[7]_PORT_A_address_reg = DFFE(GE1_q_a[7]_PORT_A_address, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[7]_PORT_B_address_reg = DFFE(GE1_q_a[7]_PORT_B_address, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_A_write_enable = GND;
GE1_q_a[7]_PORT_A_write_enable_reg = DFFE(GE1_q_a[7]_PORT_A_write_enable, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_write_enable = WB1L2;
GE1_q_a[7]_PORT_B_write_enable_reg = DFFE(GE1_q_a[7]_PORT_B_write_enable, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[7]_PORT_A_data_out = MEMORY(GE1_q_a[7]_PORT_A_data_in_reg, GE1_q_a[7]_PORT_B_data_in_reg, GE1_q_a[7]_PORT_A_address_reg, GE1_q_a[7]_PORT_B_address_reg, GE1_q_a[7]_PORT_A_write_enable_reg, GE1_q_a[7]_PORT_B_write_enable_reg, , , GE1_q_a[7]_clock_0, , , , , );
GE1_q_a[7] = GE1_q_a[7]_PORT_A_data_out[0];
 
--GE1_q_b[7] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[7] at M4K_X17_Y5
GE1_q_b[7]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[7]_PORT_A_data_in_reg = DFFE(GE1_q_b[7]_PORT_A_data_in, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_data_in = BUS(CB1_dout_2_7, CB1_dout_2_6);
GE1_q_b[7]_PORT_B_data_in_reg = DFFE(GE1_q_b[7]_PORT_B_data_in, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[7]_PORT_A_address_reg = DFFE(GE1_q_b[7]_PORT_A_address, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[7]_PORT_B_address_reg = DFFE(GE1_q_b[7]_PORT_B_address, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_A_write_enable = GND;
GE1_q_b[7]_PORT_A_write_enable_reg = DFFE(GE1_q_b[7]_PORT_A_write_enable, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_write_enable = WB1L2;
GE1_q_b[7]_PORT_B_write_enable_reg = DFFE(GE1_q_b[7]_PORT_B_write_enable, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[7]_PORT_B_data_out = MEMORY(GE1_q_b[7]_PORT_A_data_in_reg, GE1_q_b[7]_PORT_B_data_in_reg, GE1_q_b[7]_PORT_A_address_reg, GE1_q_b[7]_PORT_B_address_reg, GE1_q_b[7]_PORT_A_write_enable_reg, GE1_q_b[7]_PORT_B_write_enable_reg, , , GE1_q_b[7]_clock_0, , , , , );
GE1_q_b[7] = GE1_q_b[7]_PORT_B_data_out[0];
 
--GE1_q_a[6] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[6] at M4K_X17_Y5
GE1_q_a[7]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[7]_PORT_A_data_in_reg = DFFE(GE1_q_a[7]_PORT_A_data_in, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_data_in = BUS(CB1_dout_2_7, CB1_dout_2_6);
GE1_q_a[7]_PORT_B_data_in_reg = DFFE(GE1_q_a[7]_PORT_B_data_in, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[7]_PORT_A_address_reg = DFFE(GE1_q_a[7]_PORT_A_address, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[7]_PORT_B_address_reg = DFFE(GE1_q_a[7]_PORT_B_address, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_A_write_enable = GND;
GE1_q_a[7]_PORT_A_write_enable_reg = DFFE(GE1_q_a[7]_PORT_A_write_enable, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_PORT_B_write_enable = WB1L2;
GE1_q_a[7]_PORT_B_write_enable_reg = DFFE(GE1_q_a[7]_PORT_B_write_enable, GE1_q_a[7]_clock_0, , , );
GE1_q_a[7]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[7]_PORT_A_data_out = MEMORY(GE1_q_a[7]_PORT_A_data_in_reg, GE1_q_a[7]_PORT_B_data_in_reg, GE1_q_a[7]_PORT_A_address_reg, GE1_q_a[7]_PORT_B_address_reg, GE1_q_a[7]_PORT_A_write_enable_reg, GE1_q_a[7]_PORT_B_write_enable_reg, , , GE1_q_a[7]_clock_0, , , , , );
GE1_q_a[6] = GE1_q_a[7]_PORT_A_data_out[1];
 
--GE1_q_b[6] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[6] at M4K_X17_Y5
GE1_q_b[7]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[7]_PORT_A_data_in_reg = DFFE(GE1_q_b[7]_PORT_A_data_in, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_data_in = BUS(CB1_dout_2_7, CB1_dout_2_6);
GE1_q_b[7]_PORT_B_data_in_reg = DFFE(GE1_q_b[7]_PORT_B_data_in, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[7]_PORT_A_address_reg = DFFE(GE1_q_b[7]_PORT_A_address, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[7]_PORT_B_address_reg = DFFE(GE1_q_b[7]_PORT_B_address, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_A_write_enable = GND;
GE1_q_b[7]_PORT_A_write_enable_reg = DFFE(GE1_q_b[7]_PORT_A_write_enable, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_PORT_B_write_enable = WB1L2;
GE1_q_b[7]_PORT_B_write_enable_reg = DFFE(GE1_q_b[7]_PORT_B_write_enable, GE1_q_b[7]_clock_0, , , );
GE1_q_b[7]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[7]_PORT_B_data_out = MEMORY(GE1_q_b[7]_PORT_A_data_in_reg, GE1_q_b[7]_PORT_B_data_in_reg, GE1_q_b[7]_PORT_A_address_reg, GE1_q_b[7]_PORT_B_address_reg, GE1_q_b[7]_PORT_A_write_enable_reg, GE1_q_b[7]_PORT_B_write_enable_reg, , , GE1_q_b[7]_clock_0, , , , , );
GE1_q_b[6] = GE1_q_b[7]_PORT_B_data_out[1];
 
 
--UB1_dout_2_i_i_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_0[7] at LC_X30_Y8_N5
--operation mode is normal
 
UB1_dout_2_i_i_0[7] = RB1_byte_addr_o_1 & GE1_q_b[7] & UB1_dout_2_i_i_0_a[7] # RB1_byte_addr_o_0;
 
 
--UB1_dout_2_i_i_a3_1[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_1[7] at LC_X30_Y8_N2
--operation mode is normal
 
UB1_dout_2_i_i_a3_1[7] = RB1_ctl_o_2 & UB1_dout_2_i_i_o3_0[7] & RB1_ctl_o_1;
 
 
--UB1_dout_2_i_i_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a[7] at LC_X29_Y8_N9
--operation mode is normal
 
UB1_dout_2_i_i_a[7] = !UB1_dout_2_i_i_a2_1[7] & !UB1_dout_2_i_i_a2_2[7] & !JE1_q_b[7] # !UB1_dout_2_i_i_o2_0[7];
 
 
--RB1_ctl_o_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_3 at LC_X29_Y9_N6
--operation mode is normal
 
RB1_ctl_o_3_lut_out = QC1_dmem_ctl_o_3 & !AB1_c_29;
RB1_ctl_o_3 = DFFEAS(RB1_ctl_o_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RB1_ctl_o_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_0 at LC_X29_Y9_N2
--operation mode is normal
 
RB1_ctl_o_0_lut_out = QC1_dmem_ctl_o_0 & !AB1_c_29;
RB1_ctl_o_0 = DFFEAS(RB1_ctl_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RB1_ctl_o_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_1 at LC_X29_Y9_N1
--operation mode is normal
 
RB1_ctl_o_1_lut_out = QC1_dmem_ctl_o_1 & !AB1_c_29;
RB1_ctl_o_1 = DFFEAS(RB1_ctl_o_1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RB1_ctl_o_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|ctl_o_2 at LC_X29_Y9_N5
--operation mode is normal
 
RB1_ctl_o_2_lut_out = QC1_dmem_ctl_o_2 & !AB1_c_29;
RB1_ctl_o_2 = DFFEAS(RB1_ctl_o_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_un23_qb_i_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qb_i_0_a2 at LC_X25_Y12_N2
--operation mode is normal
 
FD1_r_rdaddress_b[4]_qfbk = FD1_r_rdaddress_b[4];
FD1_un23_qb_i_0_a2 = !FD1_r_rdaddress_b[0] & !FD1_r_rdaddress_b[1] & !FD1_r_rdaddress_b[4]_qfbk & FD1_un23_qb_i_0_a2_a;
 
--FD1_r_rdaddress_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[4] at LC_X25_Y12_N2
--operation mode is normal
 
FD1_r_rdaddress_b[4] = DFFEAS(FD1_un23_qb_i_0_a2, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[4], , , VCC);
 
 
--FD1_un14_qb_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE at LC_X26_Y14_N8
--operation mode is normal
 
FD1_un14_qb_NE = FD1_un14_qb_NE_a # FD1_un14_qb_NE_1 # FD1_r_rdaddress_b[4] $ FD1_r_wraddress[4];
 
 
--ZD1_un32_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un32_mux_fw at LC_X26_Y10_N1
--operation mode is normal
 
ZD1_un32_mux_fw = !ZD1_mux_fw_1 & WD1_un30_mux_fw # ZD1_un17_mux_fw_NE # !MC1_wb_we_o_0;
 
 
--FD1_N_16_i_0_s2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_16_i_0_s2 at LC_X26_Y10_N0
--operation mode is normal
 
FD1_N_16_i_0_s2 = !FD1_un14_qb_NE & FD1_r_wren & !FD1_un23_qb_i_0_a2 & ZD1_un32_mux_fw;
 
 
--FD1_r_rdaddress_b_0_x[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[0] at LC_X25_Y12_N6
--operation mode is normal
 
FD1_r_rdaddress_b[0]_qfbk = FD1_r_rdaddress_b[0];
FD1_r_rdaddress_b_0_x[0] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[0]_qfbk # !AD1_CurrState_Sreg0_2 & JE1_q_a[0];
 
--FD1_r_rdaddress_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[0] at LC_X25_Y12_N6
--operation mode is normal
 
FD1_r_rdaddress_b[0] = DFFEAS(FD1_r_rdaddress_b_0_x[0], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[0], , , VCC);
 
 
--FD1_r_rdaddress_b_0_x[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[1] at LC_X25_Y12_N9
--operation mode is normal
 
FD1_r_rdaddress_b_0_x[1] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[1] # !AD1_CurrState_Sreg0_2 & JE1_q_a[1];
 
 
--FD1_r_rdaddress_b_0_x[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[2] at LC_X25_Y12_N3
--operation mode is normal
 
FD1_r_rdaddress_b_0_x[2] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[2] # !AD1_CurrState_Sreg0_2 & JE1_q_a[2];
 
 
--FD1_r_rdaddress_b_0_x[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[3] at LC_X25_Y12_N7
--operation mode is normal
 
FD1_r_rdaddress_b_0_x[3] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[3] # !AD1_CurrState_Sreg0_2 & JE1_q_a[3];
 
 
--FD1_r_rdaddress_b_0_x[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b_0_x[4] at LC_X25_Y12_N0
--operation mode is normal
 
FD1_r_rdaddress_b_0_x[4] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_b[4] # !AD1_CurrState_Sreg0_2 & JE1_q_a[4];
 
 
--ZD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE_1 at LC_X26_Y9_N0
--operation mode is normal
 
ED1_r32_o_17_qfbk = ED1_r32_o_17;
ZD1_un17_mux_fw_NE_1 = ED1_r32_o_16 & NB1_r5_o_1 $ ED1_r32_o_17_qfbk # !NB1_r5_o_0 # !ED1_r32_o_16 & NB1_r5_o_0 # NB1_r5_o_1 $ ED1_r32_o_17_qfbk;
 
--ED1_r32_o_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_17 at LC_X26_Y9_N0
--operation mode is normal
 
ED1_r32_o_17 = DFFEAS(ZD1_un17_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[1], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--ZD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un17_mux_fw_NE_a at LC_X26_Y13_N1
--operation mode is normal
 
ED1_r32_o_18_qfbk = ED1_r32_o_18;
ZD1_un17_mux_fw_NE_a = NB1_r5_o_3 & ED1_r32_o_18_qfbk $ NB1_r5_o_2 # !ED1_r32_o_19 # !NB1_r5_o_3 & ED1_r32_o_19 # ED1_r32_o_18_qfbk $ NB1_r5_o_2;
 
--ED1_r32_o_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_18 at LC_X26_Y13_N1
--operation mode is normal
 
ED1_r32_o_18 = DFFEAS(ZD1_un17_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[2], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--ZD1_mux_fw_1_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1_a at LC_X26_Y12_N5
--operation mode is normal
 
ED1_r32_o_20_qfbk = ED1_r32_o_20;
ZD1_mux_fw_1_a = MB1_r5_o_4 $ ED1_r32_o_20_qfbk # !XC1_wb_we_o_0;
 
--ED1_r32_o_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_20 at LC_X26_Y12_N5
--operation mode is normal
 
ED1_r32_o_20 = DFFEAS(ZD1_mux_fw_1_a, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[4], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--ZD1_un1_mux_fw_NE_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un1_mux_fw_NE_2 at LC_X26_Y13_N0
--operation mode is normal
 
ED1_r32_o_19_qfbk = ED1_r32_o_19;
ZD1_un1_mux_fw_NE_2 = ED1_r32_o_18 & MB1_r5_o_3 $ ED1_r32_o_19_qfbk # !MB1_r5_o_2 # !ED1_r32_o_18 & MB1_r5_o_2 # MB1_r5_o_3 $ ED1_r32_o_19_qfbk;
 
--ED1_r32_o_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_19 at LC_X26_Y13_N0
--operation mode is normal
 
ED1_r32_o_19 = DFFEAS(ZD1_un1_mux_fw_NE_2, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[3], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--ZD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|un1_mux_fw_NE_1 at LC_X26_Y9_N9
--operation mode is normal
 
ED1_r32_o_16_qfbk = ED1_r32_o_16;
ZD1_un1_mux_fw_NE_1 = MB1_r5_o_1 & MB1_r5_o_0 $ ED1_r32_o_16_qfbk # !ED1_r32_o_17 # !MB1_r5_o_1 & ED1_r32_o_17 # MB1_r5_o_0 $ ED1_r32_o_16_qfbk;
 
--ED1_r32_o_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_16 at LC_X26_Y9_N9
--operation mode is normal
 
ED1_r32_o_16 = DFFEAS(ZD1_un1_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[0], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--TD1_alu_out_9_a2_0_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_0_1_0 at LC_X13_Y15_N7
--operation mode is normal
 
TD1_alu_out_9_a2_0_1_0 = !RC1_alu_func_o_2 & !RC1_alu_func_o_3;
 
 
--VD1_b_o_iv_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_9 at LC_X16_Y5_N4
--operation mode is normal
 
VD1_b_o_iv_9 = !G1_BUS15471_i_m[9] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] & AB1_r32_o_7 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[9] at LC_X16_Y5_N4
--operation mode is normal
 
VD1_op2_reged[9] = DFFEAS(VD1_b_o_iv_9, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_87_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[7] at LC_X10_Y15_N1
--operation mode is normal
 
UD1_shift_out_87_d[7] = PD1_a_o_0 & UD1_shift_out_80[7] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[7];
 
 
--VD1_b_o_iv_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_6 at LC_X20_Y5_N5
--operation mode is normal
 
VD1_b_o_iv_6 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] & !G1_BUS15471_i_m[6] & AB1_r32_o_4 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[6] at LC_X20_Y5_N5
--operation mode is normal
 
VD1_op2_reged[6] = DFFEAS(VD1_b_o_iv_6, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_85_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[7] at LC_X12_Y14_N9
--operation mode is normal
 
UD1_shift_out_85_d[7] = PD1_a_o_2 & UD1_shift_out_43[31] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[7];
 
 
--UD1_shift_out_sn_m25_0_a5_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a5_1 at LC_X14_Y8_N2
--operation mode is normal
 
UD1_shift_out_sn_m25_0_a5_1 = !UD1_shift_out587 & !UD1_shift_out588 & !UD1_shift_out586;
 
 
--PD1_a_o_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[2] at LC_X20_Y10_N9
--operation mode is normal
 
PD1_a_o_a[2] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_2 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_2;
 
 
--PD1_a_o_3_Z[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[2] at LC_X20_Y10_N6
--operation mode is normal
 
SD1_r32_o_2_qfbk = SD1_r32_o_2;
PD1_a_o_3_Z[2] = PD1_a_o_3_s[0] & SD1_r32_o_2_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[2];
 
--SD1_r32_o_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_2 at LC_X20_Y10_N6
--operation mode is normal
 
SD1_r32_o_2 = DFFEAS(PD1_a_o_3_Z[2], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_2, , , VCC);
 
 
--RD1_a_o_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|a_o_a_1 at LC_X20_Y9_N9
--operation mode is normal
 
RD1_r32_o_1__Z_qfbk = RD1_r32_o_1__Z;
RD1_a_o_a_1 = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_1 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_1__Z_qfbk;
 
--RD1_r32_o_1__Z is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_1__Z at LC_X20_Y9_N9
--operation mode is normal
 
RD1_r32_o_1__Z = DFFEAS(RD1_a_o_a_1, GLOBAL(E1__clk0), VCC, , , KB1_r32_o_1, , , VCC);
 
 
--PD1_a_o_3_Z[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[1] at LC_X20_Y9_N3
--operation mode is normal
 
SD1_r32_o_1_qfbk = SD1_r32_o_1;
PD1_a_o_3_Z[1] = PD1_a_o_3_s[0] & SD1_r32_o_1_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[1];
 
--SD1_r32_o_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_1 at LC_X20_Y9_N3
--operation mode is normal
 
SD1_r32_o_1 = DFFEAS(PD1_a_o_3_Z[1], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_1, , , VCC);
 
 
--RD1_a_o_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|a_o_a_0 at LC_X20_Y14_N7
--operation mode is normal
 
RD1_r32_o_0__Z_qfbk = RD1_r32_o_0__Z;
RD1_a_o_a_0 = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_0 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0__Z_qfbk;
 
--RD1_r32_o_0__Z is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0__Z at LC_X20_Y14_N7
--operation mode is normal
 
RD1_r32_o_0__Z = DFFEAS(RD1_a_o_a_0, GLOBAL(E1__clk0), VCC, , , KB1_r32_o_0, , , VCC);
 
 
--PD1_a_o_3_Z[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[0] at LC_X20_Y14_N3
--operation mode is normal
 
SD1_r32_o_0_qfbk = SD1_r32_o_0;
PD1_a_o_3_Z[0] = PD1_a_o_3_s[0] & SD1_r32_o_0_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[0];
 
--SD1_r32_o_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_0 at LC_X20_Y14_N3
--operation mode is normal
 
SD1_r32_o_0 = DFFEAS(PD1_a_o_3_Z[0], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_0, , , VCC);
 
 
--UD1_shift_out_sn_b9_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_b9_0 at LC_X16_Y11_N7
--operation mode is normal
 
UD1_shift_out_sn_b9_0 = !PD1_a_o_4 # !UD1_shift_out588;
 
 
--UD1_shift_out_86_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[7] at LC_X15_Y17_N7
--operation mode is normal
 
UD1_shift_out_86_a[7] = PD1_a_o_2 & !UD1_shift_out_79[11] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[15] # !UD1_shift_out587 & !UD1_shift_out_79[11];
 
 
--UD1_shift_out_74[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[7] at LC_X15_Y17_N9
--operation mode is normal
 
UD1_shift_out_74[7] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[15] # !UD1_shift_out_74_a[7] & UD1_shift_out_79[19];
 
 
--UD1_shift_out_sn_m25_0_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a at LC_X20_Y13_N2
--operation mode is normal
 
UD1_shift_out_sn_m25_0_a = !UD1_shift_out_sn_m25_0_a5_1 & UD1_shift_out588 # PD1_a_o_3 # PD1_a_o_4;
 
 
--UD1_shift_out_sn_m17_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m17_0_a2 at LC_X20_Y13_N0
--operation mode is normal
 
UD1_shift_out_sn_m17_0_a2 = !PD1_a_o_2 & !PD1_a_o_4;
 
 
--UD1_shift_out_sn_m25_0_a5_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_a5_0 at LC_X20_Y13_N3
--operation mode is normal
 
UD1_shift_out_sn_m25_0_a5_0 = !UD1_shift_out586 & !UD1_shift_out588 & UD1_shift_out_sn_m25_0_o2 & PD1_a_o_4;
 
 
--UD1_shift_out_91_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[7] at LC_X15_Y17_N0
--operation mode is normal
 
UD1_shift_out_91_a[7] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_7 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[7];
 
 
--UD1_shift_out_76[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[7] at LC_X15_Y12_N5
--operation mode is normal
 
UD1_shift_out_76[7] = UD1_shift_out587 & UD1_shift_out_76_a[7] & UD1_shift_out_79[19] # !PD1_a_o_2;
 
 
--UD1_shift_out_sn_m17_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m17_0 at LC_X20_Y13_N1
--operation mode is normal
 
UD1_shift_out_sn_m17_0 = UD1_shift_out587 & UD1_shift_out_sn_m17_0_a2 # !UD1_shift_out587 & UD1_shift_out586 # UD1_shift_out588;
 
 
--VD1_hilo_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_7 at LC_X9_Y11_N3
--operation mode is normal
 
VD1_hilo_7_lut_out = VD1_hilo_37_iv_0[7] # VD1_hilo25 & VD1_hilo_8_Z[7] # !VD1_hilo_37_iv_a[7];
VD1_hilo_7 = DFFEAS(VD1_hilo_7_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_39 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_39 at LC_X7_Y7_N2
--operation mode is normal
 
VD1_hilo_39_lut_out = !VD1_hilo_37_iv_0_a[39] & !VD1_hilo_37_iv_0_5[39] & !VD1_hilo_37_iv_0_a2[39] & !VD1_hilo_37_iv_0_4[39];
VD1_hilo_39 = DFFEAS(VD1_hilo_39_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_7 at LC_X19_Y9_N8
--operation mode is normal
 
PD1_a_o_7 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[7] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[7];
 
 
--TD1_m4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m4 at LC_X9_Y11_N6
--operation mode is normal
 
TD1_m4 = !RC1_alu_func_o_1 & RC1_alu_func_o_0 & TD1_alu_out_sn_m14_0_0;
 
 
--TD1_m11_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m11_a at LC_X9_Y11_N4
--operation mode is normal
 
TD1_m11_a = VD1_b_o_iv_7 & !TD1_m9 & PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 # !TD1_m5;
 
 
--TD1_m7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m7 at LC_X5_Y14_N2
--operation mode is normal
 
TD1_m7 = TD1_alu_out_7_0_0_o3_0 & !TD1_m5 # !TD1_alu_out_7_0_0_o3_0 & !TD1_alu_out_sn_m14_0_0 # !RC1_alu_func_o_0;
 
 
--TD1_un1_a_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add7 at LC_X12_Y9_N2
--operation mode is arithmetic
 
TD1_un1_a_add7_carry_eqn = (!TD1_un1_a_carry_4 & TD1_un1_a_carry_6) # (TD1_un1_a_carry_4 & TD1L325);
TD1_un1_a_add7 = PD1_a_o_7 $ TD1_un1_b_1_combout[7] $ TD1_un1_a_add7_carry_eqn;
 
--TD1_un1_a_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_7 at LC_X12_Y9_N2
--operation mode is arithmetic
 
TD1_un1_a_carry_7_cout_0 = PD1_a_o_7 & !TD1_un1_b_1_combout[7] & !TD1_un1_a_carry_6 # !PD1_a_o_7 & !TD1_un1_a_carry_6 # !TD1_un1_b_1_combout[7];
TD1_un1_a_carry_7 = CARRY(TD1_un1_a_carry_7_cout_0);
 
--TD1L525 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_7~COUT1_1 at LC_X12_Y9_N2
--operation mode is arithmetic
 
TD1L525_cout_1 = PD1_a_o_7 & !TD1_un1_b_1_combout[7] & !TD1L325 # !PD1_a_o_7 & !TD1L325 # !TD1_un1_b_1_combout[7];
TD1L525 = CARRY(TD1L525_cout_1);
 
 
--LB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_4 at LC_X25_Y10_N0
--operation mode is normal
 
LB1_r5_o_4_lut_out = EC1_rd_sel_o_1 & ED1_r32_o_20 # EC1_rd_sel_o_0 # !EC1_rd_sel_o_1 & ED1_r32_o_15 & EC1_rd_sel_o_0;
LB1_r5_o_4 = DFFEAS(LB1_r5_o_4_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--LB1_r5_o_3 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_3 at LC_X25_Y10_N1
--operation mode is normal
 
LB1_r5_o_3_lut_out = EC1_rd_sel_o_1 & ED1_r32_o_19 # EC1_rd_sel_o_0 # !EC1_rd_sel_o_1 & ED1_r32_o_14 & EC1_rd_sel_o_0;
LB1_r5_o_3 = DFFEAS(LB1_r5_o_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--LB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_2 at LC_X25_Y10_N9
--operation mode is normal
 
LB1_r5_o_2_lut_out = EC1_rd_sel_o_1 & ED1_r32_o_18 # EC1_rd_sel_o_0 # !EC1_rd_sel_o_1 & ED1_r32_o_13 & EC1_rd_sel_o_0;
LB1_r5_o_2 = DFFEAS(LB1_r5_o_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--LB1_r5_o_1 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_1 at LC_X25_Y10_N6
--operation mode is normal
 
LB1_r5_o_1_lut_out = EC1_rd_sel_o_1 & ED1_r32_o_17 # EC1_rd_sel_o_0 # !EC1_rd_sel_o_1 & ED1_r32_o_12 & EC1_rd_sel_o_0;
LB1_r5_o_1 = DFFEAS(LB1_r5_o_1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--LB1_r5_o_0 is mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0|r5_o_0 at LC_X25_Y10_N7
--operation mode is normal
 
LB1_r5_o_0_lut_out = EC1_rd_sel_o_1 & ED1_r32_o_16 # EC1_rd_sel_o_0 # !EC1_rd_sel_o_1 & ED1_r32_o_11 & EC1_rd_sel_o_0;
LB1_r5_o_0 = DFFEAS(LB1_r5_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--JE1_q_a[4] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[4] at M4K_X17_Y17
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
JE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[4]_PORT_A_data_in_reg = DFFE(JE1_q_a[4]_PORT_A_data_in, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_4, TB1_dout_1_2);
JE1_q_a[4]_PORT_B_data_in_reg = DFFE(JE1_q_a[4]_PORT_B_data_in, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[4]_PORT_A_address_reg = DFFE(JE1_q_a[4]_PORT_A_address, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[4]_PORT_B_address_reg = DFFE(JE1_q_a[4]_PORT_B_address, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_A_write_enable = GND;
JE1_q_a[4]_PORT_A_write_enable_reg = DFFE(JE1_q_a[4]_PORT_A_write_enable, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_write_enable = WB3L2;
JE1_q_a[4]_PORT_B_write_enable_reg = DFFE(JE1_q_a[4]_PORT_B_write_enable, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[4]_PORT_A_data_out = MEMORY(JE1_q_a[4]_PORT_A_data_in_reg, JE1_q_a[4]_PORT_B_data_in_reg, JE1_q_a[4]_PORT_A_address_reg, JE1_q_a[4]_PORT_B_address_reg, JE1_q_a[4]_PORT_A_write_enable_reg, JE1_q_a[4]_PORT_B_write_enable_reg, , , JE1_q_a[4]_clock_0, , , , , );
JE1_q_a[4] = JE1_q_a[4]_PORT_A_data_out[0];
 
--JE1_q_b[4] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[4] at M4K_X17_Y17
JE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[4]_PORT_A_data_in_reg = DFFE(JE1_q_b[4]_PORT_A_data_in, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_4, TB1_dout_1_2);
JE1_q_b[4]_PORT_B_data_in_reg = DFFE(JE1_q_b[4]_PORT_B_data_in, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[4]_PORT_A_address_reg = DFFE(JE1_q_b[4]_PORT_A_address, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[4]_PORT_B_address_reg = DFFE(JE1_q_b[4]_PORT_B_address, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_A_write_enable = GND;
JE1_q_b[4]_PORT_A_write_enable_reg = DFFE(JE1_q_b[4]_PORT_A_write_enable, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_write_enable = WB3L2;
JE1_q_b[4]_PORT_B_write_enable_reg = DFFE(JE1_q_b[4]_PORT_B_write_enable, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[4]_PORT_B_data_out = MEMORY(JE1_q_b[4]_PORT_A_data_in_reg, JE1_q_b[4]_PORT_B_data_in_reg, JE1_q_b[4]_PORT_A_address_reg, JE1_q_b[4]_PORT_B_address_reg, JE1_q_b[4]_PORT_A_write_enable_reg, JE1_q_b[4]_PORT_B_write_enable_reg, , , JE1_q_b[4]_clock_0, , , , , );
JE1_q_b[4] = JE1_q_b[4]_PORT_B_data_out[0];
 
--JE1_q_a[2] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[2] at M4K_X17_Y17
JE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[4]_PORT_A_data_in_reg = DFFE(JE1_q_a[4]_PORT_A_data_in, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_4, TB1_dout_1_2);
JE1_q_a[4]_PORT_B_data_in_reg = DFFE(JE1_q_a[4]_PORT_B_data_in, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[4]_PORT_A_address_reg = DFFE(JE1_q_a[4]_PORT_A_address, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[4]_PORT_B_address_reg = DFFE(JE1_q_a[4]_PORT_B_address, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_A_write_enable = GND;
JE1_q_a[4]_PORT_A_write_enable_reg = DFFE(JE1_q_a[4]_PORT_A_write_enable, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_PORT_B_write_enable = WB3L2;
JE1_q_a[4]_PORT_B_write_enable_reg = DFFE(JE1_q_a[4]_PORT_B_write_enable, JE1_q_a[4]_clock_0, , , );
JE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[4]_PORT_A_data_out = MEMORY(JE1_q_a[4]_PORT_A_data_in_reg, JE1_q_a[4]_PORT_B_data_in_reg, JE1_q_a[4]_PORT_A_address_reg, JE1_q_a[4]_PORT_B_address_reg, JE1_q_a[4]_PORT_A_write_enable_reg, JE1_q_a[4]_PORT_B_write_enable_reg, , , JE1_q_a[4]_clock_0, , , , , );
JE1_q_a[2] = JE1_q_a[4]_PORT_A_data_out[1];
 
--JE1_q_b[2] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[2] at M4K_X17_Y17
JE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[4]_PORT_A_data_in_reg = DFFE(JE1_q_b[4]_PORT_A_data_in, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_4, TB1_dout_1_2);
JE1_q_b[4]_PORT_B_data_in_reg = DFFE(JE1_q_b[4]_PORT_B_data_in, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[4]_PORT_A_address_reg = DFFE(JE1_q_b[4]_PORT_A_address, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[4]_PORT_B_address_reg = DFFE(JE1_q_b[4]_PORT_B_address, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_A_write_enable = GND;
JE1_q_b[4]_PORT_A_write_enable_reg = DFFE(JE1_q_b[4]_PORT_A_write_enable, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_PORT_B_write_enable = WB3L2;
JE1_q_b[4]_PORT_B_write_enable_reg = DFFE(JE1_q_b[4]_PORT_B_write_enable, JE1_q_b[4]_clock_0, , , );
JE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[4]_PORT_B_data_out = MEMORY(JE1_q_b[4]_PORT_A_data_in_reg, JE1_q_b[4]_PORT_B_data_in_reg, JE1_q_b[4]_PORT_A_address_reg, JE1_q_b[4]_PORT_B_address_reg, JE1_q_b[4]_PORT_A_write_enable_reg, JE1_q_b[4]_PORT_B_write_enable_reg, , , JE1_q_b[4]_clock_0, , , , , );
JE1_q_b[2] = JE1_q_b[4]_PORT_B_data_out[1];
 
 
--AD1_id2ra_ins_clr_1_0_i_a2_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2 at LC_X27_Y14_N6
--operation mode is normal
 
AD1_id2ra_ins_clr_1_0_i_a2_0_a2 = !AD1_CurrState_Sreg0[7] & !AD1_CurrState_Sreg0_5 & AD1_CurrState_Sreg0_i[0] & !AD1_CurrState_Sreg0[2];
 
 
--C1_G_504 is mips_sys:isys|G_504 at LC_X29_Y17_N4
--operation mode is normal
 
C1_G_504 = !AD1_id2ra_ins_clr_1_0_i_a2_0_a2 # !AD1_CurrState_Sreg0_2;
 
 
--AD1_CurrState_Sreg0_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_5 at LC_X27_Y14_N4
--operation mode is normal
 
AD1_CurrState_Sreg0_5_lut_out = !sys_rst;
AD1_CurrState_Sreg0_5 = DFFEAS(AD1_CurrState_Sreg0_5_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AD1_CurrState_Sreg0_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2 at LC_X30_Y16_N7
--operation mode is normal
 
AD1_CurrState_Sreg0_2_lut_out = AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & WB35L1 & !WB45L1 & !WB55L1;
AD1_CurrState_Sreg0_2 = DFFEAS(AD1_CurrState_Sreg0_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--TD1_m107 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m107 at LC_X13_Y15_N4
--operation mode is normal
 
TD1_m107 = RC1_alu_func_o_4 & RC1_alu_func_o_1;
 
 
--VD1_hilo_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_4 at LC_X5_Y18_N4
--operation mode is normal
 
VD1_hilo_4_lut_out = VD1_hilo_37_iv_0_0[4] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_4 # !VD1_hilo_37_iv_0_a[4];
VD1_hilo_4 = DFFEAS(VD1_hilo_4_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_36 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_36 at LC_X6_Y8_N4
--operation mode is normal
 
VD1_hilo_36_lut_out = VD1_hilo_37_iv_0_a[36] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_4 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_36 = DFFEAS(VD1_hilo_36_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--QD1_b_o_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_0_sqmuxa at LC_X21_Y12_N2
--operation mode is normal
 
QD1_b_o_0_sqmuxa = !PC1_muxb_ctl_o_1 & XD1_mux_fw_1 & PC1_muxb_ctl_o_0;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] at LC_X16_Y6_N4
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[4] = QD1_b_o18 & !QB1_r32_o_4 & QD1_un1_b_o18_2 # !FB1_r32_o_0_4 # !QD1_b_o18 & !QB1_r32_o_4 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[4] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[4] at LC_X16_Y6_N0
--operation mode is normal
 
G1_BUS15471_i_m[4] = QD1_b_o_1_sqmuxa & !FD1_wb_o_4;
 
 
--VD1_op1_sign_reged_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i at LC_X8_Y13_N4
--operation mode is normal
 
VD1_op1_sign_reged_0_sqmuxa_i = VD1_rdy_0_sqmuxa # !sys_rst;
 
 
--TD1_alu_out_7_0_0_m4_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0_a[3] at LC_X8_Y14_N0
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0_a[3] = RC1_alu_func_o_4 & !RC1_alu_func_o_1 & RC1_alu_func_o_0;
 
 
--TD1_alu_out_0_a3[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a3[28] at LC_X7_Y15_N4
--operation mode is normal
 
TD1_alu_out_0_a3[28] = !RC1_alu_func_o_0 & RC1_alu_func_o_4;
 
 
--RD1_r32_o_0_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_4 at LC_X21_Y4_N4
--operation mode is arithmetic
 
RD1_r32_o_0_4_lut_out = KB1_r32_o_4 $ HB1_BUS2446_cout[2];
RD1_r32_o_0_4 = DFFEAS(RD1_r32_o_0_4_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[4] at LC_X21_Y4_N4
--operation mode is arithmetic
 
RD1_r32_o_cout[4] = CARRY(!HB1L4 # !KB1_r32_o_4 # !KB1_r32_o_5);
 
 
--FB1_res_7_0_0_4 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_4 at LC_X21_Y11_N3
--operation mode is normal
 
FB1_res_7_0_0_4 = CD1_res_7_0_0_0_2 # CD1_res_7_0_0_o3_0 & ED1_r32_o_2;
 
--FB1_r32_o_0_4 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_4 at LC_X21_Y11_N3
--operation mode is normal
 
FB1_r32_o_0_4 = DFFEAS(FB1_res_7_0_0_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[4] at LC_X16_Y11_N4
--operation mode is normal
 
PD1_a_o_3_d[4] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_4 # !PD1_un6_a_o & !PD1_a_o_3_d_a[4] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[4];
 
 
--PD1_a_o_3_s[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_s[0] at LC_X21_Y9_N4
--operation mode is normal
 
PD1_a_o_3_s[0] = !SC1_muxa_ctl_o_1 & !PD1_a_o_sn_m2;
 
 
--PD1_a_o_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[3] at LC_X16_Y13_N5
--operation mode is normal
 
PD1_a_o_a[3] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_3 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_3;
 
 
--PD1_a_o_3_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[3] at LC_X16_Y13_N9
--operation mode is normal
 
SD1_r32_o_3_qfbk = SD1_r32_o_3;
PD1_a_o_3_Z[3] = PD1_a_o_3_s[0] & SD1_r32_o_3_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[3];
 
--SD1_r32_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_3 at LC_X16_Y13_N9
--operation mode is normal
 
SD1_r32_o_3 = DFFEAS(PD1_a_o_3_Z[3], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_3, , , VCC);
 
 
--VD1_b_o_iv_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_3 at LC_X16_Y6_N7
--operation mode is normal
 
VD1_b_o_iv_3 = !G1_BUS15471_i_m[3] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] & AB1_r32_o_1 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[3] at LC_X16_Y6_N7
--operation mode is normal
 
VD1_op2_reged[3] = DFFEAS(VD1_b_o_iv_3, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_un1_b_1_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[2] at LC_X15_Y10_N7
--operation mode is normal
 
TD1_un1_b_1_combout[2] = TD1_sum13_0_a2 $ !VD1_b_o_iv_2;
 
 
--TD1_un1_a_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add1 at LC_X12_Y10_N6
--operation mode is arithmetic
 
TD1_un1_a_add1_carry_eqn = (!TD1_un1_a_add0_start_cout & TD1_un1_a_carry_0) # (TD1_un1_a_add0_start_cout & TD1L215);
TD1_un1_a_add1 = TD1_un1_b_1_combout[1] $ PD1_a_o_1 $ TD1_un1_a_add1_carry_eqn;
 
--TD1_un1_a_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_1 at LC_X12_Y10_N6
--operation mode is arithmetic
 
TD1_un1_a_carry_1_cout_0 = TD1_un1_b_1_combout[1] & !PD1_a_o_1 & !TD1_un1_a_carry_0 # !TD1_un1_b_1_combout[1] & !TD1_un1_a_carry_0 # !PD1_a_o_1;
TD1_un1_a_carry_1 = CARRY(TD1_un1_a_carry_1_cout_0);
 
--TD1L415 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_1~COUT1_1 at LC_X12_Y10_N6
--operation mode is arithmetic
 
TD1L415_cout_1 = TD1_un1_b_1_combout[1] & !PD1_a_o_1 & !TD1L215 # !TD1_un1_b_1_combout[1] & !TD1L215 # !PD1_a_o_1;
TD1L415 = CARRY(TD1L415_cout_1);
 
 
--UD1_shift_out_85_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[4] at LC_X16_Y16_N2
--operation mode is normal
 
UD1_shift_out_85_d[4] = PD1_a_o_0 & VD1_b_o_iv_1 & !PD1_a_o_2 # !PD1_a_o_0 & PD1_a_o_2 $ !UD1_shift_out_85_d_a[4];
 
 
--UD1_shift_out_87_d[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[4] at LC_X16_Y16_N8
--operation mode is normal
 
UD1_shift_out_87_d[4] = PD1_a_o_0 & UD1_shift_out_80[4] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[4];
 
 
--UD1_shift_out587 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out587 at LC_X13_Y15_N9
--operation mode is normal
 
RC1_alu_func_o_0_qfbk = RC1_alu_func_o_0;
UD1_shift_out587 = !RC1_alu_func_o_4 & !RC1_alu_func_o_1 & RC1_alu_func_o_0_qfbk & TD1_alu_out_9_a2_0_1_0;
 
--RC1_alu_func_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_0 at LC_X13_Y15_N9
--operation mode is normal
 
RC1_alu_func_o_0 = DFFEAS(UD1_shift_out587, GLOBAL(E1__clk0), VCC, , , ZC1_alu_func_o_0, , !AD1_NET1640_i, VCC);
 
 
--UD1_shift_out_88[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[4] at LC_X19_Y13_N6
--operation mode is normal
 
UD1_shift_out_88[4] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_4 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[4];
 
 
--UD1_shift_out_91_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[4] at LC_X21_Y17_N5
--operation mode is normal
 
UD1_shift_out_91_a[4] = PD1_a_o_2 & !PD1_a_o_3 & UD1_shift_out_79[16] # !PD1_a_o_2 & UD1_shift_out_79[20];
 
 
--UD1_shift_out_86_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[4] at LC_X21_Y17_N2
--operation mode is normal
 
UD1_shift_out_86_a[4] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[8] # !PD1_a_o_2 & !UD1_shift_out_47[0] # !UD1_shift_out587 & !UD1_shift_out_79[8];
 
 
--UD1_shift_out_74[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[4] at LC_X21_Y17_N7
--operation mode is normal
 
UD1_shift_out_74[4] = PD1_a_o_2 & UD1_shift_out_74_c[4] & VD1_b_o_iv_31 # !UD1_shift_out_74_c[4] & UD1_shift_out_79[16] # !PD1_a_o_2 & UD1_shift_out_74_c[4];
 
 
--VD1_hilo_37_iv_0_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[5] at LC_X5_Y17_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[5] = VD1_hilo_4 & !VD1_hilo_2_sqmuxa & !VD1_hilo_6 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_4 & !VD1_hilo_6 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_o5_0[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0[0] at LC_X6_Y13_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_o5_0[0] = VD1_hilo_37_iv_0_a3_1[62] # VD1_addnop2109_0_a2;
 
 
--VD1_hilo_37_iv_0_0[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[5] at LC_X5_Y17_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_0[5] = VD1_hilo_5 & VD1_hilo_37_iv_0_o5[0] # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[5] # !VD1_hilo_5 & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[5];
 
 
--C1_G_505 is mips_sys:isys|G_505 at LC_X3_Y14_N5
--operation mode is normal
 
C1_G_505 = !C1_G_505_a & VD1_un17_mul_0 # !VD1_addnop2109_0_a2 # !sys_rst;
 
 
--VD1_hilo_37_iv_0_a2_7[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[37] at LC_X6_Y8_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_7[37] = VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add6 & VD1_hilo_37_iv_0_a2_7_2_1[37] & !VD1_sub_or_yn;
 
 
--VD1_hilo_37_iv_0_5[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[37] at LC_X6_Y5_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_5[37] = VD1_hilo_37_iv_0_5_a[37] # VD1_hilo_37_iv_0_1[37] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add6;
 
 
--VD1_hilo_37_iv_0_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[37] at LC_X6_Y5_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a[37] = VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_5 # !VD1_hilo_38 # !VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_5;
 
 
--VD1_hilo_37_iv_0_a3[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3[57] at LC_X6_Y7_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_a3[57] = VD1_addnop2109_0_a2 & VD1_hilo_37_iv_0_o3[34] # !RC1_alu_func_o_0;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] at LC_X16_Y4_N7
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[5] = QD1_b_o18 & !QB1_r32_o_5 & QD1_un1_b_o18_2 # !FB1_r32_o_0_5 # !QD1_b_o18 & !QB1_r32_o_5 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[5] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[5] at LC_X16_Y4_N0
--operation mode is normal
 
G1_BUS15471_i_m[5] = !FD1_wb_o_5 & QD1_b_o_1_sqmuxa;
 
 
--RD1_r32_o_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_5 at LC_X23_Y4_N4
--operation mode is arithmetic
 
RD1_r32_o_5_lut_out = KB1_r32_o_5 $ (KB1_r32_o_4 & RD1_r32_o_cout[3]);
RD1_r32_o_5 = DFFEAS(RD1_r32_o_5_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[5] at LC_X23_Y4_N4
--operation mode is arithmetic
 
RD1_r32_o_cout[5] = CARRY(!RD1L76 # !KB1_r32_o_4 # !KB1_r32_o_5);
 
 
--FB1_res_7_0_0_5 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_5 at LC_X22_Y11_N8
--operation mode is normal
 
FB1_res_7_0_0_5 = ED1_r32_o_3 & CD1_res_7_0_0_o3_0 # CD1_res_7_0_0_a2_0 & ED1_r32_o_5 # !ED1_r32_o_3 & CD1_res_7_0_0_a2_0 & ED1_r32_o_5;
 
--FB1_r32_o_0_5 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_5 at LC_X22_Y11_N8
--operation mode is normal
 
FB1_r32_o_0_5 = DFFEAS(FB1_res_7_0_0_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[5] at LC_X20_Y11_N3
--operation mode is normal
 
PD1_a_o_3_d[5] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_5 # !PD1_un6_a_o & !PD1_a_o_3_d_a[5] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[5];
 
 
--VD1_b_o_iv_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_7 at LC_X15_Y4_N3
--operation mode is normal
 
VD1_b_o_iv_7 = !G1_BUS15471_i_m[7] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] & AB1_r32_o_5 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[7] at LC_X15_Y4_N3
--operation mode is normal
 
VD1_op2_reged[7] = DFFEAS(VD1_b_o_iv_7, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_87_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[5] at LC_X15_Y19_N8
--operation mode is normal
 
UD1_shift_out_87_d[5] = PD1_a_o_0 & UD1_shift_out_80[5] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[5];
 
 
--UD1_shift_out_85_d[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[5] at LC_X15_Y19_N2
--operation mode is normal
 
UD1_shift_out_85_d[5] = PD1_a_o_2 & !PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_2 & UD1_shift_out_68[5];
 
 
--UD1_shift_out_88[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[5] at LC_X12_Y11_N0
--operation mode is normal
 
UD1_shift_out_88[5] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_5 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[5];
 
 
--UD1_shift_out_91_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[5] at LC_X15_Y14_N1
--operation mode is normal
 
UD1_shift_out_91_a[5] = PD1_a_o_2 & !PD1_a_o_3 & UD1_shift_out_79[17] # !PD1_a_o_2 & UD1_shift_out_42[1];
 
 
--UD1_shift_out_86_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[5] at LC_X14_Y14_N1
--operation mode is normal
 
UD1_shift_out_86_a[5] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[9] # !PD1_a_o_2 & !UD1_shift_out_79[13] # !UD1_shift_out587 & !UD1_shift_out_79[9];
 
 
--UD1_shift_out_74[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[5] at LC_X15_Y14_N8
--operation mode is normal
 
UD1_shift_out_74[5] = PD1_a_o_3 & !UD1_shift_out_74_a[5] # !PD1_a_o_3 & UD1_shift_out_61[5];
 
 
--VD1_b_o_iv_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_0 at LC_X20_Y16_N2
--operation mode is normal
 
VD1_b_o_iv_0 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] & !G1_BUS15471_i_m[0] & RB1_byte_addr_o_0 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[0] at LC_X20_Y16_N2
--operation mode is normal
 
VD1_op2_reged[0] = DFFEAS(VD1_b_o_iv_0, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_1 at LC_X15_Y9_N1
--operation mode is normal
 
VD1_b_o_iv_1 = !QD1_b_o_iv_1_0 & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] & FB1_r32_o_0_1 # !QD1_b_o18;
 
--VD1_op2_reged[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[1] at LC_X15_Y9_N1
--operation mode is normal
 
VD1_op2_reged[1] = DFFEAS(VD1_b_o_iv_1, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_80[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[2] at LC_X12_Y16_N4
--operation mode is normal
 
UD1_shift_out_80[2] = PD1_a_o_2 & UD1_shift_out_80_a[2] & VD1_b_o_iv_7 # !UD1_shift_out_80_a[2] & VD1_b_o_iv_9 # !PD1_a_o_2 & !UD1_shift_out_80_a[2];
 
 
--UD1_shift_out_82[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[2] at LC_X11_Y19_N0
--operation mode is normal
 
UD1_shift_out_82[2] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_8 # !PD1_a_o_1 & !UD1_shift_out_82_a[2] # !PD1_a_o_2 & !UD1_shift_out_82_a[2];
 
 
--UD1_shift_out_86_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[2] at LC_X19_Y17_N9
--operation mode is normal
 
UD1_shift_out_86_a[2] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[6] # !PD1_a_o_2 & !UD1_shift_out_79[10] # !UD1_shift_out587 & !UD1_shift_out_79[6];
 
 
--UD1_shift_out_74[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[2] at LC_X19_Y16_N8
--operation mode is normal
 
UD1_shift_out_74[2] = PD1_a_o_3 & UD1_shift_out_74_a[2] & UD1_shift_out_79[18] # !UD1_shift_out_74_a[2] & UD1_shift_out_41[2] # !PD1_a_o_3 & !UD1_shift_out_74_a[2];
 
 
--UD1_shift_out_91_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[2] at LC_X20_Y18_N4
--operation mode is normal
 
UD1_shift_out_91_a[2] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_2 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[2];
 
 
--UD1_shift_out_76[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[2] at LC_X19_Y17_N5
--operation mode is normal
 
UD1_shift_out_76[2] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_76_a[2] # !PD1_a_o_2 & UD1_shift_out_79[18];
 
 
--VD1_hilo_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2 at LC_X5_Y17_N4
--operation mode is normal
 
VD1_hilo_2_lut_out = VD1_hilo_37_iv_0_0[2] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_2 # !VD1_hilo_37_iv_0_a[2];
VD1_hilo_2 = DFFEAS(VD1_hilo_2_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_34 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_34 at LC_X6_Y7_N5
--operation mode is normal
 
VD1_hilo_34_lut_out = VD1_hilo_37_iv_0_a[34] & !VD1_hilo_37_iv_0_o3_0[34] & PD1_a_o_2 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_34 = DFFEAS(VD1_hilo_34_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_b_o_iv_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_2 at LC_X15_Y10_N8
--operation mode is normal
 
VD1_b_o_iv_2 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] & !G1_BUS15471_i_m[2] & AB1_r32_o_0 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[2] at LC_X15_Y10_N8
--operation mode is normal
 
VD1_op2_reged[2] = DFFEAS(VD1_b_o_iv_2, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_m9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m9 at LC_X11_Y11_N7
--operation mode is normal
 
TD1_m9 = TD1_alu_out_sn_m14_0_0 & RC1_alu_func_o_1;
 
 
--TD1_m112_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m112_a at LC_X11_Y9_N0
--operation mode is normal
 
TD1_m112_a = PD1_a_o_2 & !TD1_m5 & !VD1_b_o_iv_2 # !PD1_a_o_2 & VD1_b_o_iv_2 # !TD1_m4;
 
 
--MD1_c_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[3] at LC_X7_Y14_N7
--operation mode is normal
 
MD1_c_0_a[3] = VD1_un24_res & !VD1_hilo_35 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_3;
 
 
--TD1_alu_out_7_0_0_m4_0[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[3] at LC_X8_Y14_N6
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0[3] = VD1_b_o_iv_3 & TD1_alu_out_0_a3[28] & TD1_alu_out_7_0_0_o3_0 # !VD1_b_o_iv_3 & TD1_alu_out_7_0_0_m4_0_a[3];
 
 
--TD1_alu_out_7_0_0_m2_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m2_a[3] at LC_X10_Y13_N3
--operation mode is normal
 
TD1_alu_out_7_0_0_m2_a[3] = VD1_b_o_iv_3 & !TD1_m107 # !VD1_b_o_iv_3 & !TD1_alu_out_0_a3[28];
 
 
--UD1_shift_out_82[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[3] at LC_X12_Y15_N7
--operation mode is normal
 
UD1_shift_out_82[3] = PD1_a_o_1 & PD1_a_o_2 & VD1_b_o_iv_9 # !PD1_a_o_2 & !UD1_shift_out_82_a[3] # !PD1_a_o_1 & !UD1_shift_out_82_a[3];
 
 
--UD1_shift_out_89_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[3] at LC_X13_Y19_N5
--operation mode is normal
 
UD1_shift_out_89_a[3] = UD1_shift_out586 & !PD1_a_o_2 & UD1_shift_out_81[3] # !UD1_shift_out586 & !UD1_shift_out_80[3];
 
 
--UD1_shift_out_91[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[3] at LC_X15_Y15_N6
--operation mode is normal
 
UD1_shift_out_91[3] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[3] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[3];
 
 
--UD1_shift_out_86[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[3] at LC_X15_Y15_N2
--operation mode is normal
 
UD1_shift_out_86[3] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[3] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[3];
 
 
--UD1_shift_out_89_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_15 at LC_X9_Y18_N0
--operation mode is normal
 
UD1_shift_out_89_15 = UD1_shift_out586 & !UD1_shift_out_89_a[16] # !UD1_shift_out586 & UD1_shift_out_87[16];
 
 
--MD1_c_a_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_16 at LC_X13_Y12_N6
--operation mode is normal
 
MD1_c_a_16 = UD1_shift_out586 & !UD1_shift_out_92_d_8 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_8 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_16;
 
 
--MD1_c_0_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_15 at LC_X11_Y9_N6
--operation mode is normal
 
MD1_c_0_15 = RC1_alu_func_o_4 & !TD1_m36 # !RC1_alu_func_o_4 & TD1_m33 # !MD1_c_0_a[16];
 
 
--UD1_shift_out_89_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_16 at LC_X14_Y16_N0
--operation mode is normal
 
UD1_shift_out_89_16 = UD1_shift_out586 & !UD1_shift_out_89_a[17] # !UD1_shift_out586 & UD1_shift_out_87[17];
 
 
--UD1_shift_out_92_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_11 at LC_X14_Y16_N9
--operation mode is normal
 
UD1_shift_out_92_11 = UD1_shift_out586 & UD1_shift_out_92_d[17] # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[17] # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_a[17];
 
 
--MD1_c_0_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_16 at LC_X9_Y12_N3
--operation mode is normal
 
MD1_c_0_16 = RC1_alu_func_o_4 & !TD1_m41 # !RC1_alu_func_o_4 & TD1_m38 # !MD1_c_0_a[17];
 
 
--UD1_shift_out_89_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_13 at LC_X13_Y12_N8
--operation mode is normal
 
UD1_shift_out_89_13 = UD1_shift_out586 & !UD1_shift_out_89_a[14] # !UD1_shift_out586 & UD1_shift_out_87[14];
 
 
--MD1_c_a_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_14 at LC_X12_Y17_N2
--operation mode is normal
 
MD1_c_a_14 = UD1_shift_out586 & !UD1_shift_out_92_d_6 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_6 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_14;
 
 
--MD1_c_0_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_13 at LC_X8_Y12_N5
--operation mode is normal
 
MD1_c_0_13 = RC1_alu_func_o_4 & !TD1_m26 # !RC1_alu_func_o_4 & TD1_m23 # !MD1_c_0_a[14];
 
 
--UD1_shift_out_89_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_14 at LC_X11_Y12_N5
--operation mode is normal
 
UD1_shift_out_89_14 = UD1_shift_out586 & !UD1_shift_out_89_a[15] # !UD1_shift_out586 & UD1_shift_out_87[15];
 
 
--MD1_c_a_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_15 at LC_X14_Y17_N8
--operation mode is normal
 
MD1_c_a_15 = UD1_shift_out586 & !UD1_shift_out_92_d_7 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_7 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_15;
 
 
--MD1_c_0_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_14 at LC_X11_Y12_N8
--operation mode is normal
 
MD1_c_0_14 = RC1_alu_func_o_4 & !TD1_m31 # !RC1_alu_func_o_4 & TD1_m28 # !MD1_c_0_a[15];
 
 
--MD1_c_a_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_31 at LC_X11_Y10_N2
--operation mode is normal
 
MD1_c_a_31 = UD1_shift_out586 & !UD1_shift_out_85_27 # !UD1_shift_out586 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_92_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_25 at LC_X11_Y10_N5
--operation mode is normal
 
UD1_shift_out_92_25 = UD1_shift_out586 & UD1_shift_out_92_d[31] # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[31] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_83[31];
 
 
--MD1_c_0_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_30 at LC_X11_Y10_N9
--operation mode is normal
 
MD1_c_0_30 = RC1_alu_func_o_4 & !TD1_m101 # !RC1_alu_func_o_4 & TD1_m98 # !MD1_c_0_a[31];
 
 
--AB1_c_6 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_6 at LC_X16_Y15_N4
--operation mode is normal
 
AB1_c_6 = MD1_c_0_7 # UD1_shift_out_sn_m31_i & !MD1_c_a_8 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_7;
 
--AB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_6 at LC_X16_Y15_N4
--operation mode is normal
 
AB1_r32_o_6 = DFFEAS(AB1_c_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_7 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_7 at LC_X13_Y13_N6
--operation mode is normal
 
AB1_c_7 = MD1_c_0_8 # UD1_shift_out_sn_m31_i & !MD1_c_a_9 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_8;
 
--AB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_7 at LC_X13_Y13_N6
--operation mode is normal
 
AB1_r32_o_7 = DFFEAS(AB1_c_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_8 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_8 at LC_X19_Y16_N1
--operation mode is normal
 
AB1_c_8 = UD1_shift_out_10 # MD1_c_1_10 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add10;
 
--AB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_8 at LC_X19_Y16_N1
--operation mode is normal
 
AB1_r32_o_8 = DFFEAS(AB1_c_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_c_9 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_9 at LC_X15_Y16_N5
--operation mode is normal
 
AB1_c_9 = MD1_c_0_10 # UD1_shift_out_sn_m31_i & !MD1_c_a_11 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_10;
 
--AB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_9 at LC_X15_Y16_N5
--operation mode is normal
 
AB1_r32_o_9 = DFFEAS(AB1_c_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UD1_shift_out_89_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_20 at LC_X14_Y10_N9
--operation mode is normal
 
UD1_shift_out_89_20 = UD1_shift_out586 & !UD1_shift_out_89_a[21] # !UD1_shift_out586 & UD1_shift_out_87[21];
 
 
--MD1_c_a_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_21 at LC_X14_Y10_N7
--operation mode is normal
 
MD1_c_a_21 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_13;
 
 
--MD1_c_0_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_20 at LC_X9_Y8_N8
--operation mode is normal
 
MD1_c_0_20 = RC1_alu_func_o_4 & !TD1_m132 # !RC1_alu_func_o_4 & TD1_m129 # !MD1_c_0_a[21];
 
 
--UD1_shift_out_89_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_19 at LC_X10_Y14_N1
--operation mode is normal
 
UD1_shift_out_89_19 = UD1_shift_out586 & !UD1_shift_out_89_a[20] # !UD1_shift_out586 & UD1_shift_out_87[20];
 
 
--MD1_c_1_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_20 at LC_X10_Y14_N2
--operation mode is normal
 
MD1_c_1_20 = RC1_alu_func_o_4 & !TD1_m56 # !RC1_alu_func_o_4 & TD1_m53 # !MD1_c_1_a[20];
 
 
--MD1_c_a_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_20 at LC_X10_Y14_N8
--operation mode is normal
 
MD1_c_a_20 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_12;
 
 
--AB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_17 at LC_X14_Y8_N9
--operation mode is normal
 
AB1_r32_o_17_lut_out = MD1_c_0_18 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_13 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_18;
AB1_r32_o_17 = DFFEAS(AB1_r32_o_17_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_16 at LC_X10_Y16_N2
--operation mode is normal
 
AB1_r32_o_16_lut_out = MD1_c_0_17 # UD1_shift_out_sn_m31_i & UD1_shift_out_92_12 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_17;
AB1_r32_o_16 = DFFEAS(AB1_r32_o_16_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_24 at LC_X11_Y15_N7
--operation mode is normal
 
AB1_r32_o_24_lut_out = MD1_c_0_25 # UD1_shift_out_sn_m31_i & MD1_c_a_26 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_25;
AB1_r32_o_24 = DFFEAS(AB1_r32_o_24_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_25 at LC_X11_Y7_N0
--operation mode is normal
 
AB1_r32_o_25_lut_out = MD1_c_0_26 # UD1_shift_out_sn_m31_i & MD1_c_a_27 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_26;
AB1_r32_o_25 = DFFEAS(AB1_r32_o_25_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_26 at LC_X9_Y15_N4
--operation mode is normal
 
AB1_r32_o_26_lut_out = MD1_c_4_0 # UD1_shift_out_sn_m31_i & MD1_c_a_28 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_27;
AB1_r32_o_26 = DFFEAS(AB1_r32_o_26_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_27 at LC_X12_Y13_N9
--operation mode is normal
 
AB1_r32_o_27_lut_out = MD1_c_0_28 # UD1_shift_out_sn_m31_i & MD1_c_a_29 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_28;
AB1_r32_o_27 = DFFEAS(AB1_r32_o_27_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UD1_shift_out_89_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_12 at LC_X14_Y11_N5
--operation mode is normal
 
UD1_shift_out_89_12 = UD1_shift_out586 & !UD1_shift_out_89_a[13] # !UD1_shift_out586 & UD1_shift_out_87[13];
 
 
--MD1_c_a_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_13 at LC_X14_Y11_N4
--operation mode is normal
 
MD1_c_a_13 = UD1_shift_out586 & !UD1_shift_out_92_d_5 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_5 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_13;
 
 
--MD1_c_0_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_12 at LC_X11_Y11_N6
--operation mode is normal
 
MD1_c_0_12 = RC1_alu_func_o_4 & !TD1_m127 # !RC1_alu_func_o_4 & TD1_m124 # !MD1_c_0_a[13];
 
 
--VD1_hilo_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_30 at LC_X3_Y13_N4
--operation mode is normal
 
VD1_hilo_30_lut_out = VD1_hilo_37_iv_0_0[30] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_30 # !VD1_hilo_37_iv_0_a[30];
VD1_hilo_30 = DFFEAS(VD1_hilo_30_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--MD1_c_a_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_30 at LC_X11_Y13_N9
--operation mode is normal
 
MD1_c_a_30 = !UD1_shift_out_30 & !VD1_un24_res # !VD1_hilo_62;
 
 
--TD1_m97 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m97 at LC_X11_Y13_N2
--operation mode is normal
 
TD1_m97 = RC1_alu_func_o_4 & TD1_m96 # !RC1_alu_func_o_4 & !TD1_alu_out_sn_m14_0_0 # !TD1_un1_a_add30;
 
 
--AB1_c_10 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_10 at LC_X16_Y14_N4
--operation mode is normal
 
AB1_c_10 = MD1_c_0_11 # UD1_shift_out_sn_m31_i & !MD1_c_a_12 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_11;
 
--AB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_10 at LC_X16_Y14_N4
--operation mode is normal
 
AB1_r32_o_10 = DFFEAS(AB1_c_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_22 at LC_X9_Y13_N4
--operation mode is normal
 
AB1_r32_o_22_lut_out = MD1_c_0_23 # UD1_shift_out_sn_m31_i & MD1_c_a_24 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_23;
AB1_r32_o_22 = DFFEAS(AB1_r32_o_22_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_23 at LC_X13_Y10_N7
--operation mode is normal
 
AB1_r32_o_23_lut_out = MD1_c_0_24 # UD1_shift_out_sn_m31_i & MD1_c_a_25 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_24;
AB1_r32_o_23 = DFFEAS(AB1_r32_o_23_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_20 at LC_X12_Y13_N0
--operation mode is normal
 
AB1_r32_o_20_lut_out = MD1_c_0_21 # UD1_shift_out_sn_m31_i & MD1_c_a_22 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_21;
AB1_r32_o_20 = DFFEAS(AB1_r32_o_20_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_21 at LC_X14_Y7_N9
--operation mode is normal
 
AB1_r32_o_21_lut_out = MD1_c_0_22 # UD1_shift_out_sn_m31_i & MD1_c_a_23 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_22;
AB1_r32_o_21 = DFFEAS(AB1_r32_o_21_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_rx_sr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[6] at LC_X33_Y4_N4
--operation mode is normal
 
M1_rx_sr[6]_lut_out = M1_rx_sr[7];
M1_rx_sr[6] = DFFEAS(M1_rx_sr[6]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--JE1_q_a[6] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[6] at M4K_X17_Y4
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
JE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[6]_PORT_A_data_in_reg = DFFE(JE1_q_a[6]_PORT_A_data_in, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_6, TB1_dout_1_5);
JE1_q_a[6]_PORT_B_data_in_reg = DFFE(JE1_q_a[6]_PORT_B_data_in, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[6]_PORT_A_address_reg = DFFE(JE1_q_a[6]_PORT_A_address, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[6]_PORT_B_address_reg = DFFE(JE1_q_a[6]_PORT_B_address, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_A_write_enable = GND;
JE1_q_a[6]_PORT_A_write_enable_reg = DFFE(JE1_q_a[6]_PORT_A_write_enable, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_write_enable = WB3L2;
JE1_q_a[6]_PORT_B_write_enable_reg = DFFE(JE1_q_a[6]_PORT_B_write_enable, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[6]_PORT_A_data_out = MEMORY(JE1_q_a[6]_PORT_A_data_in_reg, JE1_q_a[6]_PORT_B_data_in_reg, JE1_q_a[6]_PORT_A_address_reg, JE1_q_a[6]_PORT_B_address_reg, JE1_q_a[6]_PORT_A_write_enable_reg, JE1_q_a[6]_PORT_B_write_enable_reg, , , JE1_q_a[6]_clock_0, , , , , );
JE1_q_a[6] = JE1_q_a[6]_PORT_A_data_out[0];
 
--JE1_q_b[6] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[6] at M4K_X17_Y4
JE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[6]_PORT_A_data_in_reg = DFFE(JE1_q_b[6]_PORT_A_data_in, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_6, TB1_dout_1_5);
JE1_q_b[6]_PORT_B_data_in_reg = DFFE(JE1_q_b[6]_PORT_B_data_in, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[6]_PORT_A_address_reg = DFFE(JE1_q_b[6]_PORT_A_address, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[6]_PORT_B_address_reg = DFFE(JE1_q_b[6]_PORT_B_address, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_A_write_enable = GND;
JE1_q_b[6]_PORT_A_write_enable_reg = DFFE(JE1_q_b[6]_PORT_A_write_enable, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_write_enable = WB3L2;
JE1_q_b[6]_PORT_B_write_enable_reg = DFFE(JE1_q_b[6]_PORT_B_write_enable, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[6]_PORT_B_data_out = MEMORY(JE1_q_b[6]_PORT_A_data_in_reg, JE1_q_b[6]_PORT_B_data_in_reg, JE1_q_b[6]_PORT_A_address_reg, JE1_q_b[6]_PORT_B_address_reg, JE1_q_b[6]_PORT_A_write_enable_reg, JE1_q_b[6]_PORT_B_write_enable_reg, , , JE1_q_b[6]_clock_0, , , , , );
JE1_q_b[6] = JE1_q_b[6]_PORT_B_data_out[0];
 
--JE1_q_a[5] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[5] at M4K_X17_Y4
JE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[6]_PORT_A_data_in_reg = DFFE(JE1_q_a[6]_PORT_A_data_in, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_6, TB1_dout_1_5);
JE1_q_a[6]_PORT_B_data_in_reg = DFFE(JE1_q_a[6]_PORT_B_data_in, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[6]_PORT_A_address_reg = DFFE(JE1_q_a[6]_PORT_A_address, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[6]_PORT_B_address_reg = DFFE(JE1_q_a[6]_PORT_B_address, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_A_write_enable = GND;
JE1_q_a[6]_PORT_A_write_enable_reg = DFFE(JE1_q_a[6]_PORT_A_write_enable, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_PORT_B_write_enable = WB3L2;
JE1_q_a[6]_PORT_B_write_enable_reg = DFFE(JE1_q_a[6]_PORT_B_write_enable, JE1_q_a[6]_clock_0, , , );
JE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[6]_PORT_A_data_out = MEMORY(JE1_q_a[6]_PORT_A_data_in_reg, JE1_q_a[6]_PORT_B_data_in_reg, JE1_q_a[6]_PORT_A_address_reg, JE1_q_a[6]_PORT_B_address_reg, JE1_q_a[6]_PORT_A_write_enable_reg, JE1_q_a[6]_PORT_B_write_enable_reg, , , JE1_q_a[6]_clock_0, , , , , );
JE1_q_a[5] = JE1_q_a[6]_PORT_A_data_out[1];
 
--JE1_q_b[5] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[5] at M4K_X17_Y4
JE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[6]_PORT_A_data_in_reg = DFFE(JE1_q_b[6]_PORT_A_data_in, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_6, TB1_dout_1_5);
JE1_q_b[6]_PORT_B_data_in_reg = DFFE(JE1_q_b[6]_PORT_B_data_in, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[6]_PORT_A_address_reg = DFFE(JE1_q_b[6]_PORT_A_address, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[6]_PORT_B_address_reg = DFFE(JE1_q_b[6]_PORT_B_address, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_A_write_enable = GND;
JE1_q_b[6]_PORT_A_write_enable_reg = DFFE(JE1_q_b[6]_PORT_A_write_enable, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_PORT_B_write_enable = WB3L2;
JE1_q_b[6]_PORT_B_write_enable_reg = DFFE(JE1_q_b[6]_PORT_B_write_enable, JE1_q_b[6]_clock_0, , , );
JE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[6]_PORT_B_data_out = MEMORY(JE1_q_b[6]_PORT_A_data_in_reg, JE1_q_b[6]_PORT_B_data_in_reg, JE1_q_b[6]_PORT_A_address_reg, JE1_q_b[6]_PORT_B_address_reg, JE1_q_b[6]_PORT_A_write_enable_reg, JE1_q_b[6]_PORT_B_write_enable_reg, , , JE1_q_b[6]_clock_0, , , , , );
JE1_q_b[5] = JE1_q_b[6]_PORT_B_data_out[1];
 
 
--UB1_dout_2_i_o2[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2[3] at LC_X29_Y8_N2
--operation mode is normal
 
UB1_dout_2_i_o2[3] = UB1_dout_2_i_i_o2_0[7] # !RB1_ctl_o_2 & !RB1_ctl_o_1 & !RB1_byte_addr_o_1;
 
 
--UB1_dout_2_i_0_a2_x[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[6] at LC_X31_Y14_N7
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[6] = !GE1_q_b[6] & UB1_dout_2_i_o2_0[3];
 
 
--UB1_dout_2_i_0_a[6] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[6] at LC_X31_Y14_N6
--operation mode is normal
 
UB1_dout_2_i_0_a[6] = UB1_dout_2_i_a3_0[3] & UB1_dout_2_i_a3_1[3] & !HE1_q_b[6] # !KE1_q_b[6] # !UB1_dout_2_i_a3_0[3] & UB1_dout_2_i_a3_1[3] & !HE1_q_b[6];
 
 
--VD1_b_o_iv_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_8 at LC_X20_Y5_N9
--operation mode is normal
 
VD1_b_o_iv_8 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] & !G1_BUS15471_i_m[8] & AB1_r32_o_6 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[8] at LC_X20_Y5_N9
--operation mode is normal
 
VD1_op2_reged[8] = DFFEAS(VD1_b_o_iv_8, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_87_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[6] at LC_X12_Y15_N3
--operation mode is normal
 
UD1_shift_out_87_d[6] = PD1_a_o_0 & UD1_shift_out_80[6] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[6];
 
 
--UD1_shift_out_85_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[6] at LC_X14_Y19_N0
--operation mode is normal
 
UD1_shift_out_85_d[6] = PD1_a_o_2 & UD1_shift_out_43[30] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[6];
 
 
--MD1_c_1_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[6] at LC_X6_Y15_N8
--operation mode is normal
 
MD1_c_1_a[6] = VD1_un24_res & !VD1_hilo_38 # !VD1_un24_res & !VD1_hilo_6 # !VD1_un11_res;
 
 
--TD1_alu_out_0_a2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_0 at LC_X6_Y15_N3
--operation mode is normal
 
TD1_alu_out_0_a2_0 = TD1_alu_out_sn_m14_0_0 & PD1_a_o_6 & !TD1_alu_out_0_a2_a[6] # !PD1_a_o_6 & TD1_alu_out_7_0_0_m4_0[6];
 
 
--PD1_a_o_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_6 at LC_X19_Y11_N6
--operation mode is normal
 
PD1_a_o_6 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[6] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[6];
 
 
--TD1_un1_b_1_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[6] at LC_X14_Y5_N4
--operation mode is normal
 
TD1_un1_b_1_combout[6] = VD1_b_o_iv_6 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_91_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[6] at LC_X20_Y18_N0
--operation mode is normal
 
UD1_shift_out_91_a[6] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_6 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[6];
 
 
--UD1_shift_out_76[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[6] at LC_X19_Y17_N2
--operation mode is normal
 
UD1_shift_out_76[6] = UD1_shift_out_76_a[6] & UD1_shift_out587 & UD1_shift_out_79[18] # !PD1_a_o_2;
 
 
--UD1_shift_out_86_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[6] at LC_X19_Y15_N2
--operation mode is normal
 
UD1_shift_out_86_a[6] = PD1_a_o_2 & !UD1_shift_out_79[10] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_47[2] # !UD1_shift_out587 & !UD1_shift_out_79[10];
 
 
--UD1_shift_out_74[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[6] at LC_X19_Y15_N8
--operation mode is normal
 
UD1_shift_out_74[6] = PD1_a_o_3 & !UD1_shift_out_74_a[6] # !PD1_a_o_3 & UD1_shift_out_61[6];
 
 
--M1_rx_sr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[5] at LC_X33_Y5_N2
--operation mode is normal
 
M1_rx_sr[5]_lut_out = M1_rx_sr[6];
M1_rx_sr[5] = DFFEAS(M1_rx_sr[5]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--UB1_dout_2_i_0_a2_x[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[5] at LC_X31_Y14_N1
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[5] = UB1_dout_2_i_o2_0[3] & !GE1_q_b[5];
 
 
--UB1_dout_2_i_0_a[5] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[5] at LC_X31_Y14_N0
--operation mode is normal
 
UB1_dout_2_i_0_a[5] = UB1_dout_2_i_a3_0[3] & UB1_dout_2_i_a3_1[3] & !HE1_q_b[5] # !KE1_q_b[5] # !UB1_dout_2_i_a3_0[3] & UB1_dout_2_i_a3_1[3] & !HE1_q_b[5];
 
 
--M1_rx_sr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[4] at LC_X33_Y5_N0
--operation mode is normal
 
M1_rx_sr[4]_lut_out = M1_rx_sr[5];
M1_rx_sr[4] = DFFEAS(M1_rx_sr[4]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--UB1_dout_2_i_0_a2_x[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[4] at LC_X30_Y14_N5
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[4] = !GE1_q_b[4] & UB1_dout_2_i_o2_0[3];
 
 
--UB1_dout_2_i_0_a[4] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[4] at LC_X30_Y14_N8
--operation mode is normal
 
UB1_dout_2_i_0_a[4] = HE1_q_b[4] & !KE1_q_b[4] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[4] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[4] & UB1_dout_2_i_a3_0[3];
 
 
--M1_rx_sr[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[3] at LC_X33_Y5_N3
--operation mode is normal
 
M1_rx_sr[3]_lut_out = M1_rx_sr[4];
M1_rx_sr[3] = DFFEAS(M1_rx_sr[3]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--F1_dout_0_0_a3_6_5_14[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_14[0] at LC_X33_Y13_N5
--operation mode is normal
 
F1_dout_0_0_a3_6_5_14[0] = F1_dout_0_0_a3_6_5_14_a[0] & !AB1_r32_o_3 & !AB1_r32_o_0 & F1_dout_0_0_a3_6_3[0];
 
 
--F1_dout_0_0_a3_6_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_a[0] at LC_X28_Y6_N6
--operation mode is normal
 
F1_dout_0_0_a3_6_a[0] = !JC1_rd_status_29_0_a2_0_7 # !F1_dout_0_0_a3_6_5_8[0] # !F1_dout_0_0_a3_6_5_9[0];
 
 
--M1_ua_state[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[4] at LC_X33_Y15_N1
--operation mode is normal
 
M1_ua_state[4]_lut_out = M1_clk_ctr_equ15_0_a2 & M1_ua_state_2;
M1_ua_state[4] = DFFEAS(M1_ua_state[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--JE1_q_a[3] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[3] at M4K_X17_Y15
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
JE1_q_a[3]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[3]_PORT_A_data_in_reg = DFFE(JE1_q_a[3]_PORT_A_data_in, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_data_in = BUS(TB1_dout_1_3, TB1_dout_1_1);
JE1_q_a[3]_PORT_B_data_in_reg = DFFE(JE1_q_a[3]_PORT_B_data_in, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[3]_PORT_A_address_reg = DFFE(JE1_q_a[3]_PORT_A_address, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[3]_PORT_B_address_reg = DFFE(JE1_q_a[3]_PORT_B_address, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_A_write_enable = GND;
JE1_q_a[3]_PORT_A_write_enable_reg = DFFE(JE1_q_a[3]_PORT_A_write_enable, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_write_enable = WB3L2;
JE1_q_a[3]_PORT_B_write_enable_reg = DFFE(JE1_q_a[3]_PORT_B_write_enable, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[3]_PORT_A_data_out = MEMORY(JE1_q_a[3]_PORT_A_data_in_reg, JE1_q_a[3]_PORT_B_data_in_reg, JE1_q_a[3]_PORT_A_address_reg, JE1_q_a[3]_PORT_B_address_reg, JE1_q_a[3]_PORT_A_write_enable_reg, JE1_q_a[3]_PORT_B_write_enable_reg, , , JE1_q_a[3]_clock_0, , , , , );
JE1_q_a[3] = JE1_q_a[3]_PORT_A_data_out[0];
 
--JE1_q_b[3] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[3] at M4K_X17_Y15
JE1_q_b[3]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[3]_PORT_A_data_in_reg = DFFE(JE1_q_b[3]_PORT_A_data_in, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_data_in = BUS(TB1_dout_1_3, TB1_dout_1_1);
JE1_q_b[3]_PORT_B_data_in_reg = DFFE(JE1_q_b[3]_PORT_B_data_in, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[3]_PORT_A_address_reg = DFFE(JE1_q_b[3]_PORT_A_address, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[3]_PORT_B_address_reg = DFFE(JE1_q_b[3]_PORT_B_address, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_A_write_enable = GND;
JE1_q_b[3]_PORT_A_write_enable_reg = DFFE(JE1_q_b[3]_PORT_A_write_enable, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_write_enable = WB3L2;
JE1_q_b[3]_PORT_B_write_enable_reg = DFFE(JE1_q_b[3]_PORT_B_write_enable, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[3]_PORT_B_data_out = MEMORY(JE1_q_b[3]_PORT_A_data_in_reg, JE1_q_b[3]_PORT_B_data_in_reg, JE1_q_b[3]_PORT_A_address_reg, JE1_q_b[3]_PORT_B_address_reg, JE1_q_b[3]_PORT_A_write_enable_reg, JE1_q_b[3]_PORT_B_write_enable_reg, , , JE1_q_b[3]_clock_0, , , , , );
JE1_q_b[3] = JE1_q_b[3]_PORT_B_data_out[0];
 
--JE1_q_a[1] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[1] at M4K_X17_Y15
JE1_q_a[3]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[3]_PORT_A_data_in_reg = DFFE(JE1_q_a[3]_PORT_A_data_in, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_data_in = BUS(TB1_dout_1_3, TB1_dout_1_1);
JE1_q_a[3]_PORT_B_data_in_reg = DFFE(JE1_q_a[3]_PORT_B_data_in, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[3]_PORT_A_address_reg = DFFE(JE1_q_a[3]_PORT_A_address, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[3]_PORT_B_address_reg = DFFE(JE1_q_a[3]_PORT_B_address, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_A_write_enable = GND;
JE1_q_a[3]_PORT_A_write_enable_reg = DFFE(JE1_q_a[3]_PORT_A_write_enable, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_PORT_B_write_enable = WB3L2;
JE1_q_a[3]_PORT_B_write_enable_reg = DFFE(JE1_q_a[3]_PORT_B_write_enable, JE1_q_a[3]_clock_0, , , );
JE1_q_a[3]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[3]_PORT_A_data_out = MEMORY(JE1_q_a[3]_PORT_A_data_in_reg, JE1_q_a[3]_PORT_B_data_in_reg, JE1_q_a[3]_PORT_A_address_reg, JE1_q_a[3]_PORT_B_address_reg, JE1_q_a[3]_PORT_A_write_enable_reg, JE1_q_a[3]_PORT_B_write_enable_reg, , , JE1_q_a[3]_clock_0, , , , , );
JE1_q_a[1] = JE1_q_a[3]_PORT_A_data_out[1];
 
--JE1_q_b[1] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[1] at M4K_X17_Y15
JE1_q_b[3]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[3]_PORT_A_data_in_reg = DFFE(JE1_q_b[3]_PORT_A_data_in, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_data_in = BUS(TB1_dout_1_3, TB1_dout_1_1);
JE1_q_b[3]_PORT_B_data_in_reg = DFFE(JE1_q_b[3]_PORT_B_data_in, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[3]_PORT_A_address_reg = DFFE(JE1_q_b[3]_PORT_A_address, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[3]_PORT_B_address_reg = DFFE(JE1_q_b[3]_PORT_B_address, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_A_write_enable = GND;
JE1_q_b[3]_PORT_A_write_enable_reg = DFFE(JE1_q_b[3]_PORT_A_write_enable, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_PORT_B_write_enable = WB3L2;
JE1_q_b[3]_PORT_B_write_enable_reg = DFFE(JE1_q_b[3]_PORT_B_write_enable, JE1_q_b[3]_clock_0, , , );
JE1_q_b[3]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[3]_PORT_B_data_out = MEMORY(JE1_q_b[3]_PORT_A_data_in_reg, JE1_q_b[3]_PORT_B_data_in_reg, JE1_q_b[3]_PORT_A_address_reg, JE1_q_b[3]_PORT_B_address_reg, JE1_q_b[3]_PORT_A_write_enable_reg, JE1_q_b[3]_PORT_B_write_enable_reg, , , JE1_q_b[3]_clock_0, , , , , );
JE1_q_b[1] = JE1_q_b[3]_PORT_B_data_out[1];
 
 
--UB1_dout_2_i_a2_x[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a2_x[3] at LC_X31_Y13_N5
--operation mode is normal
 
UB1_dout_2_i_a2_x[3] = !GE1_q_b[3] & UB1_dout_2_i_o2_0[3];
 
 
--UB1_dout_2_i_a[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a[3] at LC_X31_Y13_N9
--operation mode is normal
 
UB1_dout_2_i_a[3] = HE1_q_b[3] & !KE1_q_b[3] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[3] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[3] & UB1_dout_2_i_a3_0[3];
 
 
--M1_rx_sr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[2] at LC_X33_Y5_N4
--operation mode is normal
 
M1_rx_sr[2]_lut_out = M1_rx_sr[3];
M1_rx_sr[2] = DFFEAS(M1_rx_sr[2]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--UB1_dout_2_i_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[2] at LC_X30_Y13_N7
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[2] = UB1_dout_2_i_o2_0[3] & !GE1_q_b[2];
 
 
--UB1_dout_2_i_0_a[2] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[2] at LC_X30_Y9_N2
--operation mode is normal
 
UB1_dout_2_i_0_a[2] = UB1_dout_2_i_a3_0[3] & !HE1_q_b[2] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[2] # !UB1_dout_2_i_a3_0[3] & !HE1_q_b[2] & UB1_dout_2_i_a3_1[3];
 
 
--M1_rx_sr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[1] at LC_X33_Y5_N5
--operation mode is normal
 
M1_rx_sr[1]_lut_out = M1_rx_sr[2];
M1_rx_sr[1] = DFFEAS(M1_rx_sr[1]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--UB1_dout_2_i_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[1] at LC_X30_Y13_N8
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[1] = UB1_dout_2_i_o2_0[3] & !GE1_q_b[1];
 
 
--UB1_dout_2_i_0_a[1] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[1] at LC_X30_Y13_N2
--operation mode is normal
 
UB1_dout_2_i_0_a[1] = KE1_q_b[1] & UB1_dout_2_i_a3_1[3] & !HE1_q_b[1] # !KE1_q_b[1] & UB1_dout_2_i_a3_0[3] # UB1_dout_2_i_a3_1[3] & !HE1_q_b[1];
 
 
--UD1_shift_out_80[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[1] at LC_X16_Y17_N2
--operation mode is normal
 
UD1_shift_out_80[1] = PD1_a_o_2 & UD1_shift_out_80_a[1] & VD1_b_o_iv_6 # !UD1_shift_out_80_a[1] & VD1_b_o_iv_8 # !PD1_a_o_2 & !UD1_shift_out_80_a[1];
 
 
--UD1_shift_out_82[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[1] at LC_X16_Y17_N5
--operation mode is normal
 
UD1_shift_out_82[1] = PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_7 # !PD1_a_o_1 & !UD1_shift_out_82_a[1] # !PD1_a_o_2 & !UD1_shift_out_82_a[1];
 
 
--UD1_shift_out_86_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[1] at LC_X14_Y13_N0
--operation mode is normal
 
UD1_shift_out_86_a[1] = PD1_a_o_2 & !UD1_shift_out_79[5] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[9] # !UD1_shift_out587 & !UD1_shift_out_79[5];
 
 
--UD1_shift_out_74[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[1] at LC_X14_Y13_N9
--operation mode is normal
 
UD1_shift_out_74[1] = PD1_a_o_3 & UD1_shift_out_74_a[1] & UD1_shift_out_79[17] # !UD1_shift_out_74_a[1] & UD1_shift_out_41[1] # !PD1_a_o_3 & !UD1_shift_out_74_a[1];
 
 
--UD1_shift_out_91_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[1] at LC_X15_Y13_N8
--operation mode is normal
 
UD1_shift_out_91_a[1] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_1 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[1];
 
 
--UD1_shift_out_76[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[1] at LC_X15_Y13_N0
--operation mode is normal
 
UD1_shift_out_76[1] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_76_a[1] # !PD1_a_o_2 & UD1_shift_out_79[17] # !UD1_shift_out587 & !UD1_shift_out_76_a[1];
 
 
--VD1_hilo_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1 at LC_X5_Y17_N7
--operation mode is normal
 
VD1_hilo_1_lut_out = VD1_hilo_37_iv_0_0[1] # PD1_a_o_1 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[1];
VD1_hilo_1 = DFFEAS(VD1_hilo_1_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_33 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33 at LC_X8_Y8_N0
--operation mode is normal
 
VD1_hilo_33_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_2[33] & !VD1_hilo25 # !VD1_hilo_37_iv_a[33];
VD1_hilo_33 = DFFEAS(VD1_hilo_33_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--TD1_alu_out_7_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_a[1] at LC_X15_Y9_N2
--operation mode is normal
 
TD1_alu_out_7_0_a[1] = VD1_b_o_iv_1 & !PD1_a_o_1 & RC1_alu_func_o_2 $ RC1_alu_func_o_0 # !VD1_b_o_iv_1 & RC1_alu_func_o_0 # !PD1_a_o_1;
 
 
--TD1_alu_out_6_0[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_6_0[1] at LC_X12_Y10_N1
--operation mode is normal
 
TD1_alu_out_6_0[1] = RC1_alu_func_o_1 & TD1_un1_a_add1 # !RC1_alu_func_o_1 & RC1_alu_func_o_4 & TD1_alu_out_6_0_a[1] # !RC1_alu_func_o_4 & TD1_un1_a_add1;
 
 
--M1_rx_sr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rx_sr[0] at LC_X33_Y5_N8
--operation mode is normal
 
M1_rx_sr[0]_lut_out = M1_rx_sr[1];
M1_rx_sr[0] = DFFEAS(M1_rx_sr[0]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_570_x, , , !sys_rst, );
 
 
--JE1_q_a[0] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[0] at M4K_X17_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
JE1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[0]_PORT_A_data_in_reg = DFFE(JE1_q_a[0]_PORT_A_data_in, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_data_in = BUS(TB1_dout_1_0, TB1_dout_1_7);
JE1_q_a[0]_PORT_B_data_in_reg = DFFE(JE1_q_a[0]_PORT_B_data_in, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[0]_PORT_A_address_reg = DFFE(JE1_q_a[0]_PORT_A_address, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[0]_PORT_B_address_reg = DFFE(JE1_q_a[0]_PORT_B_address, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_A_write_enable = GND;
JE1_q_a[0]_PORT_A_write_enable_reg = DFFE(JE1_q_a[0]_PORT_A_write_enable, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_write_enable = WB3L2;
JE1_q_a[0]_PORT_B_write_enable_reg = DFFE(JE1_q_a[0]_PORT_B_write_enable, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[0]_PORT_A_data_out = MEMORY(JE1_q_a[0]_PORT_A_data_in_reg, JE1_q_a[0]_PORT_B_data_in_reg, JE1_q_a[0]_PORT_A_address_reg, JE1_q_a[0]_PORT_B_address_reg, JE1_q_a[0]_PORT_A_write_enable_reg, JE1_q_a[0]_PORT_B_write_enable_reg, , , JE1_q_a[0]_clock_0, , , , , );
JE1_q_a[0] = JE1_q_a[0]_PORT_A_data_out[0];
 
--JE1_q_b[0] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[0] at M4K_X17_Y8
JE1_q_b[0]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[0]_PORT_A_data_in_reg = DFFE(JE1_q_b[0]_PORT_A_data_in, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_data_in = BUS(TB1_dout_1_0, TB1_dout_1_7);
JE1_q_b[0]_PORT_B_data_in_reg = DFFE(JE1_q_b[0]_PORT_B_data_in, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[0]_PORT_A_address_reg = DFFE(JE1_q_b[0]_PORT_A_address, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[0]_PORT_B_address_reg = DFFE(JE1_q_b[0]_PORT_B_address, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_A_write_enable = GND;
JE1_q_b[0]_PORT_A_write_enable_reg = DFFE(JE1_q_b[0]_PORT_A_write_enable, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_write_enable = WB3L2;
JE1_q_b[0]_PORT_B_write_enable_reg = DFFE(JE1_q_b[0]_PORT_B_write_enable, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[0]_PORT_B_data_out = MEMORY(JE1_q_b[0]_PORT_A_data_in_reg, JE1_q_b[0]_PORT_B_data_in_reg, JE1_q_b[0]_PORT_A_address_reg, JE1_q_b[0]_PORT_B_address_reg, JE1_q_b[0]_PORT_A_write_enable_reg, JE1_q_b[0]_PORT_B_write_enable_reg, , , JE1_q_b[0]_clock_0, , , , , );
JE1_q_b[0] = JE1_q_b[0]_PORT_B_data_out[0];
 
--JE1_q_a[7] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_a[7] at M4K_X17_Y8
JE1_q_a[0]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_a[0]_PORT_A_data_in_reg = DFFE(JE1_q_a[0]_PORT_A_data_in, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_data_in = BUS(TB1_dout_1_0, TB1_dout_1_7);
JE1_q_a[0]_PORT_B_data_in_reg = DFFE(JE1_q_a[0]_PORT_B_data_in, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_a[0]_PORT_A_address_reg = DFFE(JE1_q_a[0]_PORT_A_address, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_a[0]_PORT_B_address_reg = DFFE(JE1_q_a[0]_PORT_B_address, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_A_write_enable = GND;
JE1_q_a[0]_PORT_A_write_enable_reg = DFFE(JE1_q_a[0]_PORT_A_write_enable, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_PORT_B_write_enable = WB3L2;
JE1_q_a[0]_PORT_B_write_enable_reg = DFFE(JE1_q_a[0]_PORT_B_write_enable, JE1_q_a[0]_clock_0, , , );
JE1_q_a[0]_clock_0 = GLOBAL(E1__clk0);
JE1_q_a[0]_PORT_A_data_out = MEMORY(JE1_q_a[0]_PORT_A_data_in_reg, JE1_q_a[0]_PORT_B_data_in_reg, JE1_q_a[0]_PORT_A_address_reg, JE1_q_a[0]_PORT_B_address_reg, JE1_q_a[0]_PORT_A_write_enable_reg, JE1_q_a[0]_PORT_B_write_enable_reg, , , JE1_q_a[0]_clock_0, , , , , );
JE1_q_a[7] = JE1_q_a[0]_PORT_A_data_out[1];
 
--JE1_q_b[7] is mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|q_b[7] at M4K_X17_Y8
JE1_q_b[0]_PORT_A_data_in = BUS(~GND, ~GND);
JE1_q_b[0]_PORT_A_data_in_reg = DFFE(JE1_q_b[0]_PORT_A_data_in, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_data_in = BUS(TB1_dout_1_0, TB1_dout_1_7);
JE1_q_b[0]_PORT_B_data_in_reg = DFFE(JE1_q_b[0]_PORT_B_data_in, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
JE1_q_b[0]_PORT_A_address_reg = DFFE(JE1_q_b[0]_PORT_A_address, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
JE1_q_b[0]_PORT_B_address_reg = DFFE(JE1_q_b[0]_PORT_B_address, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_A_write_enable = GND;
JE1_q_b[0]_PORT_A_write_enable_reg = DFFE(JE1_q_b[0]_PORT_A_write_enable, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_PORT_B_write_enable = WB3L2;
JE1_q_b[0]_PORT_B_write_enable_reg = DFFE(JE1_q_b[0]_PORT_B_write_enable, JE1_q_b[0]_clock_0, , , );
JE1_q_b[0]_clock_0 = GLOBAL(E1__clk0);
JE1_q_b[0]_PORT_B_data_out = MEMORY(JE1_q_b[0]_PORT_A_data_in_reg, JE1_q_b[0]_PORT_B_data_in_reg, JE1_q_b[0]_PORT_A_address_reg, JE1_q_b[0]_PORT_B_address_reg, JE1_q_b[0]_PORT_A_write_enable_reg, JE1_q_b[0]_PORT_B_write_enable_reg, , , JE1_q_b[0]_clock_0, , , , , );
JE1_q_b[7] = JE1_q_b[0]_PORT_B_data_out[1];
 
 
--UB1_dout_2_i_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a2_x[0] at LC_X31_Y7_N5
--operation mode is normal
 
UB1_dout_2_i_0_a2_x[0] = !GE1_q_b[0] & UB1_dout_2_i_o2_0[3];
 
 
--UB1_dout_2_i_0_a[0] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_0_a[0] at LC_X31_Y13_N7
--operation mode is normal
 
UB1_dout_2_i_0_a[0] = KE1_q_b[0] & !HE1_q_b[0] & UB1_dout_2_i_a3_1[3] # !KE1_q_b[0] & UB1_dout_2_i_a3_0[3] # !HE1_q_b[0] & UB1_dout_2_i_a3_1[3];
 
 
--VD1_res_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|res_2_0 at LC_X11_Y6_N5
--operation mode is normal
 
VD1_res_2_0 = VD1_un24_res & VD1_hilo[32] # !VD1_un24_res & VD1_un11_res & VD1_hilo[0];
 
 
--MD1_c_1_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[0] at LC_X9_Y14_N1
--operation mode is normal
 
MD1_c_1_a[0] = PD1_a_o_0 & RC1_alu_func_o_0 & !VD1_b_o_iv_0 # !PD1_a_o_0 & RC1_alu_func_o_2 $ RC1_alu_func_o_0 # !VD1_b_o_iv_0;
 
 
--TD1_un1_b_1_combout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[0] at LC_X12_Y10_N2
--operation mode is normal
 
TD1_un1_b_1_combout[0] = VD1_b_o_iv_0 $ !TD1_sum13_0_a2;
 
 
--TD1_un1_a_add0_start_cout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add0_start_cout at LC_X12_Y10_N4
--operation mode is arithmetic
 
TD1_un1_a_add0_start_cout = CARRY(TD1_sum13_0_a2);
 
 
--UD1_shift_out_91_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[0] at LC_X20_Y13_N7
--operation mode is normal
 
UD1_shift_out_91_a[0] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_0 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[0];
 
 
--UD1_shift_out_76[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[0] at LC_X21_Y13_N8
--operation mode is normal
 
UD1_shift_out_76[0] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_76_a[0] # !PD1_a_o_2 & UD1_shift_out_79[16];
 
 
--UD1_shift_out_87[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[0] at LC_X15_Y11_N3
--operation mode is normal
 
UD1_shift_out_87[0] = PD1_a_o_0 & UD1_shift_out_80[0] # !PD1_a_o_0 & UD1_shift_out_82[0];
 
 
--UD1_shift_out_86[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[0] at LC_X19_Y13_N8
--operation mode is normal
 
UD1_shift_out_86[0] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[0] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[0];
 
 
--PD1_a_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_31 at LC_X19_Y3_N9
--operation mode is normal
 
PD1_a_o_31 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[31] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[31];
 
 
--VD1_b_o_iv_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_31 at LC_X22_Y16_N2
--operation mode is normal
 
VD1_b_o_iv_31 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] & !G1_BUS15471_i_m[31] & AB1_r32_o_29 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[31] at LC_X22_Y16_N2
--operation mode is normal
 
VD1_op2_reged[31] = DFFEAS(VD1_b_o_iv_31, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_lt_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_30 at LC_X16_Y7_N4
--operation mode is arithmetic
 
TD1_lt_30 = CARRY(PD1_a_o_30 & VD1_b_o_iv_30 & !TD1L691 # !PD1_a_o_30 & VD1_b_o_iv_30 # !TD1L691);
 
 
--TD1_sum_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_31 at LC_X15_Y6_N5
--operation mode is arithmetic
 
TD1_sum_carry_31_cout_0 = PD1_a_o_31 & VD1_b_o_iv_31 & !TD1_sum_carry_30 # !PD1_a_o_31 & VD1_b_o_iv_31 # !TD1_sum_carry_30;
TD1_sum_carry_31 = CARRY(TD1_sum_carry_31_cout_0);
 
--TD1L444 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_31~COUT1_1 at LC_X15_Y6_N5
--operation mode is arithmetic
 
TD1L444_cout_1 = PD1_a_o_31 & VD1_b_o_iv_31 & !TD1_sum_carry_30 # !PD1_a_o_31 & VD1_b_o_iv_31 # !TD1_sum_carry_30;
TD1L444 = CARRY(TD1L444_cout_1);
 
 
--N1_tx_sr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[5] at LC_X16_Y2_N8
--operation mode is normal
 
N1_tx_sr[5]_lut_out = N1_read_request_ff & Y1_q_b[5] # !N1_read_request_ff & N1_tx_sr[6];
N1_tx_sr[5] = DFFEAS(N1_tx_sr[5]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--N1_clk_ctr26_i_0_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_0_a at LC_X14_Y3_N4
--operation mode is normal
 
N1_ua_state[4]_qfbk = N1_ua_state[4];
N1_clk_ctr26_i_0_0_a = !N1_ua_state[3] & !N1_ua_state[5] & !N1_ua_state[4]_qfbk & !N1_ua_state[2];
 
--N1_ua_state[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[4] at LC_X14_Y3_N4
--operation mode is normal
 
N1_ua_state[4] = DFFEAS(N1_clk_ctr26_i_0_0_a, GLOBAL(E1__clk0), VCC, , C1_G_451_x, N1_ua_state[3], , !sys_rst, VCC);
 
 
--N1_clk_ctr26_i_0_a4_0_6_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a4_0_6_a at LC_X15_Y2_N1
--operation mode is normal
 
N1_clk_ctr26_i_0_a4_0_6_a = !N1_clk_ctr[1] # !N1_clk_ctr[9];
 
 
--K1_cntr_30 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_30 at LC_X31_Y3_N4
--operation mode is arithmetic
 
K1_cntr_30_carry_eqn = (!K1_cntr_cout[25] & K1_cntr_cout[29]) # (K1_cntr_cout[25] & K1L251);
K1_cntr_30_lut_out = K1_cntr_30 $ K1_cntr_30_carry_eqn;
K1_cntr_30 = DFFEAS(K1_cntr_30_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[30], , , !K1_un1_ld_1);
 
--K1_cntr_cout[30] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[30] at LC_X31_Y3_N4
--operation mode is arithmetic
 
K1_cntr_cout[30] = CARRY(K1_cntr_30 # !K1L251);
 
 
--K1_cntr_31 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_31 at LC_X31_Y3_N5
--operation mode is normal
 
K1_cntr_31_carry_eqn = K1_cntr_cout[30];
K1_cntr_31_lut_out = K1_cntr_31_carry_eqn $ !K1_cntr_31;
K1_cntr_31 = DFFEAS(K1_cntr_31_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[31], , , !K1_un1_ld_1);
 
 
--K1_cntr_28 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_28 at LC_X31_Y3_N2
--operation mode is arithmetic
 
K1_cntr_28_carry_eqn = (!K1_cntr_cout[25] & K1_cntr_cout[27]) # (K1_cntr_cout[25] & K1L841);
K1_cntr_28_lut_out = K1_cntr_28 $ (K1_cntr_28_carry_eqn);
K1_cntr_28 = DFFEAS(K1_cntr_28_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[28], , , !K1_un1_ld_1);
 
--K1_cntr_cout[28] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[28] at LC_X31_Y3_N2
--operation mode is arithmetic
 
K1_cntr_cout[28]_cout_0 = K1_cntr_28 # !K1_cntr_cout[27];
K1_cntr_cout[28] = CARRY(K1_cntr_cout[28]_cout_0);
 
--K1L051 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[28]~COUT1_23 at LC_X31_Y3_N2
--operation mode is arithmetic
 
K1L051_cout_1 = K1_cntr_28 # !K1L841;
K1L051 = CARRY(K1L051_cout_1);
 
 
--K1_cntr_29 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_29 at LC_X31_Y3_N3
--operation mode is arithmetic
 
K1_cntr_29_carry_eqn = (!K1_cntr_cout[25] & K1_cntr_cout[28]) # (K1_cntr_cout[25] & K1L051);
K1_cntr_29_lut_out = K1_cntr_29 $ !K1_cntr_29_carry_eqn;
K1_cntr_29 = DFFEAS(K1_cntr_29_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[29], , , !K1_un1_ld_1);
 
--K1_cntr_cout[29] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[29] at LC_X31_Y3_N3
--operation mode is arithmetic
 
K1_cntr_cout[29]_cout_0 = !K1_cntr_29 & !K1_cntr_cout[28];
K1_cntr_cout[29] = CARRY(K1_cntr_cout[29]_cout_0);
 
--K1L251 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[29]~COUT1_24 at LC_X31_Y3_N3
--operation mode is arithmetic
 
K1L251_cout_1 = !K1_cntr_29 & !K1L051;
K1L251 = CARRY(K1L251_cout_1);
 
 
--K1_un2_w_irq_22 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_22 at LC_X30_Y3_N6
--operation mode is normal
 
K1_un2_w_irq_22 = !K1_cntr_19 & !K1_cntr_18 & !K1_cntr_17 & !K1_cntr_16;
 
 
--K1_un2_w_irq_23 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_23 at LC_X30_Y5_N8
--operation mode is normal
 
K1_un2_w_irq_23 = !K1_cntr_23 & !K1_cntr_20 & !K1_cntr_22 & !K1_cntr_21;
 
 
--K1_un2_w_irq_20 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_20 at LC_X31_Y3_N6
--operation mode is normal
 
K1_un2_w_irq_20 = !K1_cntr_27 & !K1_cntr_24 & !K1_cntr_25 & !K1_cntr_26;
 
 
--K1_un2_w_irq_16 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_16 at LC_X30_Y6_N6
--operation mode is normal
 
K1_un2_w_irq_16 = !K1_cntr_9 & !K1_cntr_11 & !K1_cntr_10 & !K1_cntr_8;
 
 
--K1_un2_w_irq_17 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_17 at LC_X30_Y6_N5
--operation mode is normal
 
K1_un2_w_irq_17 = !K1_cntr_15 & !K1_cntr_12 & !K1_cntr_14 & !K1_cntr_13;
 
 
--K1_un2_w_irq_18 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_18 at LC_X31_Y6_N3
--operation mode is normal
 
K1_un2_w_irq_18 = !K1_cntr_3 & !K1_cntr_1 & !K1_cntr_0 & !K1_cntr_2;
 
 
--K1_un2_w_irq_19 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un2_w_irq_19 at LC_X30_Y6_N2
--operation mode is normal
 
K1_un2_w_irq_19 = !K1_cntr_6 & !K1_cntr_4 & !K1_cntr_7 & !K1_cntr_5;
 
 
--CB1_dout_2_8 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_8 at LC_X20_Y5_N8
--operation mode is normal
 
CB1_dout_2_8 = ND1_dout7 & FD1_wb_o_8 # !ND1_dout7 & !ND1_dout_2_a_8;
 
--CB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_8 at LC_X20_Y5_N8
--operation mode is normal
 
CB1_r32_o_8 = DFFEAS(CB1_dout_2_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_rxq1 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rxq1 at LC_X33_Y15_N3
--operation mode is normal
 
M1_rxq1_lut_out = ser_rxd;
M1_rxq1 = DFFEAS(M1_rxq1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--C1_G_570_x is mips_sys:isys|G_570_x at LC_X33_Y5_N9
--operation mode is normal
 
C1_G_570_x = M1_clk_ctr_equ15_0_a2 # !sys_rst;
 
 
--C1_G_578_a is mips_sys:isys|G_578_a at LC_X33_Y16_N5
--operation mode is normal
 
C1_G_578_a = M1_ua_state_2 & !M1_clk_ctr_2 & M1_clk_ctr_3 & !M1_clk_ctr_0;
 
 
--M1_un1_clk_ctr_equ0_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2 at LC_X32_Y15_N9
--operation mode is normal
 
M1_un1_clk_ctr_equ0_0_a2 = !M1_clk_ctr[14] & M1_un1_clk_ctr_equ0_0_a2_a & !M1_clk_ctr[15] & !M1_clk_ctr[13];
 
 
--M1_un1_clk_ctr_equ0_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_0 at LC_X33_Y16_N3
--operation mode is normal
 
M1_un1_clk_ctr_equ0_0_a2_0 = M1_un1_clk_ctr_equ0_0_a2_0_a & M1_clk_ctr[10] & M1_clk_ctr[8] & !M1_clk_ctr[5];
 
 
--F1_dout_0_0_a3_5_3_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_5_3_a[0] at LC_X33_Y8_N1
--operation mode is normal
 
F1_dout_0_0_a3_5_3_a[0] = !JC1_dmem_ctl_o_0 & AB1_r32_o_1 & JC1_dmem_ctl_o_1 $ JC1_dmem_ctl_o_2;
 
 
--KB1_pc_next_0_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_2 at LC_X16_Y12_N0
--operation mode is normal
 
KB1_pc_next_0_iv_2 = DD1_pc_next_0_iv_1_2 # DD1_un1_pc_next46_0 & DD1_un1_pc_add2;
 
--KB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_2 at LC_X16_Y12_N0
--operation mode is normal
 
KB1_r32_o_2 = DFFEAS(KB1_pc_next_0_iv_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_3 at LC_X16_Y13_N1
--operation mode is normal
 
KB1_pc_next_0_iv_3 = DD1_pc_next_0_iv_1_3 # DD1_un1_pc_next46_0 & DD1_un1_pc_add3;
 
--KB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_3 at LC_X16_Y13_N1
--operation mode is normal
 
KB1_r32_o_3 = DFFEAS(KB1_pc_next_0_iv_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_4 at LC_X16_Y11_N1
--operation mode is normal
 
KB1_pc_next_0_iv_4 = DD1_pc_next_0_iv_1_4 # DD1_un1_pc_next46_0 & DD1_un1_pc_add4;
 
--KB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_4 at LC_X16_Y11_N1
--operation mode is normal
 
KB1_r32_o_4 = DFFEAS(KB1_pc_next_0_iv_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_5 at LC_X20_Y11_N2
--operation mode is normal
 
KB1_pc_next_0_iv_5 = DD1_pc_next_0_iv_1_5 # DD1_un1_pc_next46_0 & DD1_un1_pc_add5;
 
--KB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_5 at LC_X20_Y11_N2
--operation mode is normal
 
KB1_r32_o_5 = DFFEAS(KB1_pc_next_0_iv_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_6 at LC_X19_Y11_N9
--operation mode is normal
 
KB1_pc_next_0_iv_6 = DD1_pc_next_0_iv_1_6 # DD1_un1_pc_next46_0 & DD1_un1_pc_add6;
 
--KB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_6 at LC_X19_Y11_N9
--operation mode is normal
 
KB1_r32_o_6 = DFFEAS(KB1_pc_next_0_iv_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_7 at LC_X19_Y9_N6
--operation mode is normal
 
KB1_pc_next_0_iv_7 = DD1_pc_next_0_iv_1_7 # DD1_un1_pc_next46_0 & DD1_un1_pc_add7;
 
--KB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_7 at LC_X19_Y9_N6
--operation mode is normal
 
KB1_r32_o_7 = DFFEAS(KB1_pc_next_0_iv_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_8 at LC_X19_Y8_N3
--operation mode is normal
 
KB1_pc_next_0_iv_8 = DD1_pc_next_0_iv_1_8 # DD1_un1_pc_next46_0 & DD1_un1_pc_add8;
 
--KB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_8 at LC_X19_Y8_N3
--operation mode is normal
 
KB1_r32_o_8 = DFFEAS(KB1_pc_next_0_iv_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_9 at LC_X19_Y10_N9
--operation mode is normal
 
KB1_pc_next_0_iv_9 = DD1_pc_next_0_iv_1_9 # DD1_un1_pc_next46_0 & DD1_un1_pc_add9;
 
--KB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_9 at LC_X19_Y10_N9
--operation mode is normal
 
KB1_r32_o_9 = DFFEAS(KB1_pc_next_0_iv_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_10 at LC_X19_Y12_N9
--operation mode is normal
 
KB1_pc_next_0_iv_10 = DD1_pc_next_0_iv_1_10 # DD1_un1_pc_add10 & DD1_un1_pc_next46_0;
 
--KB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_10 at LC_X19_Y12_N9
--operation mode is normal
 
KB1_r32_o_10 = DFFEAS(KB1_pc_next_0_iv_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_11 at LC_X22_Y10_N7
--operation mode is normal
 
KB1_pc_next_0_iv_11 = DD1_pc_next_0_iv_1_11 # DD1_un1_pc_next46_0 & DD1_un1_pc_add11;
 
--KB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_11 at LC_X22_Y10_N7
--operation mode is normal
 
KB1_r32_o_11 = DFFEAS(KB1_pc_next_0_iv_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_pc_next_0_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|pc_next_0_iv_12 at LC_X23_Y12_N9
--operation mode is normal
 
KB1_pc_next_0_iv_12 = DD1_pc_next_0_iv_1_12 # DD1_un1_pc_next46_0 & DD1_un1_pc_add12;
 
--KB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_12 at LC_X23_Y12_N9
--operation mode is normal
 
KB1_r32_o_12 = DFFEAS(KB1_pc_next_0_iv_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_0_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_0_a[7] at LC_X30_Y8_N1
--operation mode is normal
 
UB1_dout_2_i_i_0_a[7] = RB1_ctl_o_3 & !RB1_ctl_o_2;
 
 
--UB1_dout_2_i_i_o3_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o3_0[7] at LC_X30_Y8_N4
--operation mode is normal
 
UB1_dout_2_i_i_o3_0[7] = RB1_byte_addr_o_1 # RB1_byte_addr_o_0 # !RB1_ctl_o_3;
 
 
--UB1_dout_2_i_i_a2_2[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_2[7] at LC_X29_Y8_N0
--operation mode is normal
 
UB1_dout_2_i_i_a2_2[7] = UB1_dout_2_i_i_a2_2_a[7] & RB1_byte_addr_o_1 & GE1_q_b[7] # !RB1_byte_addr_o_1 & JE1_q_b[7];
 
 
--UB1_dout_2_i_i_a2_1[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_1[7] at LC_X29_Y8_N8
--operation mode is normal
 
UB1_dout_2_i_i_a2_1[7] = UB1_dout_2_i_i_a2_1_a[7] & RB1_byte_addr_o_1 & HE1_q_b[7] # !RB1_byte_addr_o_1 & KE1_q_b[7];
 
 
--UB1_dout_2_i_i_o2_0[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o2_0[7] at LC_X29_Y8_N1
--operation mode is normal
 
UB1_dout_2_i_i_o2_0[7] = !RB1_byte_addr_o_1 & UB1_dout_2_i_i_o2_0_a[7];
 
 
--FD1_un23_qb_i_0_a2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qb_i_0_a2_a at LC_X25_Y12_N1
--operation mode is normal
 
FD1_r_rdaddress_b[2]_qfbk = FD1_r_rdaddress_b[2];
FD1_un23_qb_i_0_a2_a = !FD1_r_rdaddress_b[2]_qfbk & !FD1_r_rdaddress_b[3];
 
--FD1_r_rdaddress_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[2] at LC_X25_Y12_N1
--operation mode is normal
 
FD1_r_rdaddress_b[2] = DFFEAS(FD1_un23_qb_i_0_a2_a, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[2], , , VCC);
 
 
--FD1_un14_qb_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE_1 at LC_X26_Y14_N7
--operation mode is normal
 
FD1_r_rdaddress_b[1]_qfbk = FD1_r_rdaddress_b[1];
FD1_un14_qb_NE_1 = FD1_r_wraddress[0] & FD1_r_wraddress[1] $ FD1_r_rdaddress_b[1]_qfbk # !FD1_r_rdaddress_b[0] # !FD1_r_wraddress[0] & FD1_r_rdaddress_b[0] # FD1_r_wraddress[1] $ FD1_r_rdaddress_b[1]_qfbk;
 
--FD1_r_rdaddress_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[1] at LC_X26_Y14_N7
--operation mode is normal
 
FD1_r_rdaddress_b[1] = DFFEAS(FD1_un14_qb_NE_1, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[1], , , VCC);
 
 
--FD1_un14_qb_NE_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qb_NE_a at LC_X26_Y14_N9
--operation mode is normal
 
FD1_r_rdaddress_b[3]_qfbk = FD1_r_rdaddress_b[3];
FD1_un14_qb_NE_a = FD1_r_rdaddress_b[2] & FD1_r_wraddress[3] $ FD1_r_rdaddress_b[3]_qfbk # !FD1_r_wraddress[2] # !FD1_r_rdaddress_b[2] & FD1_r_wraddress[2] # FD1_r_wraddress[3] $ FD1_r_rdaddress_b[3]_qfbk;
 
--FD1_r_rdaddress_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_b[3] at LC_X26_Y14_N9
--operation mode is normal
 
FD1_r_rdaddress_b[3] = DFFEAS(FD1_un14_qb_NE_a, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[3], , , VCC);
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] at LC_X16_Y5_N6
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[9] = FB1_r32_o_0_9 & !QB1_r32_o_9 & QD1_un1_b_o18_2 # !FB1_r32_o_0_9 & QD1_b_o18 # !QB1_r32_o_9 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[9] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[9] at LC_X16_Y5_N5
--operation mode is normal
 
G1_BUS15471_i_m[9] = QD1_b_o_1_sqmuxa & !FD1_wb_o_9;
 
 
--UD1_shift_out_87_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[7] at LC_X10_Y15_N5
--operation mode is normal
 
UD1_shift_out_87_d_a[7] = PD1_a_o_1 & !VD1_b_o_iv_13 # !PD1_a_o_1 & !VD1_b_o_iv_11;
 
 
--UD1_shift_out_80[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[7] at LC_X10_Y15_N0
--operation mode is normal
 
UD1_shift_out_80[7] = PD1_a_o_2 & UD1_shift_out_80_a[7] & VD1_b_o_iv_12 # !UD1_shift_out_80_a[7] & VD1_b_o_iv_14 # !PD1_a_o_2 & !UD1_shift_out_80_a[7];
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] at LC_X20_Y5_N2
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[6] = FB1_r32_o_0_6 & !QB1_r32_o_6 & QD1_un1_b_o18_2 # !FB1_r32_o_0_6 & QD1_b_o18 # !QB1_r32_o_6 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[6] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[6] at LC_X20_Y5_N4
--operation mode is normal
 
G1_BUS15471_i_m[6] = QD1_b_o_1_sqmuxa & !FD1_wb_o_6;
 
 
--UD1_shift_out_85_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[7] at LC_X12_Y16_N6
--operation mode is normal
 
UD1_shift_out_85_d_a[7] = PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_0 & !VD1_b_o_iv_5;
 
 
--UD1_shift_out_43[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[31] at LC_X12_Y14_N5
--operation mode is normal
 
UD1_shift_out_43[31] = PD1_a_o_1 & !UD1_shift_out_43_a[31] # !PD1_a_o_1 & UD1_shift_out_43_a[31] & VD1_b_o_iv_3 # !UD1_shift_out_43_a[31] & VD1_b_o_iv_2;
 
 
--UD1_shift_out588 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out588 at LC_X13_Y15_N5
--operation mode is normal
 
RC1_alu_func_o_1_qfbk = RC1_alu_func_o_1;
UD1_shift_out588 = !RC1_alu_func_o_0 & !RC1_alu_func_o_4 & !RC1_alu_func_o_1_qfbk & UD1_shift_out588_0;
 
--RC1_alu_func_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_1 at LC_X13_Y15_N5
--operation mode is normal
 
RC1_alu_func_o_1 = DFFEAS(UD1_shift_out588, GLOBAL(E1__clk0), VCC, , , ZC1_alu_func_o_1, , !AD1_NET1640_i, VCC);
 
 
--RD1_r32_o_0_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_2 at LC_X20_Y10_N0
--operation mode is normal
 
RD1_r32_o_0_2_lut_out = !KB1_r32_o_2;
RD1_r32_o_0_2 = DFFEAS(RD1_r32_o_0_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_2 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_2 at LC_X21_Y11_N0
--operation mode is normal
 
FB1_res_7_0_0_2 = CD1_res_7_0_0_0_0 # CD1_res_7_0_0_o3_0 & ED1_r32_o_0;
 
--FB1_r32_o_0_2 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_2 at LC_X21_Y11_N0
--operation mode is normal
 
FB1_r32_o_0_2 = DFFEAS(FB1_res_7_0_0_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[2] at LC_X20_Y10_N5
--operation mode is normal
 
PD1_a_o_3_d[2] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_2 # !PD1_un6_a_o & !PD1_a_o_3_d_a[2] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[2];
 
 
--FB1_res_7_0_0_1 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_1 at LC_X22_Y11_N3
--operation mode is normal
 
FB1_res_7_0_0_1 = CD1_res_7_0_0_a2_0 & ED1_r32_o_1 # ED1_r32_o_7 & CD1_res_7_0_0_0_a_0 # !CD1_res_7_0_0_a2_0 & ED1_r32_o_7 & CD1_res_7_0_0_0_a_0;
 
--FB1_r32_o_0_1 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_1 at LC_X22_Y11_N3
--operation mode is normal
 
FB1_r32_o_0_1 = DFFEAS(FB1_res_7_0_0_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_1 at LC_X20_Y9_N0
--operation mode is normal
 
KB1_r32_o_1_lut_out = DD1_pc_next_0_iv_1_1 # DD1_un1_pc_next46_0 & DD1_un1_pc_add1;
KB1_r32_o_1 = DFFEAS(KB1_r32_o_1_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[1] at LC_X20_Y9_N2
--operation mode is normal
 
PD1_a_o_3_d[1] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_1 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[1] # !PD1_un6_a_o & !PD1_a_o_3_d_a[1];
 
 
--FB1_res_7_0_0_0_d0 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_0_d0 at LC_X21_Y11_N7
--operation mode is normal
 
FB1_res_7_0_0_0_d0 = CD1_res_7_0_0_0_a_0 & ED1_r32_o_6 # CD1_res_7_0_0_a2_0 & ED1_r32_o_0 # !CD1_res_7_0_0_0_a_0 & CD1_res_7_0_0_a2_0 & ED1_r32_o_0;
 
--FB1_r32_o_0_0 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_0 at LC_X21_Y11_N7
--operation mode is normal
 
FB1_r32_o_0_0 = DFFEAS(FB1_res_7_0_0_0_d0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_0 at LC_X27_Y10_N6
--operation mode is normal
 
KB1_r32_o_0_lut_out = DD1_pc_next_0_iv_1_0 # DD1_un1_pc_next46_0 & DD1_un1_pc_add0;
KB1_r32_o_0 = DFFEAS(KB1_r32_o_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[0] at LC_X20_Y14_N2
--operation mode is normal
 
PD1_a_o_3_d[0] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_0 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[0] # !PD1_un6_a_o & !PD1_a_o_3_d_a[0];
 
 
--UD1_shift_out_79[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[11] at LC_X13_Y16_N7
--operation mode is normal
 
UD1_shift_out_79[11] = PD1_a_o_1 & UD1_shift_out_79_a[11] & VD1_b_o_iv_21 # !UD1_shift_out_79_a[11] & VD1_b_o_iv_22 # !PD1_a_o_1 & !UD1_shift_out_79_a[11];
 
 
--UD1_shift_out_79[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[15] at LC_X15_Y18_N7
--operation mode is normal
 
UD1_shift_out_79[15] = PD1_a_o_1 & UD1_shift_out_79_a[15] & VD1_b_o_iv_25 # !UD1_shift_out_79_a[15] & VD1_b_o_iv_26 # !PD1_a_o_1 & !UD1_shift_out_79_a[15];
 
 
--UD1_shift_out_74_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[7] at LC_X21_Y17_N9
--operation mode is normal
 
UD1_shift_out_74_a[7] = PD1_a_o_3 & !VD1_b_o_iv_31 # !PD1_a_o_3 & !PD1_a_o_2;
 
 
--UD1_shift_out_79[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[19] at LC_X14_Y10_N2
--operation mode is normal
 
UD1_shift_out_79[19] = PD1_a_o_1 & UD1_shift_out_79_a[19] & VD1_b_o_iv_29 # !UD1_shift_out_79_a[19] & VD1_b_o_iv_30 # !PD1_a_o_1 & !UD1_shift_out_79_a[19];
 
 
--UD1_shift_out_sn_m25_0_o2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0_o2 at LC_X16_Y13_N4
--operation mode is normal
 
UD1_shift_out_sn_m25_0_o2 = PD1_a_o_2 # PD1_a_o_3;
 
 
--UD1_shift_out_sn_b10_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_b10_0 at LC_X20_Y13_N9
--operation mode is normal
 
UD1_shift_out_sn_b10_0 = !UD1_shift_out588 & !UD1_shift_out587 # !PD1_a_o_3;
 
 
--UD1_shift_out_79[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[7] at LC_X15_Y17_N2
--operation mode is normal
 
UD1_shift_out_79[7] = PD1_a_o_1 & UD1_shift_out_79_a[7] & VD1_b_o_iv_17 # !UD1_shift_out_79_a[7] & VD1_b_o_iv_18 # !PD1_a_o_1 & !UD1_shift_out_79_a[7];
 
 
--UD1_shift_out_76_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[7] at LC_X15_Y12_N4
--operation mode is normal
 
UD1_shift_out_76_a[7] = PD1_a_o_2 & !PD1_a_o_3 # !PD1_a_o_2 & UD1_shift_out_39[19] & !PD1_a_o_1;
 
 
--VD1_hilo25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo25 at LC_X8_Y14_N1
--operation mode is normal
 
VD1_hilo25 = RC1_alu_func_o_3 & !TD1_alu_out_7_0_0_o3_0 & RC1_alu_func_o_4;
 
 
--VD1_hilo_37_iv_0[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[7] at LC_X4_Y16_N0
--operation mode is normal
 
VD1_hilo_37_iv_0[7] = VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_8 # !VD1_hilo_37_iv_0_a[7] # !VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_8;
 
 
--VD1_hilo_8_Z[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[7] at LC_X9_Y11_N8
--operation mode is normal
 
VD1_hilo_8_Z[7] = RC1_alu_func_o_0 & VD1_hilo_7 # !RC1_alu_func_o_0 & PD1_a_o_7;
 
 
--VD1_hilo_37_iv_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[7] at LC_X9_Y11_N2
--operation mode is normal
 
VD1_hilo_37_iv_a[7] = VD1_hilo_6 & !VD1_hilo_2_sqmuxa & !PD1_a_o_7 # !VD1_addnop2109_0_a2 # !VD1_hilo_6 & !PD1_a_o_7 # !VD1_addnop2109_0_a2;
 
 
--VD1_hilo_37_iv_0_5[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[39] at LC_X7_Y3_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_5[39] = VD1_hilo_40 & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add8 # !VD1_hilo_40 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add8;
 
 
--VD1_hilo_37_iv_0_4[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[39] at LC_X7_Y7_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_4[39] = VD1_hilo_37_iv_0_4_a[39] # VD1_hilo_37_iv_0_1[39] # !VD1_un59_hilo_add8 & VD1_hilo_37_iv_0_a6_1_0[40];
 
 
--VD1_hilo_37_iv_0_a[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[39] at LC_X3_Y7_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_a[39] = VD1_hilo_24_add7 & !PD1_a_o_7 & VD1_hilo_37_iv_0_a3_1[0] # !VD1_hilo_24_add7 & VD1_hilo_2_sqmuxa # !PD1_a_o_7 & VD1_hilo_37_iv_0_a3_1[0];
 
 
--VD1_hilo_37_iv_0_a2[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2[39] at LC_X7_Y7_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_a2[39] = VD1_hilo_37_iv_0_o3[34] & VD1_addnop2109_0_a2;
 
 
--PD1_a_o_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[7] at LC_X23_Y4_N2
--operation mode is normal
 
PD1_a_o_a[7] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_7 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_7;
 
 
--PD1_a_o_3_Z[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[7] at LC_X19_Y9_N7
--operation mode is normal
 
SD1_r32_o_7_qfbk = SD1_r32_o_7;
PD1_a_o_3_Z[7] = PD1_a_o_3_s[0] & SD1_r32_o_7_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[7];
 
--SD1_r32_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_7 at LC_X19_Y9_N7
--operation mode is normal
 
SD1_r32_o_7 = DFFEAS(PD1_a_o_3_Z[7], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_7, , , VCC);
 
 
--TD1_m5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m5 at LC_X5_Y14_N9
--operation mode is normal
 
TD1_m5 = !RC1_alu_func_o_0 & TD1_alu_out_sn_m14_0_0;
 
 
--TD1_un1_b_1_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[7] at LC_X12_Y15_N5
--operation mode is normal
 
TD1_un1_b_1_combout[7] = VD1_b_o_iv_7 $ (!TD1_sum13_0_a2);
 
 
--ED1_r32_o_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_11 at LC_X23_Y17_N4
--operation mode is normal
 
ED1_r32_o_11_lut_out = HE1_q_a[3];
ED1_r32_o_11 = DFFEAS(ED1_r32_o_11_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--TB1_dout_1_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_4 at LC_X27_Y13_N8
--operation mode is normal
 
TB1_dout_1_4 = TB1_dout22 & CB1_dout_2_4 # !TB1_dout22 & TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & CB1_dout_2_20;
 
 
--AD1_CurrState_Sreg0_i[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_i[0] at LC_X30_Y17_N2
--operation mode is normal
 
AD1_CurrState_Sreg0_i[0]_lut_out = !AD1_CurrState_Sreg0[2] & AD1_CurrState_Sreg0_ns_0_i_o2[0] # !sys_rst;
AD1_CurrState_Sreg0_i[0] = DFFEAS(AD1_CurrState_Sreg0_i[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AD1_CurrState_Sreg0[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[7] at LC_X30_Y16_N2
--operation mode is normal
 
AD1_CurrState_Sreg0[7]_lut_out = AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & WB35L1 & !WB45L1 & WB55L1;
AD1_CurrState_Sreg0[7] = DFFEAS(AD1_CurrState_Sreg0[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--AD1_CurrState_Sreg0[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[2] at LC_X30_Y16_N6
--operation mode is normal
 
AD1_CurrState_Sreg0[2]_lut_out = AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & !WB35L1 & WB45L1 & !WB55L1;
AD1_CurrState_Sreg0[2] = DFFEAS(AD1_CurrState_Sreg0[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--YB1_alu_func_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1 at LC_X27_Y16_N0
--operation mode is normal
 
YB1_alu_func_2_0_0_1 = YB1_alu_func_2_0_0_a3_1[1] # YB1_alu_func_2_0_0_3_Z[1] # WB83L1 & YB1_alu_func_2_0_0_a2_3[1];
 
 
--YB1_un1_muxa_ctl370_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_x at LC_X27_Y19_N9
--operation mode is normal
 
YB1_un1_muxa_ctl370_x = YB1_un1_muxa_ctl370_5 # YB1_un1_muxa_ctl370_6;
 
 
--YB1_un1_ins_i_22_1_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_1_x at LC_X28_Y18_N2
--operation mode is normal
 
YB1_un1_ins_i_22_1_x = !KE1_q_a[6] & KE1_q_a[7] & YB1_un1_ins_i_22_1_a;
 
 
--WB83L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_1_|lpm_latch:U1|q[0]~56 at LC_X27_Y16_N1
--operation mode is normal
 
WB83L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB83L1;
 
--ZC1_alu_func_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_1 at LC_X27_Y16_N1
--operation mode is normal
 
ZC1_alu_func_o_1 = DFFEAS(WB83L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_a3_0_o2_0 at LC_X30_Y16_N1
--operation mode is normal
 
AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 = AD1_CurrState_Sreg0[1] # AD1_CurrState_Sreg0[8];
 
 
--YB1_alu_func_2_0_0_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_4 at LC_X27_Y16_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_4 = YB1_alu_func_2_0_0_2[4] # YB1_alu_func_2_0_0_a2_3[1] & WB14L1 # !YB1_alu_func_2_0_0_a[4];
 
 
--WB14L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_4_|lpm_latch:U1|q[0]~56 at LC_X27_Y16_N4
--operation mode is normal
 
WB14L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_4 # !YB1_un1_muxa_ctl370_x & WB14L1;
 
--ZC1_alu_func_o_4 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_4 at LC_X27_Y16_N4
--operation mode is normal
 
ZC1_alu_func_o_4 = DFFEAS(WB14L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_alu_func_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0 at LC_X26_Y18_N8
--operation mode is normal
 
YB1_alu_func_2_0_0_0 = YB1_alu_func_2_0_0_a3_0[0] # YB1_alu_func_2_0_0_2_x[0] # YB1_alu_func_2_0_0_a3[0] # !YB1_alu_func_2_0_0_a[0];
 
 
--WB73L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_func_1_0_|lpm_latch:U1|q[0]~56 at LC_X26_Y18_N9
--operation mode is normal
 
WB73L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB73L1;
 
--ZC1_alu_func_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_0 at LC_X26_Y18_N9
--operation mode is normal
 
ZC1_alu_func_o_0 = DFFEAS(WB73L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--VD1_hilo_37_iv_0_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[4] at LC_X5_Y18_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[4] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_5 & !VD1_hilo_3 # !VD1_hilo_2_sqmuxa # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_3 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[4] at LC_X5_Y18_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_0[4] = VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[4] # VD1_hilo_37_iv_0_o5[0] & VD1_hilo_4 # !VD1_hilo_37_iv_0_a3_0[0] & VD1_hilo_37_iv_0_o5[0] & VD1_hilo_4;
 
 
--VD1_hilo_37_iv_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_1[0] at LC_X8_Y10_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_1[0] = VD1_hilo25 & RC1_alu_func_o_0;
 
 
--VD1_hilo_37_iv_0_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[36] at LC_X6_Y8_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[36] = !VD1_hilo_37_iv_0_5[36] & !VD1_hilo_37_iv_0_a2_7[36] & VD1_hilo_37 # !VD1_hilo_37_iv_0_a6_0_1[40];
 
 
--QD1_b_o18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o18 at LC_X21_Y12_N3
--operation mode is normal
 
PC1_muxb_ctl_o_0_qfbk = PC1_muxb_ctl_o_0;
QD1_b_o18 = PC1_muxb_ctl_o_1 & !PC1_muxb_ctl_o_0_qfbk;
 
--PC1_muxb_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14|muxb_ctl_o_0 at LC_X21_Y12_N3
--operation mode is normal
 
PC1_muxb_ctl_o_0 = DFFEAS(QD1_b_o18, GLOBAL(E1__clk0), VCC, , , AC1_muxb_ctl_o_0, , !AD1_NET1640_i, VCC);
 
 
--QD1_un1_b_o18_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|un1_b_o18_2 at LC_X21_Y12_N6
--operation mode is normal
 
QD1_un1_b_o18_2 = PC1_muxb_ctl_o_1 & !QD1_b_o18 # !PC1_muxb_ctl_o_1 & PC1_muxb_ctl_o_0 & XD1_un32_mux_fw # !PC1_muxb_ctl_o_0 & !QD1_b_o18;
 
 
--QD1_b_o_1_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa at LC_X21_Y12_N9
--operation mode is normal
 
PC1_muxb_ctl_o_1_qfbk = PC1_muxb_ctl_o_1;
QD1_b_o_1_sqmuxa = PC1_muxb_ctl_o_0 & !PC1_muxb_ctl_o_1_qfbk & ND1_dout7;
 
--PC1_muxb_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14|muxb_ctl_o_1 at LC_X21_Y12_N9
--operation mode is normal
 
PC1_muxb_ctl_o_1 = DFFEAS(QD1_b_o_1_sqmuxa, GLOBAL(E1__clk0), VCC, , , AC1_muxb_ctl_o_1, , !AD1_NET1640_i, VCC);
 
 
--VD1_rdy_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy_0_sqmuxa at LC_X8_Y13_N3
--operation mode is normal
 
VD1_rdy_0_sqmuxa = !RC1_alu_func_o_2 & VD1_addnop2109_0_a2 & RC1_alu_func_o_3 & !RC1_alu_func_o_4;
 
 
--HB1_BUS2446_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|BUS2446_cout[2] at LC_X21_Y4_N3
--operation mode is arithmetic
 
HB1_BUS2446_cout[2]_cout_0 = KB1_r32_o_2 & KB1_r32_o_3;
HB1_BUS2446_cout[2] = CARRY(HB1_BUS2446_cout[2]_cout_0);
 
--HB1L4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|BUS2446_cout[2]~COUT1_1 at LC_X21_Y4_N3
--operation mode is arithmetic
 
HB1L4_cout_1 = KB1_r32_o_2 & KB1_r32_o_3;
HB1L4 = CARRY(HB1L4_cout_1);
 
 
--CD1_res_7_0_0_0_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_2 at LC_X21_Y11_N9
--operation mode is normal
 
ED1_r32_o_4_qfbk = ED1_r32_o_4;
CD1_res_7_0_0_0_2 = CD1_res_7_0_0_0_a_0 & ED1_r32_o_10 # CD1_res_7_0_0_a2_0 & ED1_r32_o_4_qfbk # !CD1_res_7_0_0_0_a_0 & CD1_res_7_0_0_a2_0 & ED1_r32_o_4_qfbk;
 
--ED1_r32_o_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_4 at LC_X21_Y11_N9
--operation mode is normal
 
ED1_r32_o_4 = DFFEAS(CD1_res_7_0_0_0_2, GLOBAL(E1__clk0), VCC, , C1_G_504, GE1_q_a[4], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--CD1_res_7_0_0_o3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_o3_0 at LC_X22_Y16_N7
--operation mode is normal
 
CD1_res_7_0_0_o3_0 = CD1_res_7_0_0_a2[18] # !DC1_ext_ctl_o_0 & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2;
 
 
--PD1_a_o_sn_m2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_sn_m2 at LC_X21_Y9_N0
--operation mode is normal
 
SC1_muxa_ctl_o_1_qfbk = SC1_muxa_ctl_o_1;
PD1_a_o_sn_m2 = SC1_muxa_ctl_o_1_qfbk & WD1_un14_mux_fw # WD1_un1_mux_fw_NE # !XC1_wb_we_o_0;
 
--SC1_muxa_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_1 at LC_X21_Y9_N0
--operation mode is normal
 
SC1_muxa_ctl_o_1 = DFFEAS(PD1_a_o_sn_m2, GLOBAL(E1__clk0), VCC, , , GC1_muxa_ctl_o_1, , !AD1_NET1640_i, VCC);
 
 
--PD1_a_o_3_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[4] at LC_X16_Y11_N3
--operation mode is normal
 
PD1_a_o_3_d_a[4] = PD1_a_o_sn_m2 & !PB1_r32_o_4 # !PD1_a_o_sn_m2 & !AB1_r32_o_2;
 
 
--PD1_un6_a_o is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o at LC_X25_Y9_N5
--operation mode is normal
 
PD1_un6_a_o = PD1_un6_a_o_a & WD1_un14_mux_fw # WD1_un1_mux_fw_NE # !XC1_wb_we_o_0;
 
 
--RD1_r32_o_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_3 at LC_X23_Y4_N3
--operation mode is arithmetic
 
RD1_r32_o_3_lut_out = KB1_r32_o_2 $ KB1_r32_o_3;
RD1_r32_o_3 = DFFEAS(RD1_r32_o_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[3] at LC_X23_Y4_N3
--operation mode is arithmetic
 
RD1_r32_o_cout[3]_cout_0 = KB1_r32_o_2 & KB1_r32_o_3;
RD1_r32_o_cout[3] = CARRY(RD1_r32_o_cout[3]_cout_0);
 
--RD1L76 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[3]~COUT1_11 at LC_X23_Y4_N3
--operation mode is arithmetic
 
RD1L76_cout_1 = KB1_r32_o_2 & KB1_r32_o_3;
RD1L76 = CARRY(RD1L76_cout_1);
 
 
--FB1_res_7_0_0_3 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_3 at LC_X22_Y11_N2
--operation mode is normal
 
FB1_res_7_0_0_3 = ED1_r32_o_1 & CD1_res_7_0_0_o3_0 # !CD1_res_7_0_0_a_0;
 
--FB1_r32_o_0_3 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_3 at LC_X22_Y11_N2
--operation mode is normal
 
FB1_r32_o_0_3 = DFFEAS(FB1_res_7_0_0_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[3] at LC_X16_Y13_N3
--operation mode is normal
 
PD1_a_o_3_d[3] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_3 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[3] # !PD1_un6_a_o & !PD1_a_o_3_d_a[3];
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] at LC_X16_Y6_N6
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[3] = QD1_b_o18 & !QB1_r32_o_3 & QD1_un1_b_o18_2 # !FB1_r32_o_0_3 # !QD1_b_o18 & !QB1_r32_o_3 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[3] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[3] at LC_X16_Y6_N9
--operation mode is normal
 
G1_BUS15471_i_m[3] = QD1_b_o_1_sqmuxa & !FD1_wb_o_3;
 
 
--TD1_un1_b_1_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[1] at LC_X12_Y10_N3
--operation mode is normal
 
TD1_un1_b_1_combout[1] = VD1_b_o_iv_1 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_85_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[4] at LC_X16_Y16_N1
--operation mode is normal
 
UD1_shift_out_85_d_a[4] = PD1_a_o_2 & !PD1_a_o_1 & VD1_b_o_iv_0 # !PD1_a_o_2 & !VD1_b_o_iv_2;
 
 
--UD1_shift_out_87_d_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[4] at LC_X16_Y16_N7
--operation mode is normal
 
UD1_shift_out_87_d_a[4] = PD1_a_o_1 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !VD1_b_o_iv_8;
 
 
--UD1_shift_out_80[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[4] at LC_X12_Y16_N2
--operation mode is normal
 
UD1_shift_out_80[4] = PD1_a_o_2 & UD1_shift_out_80_a[4] & VD1_b_o_iv_9 # !UD1_shift_out_80_a[4] & VD1_b_o_iv_11 # !PD1_a_o_2 & !UD1_shift_out_80_a[4];
 
 
--UD1_shift_out_79[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[4] at LC_X19_Y13_N4
--operation mode is normal
 
UD1_shift_out_79[4] = PD1_a_o_1 & UD1_shift_out_79_a[4] & VD1_b_o_iv_14 # !UD1_shift_out_79_a[4] & VD1_b_o_iv_15 # !PD1_a_o_1 & !UD1_shift_out_79_a[4];
 
 
--UD1_shift_out_79[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[16] at LC_X20_Y12_N7
--operation mode is normal
 
UD1_shift_out_79[16] = PD1_a_o_1 & UD1_shift_out_79_a[16] & VD1_b_o_iv_26 # !UD1_shift_out_79_a[16] & VD1_b_o_iv_27 # !PD1_a_o_1 & !UD1_shift_out_79_a[16];
 
 
--UD1_shift_out_79[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[20] at LC_X21_Y13_N9
--operation mode is normal
 
UD1_shift_out_79[20] = PD1_a_o_1 & UD1_shift_out_79_a[20] & VD1_b_o_iv_30 # !UD1_shift_out_79_a[20] & VD1_b_o_iv_31 # !PD1_a_o_1 & !UD1_shift_out_79_a[20];
 
 
--UD1_shift_out_79[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[8] at LC_X21_Y13_N1
--operation mode is normal
 
UD1_shift_out_79[8] = PD1_a_o_1 & UD1_shift_out_79_a[8] & VD1_b_o_iv_18 # !UD1_shift_out_79_a[8] & VD1_b_o_iv_19 # !PD1_a_o_1 & !UD1_shift_out_79_a[8];
 
 
--UD1_shift_out_47[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47[0] at LC_X21_Y13_N2
--operation mode is normal
 
UD1_shift_out_47[0] = PD1_a_o_1 & !UD1_shift_out_47_a[0] # !PD1_a_o_1 & UD1_shift_out_47_a[0] & VD1_b_o_iv_20 # !UD1_shift_out_47_a[0] & VD1_b_o_iv_21;
 
 
--UD1_shift_out_74_c[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_c[4] at LC_X21_Y17_N1
--operation mode is normal
 
UD1_shift_out_74_c[4] = PD1_a_o_3 & UD1_shift_out_79[20] # PD1_a_o_2 # !PD1_a_o_3 & UD1_shift_out_47[0] & !PD1_a_o_2;
 
 
--VD1_hilo_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_6 at LC_X6_Y15_N9
--operation mode is normal
 
VD1_hilo_6_lut_out = VD1_hilo_37_iv_0_0[6] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_6 # !VD1_hilo_37_iv_0_a[6];
VD1_hilo_6 = DFFEAS(VD1_hilo_6_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_1_sqmuxa_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_1 at LC_X2_Y15_N2
--operation mode is normal
 
VD1_hilo_1_sqmuxa_1 = !VD1_count[5] & !VD1_overflow & VD1_addnop2110 & VD1_mul;
 
 
--VD1_hilo_2_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2_sqmuxa at LC_X2_Y15_N4
--operation mode is normal
 
VD1_hilo_2_sqmuxa = !VD1_count[5] & !VD1_overflow & VD1_addnop2110 & !VD1_mul;
 
 
--VD1_addnop2109_0_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2109_0_a2 at LC_X3_Y14_N8
--operation mode is normal
 
VD1_addnop2109_0_a2 = !VD1_hilo25 & VD1_rdy;
 
 
--VD1_hilo_37_iv_0_a3_1[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_1[62] at LC_X3_Y8_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_1[62] = VD1_hilo25 & !RC1_alu_func_o_0;
 
 
--VD1_un134_hilo_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[5] at LC_X4_Y16_N4
--operation mode is arithmetic
 
VD1_un134_hilo_combout[5] = VD1_hilo_5 $ (VD1_hilo_4 & !VD1_un134_hilo_cout[3]);
 
--VD1_un134_hilo_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[5] at LC_X4_Y16_N4
--operation mode is arithmetic
 
VD1_un134_hilo_cout[5] = CARRY(VD1_hilo_4 & VD1_hilo_5 & !VD1L5591);
 
 
--VD1_hilo_37_iv_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_0[0] at LC_X3_Y16_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_0[0] = VD1_add1 & VD1_hilo_3_sqmuxa;
 
 
--VD1_hilo_37_iv_0_o5[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[0] at LC_X3_Y15_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_o5[0] = VD1_hilo_37_iv_0_a3_1[0] # VD1_hilo_3_sqmuxa & !VD1_add1;
 
 
--VD1_un17_mul_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un17_mul_0 at LC_X9_Y14_N0
--operation mode is normal
 
VD1_un17_mul_0 = !RC1_alu_func_o_4 & !RC1_alu_func_o_2 & RC1_alu_func_o_3;
 
--VD1_start is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|start at LC_X9_Y14_N0
--operation mode is normal
 
VD1_start = DFFEAS(VD1_un17_mul_0, GLOBAL(E1__clk0), VCC, , VD1_mul_0_sqmuxa_i, , , , );
 
 
--C1_G_505_a is mips_sys:isys|G_505_a at LC_X3_Y14_N4
--operation mode is normal
 
C1_G_505_a = !VD1_hilo25 & !VD1_rdy & VD1_hilo_4_sqmuxa_0 # !VD1_start;
 
 
--VD1_sub_or_yn is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn at LC_X3_Y14_N7
--operation mode is normal
 
VD1_sub_or_yn_lut_out = C1_I_437_a_x & VD1_mul & VD1_hilo[0] # !VD1_mul & !VD1_eqop2_2_32;
VD1_sub_or_yn = DFFEAS(VD1_sub_or_yn_lut_out, GLOBAL(E1__clk0), VCC, , VD1_sub_or_yn_0_sqmuxa_1_i, , , , );
 
 
--VD1_hilo_37_iv_0_a2_7_2_1[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7_2_1[37] at LC_X6_Y8_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_7_2_1[37] = VD1_hilo[0] & VD1_sign;
 
 
--VD1_un50_hilo_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add6 at LC_X10_Y4_N0
--operation mode is arithmetic
 
VD1_un50_hilo_add6_carry_eqn = VD1_un50_hilo_carry_5;
VD1_un50_hilo_add6 = VD1_hilo_38 $ VD1_nop2_reged[6] $ !VD1_un50_hilo_add6_carry_eqn;
 
--VD1_un50_hilo_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_6 at LC_X10_Y4_N0
--operation mode is arithmetic
 
VD1_un50_hilo_carry_6_cout_0 = VD1_hilo_38 & VD1_nop2_reged[6] # !VD1_un50_hilo_carry_5 # !VD1_hilo_38 & VD1_nop2_reged[6] & !VD1_un50_hilo_carry_5;
VD1_un50_hilo_carry_6 = CARRY(VD1_un50_hilo_carry_6_cout_0);
 
--VD1L4171 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_6~COUT1_1 at LC_X10_Y4_N0
--operation mode is arithmetic
 
VD1L4171_cout_1 = VD1_hilo_38 & VD1_nop2_reged[6] # !VD1_un50_hilo_carry_5 # !VD1_hilo_38 & VD1_nop2_reged[6] & !VD1_un50_hilo_carry_5;
VD1L4171 = CARRY(VD1L4171_cout_1);
 
 
--VD1_un59_hilo_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add6 at LC_X9_Y5_N0
--operation mode is arithmetic
 
VD1_un59_hilo_add6_carry_eqn = VD1_un59_hilo_carry_5;
VD1_un59_hilo_add6 = VD1_hilo_38 $ VD1_op2_reged[6] $ !VD1_un59_hilo_add6_carry_eqn;
 
--VD1_un59_hilo_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_6 at LC_X9_Y5_N0
--operation mode is arithmetic
 
VD1_un59_hilo_carry_6_cout_0 = VD1_hilo_38 & VD1_op2_reged[6] # !VD1_un59_hilo_carry_5 # !VD1_hilo_38 & VD1_op2_reged[6] & !VD1_un59_hilo_carry_5;
VD1_un59_hilo_carry_6 = CARRY(VD1_un59_hilo_carry_6_cout_0);
 
--VD1L7381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_6~COUT1_1 at LC_X9_Y5_N0
--operation mode is arithmetic
 
VD1L7381_cout_1 = VD1_hilo_38 & VD1_op2_reged[6] # !VD1_un59_hilo_carry_5 # !VD1_hilo_38 & VD1_op2_reged[6] & !VD1_un59_hilo_carry_5;
VD1L7381 = CARRY(VD1L7381_cout_1);
 
 
--VD1_hilo_37_iv_0_1[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[37] at LC_X5_Y6_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_1[37] = VD1_hilo_37_iv_0_1_a[37] # !VD1_un59_hilo_add5 & VD1_hilo_37_iv_0_a2_7[34] & VD1_addop2;
 
 
--VD1_hilo_37_iv_0_a6_1_0[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_1_0[40] at LC_X4_Y7_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_a6_1_0[40] = VD1_hilo_1_sqmuxa_1 & VD1_hilo[0] & !VD1_sign # !VD1_hilo[0] & VD1_sub_or_yn & VD1_sign;
 
 
--VD1_hilo_37_iv_0_5_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[37] at LC_X6_Y5_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_5_a[37] = VD1_un50_hilo_add5 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add5 # !VD1_un50_hilo_add5 & VD1_hilo_37_iv_0_a2_6_0[37] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add5;
 
 
--VD1_hilo_38 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_38 at LC_X7_Y7_N7
--operation mode is normal
 
VD1_hilo_38_lut_out = !VD1_hilo_37_iv_0_a[38] & !VD1_hilo_37_iv_0_4[38] & !VD1_hilo_37_iv_0_a2[39] & !VD1_hilo_37_iv_0_5[38];
VD1_hilo_38 = DFFEAS(VD1_hilo_38_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_37_iv_0_a6_0_1[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_0_1[40] at LC_X6_Y8_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a6_0_1[40] = VD1_hilo_1_sqmuxa_1 & VD1_hilo[0] $ (!VD1_sign # !VD1_sub_or_yn);
 
 
--VD1_hilo_37_iv_0_o3[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[34] at LC_X8_Y13_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_o3[34] = VD1_un29_sign_0_o2_0 # !RC1_alu_func_o_3 # !PD1_a_o_31 # !RC1_alu_func_o_1;
 
 
--ED1_r32_o_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_5 at LC_X21_Y18_N3
--operation mode is normal
 
ED1_r32_o_5_lut_out = GE1_q_a[5];
ED1_r32_o_5 = DFFEAS(ED1_r32_o_5_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--CD1_res_7_0_0_a2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2_0 at LC_X22_Y16_N5
--operation mode is normal
 
CD1_res_7_0_0_a2_0 = !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0 $ DC1_ext_ctl_o_1;
 
 
--PD1_a_o_3_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[5] at LC_X20_Y11_N0
--operation mode is normal
 
PD1_a_o_3_d_a[5] = PD1_a_o_sn_m2 & !PB1_r32_o_5 # !PD1_a_o_sn_m2 & !AB1_r32_o_3;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] at LC_X15_Y4_N8
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[7] = QD1_b_o18 & !QB1_r32_o_7 & QD1_un1_b_o18_2 # !FB1_r32_o_0_7 # !QD1_b_o18 & !QB1_r32_o_7 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[7] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[7] at LC_X15_Y4_N9
--operation mode is normal
 
G1_BUS15471_i_m[7] = !FD1_wb_o_7 & QD1_b_o_1_sqmuxa;
 
 
--UD1_shift_out_87_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[5] at LC_X15_Y19_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[5] = PD1_a_o_1 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !VD1_b_o_iv_9;
 
 
--UD1_shift_out_80[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[5] at LC_X15_Y19_N7
--operation mode is normal
 
UD1_shift_out_80[5] = UD1_shift_out_80_a[5] & PD1_a_o_2 & VD1_b_o_iv_10 # !UD1_shift_out_80_a[5] & VD1_b_o_iv_12 # !PD1_a_o_2;
 
 
--UD1_shift_out_85_d_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[5] at LC_X14_Y18_N2
--operation mode is normal
 
UD1_shift_out_85_d_a[5] = PD1_a_o_0 & !VD1_b_o_iv_0 # !PD1_a_o_0 & !VD1_b_o_iv_1;
 
 
--UD1_shift_out_68[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[5] at LC_X15_Y19_N4
--operation mode is normal
 
UD1_shift_out_68[5] = PD1_a_o_0 & VD1_b_o_iv_2 # !PD1_a_o_0 & VD1_b_o_iv_3;
 
 
--UD1_shift_out_79[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[5] at LC_X14_Y13_N4
--operation mode is normal
 
UD1_shift_out_79[5] = UD1_shift_out_79_a[5] & PD1_a_o_1 & VD1_b_o_iv_15 # !UD1_shift_out_79_a[5] & VD1_b_o_iv_16 # !PD1_a_o_1;
 
 
--UD1_shift_out_79[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[17] at LC_X15_Y13_N2
--operation mode is normal
 
UD1_shift_out_79[17] = PD1_a_o_1 & UD1_shift_out_79_a[17] & VD1_b_o_iv_27 # !UD1_shift_out_79_a[17] & VD1_b_o_iv_28 # !PD1_a_o_1 & !UD1_shift_out_79_a[17];
 
 
--UD1_shift_out_42[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_42[1] at LC_X15_Y14_N3
--operation mode is normal
 
UD1_shift_out_42[1] = PD1_a_o_1 & !PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_1 & UD1_shift_out_39[17];
 
 
--UD1_shift_out_79[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[9] at LC_X21_Y16_N8
--operation mode is normal
 
UD1_shift_out_79[9] = PD1_a_o_1 & UD1_shift_out_79_a[9] & VD1_b_o_iv_19 # !UD1_shift_out_79_a[9] & VD1_b_o_iv_20 # !PD1_a_o_1 & !UD1_shift_out_79_a[9];
 
 
--UD1_shift_out_79[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[13] at LC_X21_Y14_N5
--operation mode is normal
 
UD1_shift_out_79[13] = PD1_a_o_1 & UD1_shift_out_79_a[13] & VD1_b_o_iv_23 # !UD1_shift_out_79_a[13] & VD1_b_o_iv_24 # !PD1_a_o_1 & !UD1_shift_out_79_a[13];
 
 
--UD1_shift_out_74_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[5] at LC_X15_Y14_N7
--operation mode is normal
 
UD1_shift_out_74_a[5] = PD1_a_o_2 & !VD1_b_o_iv_31 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !UD1_shift_out_39[17];
 
 
--UD1_shift_out_61[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_61[5] at LC_X15_Y14_N4
--operation mode is normal
 
UD1_shift_out_61[5] = PD1_a_o_2 & UD1_shift_out_79[17] # !PD1_a_o_2 & UD1_shift_out_79[13];
 
 
--YB1_un1_ins_i_15_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_15_x at LC_X24_Y18_N3
--operation mode is normal
 
YB1_un1_ins_i_15_x = !KE1_q_a[4] & KE1_q_a[2] & YB1_un1_ins_i_18_0_0_a2_x;
 
 
--YB1_dmem_ctl_2_0_0_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_2 at LC_X28_Y18_N4
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_2 = YB1_dmem_ctl_2_0_0_a3[2] # YB1_dmem_ctl_2_0_0_a[2] & !KE1_q_a[5] & !KE1_q_a[6];
 
 
--WB84L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~68 at LC_X24_Y18_N2
--operation mode is normal
 
WB84L1 = YB1_un1_ins_i_15_x # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_2 # !YB1_un1_muxa_ctl370_x & WB84L2;
 
 
--YB1_un1_ins_i_18_m_0_0_a3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_m_0_0_a3 at LC_X24_Y18_N8
--operation mode is normal
 
YB1_un1_ins_i_18_m_0_0_a3 = !KE1_q_a[6] & !KE1_q_a[2] & KE1_q_a[7] & !YB1_un1_ins_i_18_m_0_0_a3_a_x;
 
 
--WB84L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1|q[0]~69 at LC_X24_Y18_N1
--operation mode is normal
 
WB84L2 = !YB1_un1_ins_i_18_m_0_0_a3 & WB84L1;
 
--CC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_2 at LC_X24_Y18_N1
--operation mode is normal
 
CC1_dmem_ctl_o_2 = DFFEAS(WB84L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] at LC_X20_Y16_N4
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[0] = QD1_un1_b_o18_2 & !FB1_r32_o_0_0 & QD1_b_o18 # !QB1_r32_o_0 # !QD1_un1_b_o18_2 & !FB1_r32_o_0_0 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[0] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[0] at LC_X20_Y16_N5
--operation mode is normal
 
G1_BUS15471_i_m[0] = QD1_b_o_1_sqmuxa & !FD1_wb_o_0;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] at LC_X15_Y9_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[1] = !QB1_r32_o_1 & QD1_un1_b_o18_2;
 
 
--QD1_b_o_iv_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_iv_1_0 at LC_X20_Y9_N8
--operation mode is normal
 
QD1_b_o_iv_1_0 = FD1_wb_o_1 & !RB1_byte_addr_o_1 & QD1_b_o_0_sqmuxa # !FD1_wb_o_1 & QD1_b_o_1_sqmuxa # !RB1_byte_addr_o_1 & QD1_b_o_0_sqmuxa;
 
 
--UD1_shift_out_80_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[2] at LC_X12_Y16_N3
--operation mode is normal
 
UD1_shift_out_80_a[2] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_5 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_3;
 
 
--UD1_shift_out_82_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[2] at LC_X11_Y19_N6
--operation mode is normal
 
UD1_shift_out_82_a[2] = PD1_a_o_2 & !VD1_b_o_iv_6 # !PD1_a_o_2 & !VD1_b_o_iv_4;
 
 
--UD1_shift_out_79[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[6] at LC_X19_Y18_N4
--operation mode is normal
 
UD1_shift_out_79[6] = PD1_a_o_1 & UD1_shift_out_79_a[6] & VD1_b_o_iv_16 # !UD1_shift_out_79_a[6] & VD1_b_o_iv_17 # !PD1_a_o_1 & !UD1_shift_out_79_a[6];
 
 
--UD1_shift_out_79[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[10] at LC_X13_Y16_N2
--operation mode is normal
 
UD1_shift_out_79[10] = PD1_a_o_1 & UD1_shift_out_79_a[10] & VD1_b_o_iv_20 # !UD1_shift_out_79_a[10] & VD1_b_o_iv_21 # !PD1_a_o_1 & !UD1_shift_out_79_a[10];
 
 
--UD1_shift_out_41[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_41[2] at LC_X13_Y17_N1
--operation mode is normal
 
UD1_shift_out_41[2] = PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & VD1_b_o_iv_30;
 
 
--UD1_shift_out_79[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[18] at LC_X19_Y14_N4
--operation mode is normal
 
UD1_shift_out_79[18] = UD1_shift_out_79_a[18] & VD1_b_o_iv_28 & PD1_a_o_1 # !UD1_shift_out_79_a[18] & VD1_b_o_iv_29 # !PD1_a_o_1;
 
 
--UD1_shift_out_74_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[2] at LC_X19_Y16_N7
--operation mode is normal
 
UD1_shift_out_74_a[2] = PD1_a_o_2 & !UD1_shift_out_47[2] & !PD1_a_o_3 # !PD1_a_o_2 & PD1_a_o_3 # !UD1_shift_out_79[10];
 
 
--UD1_shift_out_79[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[2] at LC_X20_Y15_N5
--operation mode is normal
 
UD1_shift_out_79[2] = UD1_shift_out_79_a[2] & VD1_b_o_iv_12 & PD1_a_o_1 # !UD1_shift_out_79_a[2] & VD1_b_o_iv_13 # !PD1_a_o_1;
 
 
--UD1_shift_out_76_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[2] at LC_X19_Y17_N4
--operation mode is normal
 
UD1_shift_out_76_a[2] = PD1_a_o_3 & UD1_shift_out_39[18] & !PD1_a_o_1 # !PD1_a_o_3 & UD1_shift_out_47[2];
 
 
--VD1_hilo_37_iv_0_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[2] at LC_X5_Y17_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[2] = VD1_hilo_1 & !VD1_hilo_2_sqmuxa & !VD1_hilo_3 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_1 & !VD1_hilo_3 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[2] at LC_X5_Y17_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_0[2] = VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[2] # VD1_hilo_37_iv_0_o5[0] & VD1_hilo_2 # !VD1_hilo_37_iv_0_a3_0[0] & VD1_hilo_37_iv_0_o5[0] & VD1_hilo_2;
 
 
--VD1_hilo_37_iv_0_o3_0[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0[34] at LC_X8_Y5_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_0[34] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add3 # !VD1_hilo_24_add2 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add3;
 
 
--VD1_hilo_37_iv_0_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[34] at LC_X6_Y7_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_a[34] = !VD1_hilo_37_iv_0_o3_1[34] & !VD1_hilo_37_iv_0_2[34] & !VD1_hilo_37_iv_0_o3[34] # !VD1_addnop2109_0_a2;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] at LC_X15_Y10_N9
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[2] = QB1_r32_o_2 & QD1_b_o18 & !FB1_r32_o_0_2 # !QB1_r32_o_2 & QD1_un1_b_o18_2 # QD1_b_o18 & !FB1_r32_o_0_2;
 
 
--G1_BUS15471_i_m[2] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[2] at LC_X15_Y10_N6
--operation mode is normal
 
G1_BUS15471_i_m[2] = !FD1_wb_o_2 & QD1_b_o_1_sqmuxa;
 
 
--VD1_hilo_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3 at LC_X6_Y16_N9
--operation mode is normal
 
VD1_hilo_3_lut_out = VD1_hilo_37_iv_0[3] # VD1_hilo25 & VD1_hilo_8_Z[3] # !VD1_hilo_37_iv_a[3];
VD1_hilo_3 = DFFEAS(VD1_hilo_3_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_35 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_35 at LC_X5_Y8_N8
--operation mode is normal
 
VD1_hilo_35_lut_out = !VD1_hilo_37_iv_2[35] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[35] # !VD1_hilo25;
VD1_hilo_35 = DFFEAS(VD1_hilo_35_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--UD1_shift_out_82_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[3] at LC_X12_Y15_N6
--operation mode is normal
 
UD1_shift_out_82_a[3] = PD1_a_o_2 & !VD1_b_o_iv_7 # !PD1_a_o_2 & !VD1_b_o_iv_5;
 
 
--UD1_shift_out_80[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[3] at LC_X13_Y19_N4
--operation mode is normal
 
UD1_shift_out_80[3] = PD1_a_o_2 & UD1_shift_out_80_a[3] & VD1_b_o_iv_8 # !UD1_shift_out_80_a[3] & VD1_b_o_iv_10 # !PD1_a_o_2 & !UD1_shift_out_80_a[3];
 
 
--UD1_shift_out_81[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_81[3] at LC_X13_Y19_N2
--operation mode is normal
 
UD1_shift_out_81[3] = PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_1 & VD1_b_o_iv_2;
 
 
--UD1_shift_out_91_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[3] at LC_X16_Y18_N1
--operation mode is normal
 
UD1_shift_out_91_a[3] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_3 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[3];
 
 
--UD1_shift_out_76[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[3] at LC_X15_Y15_N9
--operation mode is normal
 
UD1_shift_out_76[3] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_76_a[3] # !PD1_a_o_2 & UD1_shift_out_79[19];
 
 
--UD1_shift_out_86_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[3] at LC_X15_Y17_N3
--operation mode is normal
 
UD1_shift_out_86_a[3] = PD1_a_o_2 & !UD1_shift_out_79[7] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[11] # !UD1_shift_out587 & !UD1_shift_out_79[7];
 
 
--UD1_shift_out_74[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[3] at LC_X15_Y15_N1
--operation mode is normal
 
UD1_shift_out_74[3] = PD1_a_o_2 & UD1_shift_out_74_c[3] & VD1_b_o_iv_31 # !UD1_shift_out_74_c[3] & UD1_shift_out_79[15] # !PD1_a_o_2 & UD1_shift_out_74_c[3];
 
 
--YB1_un1_ins_i_20 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_20 at LC_X24_Y18_N6
--operation mode is normal
 
YB1_un1_ins_i_20 = !KE1_q_a[4] & YB1_un1_ins_i_18_0_0_a2_x & KE1_q_a[2] # !KE1_q_a[3];
 
 
--YB1_dmem_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_0 at LC_X28_Y15_N8
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_0 = YB1_alu_func_2_0_0_a3_1_x[4] # WB64L2 & YB1_fsm_dly_2_0_0_o2_x[2] & YB1_alu_func_2_0_0_a2_0[1];
 
 
--WB64L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~68 at LC_X28_Y15_N0
--operation mode is normal
 
WB64L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB64L2;
 
 
--YB1_un1_ins_i_23_2_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_23_2_0 at LC_X28_Y18_N7
--operation mode is normal
 
YB1_un1_ins_i_23_2_0 = KE1_q_a[3] & YB1_un1_ins_i_23_2_0_a_x & KE1_q_a[5] # KE1_q_a[4];
 
 
--WB64L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1|q[0]~69 at LC_X28_Y15_N1
--operation mode is normal
 
WB64L2 = !YB1_un1_ins_i_23_2_0 & WB64L1;
 
--CC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_0 at LC_X28_Y15_N1
--operation mode is normal
 
CC1_dmem_ctl_o_0 = DFFEAS(WB64L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_muxa_ctl373 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl373 at LC_X29_Y18_N0
--operation mode is normal
 
YB1_muxa_ctl373 = !KE1_q_a[4] & !KE1_q_a[3] & !KE1_q_a[6] & !YB1_muxa_ctl373_a_x;
 
 
--YB1_dmem_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1 at LC_X29_Y18_N3
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_1 = YB1_dmem_ctl_2_0_0_1_Z[1] # YB1_alu_func_2_0_0_a2_0[1] & !YB1_dmem_ctl_2_0_0_a_x[1] & WB74L2;
 
 
--WB74L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~68 at LC_X29_Y18_N1
--operation mode is normal
 
WB74L1 = YB1_muxa_ctl373 # YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB74L2;
 
 
--YB1_un1_ins_i_22_u_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_u_x at LC_X29_Y18_N4
--operation mode is normal
 
YB1_un1_ins_i_22_u_x = YB1_un1_ins_i_22_1_x & KE1_q_a[3] # !KE1_q_a[2];
 
 
--WB74L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1|q[0]~69 at LC_X29_Y18_N2
--operation mode is normal
 
WB74L2 = !YB1_un1_ins_i_22_u_x & WB74L1;
 
--CC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_1 at LC_X29_Y18_N2
--operation mode is normal
 
CC1_dmem_ctl_o_1 = DFFEAS(WB74L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--UD1_shift_out_87[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[16] at LC_X9_Y18_N4
--operation mode is normal
 
UD1_shift_out_87[16] = PD1_a_o_0 & UD1_shift_out_87_d[16] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[16] # !PD1_a_o_2 & VD1_b_o_iv_18;
 
 
--UD1_shift_out_89_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[16] at LC_X9_Y18_N3
--operation mode is normal
 
UD1_shift_out_89_a[16] = PD1_a_o_1 & !UD1_shift_out_85_d[16] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[16] # !PD1_a_o_2 & !VD1_b_o_iv_15;
 
 
--UD1_shift_out_86_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_16 at LC_X13_Y12_N4
--operation mode is normal
 
UD1_shift_out_86_16 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[16] & UD1_shift_out_79[20] # !UD1_shift_out_sn_b9_0 & VD1_b_o_iv_31;
 
 
--UD1_shift_out_92_d_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_8 at LC_X13_Y12_N3
--operation mode is normal
 
UD1_shift_out_92_d_8 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[16] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[16];
 
 
--MD1_c_0_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[16] at LC_X11_Y9_N8
--operation mode is normal
 
MD1_c_0_a[16] = VD1_un24_res & !VD1_hilo_48 # !VD1_un24_res & !VD1_hilo_16 # !VD1_un11_res;
 
 
--TD1_m36 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m36 at LC_X11_Y9_N2
--operation mode is normal
 
TD1_m36 = TD1_m36_a & PD1_a_o_16 # !TD1_m4 # !TD1_m36_a & TD1_m7 & !PD1_a_o_16;
 
 
--TD1_m33 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m33 at LC_X11_Y9_N1
--operation mode is normal
 
TD1_m33 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add16;
 
 
--UD1_shift_out_87[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[17] at LC_X7_Y17_N8
--operation mode is normal
 
UD1_shift_out_87[17] = PD1_a_o_0 & UD1_shift_out_87_d[17] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[17] # !PD1_a_o_2 & VD1_b_o_iv_19;
 
 
--UD1_shift_out_89_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[17] at LC_X14_Y15_N7
--operation mode is normal
 
UD1_shift_out_89_a[17] = PD1_a_o_2 & !UD1_shift_out_85_d[17] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[17] # !PD1_a_o_1 & !VD1_b_o_iv_16;
 
 
--UD1_shift_out_92_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[17] at LC_X14_Y12_N2
--operation mode is normal
 
UD1_shift_out_92_a[17] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_83[17] # !UD1_shift_out_sn_b9_0 & !VD1_b_o_iv_31;
 
 
--UD1_shift_out_92_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[17] at LC_X14_Y16_N8
--operation mode is normal
 
UD1_shift_out_92_d[17] = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[17] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[17];
 
 
--MD1_c_0_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[17] at LC_X9_Y12_N9
--operation mode is normal
 
MD1_c_0_a[17] = VD1_un24_res & !VD1_hilo_49 # !VD1_un24_res & !VD1_hilo_17 # !VD1_un11_res;
 
 
--TD1_m41 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m41 at LC_X9_Y12_N8
--operation mode is normal
 
TD1_m41 = PD1_a_o_17 & TD1_m41_a # !PD1_a_o_17 & TD1_m41_a & !TD1_m4 # !TD1_m41_a & TD1_m7;
 
 
--TD1_m38 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m38 at LC_X9_Y12_N2
--operation mode is normal
 
TD1_m38 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add17;
 
 
--UD1_shift_out_87[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[14] at LC_X20_Y17_N8
--operation mode is normal
 
UD1_shift_out_87[14] = PD1_a_o_0 & UD1_shift_out_87_d[14] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[14] # !PD1_a_o_2 & VD1_b_o_iv_16;
 
 
--UD1_shift_out_89_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[14] at LC_X11_Y17_N4
--operation mode is normal
 
UD1_shift_out_89_a[14] = PD1_a_o_1 & !UD1_shift_out_85_d[14] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[14] # !PD1_a_o_2 & !VD1_b_o_iv_13;
 
 
--UD1_shift_out_86_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_14 at LC_X13_Y17_N5
--operation mode is normal
 
UD1_shift_out_86_14 = UD1_shift_out_sn_b9_0 & UD1_shift_out_83[14] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[14];
 
 
--UD1_shift_out_92_d_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_6 at LC_X12_Y17_N3
--operation mode is normal
 
UD1_shift_out_92_d_6 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[14] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[22];
 
 
--MD1_c_0_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[14] at LC_X8_Y12_N6
--operation mode is normal
 
MD1_c_0_a[14] = VD1_un24_res & !VD1_hilo_46 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_14;
 
 
--TD1_m26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m26 at LC_X9_Y12_N5
--operation mode is normal
 
TD1_m26 = PD1_a_o_14 & TD1_m26_a # !PD1_a_o_14 & TD1_m26_a & !TD1_m4 # !TD1_m26_a & TD1_m7;
 
 
--TD1_m23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m23 at LC_X8_Y12_N1
--operation mode is normal
 
TD1_m23 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add14;
 
 
--UD1_shift_out_87[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[15] at LC_X13_Y16_N4
--operation mode is normal
 
UD1_shift_out_87[15] = PD1_a_o_0 & UD1_shift_out_87_d[15] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[15] # !PD1_a_o_2 & VD1_b_o_iv_17;
 
 
--UD1_shift_out_89_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[15] at LC_X11_Y12_N4
--operation mode is normal
 
UD1_shift_out_89_a[15] = PD1_a_o_2 & !UD1_shift_out_85_d[15] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[15] # !PD1_a_o_1 & !VD1_b_o_iv_14;
 
 
--UD1_shift_out_86_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_15 at LC_X14_Y17_N7
--operation mode is normal
 
UD1_shift_out_86_15 = UD1_shift_out_sn_b9_0 & UD1_shift_out_83[15] # !UD1_shift_out_sn_b9_0 & VD1_b_o_iv_31;
 
 
--UD1_shift_out_92_d_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_7 at LC_X14_Y17_N9
--operation mode is normal
 
UD1_shift_out_92_d_7 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[15] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[23];
 
 
--MD1_c_0_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[15] at LC_X11_Y12_N1
--operation mode is normal
 
MD1_c_0_a[15] = VD1_un24_res & !VD1_hilo_47 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_15;
 
 
--TD1_m31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m31 at LC_X9_Y12_N7
--operation mode is normal
 
TD1_m31 = PD1_a_o_15 & TD1_m31_a # !PD1_a_o_15 & TD1_m31_a & !TD1_m4 # !TD1_m31_a & TD1_m7;
 
 
--TD1_m28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m28 at LC_X11_Y12_N3
--operation mode is normal
 
TD1_m28 = TD1_un1_a_add15 & TD1_alu_out_sn_m14_0_0;
 
 
--UD1_shift_out_36_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_36_0 at LC_X8_Y15_N0
--operation mode is normal
 
UD1_shift_out_36_0 = UD1_shift_out588 & VD1_b_o_iv_31;
 
 
--UD1_shift_out_85_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_27 at LC_X11_Y14_N5
--operation mode is normal
 
UD1_shift_out_85_27 = PD1_a_o_2 & UD1_shift_out_85_c[31] & UD1_shift_out_68[27] # !UD1_shift_out_85_c[31] & UD1_shift_out_68[29] # !PD1_a_o_2 & UD1_shift_out_85_c[31];
 
 
--UD1_shift_out_83[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[31] at LC_X11_Y10_N1
--operation mode is normal
 
UD1_shift_out_83[31] = VD1_b_o_iv_31 & !UD1_shift_out587;
 
 
--UD1_shift_out_92_d[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[31] at LC_X11_Y10_N4
--operation mode is normal
 
UD1_shift_out_92_d[31] = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[31] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[31];
 
 
--MD1_c_0_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[31] at LC_X11_Y10_N8
--operation mode is normal
 
MD1_c_0_a[31] = VD1_un24_res & !VD1_hilo_63 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_31;
 
 
--TD1_m101 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m101 at LC_X12_Y6_N8
--operation mode is normal
 
TD1_m101 = TD1_m101_a & TD1_m7 # !VD1_b_o_iv_31 # !TD1_m101_a & VD1_b_o_iv_31 & !TD1_m9;
 
 
--TD1_m98 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m98 at LC_X12_Y7_N7
--operation mode is normal
 
TD1_m98 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add31;
 
 
--UD1_shift_out_89_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_7 at LC_X16_Y15_N5
--operation mode is normal
 
UD1_shift_out_89_7 = UD1_shift_out586 & !UD1_shift_out_89_a[8] # !UD1_shift_out586 & UD1_shift_out_87[8];
 
 
--MD1_c_a_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_8 at LC_X16_Y15_N7
--operation mode is normal
 
MD1_c_a_8 = UD1_shift_out586 & !UD1_shift_out_92_d_0 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_0 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_8;
 
 
--MD1_c_0_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_7 at LC_X16_Y15_N3
--operation mode is normal
 
MD1_c_0_7 = RC1_alu_func_o_4 & !TD1_m16 # !RC1_alu_func_o_4 & TD1_m13 # !MD1_c_0_a[8];
 
 
--UD1_shift_out_89_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_8 at LC_X13_Y13_N9
--operation mode is normal
 
UD1_shift_out_89_8 = UD1_shift_out586 & !UD1_shift_out_89_a[9] # !UD1_shift_out586 & UD1_shift_out_87[9];
 
 
--MD1_c_a_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_9 at LC_X13_Y13_N5
--operation mode is normal
 
MD1_c_a_9 = UD1_shift_out586 & !UD1_shift_out_92_d_1 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_1 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_9;
 
 
--MD1_c_0_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_8 at LC_X13_Y13_N4
--operation mode is normal
 
MD1_c_0_8 = RC1_alu_func_o_4 & !TD1_m117 # !RC1_alu_func_o_4 & TD1_m114 # !MD1_c_0_a[9];
 
 
--MD1_c_1_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_10 at LC_X7_Y14_N4
--operation mode is normal
 
MD1_c_1_10 = TD1_alu_out_0_a2_4 # VD1_b_o_iv_10 & TD1_alu_out_0_a3_0_0 # !MD1_c_1_a[10];
 
 
--TD1_un1_a_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add10 at LC_X12_Y9_N5
--operation mode is arithmetic
 
TD1_un1_a_add10_carry_eqn = TD1_un1_a_carry_9;
TD1_un1_a_add10 = PD1_a_o_10 $ TD1_un1_b_1_combout[10] $ !TD1_un1_a_add10_carry_eqn;
 
--TD1_un1_a_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_10 at LC_X12_Y9_N5
--operation mode is arithmetic
 
TD1_un1_a_carry_10_cout_0 = PD1_a_o_10 & TD1_un1_b_1_combout[10] # !TD1_un1_a_carry_9 # !PD1_a_o_10 & TD1_un1_b_1_combout[10] & !TD1_un1_a_carry_9;
TD1_un1_a_carry_10 = CARRY(TD1_un1_a_carry_10_cout_0);
 
--TD1L035 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_10~COUT1_1 at LC_X12_Y9_N5
--operation mode is arithmetic
 
TD1L035_cout_1 = PD1_a_o_10 & TD1_un1_b_1_combout[10] # !TD1_un1_a_carry_9 # !PD1_a_o_10 & TD1_un1_b_1_combout[10] & !TD1_un1_a_carry_9;
TD1L035 = CARRY(TD1L035_cout_1);
 
 
--UD1_shift_out_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_10 at LC_X19_Y16_N2
--operation mode is normal
 
UD1_shift_out_10 = UD1_shift_out_sn_m31_i & UD1_shift_out_92[10] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[10];
 
 
--UD1_shift_out_89_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_10 at LC_X15_Y16_N9
--operation mode is normal
 
UD1_shift_out_89_10 = UD1_shift_out586 & !UD1_shift_out_89_a[11] # !UD1_shift_out586 & UD1_shift_out_87[11];
 
 
--MD1_c_a_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_11 at LC_X15_Y16_N6
--operation mode is normal
 
MD1_c_a_11 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_3 # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 & !UD1_shift_out_92_d_3 # !UD1_shift_out586 & !UD1_shift_out_86_11;
 
 
--MD1_c_0_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_10 at LC_X15_Y16_N7
--operation mode is normal
 
MD1_c_0_10 = RC1_alu_func_o_4 & !TD1_m21 # !RC1_alu_func_o_4 & TD1_m18 # !MD1_c_0_a[11];
 
 
--UD1_shift_out_87[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[21] at LC_X7_Y18_N4
--operation mode is normal
 
UD1_shift_out_87[21] = PD1_a_o_0 & UD1_shift_out_87_d[21] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[21] # !PD1_a_o_2 & VD1_b_o_iv_23;
 
 
--UD1_shift_out_89_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[21] at LC_X14_Y12_N7
--operation mode is normal
 
UD1_shift_out_89_a[21] = PD1_a_o_1 & !UD1_shift_out_85_d[21] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[21] # !PD1_a_o_2 & !VD1_b_o_iv_20;
 
 
--UD1_shift_out_92_d_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_13 at LC_X14_Y10_N6
--operation mode is normal
 
UD1_shift_out_92_d_13 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[21] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[21];
 
 
--UD1_shift_out_92_s_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_s_0 at LC_X14_Y10_N4
--operation mode is normal
 
UD1_shift_out_92_s_0 = !UD1_shift_out586 & !UD1_shift_out_sn_m25_0;
 
 
--MD1_c_0_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[21] at LC_X9_Y8_N6
--operation mode is normal
 
MD1_c_0_a[21] = VD1_un24_res & !VD1_hilo_53 # !VD1_un24_res & !VD1_hilo_21 # !VD1_un11_res;
 
 
--TD1_m132 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m132 at LC_X9_Y8_N7
--operation mode is normal
 
TD1_m132 = PD1_a_o_21 & TD1_m132_a # !PD1_a_o_21 & TD1_m132_a & !TD1_m4 # !TD1_m132_a & TD1_m7;
 
 
--TD1_m129 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m129 at LC_X9_Y8_N9
--operation mode is normal
 
TD1_m129 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add21;
 
 
--UD1_shift_out_87[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[20] at LC_X6_Y18_N4
--operation mode is normal
 
UD1_shift_out_87[20] = PD1_a_o_2 & UD1_shift_out_87_d[20] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[20] # !PD1_a_o_0 & VD1_b_o_iv_22;
 
 
--UD1_shift_out_89_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[20] at LC_X10_Y18_N4
--operation mode is normal
 
UD1_shift_out_89_a[20] = PD1_a_o_1 & !UD1_shift_out_85_d[20] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[20] # !PD1_a_o_2 & !VD1_b_o_iv_19;
 
 
--MD1_c_1_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[20] at LC_X9_Y8_N4
--operation mode is normal
 
MD1_c_1_a[20] = VD1_un11_res & !VD1_hilo_20 & !VD1_un24_res # !VD1_hilo_52 # !VD1_un11_res & !VD1_un24_res # !VD1_hilo_52;
 
 
--TD1_m56 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m56 at LC_X10_Y14_N4
--operation mode is normal
 
TD1_m56 = PD1_a_o_20 & TD1_m56_a # !PD1_a_o_20 & TD1_m56_a & !TD1_m4 # !TD1_m56_a & TD1_m7;
 
 
--TD1_m53 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m53 at LC_X10_Y14_N9
--operation mode is normal
 
TD1_m53 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add20;
 
 
--UD1_shift_out_92_d_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_12 at LC_X10_Y17_N6
--operation mode is normal
 
UD1_shift_out_92_d_12 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[20] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[20];
 
 
--UD1_shift_out_89_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_18 at LC_X14_Y8_N7
--operation mode is normal
 
UD1_shift_out_89_18 = UD1_shift_out586 & !UD1_shift_out_89_a[19] # !UD1_shift_out586 & UD1_shift_out_87[19];
 
 
--MD1_c_0_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_18 at LC_X10_Y7_N6
--operation mode is normal
 
MD1_c_0_18 = RC1_alu_func_o_4 & !TD1_m51 # !RC1_alu_func_o_4 & TD1_m48 # !MD1_c_0_a[19];
 
 
--UD1_shift_out_92_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_13 at LC_X14_Y8_N6
--operation mode is normal
 
UD1_shift_out_92_13 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & UD1_shift_out_92_a[19] # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d[19];
 
 
--UD1_shift_out_89_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_17 at LC_X10_Y16_N6
--operation mode is normal
 
UD1_shift_out_89_17 = UD1_shift_out586 & !UD1_shift_out_89_a[18] # !UD1_shift_out586 & UD1_shift_out_87[18];
 
 
--UD1_shift_out_92_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_12 at LC_X10_Y16_N1
--operation mode is normal
 
UD1_shift_out_92_12 = UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d[18] # !UD1_shift_out_sn_m25_0 & UD1_shift_out586 & UD1_shift_out_92_d[18] # !UD1_shift_out586 & !UD1_shift_out_92_a[18];
 
 
--MD1_c_0_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_17 at LC_X5_Y14_N5
--operation mode is normal
 
MD1_c_0_17 = RC1_alu_func_o_4 & !TD1_m46 # !RC1_alu_func_o_4 & TD1_m43 # !MD1_c_0_a[18];
 
 
--UD1_shift_out_89_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_25 at LC_X8_Y15_N6
--operation mode is normal
 
UD1_shift_out_89_25 = UD1_shift_out586 & UD1_shift_out_85[26] # !UD1_shift_out586 & !UD1_shift_out_89_a[26];
 
 
--MD1_c_a_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_26 at LC_X11_Y15_N6
--operation mode is normal
 
MD1_c_a_26 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_18;
 
 
--MD1_c_0_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_25 at LC_X6_Y14_N6
--operation mode is normal
 
MD1_c_0_25 = RC1_alu_func_o_4 & !TD1_m81 # !RC1_alu_func_o_4 & TD1_m78 # !MD1_c_0_a[26];
 
 
--UD1_shift_out_89_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_26 at LC_X11_Y7_N7
--operation mode is normal
 
UD1_shift_out_89_26 = UD1_shift_out586 & UD1_shift_out_85[27] # !UD1_shift_out586 & !UD1_shift_out_89_a[27];
 
 
--MD1_c_a_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_27 at LC_X12_Y13_N4
--operation mode is normal
 
MD1_c_a_27 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_19;
 
 
--MD1_c_0_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_26 at LC_X11_Y7_N5
--operation mode is normal
 
MD1_c_0_26 = RC1_alu_func_o_4 & !TD1_m86 # !RC1_alu_func_o_4 & TD1_m83 # !MD1_c_0_a[27];
 
 
--UD1_shift_out_89_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_27 at LC_X8_Y16_N2
--operation mode is normal
 
UD1_shift_out_89_27 = UD1_shift_out586 & UD1_shift_out_85[28] # !UD1_shift_out586 & UD1_shift_out_87[28];
 
 
--MD1_c_4_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_4_0 at LC_X9_Y15_N3
--operation mode is normal
 
MD1_c_4_0 = MD1_c_2[28] # TD1_alu_out_0_a2_22 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add28;
 
 
--MD1_c_a_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_28 at LC_X9_Y16_N5
--operation mode is normal
 
MD1_c_a_28 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_20;
 
 
--UD1_shift_out_89_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_28 at LC_X8_Y15_N8
--operation mode is normal
 
UD1_shift_out_89_28 = UD1_shift_out586 & UD1_shift_out_85[29] # !UD1_shift_out586 & UD1_shift_out_87[29];
 
 
--MD1_c_a_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_29 at LC_X12_Y13_N8
--operation mode is normal
 
MD1_c_a_29 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_21;
 
 
--MD1_c_0_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_28 at LC_X9_Y10_N4
--operation mode is normal
 
MD1_c_0_28 = RC1_alu_func_o_4 & !TD1_m91 # !RC1_alu_func_o_4 & TD1_m88 # !MD1_c_0_a[29];
 
 
--UD1_shift_out_87[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[13] at LC_X13_Y18_N5
--operation mode is normal
 
UD1_shift_out_87[13] = PD1_a_o_0 & UD1_shift_out_87_d[13] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[13] # !PD1_a_o_2 & VD1_b_o_iv_15;
 
 
--UD1_shift_out_89_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[13] at LC_X14_Y11_N0
--operation mode is normal
 
UD1_shift_out_89_a[13] = PD1_a_o_1 & !UD1_shift_out_85_d[13] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[13] # !PD1_a_o_2 & !VD1_b_o_iv_12;
 
 
--UD1_shift_out_86_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_13 at LC_X15_Y14_N6
--operation mode is normal
 
UD1_shift_out_86_13 = UD1_shift_out_sn_b9_0 & UD1_shift_out_86_a[13] & UD1_shift_out_42[1] # !UD1_shift_out_86_a[13] & UD1_shift_out_79[17] # !UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[13];
 
 
--UD1_shift_out_92_d_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_5 at LC_X14_Y11_N9
--operation mode is normal
 
UD1_shift_out_92_d_5 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[13] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[21];
 
 
--MD1_c_0_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[13] at LC_X11_Y11_N5
--operation mode is normal
 
MD1_c_0_a[13] = VD1_un24_res & !VD1_hilo_45 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_13;
 
 
--TD1_m127 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m127 at LC_X11_Y11_N3
--operation mode is normal
 
TD1_m127 = TD1_m127_a & PD1_a_o_13 # !TD1_m4 # !TD1_m127_a & TD1_m7 & !PD1_a_o_13;
 
 
--TD1_m124 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m124 at LC_X11_Y11_N4
--operation mode is normal
 
TD1_m124 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add13;
 
 
--VD1_hilo_37_iv_0_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[30] at LC_X3_Y13_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[30] = VD1_hilo_2_sqmuxa & !VD1_hilo_29 & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_31 # !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_31;
 
 
--VD1_hilo_37_iv_0_0[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[30] at LC_X3_Y13_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_0[30] = VD1_un134_hilo_combout[30] & VD1_hilo_37_iv_0_a3_0[0] # VD1_hilo_30 & VD1_hilo_37_iv_0_o5[0] # !VD1_un134_hilo_combout[30] & VD1_hilo_30 & VD1_hilo_37_iv_0_o5[0];
 
 
--PD1_a_o_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_30 at LC_X24_Y3_N9
--operation mode is normal
 
PD1_a_o_30 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[30] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[30];
 
 
--VD1_hilo_62 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_62 at LC_X8_Y8_N8
--operation mode is normal
 
VD1_hilo_62_lut_out = !VD1_hilo_37_iv_0_o5_0[62] & VD1_hilo_37_iv_0_a[62] & VD1_hilo_62 # !VD1_hilo_37_iv_0_a3_4[62];
VD1_hilo_62 = DFFEAS(VD1_hilo_62_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--UD1_shift_out_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_30 at LC_X11_Y13_N8
--operation mode is normal
 
UD1_shift_out_30 = UD1_shift_out_sn_m31_i & UD1_shift_out_a[30] & UD1_shift_out_83[31] # !UD1_shift_out_a[30] & UD1_shift_out_92_d[30] # !UD1_shift_out_sn_m31_i & !UD1_shift_out_a[30];
 
 
--TD1_m96 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m96 at LC_X13_Y14_N5
--operation mode is normal
 
TD1_m96 = PD1_a_o_30 & TD1_m96_a # !PD1_a_o_30 & TD1_m96_a & !TD1_m4 # !TD1_m96_a & TD1_m7;
 
 
--TD1_un1_a_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add30 at LC_X12_Y7_N5
--operation mode is arithmetic
 
TD1_un1_a_add30_carry_eqn = TD1_un1_a_carry_29;
TD1_un1_a_add30 = TD1_un1_b_1_combout[30] $ PD1_a_o_30 $ !TD1_un1_a_add30_carry_eqn;
 
--TD1_un1_a_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_30 at LC_X12_Y7_N5
--operation mode is arithmetic
 
TD1_un1_a_carry_30_cout_0 = TD1_un1_b_1_combout[30] & PD1_a_o_30 # !TD1_un1_a_carry_29 # !TD1_un1_b_1_combout[30] & PD1_a_o_30 & !TD1_un1_a_carry_29;
TD1_un1_a_carry_30 = CARRY(TD1_un1_a_carry_30_cout_0);
 
--TD1L665 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_30~COUT1_1 at LC_X12_Y7_N5
--operation mode is arithmetic
 
TD1L665_cout_1 = TD1_un1_b_1_combout[30] & PD1_a_o_30 # !TD1_un1_a_carry_29 # !TD1_un1_b_1_combout[30] & PD1_a_o_30 & !TD1_un1_a_carry_29;
TD1L665 = CARRY(TD1L665_cout_1);
 
 
--UD1_shift_out_89_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_11 at LC_X19_Y18_N3
--operation mode is normal
 
UD1_shift_out_89_11 = UD1_shift_out586 & !UD1_shift_out_89_a[12] # !UD1_shift_out586 & UD1_shift_out_87[12];
 
 
--MD1_c_a_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_12 at LC_X16_Y14_N3
--operation mode is normal
 
MD1_c_a_12 = UD1_shift_out586 & !UD1_shift_out_92_d_4 # !UD1_shift_out586 & UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_4 # !UD1_shift_out_sn_m25_0 & !UD1_shift_out_86_12;
 
 
--MD1_c_0_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_11 at LC_X16_Y14_N6
--operation mode is normal
 
MD1_c_0_11 = RC1_alu_func_o_4 & !TD1_m122 # !RC1_alu_func_o_4 & TD1_m119 # !MD1_c_0_a[12];
 
 
--UD1_shift_out_89_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_23 at LC_X8_Y18_N8
--operation mode is normal
 
UD1_shift_out_89_23 = UD1_shift_out586 & UD1_shift_out_85[24] # !UD1_shift_out586 & !UD1_shift_out_89_a[24];
 
 
--MD1_c_a_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_24 at LC_X9_Y13_N3
--operation mode is normal
 
MD1_c_a_24 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_16;
 
 
--MD1_c_0_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_23 at LC_X9_Y13_N8
--operation mode is normal
 
MD1_c_0_23 = RC1_alu_func_o_4 & !TD1_m71 # !RC1_alu_func_o_4 & TD1_m68 # !MD1_c_0_a[24];
 
 
--UD1_shift_out_89_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_24 at LC_X13_Y10_N8
--operation mode is normal
 
UD1_shift_out_89_24 = UD1_shift_out586 & UD1_shift_out_85[25] # !UD1_shift_out586 & !UD1_shift_out_89_a[25];
 
 
--MD1_c_a_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_25 at LC_X14_Y15_N2
--operation mode is normal
 
MD1_c_a_25 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_17;
 
 
--MD1_c_0_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_24 at LC_X13_Y10_N0
--operation mode is normal
 
MD1_c_0_24 = RC1_alu_func_o_4 & !TD1_m76 # !RC1_alu_func_o_4 & TD1_m73 # !MD1_c_0_a[25];
 
 
--UD1_shift_out_89_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_21 at LC_X8_Y17_N5
--operation mode is normal
 
UD1_shift_out_89_21 = UD1_shift_out586 & UD1_shift_out_85[22] # !UD1_shift_out586 & UD1_shift_out_87[22];
 
 
--MD1_c_a_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_22 at LC_X12_Y13_N7
--operation mode is normal
 
MD1_c_a_22 = UD1_shift_out_92_s_0 & VD1_b_o_iv_31 & !UD1_shift_out587 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_14;
 
 
--MD1_c_0_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_21 at LC_X5_Y13_N6
--operation mode is normal
 
MD1_c_0_21 = RC1_alu_func_o_4 & !TD1_m61 # !RC1_alu_func_o_4 & TD1_m58 # !MD1_c_0_a[22];
 
 
--UD1_shift_out_89_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_22 at LC_X14_Y7_N3
--operation mode is normal
 
UD1_shift_out_89_22 = UD1_shift_out586 & UD1_shift_out_85[23] # !UD1_shift_out586 & !UD1_shift_out_89_a[23];
 
 
--MD1_c_a_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_a_23 at LC_X12_Y12_N8
--operation mode is normal
 
MD1_c_a_23 = UD1_shift_out_92_s_0 & !UD1_shift_out587 & VD1_b_o_iv_31 # !UD1_shift_out_92_s_0 & UD1_shift_out_92_d_15;
 
 
--MD1_c_0_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_22 at LC_X14_Y7_N8
--operation mode is normal
 
MD1_c_0_22 = RC1_alu_func_o_4 & !TD1_m66 # !RC1_alu_func_o_4 & TD1_m63 # !MD1_c_0_a[23];
 
 
--TB1_dout_1_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_6 at LC_X24_Y16_N2
--operation mode is normal
 
TB1_dout_1_6 = TB1_dout22 & CB1_dout_2_6 # !TB1_dout22 & TB1_dout21 & CB1_dout_2_6 # !TB1_dout21 & CB1_dout_2_22;
 
 
--UB1_dout_2_i_o2_0[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2_0[3] at LC_X31_Y9_N3
--operation mode is normal
 
UB1_dout_2_i_o2_0[3] = RB1_byte_addr_o_1 & RB1_byte_addr_o_0 # !UB1_dout_2_i_o2_0_a[3] # !RB1_byte_addr_o_1 & !UB1_dout_2_i_o2_0_a[3] & RB1_byte_addr_o_0 # !RB1_ctl_o_3;
 
 
--HE1_q_a[6] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[6] at M4K_X17_Y18
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
HE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[6]_PORT_A_data_in_reg = DFFE(HE1_q_a[6]_PORT_A_data_in, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_x_6, TB1_dout_1_x_5);
HE1_q_a[6]_PORT_B_data_in_reg = DFFE(HE1_q_a[6]_PORT_B_data_in, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[6]_PORT_A_address_reg = DFFE(HE1_q_a[6]_PORT_A_address, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[6]_PORT_B_address_reg = DFFE(HE1_q_a[6]_PORT_B_address, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_A_write_enable = GND;
HE1_q_a[6]_PORT_A_write_enable_reg = DFFE(HE1_q_a[6]_PORT_A_write_enable, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_write_enable = WB2L2;
HE1_q_a[6]_PORT_B_write_enable_reg = DFFE(HE1_q_a[6]_PORT_B_write_enable, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[6]_PORT_A_data_out = MEMORY(HE1_q_a[6]_PORT_A_data_in_reg, HE1_q_a[6]_PORT_B_data_in_reg, HE1_q_a[6]_PORT_A_address_reg, HE1_q_a[6]_PORT_B_address_reg, HE1_q_a[6]_PORT_A_write_enable_reg, HE1_q_a[6]_PORT_B_write_enable_reg, , , HE1_q_a[6]_clock_0, , , , , );
HE1_q_a[6] = HE1_q_a[6]_PORT_A_data_out[0];
 
--HE1_q_b[6] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[6] at M4K_X17_Y18
HE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[6]_PORT_A_data_in_reg = DFFE(HE1_q_b[6]_PORT_A_data_in, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_x_6, TB1_dout_1_x_5);
HE1_q_b[6]_PORT_B_data_in_reg = DFFE(HE1_q_b[6]_PORT_B_data_in, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[6]_PORT_A_address_reg = DFFE(HE1_q_b[6]_PORT_A_address, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[6]_PORT_B_address_reg = DFFE(HE1_q_b[6]_PORT_B_address, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_A_write_enable = GND;
HE1_q_b[6]_PORT_A_write_enable_reg = DFFE(HE1_q_b[6]_PORT_A_write_enable, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_write_enable = WB2L2;
HE1_q_b[6]_PORT_B_write_enable_reg = DFFE(HE1_q_b[6]_PORT_B_write_enable, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[6]_PORT_B_data_out = MEMORY(HE1_q_b[6]_PORT_A_data_in_reg, HE1_q_b[6]_PORT_B_data_in_reg, HE1_q_b[6]_PORT_A_address_reg, HE1_q_b[6]_PORT_B_address_reg, HE1_q_b[6]_PORT_A_write_enable_reg, HE1_q_b[6]_PORT_B_write_enable_reg, , , HE1_q_b[6]_clock_0, , , , , );
HE1_q_b[6] = HE1_q_b[6]_PORT_B_data_out[0];
 
--HE1_q_a[5] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[5] at M4K_X17_Y18
HE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[6]_PORT_A_data_in_reg = DFFE(HE1_q_a[6]_PORT_A_data_in, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_x_6, TB1_dout_1_x_5);
HE1_q_a[6]_PORT_B_data_in_reg = DFFE(HE1_q_a[6]_PORT_B_data_in, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[6]_PORT_A_address_reg = DFFE(HE1_q_a[6]_PORT_A_address, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[6]_PORT_B_address_reg = DFFE(HE1_q_a[6]_PORT_B_address, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_A_write_enable = GND;
HE1_q_a[6]_PORT_A_write_enable_reg = DFFE(HE1_q_a[6]_PORT_A_write_enable, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_PORT_B_write_enable = WB2L2;
HE1_q_a[6]_PORT_B_write_enable_reg = DFFE(HE1_q_a[6]_PORT_B_write_enable, HE1_q_a[6]_clock_0, , , );
HE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[6]_PORT_A_data_out = MEMORY(HE1_q_a[6]_PORT_A_data_in_reg, HE1_q_a[6]_PORT_B_data_in_reg, HE1_q_a[6]_PORT_A_address_reg, HE1_q_a[6]_PORT_B_address_reg, HE1_q_a[6]_PORT_A_write_enable_reg, HE1_q_a[6]_PORT_B_write_enable_reg, , , HE1_q_a[6]_clock_0, , , , , );
HE1_q_a[5] = HE1_q_a[6]_PORT_A_data_out[1];
 
--HE1_q_b[5] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[5] at M4K_X17_Y18
HE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[6]_PORT_A_data_in_reg = DFFE(HE1_q_b[6]_PORT_A_data_in, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_x_6, TB1_dout_1_x_5);
HE1_q_b[6]_PORT_B_data_in_reg = DFFE(HE1_q_b[6]_PORT_B_data_in, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[6]_PORT_A_address_reg = DFFE(HE1_q_b[6]_PORT_A_address, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[6]_PORT_B_address_reg = DFFE(HE1_q_b[6]_PORT_B_address, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_A_write_enable = GND;
HE1_q_b[6]_PORT_A_write_enable_reg = DFFE(HE1_q_b[6]_PORT_A_write_enable, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_PORT_B_write_enable = WB2L2;
HE1_q_b[6]_PORT_B_write_enable_reg = DFFE(HE1_q_b[6]_PORT_B_write_enable, HE1_q_b[6]_clock_0, , , );
HE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[6]_PORT_B_data_out = MEMORY(HE1_q_b[6]_PORT_A_data_in_reg, HE1_q_b[6]_PORT_B_data_in_reg, HE1_q_b[6]_PORT_A_address_reg, HE1_q_b[6]_PORT_B_address_reg, HE1_q_b[6]_PORT_A_write_enable_reg, HE1_q_b[6]_PORT_B_write_enable_reg, , , HE1_q_b[6]_clock_0, , , , , );
HE1_q_b[5] = HE1_q_b[6]_PORT_B_data_out[1];
 
 
--KE1_q_a[6] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[6] at M4K_X17_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[6]_PORT_A_data_in_reg = DFFE(KE1_q_a[6]_PORT_A_data_in, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_2_6, TB1_dout_1_2_2);
KE1_q_a[6]_PORT_B_data_in_reg = DFFE(KE1_q_a[6]_PORT_B_data_in, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[6]_PORT_A_address_reg = DFFE(KE1_q_a[6]_PORT_A_address, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[6]_PORT_B_address_reg = DFFE(KE1_q_a[6]_PORT_B_address, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_A_write_enable = GND;
KE1_q_a[6]_PORT_A_write_enable_reg = DFFE(KE1_q_a[6]_PORT_A_write_enable, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_write_enable = WB4L2;
KE1_q_a[6]_PORT_B_write_enable_reg = DFFE(KE1_q_a[6]_PORT_B_write_enable, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[6]_PORT_A_data_out = MEMORY(KE1_q_a[6]_PORT_A_data_in_reg, KE1_q_a[6]_PORT_B_data_in_reg, KE1_q_a[6]_PORT_A_address_reg, KE1_q_a[6]_PORT_B_address_reg, KE1_q_a[6]_PORT_A_write_enable_reg, KE1_q_a[6]_PORT_B_write_enable_reg, , , KE1_q_a[6]_clock_0, , , , , );
KE1_q_a[6] = KE1_q_a[6]_PORT_A_data_out[0];
 
--KE1_q_b[6] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[6] at M4K_X17_Y6
KE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[6]_PORT_A_data_in_reg = DFFE(KE1_q_b[6]_PORT_A_data_in, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_2_6, TB1_dout_1_2_2);
KE1_q_b[6]_PORT_B_data_in_reg = DFFE(KE1_q_b[6]_PORT_B_data_in, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[6]_PORT_A_address_reg = DFFE(KE1_q_b[6]_PORT_A_address, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[6]_PORT_B_address_reg = DFFE(KE1_q_b[6]_PORT_B_address, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_A_write_enable = GND;
KE1_q_b[6]_PORT_A_write_enable_reg = DFFE(KE1_q_b[6]_PORT_A_write_enable, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_write_enable = WB4L2;
KE1_q_b[6]_PORT_B_write_enable_reg = DFFE(KE1_q_b[6]_PORT_B_write_enable, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[6]_PORT_B_data_out = MEMORY(KE1_q_b[6]_PORT_A_data_in_reg, KE1_q_b[6]_PORT_B_data_in_reg, KE1_q_b[6]_PORT_A_address_reg, KE1_q_b[6]_PORT_B_address_reg, KE1_q_b[6]_PORT_A_write_enable_reg, KE1_q_b[6]_PORT_B_write_enable_reg, , , KE1_q_b[6]_clock_0, , , , , );
KE1_q_b[6] = KE1_q_b[6]_PORT_B_data_out[0];
 
--KE1_q_a[2] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[2] at M4K_X17_Y6
KE1_q_a[6]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[6]_PORT_A_data_in_reg = DFFE(KE1_q_a[6]_PORT_A_data_in, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_data_in = BUS(TB1_dout_1_2_6, TB1_dout_1_2_2);
KE1_q_a[6]_PORT_B_data_in_reg = DFFE(KE1_q_a[6]_PORT_B_data_in, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[6]_PORT_A_address_reg = DFFE(KE1_q_a[6]_PORT_A_address, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[6]_PORT_B_address_reg = DFFE(KE1_q_a[6]_PORT_B_address, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_A_write_enable = GND;
KE1_q_a[6]_PORT_A_write_enable_reg = DFFE(KE1_q_a[6]_PORT_A_write_enable, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_PORT_B_write_enable = WB4L2;
KE1_q_a[6]_PORT_B_write_enable_reg = DFFE(KE1_q_a[6]_PORT_B_write_enable, KE1_q_a[6]_clock_0, , , );
KE1_q_a[6]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[6]_PORT_A_data_out = MEMORY(KE1_q_a[6]_PORT_A_data_in_reg, KE1_q_a[6]_PORT_B_data_in_reg, KE1_q_a[6]_PORT_A_address_reg, KE1_q_a[6]_PORT_B_address_reg, KE1_q_a[6]_PORT_A_write_enable_reg, KE1_q_a[6]_PORT_B_write_enable_reg, , , KE1_q_a[6]_clock_0, , , , , );
KE1_q_a[2] = KE1_q_a[6]_PORT_A_data_out[1];
 
--KE1_q_b[2] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[2] at M4K_X17_Y6
KE1_q_b[6]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[6]_PORT_A_data_in_reg = DFFE(KE1_q_b[6]_PORT_A_data_in, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_data_in = BUS(TB1_dout_1_2_6, TB1_dout_1_2_2);
KE1_q_b[6]_PORT_B_data_in_reg = DFFE(KE1_q_b[6]_PORT_B_data_in, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[6]_PORT_A_address_reg = DFFE(KE1_q_b[6]_PORT_A_address, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[6]_PORT_B_address_reg = DFFE(KE1_q_b[6]_PORT_B_address, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_A_write_enable = GND;
KE1_q_b[6]_PORT_A_write_enable_reg = DFFE(KE1_q_b[6]_PORT_A_write_enable, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_PORT_B_write_enable = WB4L2;
KE1_q_b[6]_PORT_B_write_enable_reg = DFFE(KE1_q_b[6]_PORT_B_write_enable, KE1_q_b[6]_clock_0, , , );
KE1_q_b[6]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[6]_PORT_B_data_out = MEMORY(KE1_q_b[6]_PORT_A_data_in_reg, KE1_q_b[6]_PORT_B_data_in_reg, KE1_q_b[6]_PORT_A_address_reg, KE1_q_b[6]_PORT_B_address_reg, KE1_q_b[6]_PORT_A_write_enable_reg, KE1_q_b[6]_PORT_B_write_enable_reg, , , KE1_q_b[6]_clock_0, , , , , );
KE1_q_b[2] = KE1_q_b[6]_PORT_B_data_out[1];
 
 
--UB1_dout_2_i_a3_1[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a3_1[3] at LC_X31_Y14_N8
--operation mode is normal
 
UB1_dout_2_i_a3_1[3] = RB1_byte_addr_o_1 & !RB1_byte_addr_o_0 & UB1_dout_2_i_i_o3[7];
 
 
--UB1_dout_2_i_a3_0[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_a3_0[3] at LC_X31_Y14_N9
--operation mode is normal
 
UB1_dout_2_i_a3_0[3] = !RB1_byte_addr_o_1 & !RB1_byte_addr_o_0 & UB1_dout_2_i_i_o3[7];
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] at LC_X20_Y5_N1
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[8] = QD1_b_o18 & !QB1_r32_o_8 & QD1_un1_b_o18_2 # !FB1_r32_o_0_8 # !QD1_b_o18 & !QB1_r32_o_8 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[8] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[8] at LC_X20_Y5_N3
--operation mode is normal
 
G1_BUS15471_i_m[8] = QD1_b_o_1_sqmuxa & !FD1_wb_o_8;
 
 
--UD1_shift_out_87_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[6] at LC_X12_Y15_N9
--operation mode is normal
 
UD1_shift_out_87_d_a[6] = PD1_a_o_1 & !VD1_b_o_iv_12 # !PD1_a_o_1 & !VD1_b_o_iv_10;
 
 
--UD1_shift_out_80[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[6] at LC_X12_Y15_N2
--operation mode is normal
 
UD1_shift_out_80[6] = PD1_a_o_2 & UD1_shift_out_80_a[6] & VD1_b_o_iv_11 # !UD1_shift_out_80_a[6] & VD1_b_o_iv_13 # !PD1_a_o_2 & !UD1_shift_out_80_a[6];
 
 
--UD1_shift_out_85_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[6] at LC_X14_Y19_N1
--operation mode is normal
 
UD1_shift_out_85_d_a[6] = PD1_a_o_0 & !VD1_b_o_iv_3 # !PD1_a_o_0 & !VD1_b_o_iv_4;
 
 
--UD1_shift_out_43[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[30] at LC_X14_Y18_N6
--operation mode is normal
 
UD1_shift_out_43[30] = PD1_a_o_0 & !PD1_a_o_1 & VD1_b_o_iv_1 # !PD1_a_o_0 & !UD1_shift_out_43_a[30];
 
 
--TD1_alu_out_7_0_0_m4_0[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[6] at LC_X8_Y14_N8
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0[6] = VD1_b_o_iv_6 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_6 & TD1_alu_out_7_0_0_m4_0_a[3];
 
 
--TD1_alu_out_0_a2_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[6] at LC_X6_Y15_N6
--operation mode is normal
 
TD1_alu_out_0_a2_a[6] = VD1_b_o_iv_6 & !TD1_m107 # !VD1_b_o_iv_6 & !TD1_alu_out_0_a3[28];
 
 
--PD1_a_o_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[6] at LC_X21_Y4_N1
--operation mode is normal
 
PD1_a_o_a[6] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_6 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_6;
 
 
--PD1_a_o_3_Z[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[6] at LC_X19_Y11_N5
--operation mode is normal
 
SD1_r32_o_6_qfbk = SD1_r32_o_6;
PD1_a_o_3_Z[6] = PD1_a_o_3_s[0] & SD1_r32_o_6_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[6];
 
--SD1_r32_o_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_6 at LC_X19_Y11_N5
--operation mode is normal
 
SD1_r32_o_6 = DFFEAS(PD1_a_o_3_Z[6], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_6, , , VCC);
 
 
--UD1_shift_out_76_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[6] at LC_X19_Y17_N1
--operation mode is normal
 
UD1_shift_out_76_a[6] = PD1_a_o_2 & !PD1_a_o_3 # !PD1_a_o_2 & !PD1_a_o_1 & UD1_shift_out_39[18];
 
 
--UD1_shift_out_47[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47[2] at LC_X15_Y18_N9
--operation mode is normal
 
UD1_shift_out_47[2] = PD1_a_o_1 & !UD1_shift_out_47_a[2] # !PD1_a_o_1 & UD1_shift_out_47_a[2] & VD1_b_o_iv_22 # !UD1_shift_out_47_a[2] & VD1_b_o_iv_23;
 
 
--UD1_shift_out_61[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_61[6] at LC_X19_Y15_N9
--operation mode is normal
 
UD1_shift_out_61[6] = PD1_a_o_2 & UD1_shift_out_79[18] # !PD1_a_o_2 & UD1_shift_out_47[2];
 
 
--UD1_shift_out_74_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[6] at LC_X19_Y15_N7
--operation mode is normal
 
UD1_shift_out_74_a[6] = UD1_shift_out_63_a[17] & PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & !VD1_b_o_iv_30 # !UD1_shift_out_63_a[17] & !VD1_b_o_iv_31;
 
 
--TB1_dout_1_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_5 at LC_X21_Y14_N1
--operation mode is normal
 
TB1_dout_1_5 = TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_5 # !TB1_dout22 & CB1_dout_2_21;
 
 
--GE1_q_a[5] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[5] at M4K_X17_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
GE1_q_a[5]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[5]_PORT_A_data_in_reg = DFFE(GE1_q_a[5]_PORT_A_data_in, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_data_in = BUS(CB1_dout_2_5, CB1_dout_2_2);
GE1_q_a[5]_PORT_B_data_in_reg = DFFE(GE1_q_a[5]_PORT_B_data_in, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[5]_PORT_A_address_reg = DFFE(GE1_q_a[5]_PORT_A_address, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[5]_PORT_B_address_reg = DFFE(GE1_q_a[5]_PORT_B_address, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_A_write_enable = GND;
GE1_q_a[5]_PORT_A_write_enable_reg = DFFE(GE1_q_a[5]_PORT_A_write_enable, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_write_enable = WB1L2;
GE1_q_a[5]_PORT_B_write_enable_reg = DFFE(GE1_q_a[5]_PORT_B_write_enable, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[5]_PORT_A_data_out = MEMORY(GE1_q_a[5]_PORT_A_data_in_reg, GE1_q_a[5]_PORT_B_data_in_reg, GE1_q_a[5]_PORT_A_address_reg, GE1_q_a[5]_PORT_B_address_reg, GE1_q_a[5]_PORT_A_write_enable_reg, GE1_q_a[5]_PORT_B_write_enable_reg, , , GE1_q_a[5]_clock_0, , , , , );
GE1_q_a[5] = GE1_q_a[5]_PORT_A_data_out[0];
 
--GE1_q_b[5] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[5] at M4K_X17_Y13
GE1_q_b[5]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[5]_PORT_A_data_in_reg = DFFE(GE1_q_b[5]_PORT_A_data_in, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_data_in = BUS(CB1_dout_2_5, CB1_dout_2_2);
GE1_q_b[5]_PORT_B_data_in_reg = DFFE(GE1_q_b[5]_PORT_B_data_in, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[5]_PORT_A_address_reg = DFFE(GE1_q_b[5]_PORT_A_address, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[5]_PORT_B_address_reg = DFFE(GE1_q_b[5]_PORT_B_address, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_A_write_enable = GND;
GE1_q_b[5]_PORT_A_write_enable_reg = DFFE(GE1_q_b[5]_PORT_A_write_enable, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_write_enable = WB1L2;
GE1_q_b[5]_PORT_B_write_enable_reg = DFFE(GE1_q_b[5]_PORT_B_write_enable, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[5]_PORT_B_data_out = MEMORY(GE1_q_b[5]_PORT_A_data_in_reg, GE1_q_b[5]_PORT_B_data_in_reg, GE1_q_b[5]_PORT_A_address_reg, GE1_q_b[5]_PORT_B_address_reg, GE1_q_b[5]_PORT_A_write_enable_reg, GE1_q_b[5]_PORT_B_write_enable_reg, , , GE1_q_b[5]_clock_0, , , , , );
GE1_q_b[5] = GE1_q_b[5]_PORT_B_data_out[0];
 
--GE1_q_a[2] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[2] at M4K_X17_Y13
GE1_q_a[5]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[5]_PORT_A_data_in_reg = DFFE(GE1_q_a[5]_PORT_A_data_in, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_data_in = BUS(CB1_dout_2_5, CB1_dout_2_2);
GE1_q_a[5]_PORT_B_data_in_reg = DFFE(GE1_q_a[5]_PORT_B_data_in, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[5]_PORT_A_address_reg = DFFE(GE1_q_a[5]_PORT_A_address, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[5]_PORT_B_address_reg = DFFE(GE1_q_a[5]_PORT_B_address, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_A_write_enable = GND;
GE1_q_a[5]_PORT_A_write_enable_reg = DFFE(GE1_q_a[5]_PORT_A_write_enable, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_PORT_B_write_enable = WB1L2;
GE1_q_a[5]_PORT_B_write_enable_reg = DFFE(GE1_q_a[5]_PORT_B_write_enable, GE1_q_a[5]_clock_0, , , );
GE1_q_a[5]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[5]_PORT_A_data_out = MEMORY(GE1_q_a[5]_PORT_A_data_in_reg, GE1_q_a[5]_PORT_B_data_in_reg, GE1_q_a[5]_PORT_A_address_reg, GE1_q_a[5]_PORT_B_address_reg, GE1_q_a[5]_PORT_A_write_enable_reg, GE1_q_a[5]_PORT_B_write_enable_reg, , , GE1_q_a[5]_clock_0, , , , , );
GE1_q_a[2] = GE1_q_a[5]_PORT_A_data_out[1];
 
--GE1_q_b[2] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[2] at M4K_X17_Y13
GE1_q_b[5]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[5]_PORT_A_data_in_reg = DFFE(GE1_q_b[5]_PORT_A_data_in, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_data_in = BUS(CB1_dout_2_5, CB1_dout_2_2);
GE1_q_b[5]_PORT_B_data_in_reg = DFFE(GE1_q_b[5]_PORT_B_data_in, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[5]_PORT_A_address_reg = DFFE(GE1_q_b[5]_PORT_A_address, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[5]_PORT_B_address_reg = DFFE(GE1_q_b[5]_PORT_B_address, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_A_write_enable = GND;
GE1_q_b[5]_PORT_A_write_enable_reg = DFFE(GE1_q_b[5]_PORT_A_write_enable, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_PORT_B_write_enable = WB1L2;
GE1_q_b[5]_PORT_B_write_enable_reg = DFFE(GE1_q_b[5]_PORT_B_write_enable, GE1_q_b[5]_clock_0, , , );
GE1_q_b[5]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[5]_PORT_B_data_out = MEMORY(GE1_q_b[5]_PORT_A_data_in_reg, GE1_q_b[5]_PORT_B_data_in_reg, GE1_q_b[5]_PORT_A_address_reg, GE1_q_b[5]_PORT_B_address_reg, GE1_q_b[5]_PORT_A_write_enable_reg, GE1_q_b[5]_PORT_B_write_enable_reg, , , GE1_q_b[5]_clock_0, , , , , );
GE1_q_b[2] = GE1_q_b[5]_PORT_B_data_out[1];
 
 
--KE1_q_a[5] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[5] at M4K_X17_Y16
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KE1_q_a[5]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[5]_PORT_A_data_in_reg = DFFE(KE1_q_a[5]_PORT_A_data_in, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_data_in = BUS(TB1_dout_1_2_5, TB1_dout_1_2_7);
KE1_q_a[5]_PORT_B_data_in_reg = DFFE(KE1_q_a[5]_PORT_B_data_in, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[5]_PORT_A_address_reg = DFFE(KE1_q_a[5]_PORT_A_address, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[5]_PORT_B_address_reg = DFFE(KE1_q_a[5]_PORT_B_address, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_A_write_enable = GND;
KE1_q_a[5]_PORT_A_write_enable_reg = DFFE(KE1_q_a[5]_PORT_A_write_enable, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_write_enable = WB4L2;
KE1_q_a[5]_PORT_B_write_enable_reg = DFFE(KE1_q_a[5]_PORT_B_write_enable, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[5]_PORT_A_data_out = MEMORY(KE1_q_a[5]_PORT_A_data_in_reg, KE1_q_a[5]_PORT_B_data_in_reg, KE1_q_a[5]_PORT_A_address_reg, KE1_q_a[5]_PORT_B_address_reg, KE1_q_a[5]_PORT_A_write_enable_reg, KE1_q_a[5]_PORT_B_write_enable_reg, , , KE1_q_a[5]_clock_0, , , , , );
KE1_q_a[5] = KE1_q_a[5]_PORT_A_data_out[0];
 
--KE1_q_b[5] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[5] at M4K_X17_Y16
KE1_q_b[5]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[5]_PORT_A_data_in_reg = DFFE(KE1_q_b[5]_PORT_A_data_in, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_data_in = BUS(TB1_dout_1_2_5, TB1_dout_1_2_7);
KE1_q_b[5]_PORT_B_data_in_reg = DFFE(KE1_q_b[5]_PORT_B_data_in, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[5]_PORT_A_address_reg = DFFE(KE1_q_b[5]_PORT_A_address, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[5]_PORT_B_address_reg = DFFE(KE1_q_b[5]_PORT_B_address, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_A_write_enable = GND;
KE1_q_b[5]_PORT_A_write_enable_reg = DFFE(KE1_q_b[5]_PORT_A_write_enable, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_write_enable = WB4L2;
KE1_q_b[5]_PORT_B_write_enable_reg = DFFE(KE1_q_b[5]_PORT_B_write_enable, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[5]_PORT_B_data_out = MEMORY(KE1_q_b[5]_PORT_A_data_in_reg, KE1_q_b[5]_PORT_B_data_in_reg, KE1_q_b[5]_PORT_A_address_reg, KE1_q_b[5]_PORT_B_address_reg, KE1_q_b[5]_PORT_A_write_enable_reg, KE1_q_b[5]_PORT_B_write_enable_reg, , , KE1_q_b[5]_clock_0, , , , , );
KE1_q_b[5] = KE1_q_b[5]_PORT_B_data_out[0];
 
--KE1_q_a[7] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[7] at M4K_X17_Y16
KE1_q_a[5]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[5]_PORT_A_data_in_reg = DFFE(KE1_q_a[5]_PORT_A_data_in, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_data_in = BUS(TB1_dout_1_2_5, TB1_dout_1_2_7);
KE1_q_a[5]_PORT_B_data_in_reg = DFFE(KE1_q_a[5]_PORT_B_data_in, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[5]_PORT_A_address_reg = DFFE(KE1_q_a[5]_PORT_A_address, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[5]_PORT_B_address_reg = DFFE(KE1_q_a[5]_PORT_B_address, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_A_write_enable = GND;
KE1_q_a[5]_PORT_A_write_enable_reg = DFFE(KE1_q_a[5]_PORT_A_write_enable, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_PORT_B_write_enable = WB4L2;
KE1_q_a[5]_PORT_B_write_enable_reg = DFFE(KE1_q_a[5]_PORT_B_write_enable, KE1_q_a[5]_clock_0, , , );
KE1_q_a[5]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[5]_PORT_A_data_out = MEMORY(KE1_q_a[5]_PORT_A_data_in_reg, KE1_q_a[5]_PORT_B_data_in_reg, KE1_q_a[5]_PORT_A_address_reg, KE1_q_a[5]_PORT_B_address_reg, KE1_q_a[5]_PORT_A_write_enable_reg, KE1_q_a[5]_PORT_B_write_enable_reg, , , KE1_q_a[5]_clock_0, , , , , );
KE1_q_a[7] = KE1_q_a[5]_PORT_A_data_out[1];
 
--KE1_q_b[7] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[7] at M4K_X17_Y16
KE1_q_b[5]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[5]_PORT_A_data_in_reg = DFFE(KE1_q_b[5]_PORT_A_data_in, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_data_in = BUS(TB1_dout_1_2_5, TB1_dout_1_2_7);
KE1_q_b[5]_PORT_B_data_in_reg = DFFE(KE1_q_b[5]_PORT_B_data_in, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[5]_PORT_A_address_reg = DFFE(KE1_q_b[5]_PORT_A_address, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[5]_PORT_B_address_reg = DFFE(KE1_q_b[5]_PORT_B_address, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_A_write_enable = GND;
KE1_q_b[5]_PORT_A_write_enable_reg = DFFE(KE1_q_b[5]_PORT_A_write_enable, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_PORT_B_write_enable = WB4L2;
KE1_q_b[5]_PORT_B_write_enable_reg = DFFE(KE1_q_b[5]_PORT_B_write_enable, KE1_q_b[5]_clock_0, , , );
KE1_q_b[5]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[5]_PORT_B_data_out = MEMORY(KE1_q_b[5]_PORT_A_data_in_reg, KE1_q_b[5]_PORT_B_data_in_reg, KE1_q_b[5]_PORT_A_address_reg, KE1_q_b[5]_PORT_B_address_reg, KE1_q_b[5]_PORT_A_write_enable_reg, KE1_q_b[5]_PORT_B_write_enable_reg, , , KE1_q_b[5]_clock_0, , , , , );
KE1_q_b[7] = KE1_q_b[5]_PORT_B_data_out[1];
 
 
--GE1_q_a[4] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[4] at M4K_X17_Y14
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
GE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[4]_PORT_A_data_in_reg = DFFE(GE1_q_a[4]_PORT_A_data_in, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_data_in = BUS(CB1_dout_2_4, CB1_dout_2_3);
GE1_q_a[4]_PORT_B_data_in_reg = DFFE(GE1_q_a[4]_PORT_B_data_in, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[4]_PORT_A_address_reg = DFFE(GE1_q_a[4]_PORT_A_address, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[4]_PORT_B_address_reg = DFFE(GE1_q_a[4]_PORT_B_address, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_A_write_enable = GND;
GE1_q_a[4]_PORT_A_write_enable_reg = DFFE(GE1_q_a[4]_PORT_A_write_enable, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_write_enable = WB1L2;
GE1_q_a[4]_PORT_B_write_enable_reg = DFFE(GE1_q_a[4]_PORT_B_write_enable, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[4]_PORT_A_data_out = MEMORY(GE1_q_a[4]_PORT_A_data_in_reg, GE1_q_a[4]_PORT_B_data_in_reg, GE1_q_a[4]_PORT_A_address_reg, GE1_q_a[4]_PORT_B_address_reg, GE1_q_a[4]_PORT_A_write_enable_reg, GE1_q_a[4]_PORT_B_write_enable_reg, , , GE1_q_a[4]_clock_0, , , , , );
GE1_q_a[4] = GE1_q_a[4]_PORT_A_data_out[0];
 
--GE1_q_b[4] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[4] at M4K_X17_Y14
GE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[4]_PORT_A_data_in_reg = DFFE(GE1_q_b[4]_PORT_A_data_in, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_data_in = BUS(CB1_dout_2_4, CB1_dout_2_3);
GE1_q_b[4]_PORT_B_data_in_reg = DFFE(GE1_q_b[4]_PORT_B_data_in, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[4]_PORT_A_address_reg = DFFE(GE1_q_b[4]_PORT_A_address, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[4]_PORT_B_address_reg = DFFE(GE1_q_b[4]_PORT_B_address, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_A_write_enable = GND;
GE1_q_b[4]_PORT_A_write_enable_reg = DFFE(GE1_q_b[4]_PORT_A_write_enable, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_write_enable = WB1L2;
GE1_q_b[4]_PORT_B_write_enable_reg = DFFE(GE1_q_b[4]_PORT_B_write_enable, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[4]_PORT_B_data_out = MEMORY(GE1_q_b[4]_PORT_A_data_in_reg, GE1_q_b[4]_PORT_B_data_in_reg, GE1_q_b[4]_PORT_A_address_reg, GE1_q_b[4]_PORT_B_address_reg, GE1_q_b[4]_PORT_A_write_enable_reg, GE1_q_b[4]_PORT_B_write_enable_reg, , , GE1_q_b[4]_clock_0, , , , , );
GE1_q_b[4] = GE1_q_b[4]_PORT_B_data_out[0];
 
--GE1_q_a[3] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[3] at M4K_X17_Y14
GE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[4]_PORT_A_data_in_reg = DFFE(GE1_q_a[4]_PORT_A_data_in, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_data_in = BUS(CB1_dout_2_4, CB1_dout_2_3);
GE1_q_a[4]_PORT_B_data_in_reg = DFFE(GE1_q_a[4]_PORT_B_data_in, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[4]_PORT_A_address_reg = DFFE(GE1_q_a[4]_PORT_A_address, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[4]_PORT_B_address_reg = DFFE(GE1_q_a[4]_PORT_B_address, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_A_write_enable = GND;
GE1_q_a[4]_PORT_A_write_enable_reg = DFFE(GE1_q_a[4]_PORT_A_write_enable, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_PORT_B_write_enable = WB1L2;
GE1_q_a[4]_PORT_B_write_enable_reg = DFFE(GE1_q_a[4]_PORT_B_write_enable, GE1_q_a[4]_clock_0, , , );
GE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[4]_PORT_A_data_out = MEMORY(GE1_q_a[4]_PORT_A_data_in_reg, GE1_q_a[4]_PORT_B_data_in_reg, GE1_q_a[4]_PORT_A_address_reg, GE1_q_a[4]_PORT_B_address_reg, GE1_q_a[4]_PORT_A_write_enable_reg, GE1_q_a[4]_PORT_B_write_enable_reg, , , GE1_q_a[4]_clock_0, , , , , );
GE1_q_a[3] = GE1_q_a[4]_PORT_A_data_out[1];
 
--GE1_q_b[3] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[3] at M4K_X17_Y14
GE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[4]_PORT_A_data_in_reg = DFFE(GE1_q_b[4]_PORT_A_data_in, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_data_in = BUS(CB1_dout_2_4, CB1_dout_2_3);
GE1_q_b[4]_PORT_B_data_in_reg = DFFE(GE1_q_b[4]_PORT_B_data_in, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[4]_PORT_A_address_reg = DFFE(GE1_q_b[4]_PORT_A_address, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[4]_PORT_B_address_reg = DFFE(GE1_q_b[4]_PORT_B_address, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_A_write_enable = GND;
GE1_q_b[4]_PORT_A_write_enable_reg = DFFE(GE1_q_b[4]_PORT_A_write_enable, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_PORT_B_write_enable = WB1L2;
GE1_q_b[4]_PORT_B_write_enable_reg = DFFE(GE1_q_b[4]_PORT_B_write_enable, GE1_q_b[4]_clock_0, , , );
GE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[4]_PORT_B_data_out = MEMORY(GE1_q_b[4]_PORT_A_data_in_reg, GE1_q_b[4]_PORT_B_data_in_reg, GE1_q_b[4]_PORT_A_address_reg, GE1_q_b[4]_PORT_B_address_reg, GE1_q_b[4]_PORT_A_write_enable_reg, GE1_q_b[4]_PORT_B_write_enable_reg, , , GE1_q_b[4]_clock_0, , , , , );
GE1_q_b[3] = GE1_q_b[4]_PORT_B_data_out[1];
 
 
--KE1_q_a[4] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[4] at M4K_X17_Y19
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[4]_PORT_A_data_in_reg = DFFE(KE1_q_a[4]_PORT_A_data_in, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_2_4, TB1_dout_1_2_3);
KE1_q_a[4]_PORT_B_data_in_reg = DFFE(KE1_q_a[4]_PORT_B_data_in, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[4]_PORT_A_address_reg = DFFE(KE1_q_a[4]_PORT_A_address, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[4]_PORT_B_address_reg = DFFE(KE1_q_a[4]_PORT_B_address, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_A_write_enable = GND;
KE1_q_a[4]_PORT_A_write_enable_reg = DFFE(KE1_q_a[4]_PORT_A_write_enable, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_write_enable = WB4L2;
KE1_q_a[4]_PORT_B_write_enable_reg = DFFE(KE1_q_a[4]_PORT_B_write_enable, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[4]_PORT_A_data_out = MEMORY(KE1_q_a[4]_PORT_A_data_in_reg, KE1_q_a[4]_PORT_B_data_in_reg, KE1_q_a[4]_PORT_A_address_reg, KE1_q_a[4]_PORT_B_address_reg, KE1_q_a[4]_PORT_A_write_enable_reg, KE1_q_a[4]_PORT_B_write_enable_reg, , , KE1_q_a[4]_clock_0, , , , , );
KE1_q_a[4] = KE1_q_a[4]_PORT_A_data_out[0];
 
--KE1_q_b[4] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[4] at M4K_X17_Y19
KE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[4]_PORT_A_data_in_reg = DFFE(KE1_q_b[4]_PORT_A_data_in, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_2_4, TB1_dout_1_2_3);
KE1_q_b[4]_PORT_B_data_in_reg = DFFE(KE1_q_b[4]_PORT_B_data_in, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[4]_PORT_A_address_reg = DFFE(KE1_q_b[4]_PORT_A_address, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[4]_PORT_B_address_reg = DFFE(KE1_q_b[4]_PORT_B_address, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_A_write_enable = GND;
KE1_q_b[4]_PORT_A_write_enable_reg = DFFE(KE1_q_b[4]_PORT_A_write_enable, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_write_enable = WB4L2;
KE1_q_b[4]_PORT_B_write_enable_reg = DFFE(KE1_q_b[4]_PORT_B_write_enable, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[4]_PORT_B_data_out = MEMORY(KE1_q_b[4]_PORT_A_data_in_reg, KE1_q_b[4]_PORT_B_data_in_reg, KE1_q_b[4]_PORT_A_address_reg, KE1_q_b[4]_PORT_B_address_reg, KE1_q_b[4]_PORT_A_write_enable_reg, KE1_q_b[4]_PORT_B_write_enable_reg, , , KE1_q_b[4]_clock_0, , , , , );
KE1_q_b[4] = KE1_q_b[4]_PORT_B_data_out[0];
 
--KE1_q_a[3] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[3] at M4K_X17_Y19
KE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[4]_PORT_A_data_in_reg = DFFE(KE1_q_a[4]_PORT_A_data_in, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_2_4, TB1_dout_1_2_3);
KE1_q_a[4]_PORT_B_data_in_reg = DFFE(KE1_q_a[4]_PORT_B_data_in, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[4]_PORT_A_address_reg = DFFE(KE1_q_a[4]_PORT_A_address, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[4]_PORT_B_address_reg = DFFE(KE1_q_a[4]_PORT_B_address, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_A_write_enable = GND;
KE1_q_a[4]_PORT_A_write_enable_reg = DFFE(KE1_q_a[4]_PORT_A_write_enable, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_PORT_B_write_enable = WB4L2;
KE1_q_a[4]_PORT_B_write_enable_reg = DFFE(KE1_q_a[4]_PORT_B_write_enable, KE1_q_a[4]_clock_0, , , );
KE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[4]_PORT_A_data_out = MEMORY(KE1_q_a[4]_PORT_A_data_in_reg, KE1_q_a[4]_PORT_B_data_in_reg, KE1_q_a[4]_PORT_A_address_reg, KE1_q_a[4]_PORT_B_address_reg, KE1_q_a[4]_PORT_A_write_enable_reg, KE1_q_a[4]_PORT_B_write_enable_reg, , , KE1_q_a[4]_clock_0, , , , , );
KE1_q_a[3] = KE1_q_a[4]_PORT_A_data_out[1];
 
--KE1_q_b[3] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[3] at M4K_X17_Y19
KE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[4]_PORT_A_data_in_reg = DFFE(KE1_q_b[4]_PORT_A_data_in, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_2_4, TB1_dout_1_2_3);
KE1_q_b[4]_PORT_B_data_in_reg = DFFE(KE1_q_b[4]_PORT_B_data_in, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[4]_PORT_A_address_reg = DFFE(KE1_q_b[4]_PORT_A_address, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[4]_PORT_B_address_reg = DFFE(KE1_q_b[4]_PORT_B_address, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_A_write_enable = GND;
KE1_q_b[4]_PORT_A_write_enable_reg = DFFE(KE1_q_b[4]_PORT_A_write_enable, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_PORT_B_write_enable = WB4L2;
KE1_q_b[4]_PORT_B_write_enable_reg = DFFE(KE1_q_b[4]_PORT_B_write_enable, KE1_q_b[4]_clock_0, , , );
KE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[4]_PORT_B_data_out = MEMORY(KE1_q_b[4]_PORT_A_data_in_reg, KE1_q_b[4]_PORT_B_data_in_reg, KE1_q_b[4]_PORT_A_address_reg, KE1_q_b[4]_PORT_B_address_reg, KE1_q_b[4]_PORT_A_write_enable_reg, KE1_q_b[4]_PORT_B_write_enable_reg, , , KE1_q_b[4]_clock_0, , , , , );
KE1_q_b[3] = KE1_q_b[4]_PORT_B_data_out[1];
 
 
--HE1_q_a[4] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[4] at M4K_X17_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
HE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[4]_PORT_A_data_in_reg = DFFE(HE1_q_a[4]_PORT_A_data_in, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_x_4, TB1_dout_1_x_7);
HE1_q_a[4]_PORT_B_data_in_reg = DFFE(HE1_q_a[4]_PORT_B_data_in, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[4]_PORT_A_address_reg = DFFE(HE1_q_a[4]_PORT_A_address, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[4]_PORT_B_address_reg = DFFE(HE1_q_a[4]_PORT_B_address, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_A_write_enable = GND;
HE1_q_a[4]_PORT_A_write_enable_reg = DFFE(HE1_q_a[4]_PORT_A_write_enable, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_write_enable = WB2L2;
HE1_q_a[4]_PORT_B_write_enable_reg = DFFE(HE1_q_a[4]_PORT_B_write_enable, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[4]_PORT_A_data_out = MEMORY(HE1_q_a[4]_PORT_A_data_in_reg, HE1_q_a[4]_PORT_B_data_in_reg, HE1_q_a[4]_PORT_A_address_reg, HE1_q_a[4]_PORT_B_address_reg, HE1_q_a[4]_PORT_A_write_enable_reg, HE1_q_a[4]_PORT_B_write_enable_reg, , , HE1_q_a[4]_clock_0, , , , , );
HE1_q_a[4] = HE1_q_a[4]_PORT_A_data_out[0];
 
--HE1_q_b[4] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[4] at M4K_X17_Y11
HE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[4]_PORT_A_data_in_reg = DFFE(HE1_q_b[4]_PORT_A_data_in, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_x_4, TB1_dout_1_x_7);
HE1_q_b[4]_PORT_B_data_in_reg = DFFE(HE1_q_b[4]_PORT_B_data_in, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[4]_PORT_A_address_reg = DFFE(HE1_q_b[4]_PORT_A_address, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[4]_PORT_B_address_reg = DFFE(HE1_q_b[4]_PORT_B_address, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_A_write_enable = GND;
HE1_q_b[4]_PORT_A_write_enable_reg = DFFE(HE1_q_b[4]_PORT_A_write_enable, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_write_enable = WB2L2;
HE1_q_b[4]_PORT_B_write_enable_reg = DFFE(HE1_q_b[4]_PORT_B_write_enable, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[4]_PORT_B_data_out = MEMORY(HE1_q_b[4]_PORT_A_data_in_reg, HE1_q_b[4]_PORT_B_data_in_reg, HE1_q_b[4]_PORT_A_address_reg, HE1_q_b[4]_PORT_B_address_reg, HE1_q_b[4]_PORT_A_write_enable_reg, HE1_q_b[4]_PORT_B_write_enable_reg, , , HE1_q_b[4]_clock_0, , , , , );
HE1_q_b[4] = HE1_q_b[4]_PORT_B_data_out[0];
 
--HE1_q_a[7] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[7] at M4K_X17_Y11
HE1_q_a[4]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[4]_PORT_A_data_in_reg = DFFE(HE1_q_a[4]_PORT_A_data_in, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_data_in = BUS(TB1_dout_1_x_4, TB1_dout_1_x_7);
HE1_q_a[4]_PORT_B_data_in_reg = DFFE(HE1_q_a[4]_PORT_B_data_in, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[4]_PORT_A_address_reg = DFFE(HE1_q_a[4]_PORT_A_address, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[4]_PORT_B_address_reg = DFFE(HE1_q_a[4]_PORT_B_address, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_A_write_enable = GND;
HE1_q_a[4]_PORT_A_write_enable_reg = DFFE(HE1_q_a[4]_PORT_A_write_enable, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_PORT_B_write_enable = WB2L2;
HE1_q_a[4]_PORT_B_write_enable_reg = DFFE(HE1_q_a[4]_PORT_B_write_enable, HE1_q_a[4]_clock_0, , , );
HE1_q_a[4]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[4]_PORT_A_data_out = MEMORY(HE1_q_a[4]_PORT_A_data_in_reg, HE1_q_a[4]_PORT_B_data_in_reg, HE1_q_a[4]_PORT_A_address_reg, HE1_q_a[4]_PORT_B_address_reg, HE1_q_a[4]_PORT_A_write_enable_reg, HE1_q_a[4]_PORT_B_write_enable_reg, , , HE1_q_a[4]_clock_0, , , , , );
HE1_q_a[7] = HE1_q_a[4]_PORT_A_data_out[1];
 
--HE1_q_b[7] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[7] at M4K_X17_Y11
HE1_q_b[4]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[4]_PORT_A_data_in_reg = DFFE(HE1_q_b[4]_PORT_A_data_in, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_data_in = BUS(TB1_dout_1_x_4, TB1_dout_1_x_7);
HE1_q_b[4]_PORT_B_data_in_reg = DFFE(HE1_q_b[4]_PORT_B_data_in, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[4]_PORT_A_address_reg = DFFE(HE1_q_b[4]_PORT_A_address, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[4]_PORT_B_address_reg = DFFE(HE1_q_b[4]_PORT_B_address, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_A_write_enable = GND;
HE1_q_b[4]_PORT_A_write_enable_reg = DFFE(HE1_q_b[4]_PORT_A_write_enable, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_PORT_B_write_enable = WB2L2;
HE1_q_b[4]_PORT_B_write_enable_reg = DFFE(HE1_q_b[4]_PORT_B_write_enable, HE1_q_b[4]_clock_0, , , );
HE1_q_b[4]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[4]_PORT_B_data_out = MEMORY(HE1_q_b[4]_PORT_A_data_in_reg, HE1_q_b[4]_PORT_B_data_in_reg, HE1_q_b[4]_PORT_A_address_reg, HE1_q_b[4]_PORT_B_address_reg, HE1_q_b[4]_PORT_A_write_enable_reg, HE1_q_b[4]_PORT_B_write_enable_reg, , , HE1_q_b[4]_clock_0, , , , , );
HE1_q_b[7] = HE1_q_b[4]_PORT_B_data_out[1];
 
 
--F1_dout_0_0_a3_6_5_14_a[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_5_14_a[0] at LC_X33_Y13_N2
--operation mode is normal
 
sys_rst_qfbk = sys_rst;
F1_dout_0_0_a3_6_5_14_a[0] = AB1_r32_o_1 & !AB1_r32_o_11 & sys_rst_qfbk & !AB1_r32_o_28;
 
--sys_rst is sys_rst at LC_X33_Y13_N2
--operation mode is normal
 
sys_rst = DFFEAS(F1_dout_0_0_a3_6_5_14_a[0], GLOBAL(E1__clk0), VCC, , , r_rst, , , VCC);
 
 
--F1_dout_0_0_a3_6_3[0] is mips_sys:isys|mips_dvc:imips_dvc|dout_0_0_a3_6_3[0] at LC_X33_Y13_N6
--operation mode is normal
 
JC1_dmem_ctl_o_1_qfbk = JC1_dmem_ctl_o_1;
F1_dout_0_0_a3_6_3[0] = JC1_dmem_ctl_o_2 & AB1_r32_o_2 & JC1_dmem_ctl_o_1_qfbk & !JC1_dmem_ctl_o_0;
 
--JC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_1 at LC_X33_Y13_N6
--operation mode is normal
 
JC1_dmem_ctl_o_1 = DFFEAS(F1_dout_0_0_a3_6_3[0], GLOBAL(E1__clk0), VCC, , , QC1_dmem_ctl_o_1, , , VCC);
 
 
--M1_ua_state_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_2 at LC_X33_Y15_N5
--operation mode is normal
 
M1_ua_state_2_lut_out = M1_ua_state_2 & !M1_clk_ctr_equ15_0_a2 # !M1_ua_state_2 & M1_ua_state[2] & M1_clk_ctr_equ15_0_a2 & !M1_ua_state_ns_0_a[2];
M1_ua_state_2 = DFFEAS(M1_ua_state_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--M1_clk_ctr_equ15_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_equ15_0_a2 at LC_X33_Y16_N9
--operation mode is normal
 
M1_clk_ctr_equ15_0_a2 = M1_clk_ctr_equ15_0_a2_a & M1_un1_clk_ctr_equ0_0_a2_0 & M1_un1_clk_ctr_equ0_0_a2 & M1_clk_ctr_0;
 
 
--TB1_dout_1_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_3 at LC_X22_Y15_N9
--operation mode is normal
 
TB1_dout_1_3 = TB1_dout21 & CB1_dout_2_3 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_3 # !TB1_dout22 & CB1_dout_2_19;
 
 
--HE1_q_a[3] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[3] at M4K_X17_Y20
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
HE1_q_a[3]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[3]_PORT_A_data_in_reg = DFFE(HE1_q_a[3]_PORT_A_data_in, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_data_in = BUS(TB1_dout_1_x_3, TB1_dout_1_x_0);
HE1_q_a[3]_PORT_B_data_in_reg = DFFE(HE1_q_a[3]_PORT_B_data_in, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[3]_PORT_A_address_reg = DFFE(HE1_q_a[3]_PORT_A_address, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[3]_PORT_B_address_reg = DFFE(HE1_q_a[3]_PORT_B_address, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_A_write_enable = GND;
HE1_q_a[3]_PORT_A_write_enable_reg = DFFE(HE1_q_a[3]_PORT_A_write_enable, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_write_enable = WB2L2;
HE1_q_a[3]_PORT_B_write_enable_reg = DFFE(HE1_q_a[3]_PORT_B_write_enable, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[3]_PORT_A_data_out = MEMORY(HE1_q_a[3]_PORT_A_data_in_reg, HE1_q_a[3]_PORT_B_data_in_reg, HE1_q_a[3]_PORT_A_address_reg, HE1_q_a[3]_PORT_B_address_reg, HE1_q_a[3]_PORT_A_write_enable_reg, HE1_q_a[3]_PORT_B_write_enable_reg, , , HE1_q_a[3]_clock_0, , , , , );
HE1_q_a[3] = HE1_q_a[3]_PORT_A_data_out[0];
 
--HE1_q_b[3] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[3] at M4K_X17_Y20
HE1_q_b[3]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[3]_PORT_A_data_in_reg = DFFE(HE1_q_b[3]_PORT_A_data_in, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_data_in = BUS(TB1_dout_1_x_3, TB1_dout_1_x_0);
HE1_q_b[3]_PORT_B_data_in_reg = DFFE(HE1_q_b[3]_PORT_B_data_in, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[3]_PORT_A_address_reg = DFFE(HE1_q_b[3]_PORT_A_address, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[3]_PORT_B_address_reg = DFFE(HE1_q_b[3]_PORT_B_address, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_A_write_enable = GND;
HE1_q_b[3]_PORT_A_write_enable_reg = DFFE(HE1_q_b[3]_PORT_A_write_enable, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_write_enable = WB2L2;
HE1_q_b[3]_PORT_B_write_enable_reg = DFFE(HE1_q_b[3]_PORT_B_write_enable, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[3]_PORT_B_data_out = MEMORY(HE1_q_b[3]_PORT_A_data_in_reg, HE1_q_b[3]_PORT_B_data_in_reg, HE1_q_b[3]_PORT_A_address_reg, HE1_q_b[3]_PORT_B_address_reg, HE1_q_b[3]_PORT_A_write_enable_reg, HE1_q_b[3]_PORT_B_write_enable_reg, , , HE1_q_b[3]_clock_0, , , , , );
HE1_q_b[3] = HE1_q_b[3]_PORT_B_data_out[0];
 
--HE1_q_a[0] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[0] at M4K_X17_Y20
HE1_q_a[3]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[3]_PORT_A_data_in_reg = DFFE(HE1_q_a[3]_PORT_A_data_in, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_data_in = BUS(TB1_dout_1_x_3, TB1_dout_1_x_0);
HE1_q_a[3]_PORT_B_data_in_reg = DFFE(HE1_q_a[3]_PORT_B_data_in, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[3]_PORT_A_address_reg = DFFE(HE1_q_a[3]_PORT_A_address, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[3]_PORT_B_address_reg = DFFE(HE1_q_a[3]_PORT_B_address, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_A_write_enable = GND;
HE1_q_a[3]_PORT_A_write_enable_reg = DFFE(HE1_q_a[3]_PORT_A_write_enable, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_PORT_B_write_enable = WB2L2;
HE1_q_a[3]_PORT_B_write_enable_reg = DFFE(HE1_q_a[3]_PORT_B_write_enable, HE1_q_a[3]_clock_0, , , );
HE1_q_a[3]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[3]_PORT_A_data_out = MEMORY(HE1_q_a[3]_PORT_A_data_in_reg, HE1_q_a[3]_PORT_B_data_in_reg, HE1_q_a[3]_PORT_A_address_reg, HE1_q_a[3]_PORT_B_address_reg, HE1_q_a[3]_PORT_A_write_enable_reg, HE1_q_a[3]_PORT_B_write_enable_reg, , , HE1_q_a[3]_clock_0, , , , , );
HE1_q_a[0] = HE1_q_a[3]_PORT_A_data_out[1];
 
--HE1_q_b[0] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[0] at M4K_X17_Y20
HE1_q_b[3]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[3]_PORT_A_data_in_reg = DFFE(HE1_q_b[3]_PORT_A_data_in, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_data_in = BUS(TB1_dout_1_x_3, TB1_dout_1_x_0);
HE1_q_b[3]_PORT_B_data_in_reg = DFFE(HE1_q_b[3]_PORT_B_data_in, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[3]_PORT_A_address_reg = DFFE(HE1_q_b[3]_PORT_A_address, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[3]_PORT_B_address_reg = DFFE(HE1_q_b[3]_PORT_B_address, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_A_write_enable = GND;
HE1_q_b[3]_PORT_A_write_enable_reg = DFFE(HE1_q_b[3]_PORT_A_write_enable, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_PORT_B_write_enable = WB2L2;
HE1_q_b[3]_PORT_B_write_enable_reg = DFFE(HE1_q_b[3]_PORT_B_write_enable, HE1_q_b[3]_clock_0, , , );
HE1_q_b[3]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[3]_PORT_B_data_out = MEMORY(HE1_q_b[3]_PORT_A_data_in_reg, HE1_q_b[3]_PORT_B_data_in_reg, HE1_q_b[3]_PORT_A_address_reg, HE1_q_b[3]_PORT_B_address_reg, HE1_q_b[3]_PORT_A_write_enable_reg, HE1_q_b[3]_PORT_B_write_enable_reg, , , HE1_q_b[3]_clock_0, , , , , );
HE1_q_b[0] = HE1_q_b[3]_PORT_B_data_out[1];
 
 
--TB1_dout_1_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2 at LC_X29_Y6_N4
--operation mode is normal
 
TB1_dout_1_2 = TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_2 # !TB1_dout22 & CB1_dout_2_18;
 
 
--HE1_q_a[2] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[2] at M4K_X17_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
HE1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[2]_PORT_A_data_in_reg = DFFE(HE1_q_a[2]_PORT_A_data_in, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_data_in = BUS(TB1_dout_1_x_2, TB1_dout_1_x_1);
HE1_q_a[2]_PORT_B_data_in_reg = DFFE(HE1_q_a[2]_PORT_B_data_in, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[2]_PORT_A_address_reg = DFFE(HE1_q_a[2]_PORT_A_address, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[2]_PORT_B_address_reg = DFFE(HE1_q_a[2]_PORT_B_address, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_A_write_enable = GND;
HE1_q_a[2]_PORT_A_write_enable_reg = DFFE(HE1_q_a[2]_PORT_A_write_enable, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_write_enable = WB2L2;
HE1_q_a[2]_PORT_B_write_enable_reg = DFFE(HE1_q_a[2]_PORT_B_write_enable, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[2]_PORT_A_data_out = MEMORY(HE1_q_a[2]_PORT_A_data_in_reg, HE1_q_a[2]_PORT_B_data_in_reg, HE1_q_a[2]_PORT_A_address_reg, HE1_q_a[2]_PORT_B_address_reg, HE1_q_a[2]_PORT_A_write_enable_reg, HE1_q_a[2]_PORT_B_write_enable_reg, , , HE1_q_a[2]_clock_0, , , , , );
HE1_q_a[2] = HE1_q_a[2]_PORT_A_data_out[0];
 
--HE1_q_b[2] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[2] at M4K_X17_Y7
HE1_q_b[2]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[2]_PORT_A_data_in_reg = DFFE(HE1_q_b[2]_PORT_A_data_in, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_data_in = BUS(TB1_dout_1_x_2, TB1_dout_1_x_1);
HE1_q_b[2]_PORT_B_data_in_reg = DFFE(HE1_q_b[2]_PORT_B_data_in, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[2]_PORT_A_address_reg = DFFE(HE1_q_b[2]_PORT_A_address, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[2]_PORT_B_address_reg = DFFE(HE1_q_b[2]_PORT_B_address, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_A_write_enable = GND;
HE1_q_b[2]_PORT_A_write_enable_reg = DFFE(HE1_q_b[2]_PORT_A_write_enable, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_write_enable = WB2L2;
HE1_q_b[2]_PORT_B_write_enable_reg = DFFE(HE1_q_b[2]_PORT_B_write_enable, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[2]_PORT_B_data_out = MEMORY(HE1_q_b[2]_PORT_A_data_in_reg, HE1_q_b[2]_PORT_B_data_in_reg, HE1_q_b[2]_PORT_A_address_reg, HE1_q_b[2]_PORT_B_address_reg, HE1_q_b[2]_PORT_A_write_enable_reg, HE1_q_b[2]_PORT_B_write_enable_reg, , , HE1_q_b[2]_clock_0, , , , , );
HE1_q_b[2] = HE1_q_b[2]_PORT_B_data_out[0];
 
--HE1_q_a[1] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_a[1] at M4K_X17_Y7
HE1_q_a[2]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_a[2]_PORT_A_data_in_reg = DFFE(HE1_q_a[2]_PORT_A_data_in, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_data_in = BUS(TB1_dout_1_x_2, TB1_dout_1_x_1);
HE1_q_a[2]_PORT_B_data_in_reg = DFFE(HE1_q_a[2]_PORT_B_data_in, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_a[2]_PORT_A_address_reg = DFFE(HE1_q_a[2]_PORT_A_address, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_a[2]_PORT_B_address_reg = DFFE(HE1_q_a[2]_PORT_B_address, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_A_write_enable = GND;
HE1_q_a[2]_PORT_A_write_enable_reg = DFFE(HE1_q_a[2]_PORT_A_write_enable, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_PORT_B_write_enable = WB2L2;
HE1_q_a[2]_PORT_B_write_enable_reg = DFFE(HE1_q_a[2]_PORT_B_write_enable, HE1_q_a[2]_clock_0, , , );
HE1_q_a[2]_clock_0 = GLOBAL(E1__clk0);
HE1_q_a[2]_PORT_A_data_out = MEMORY(HE1_q_a[2]_PORT_A_data_in_reg, HE1_q_a[2]_PORT_B_data_in_reg, HE1_q_a[2]_PORT_A_address_reg, HE1_q_a[2]_PORT_B_address_reg, HE1_q_a[2]_PORT_A_write_enable_reg, HE1_q_a[2]_PORT_B_write_enable_reg, , , HE1_q_a[2]_clock_0, , , , , );
HE1_q_a[1] = HE1_q_a[2]_PORT_A_data_out[1];
 
--HE1_q_b[1] is mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|q_b[1] at M4K_X17_Y7
HE1_q_b[2]_PORT_A_data_in = BUS(~GND, ~GND);
HE1_q_b[2]_PORT_A_data_in_reg = DFFE(HE1_q_b[2]_PORT_A_data_in, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_data_in = BUS(TB1_dout_1_x_2, TB1_dout_1_x_1);
HE1_q_b[2]_PORT_B_data_in_reg = DFFE(HE1_q_b[2]_PORT_B_data_in, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
HE1_q_b[2]_PORT_A_address_reg = DFFE(HE1_q_b[2]_PORT_A_address, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
HE1_q_b[2]_PORT_B_address_reg = DFFE(HE1_q_b[2]_PORT_B_address, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_A_write_enable = GND;
HE1_q_b[2]_PORT_A_write_enable_reg = DFFE(HE1_q_b[2]_PORT_A_write_enable, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_PORT_B_write_enable = WB2L2;
HE1_q_b[2]_PORT_B_write_enable_reg = DFFE(HE1_q_b[2]_PORT_B_write_enable, HE1_q_b[2]_clock_0, , , );
HE1_q_b[2]_clock_0 = GLOBAL(E1__clk0);
HE1_q_b[2]_PORT_B_data_out = MEMORY(HE1_q_b[2]_PORT_A_data_in_reg, HE1_q_b[2]_PORT_B_data_in_reg, HE1_q_b[2]_PORT_A_address_reg, HE1_q_b[2]_PORT_B_address_reg, HE1_q_b[2]_PORT_A_write_enable_reg, HE1_q_b[2]_PORT_B_write_enable_reg, , , HE1_q_b[2]_clock_0, , , , , );
HE1_q_b[1] = HE1_q_b[2]_PORT_B_data_out[1];
 
 
--TB1_dout_1_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_1 at LC_X25_Y3_N0
--operation mode is normal
 
TB1_dout_1_1 = TB1_dout21 & CB1_dout_2_1 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_1 # !TB1_dout22 & CB1_dout_2_17;
 
 
--GE1_q_a[1] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[1] at M4K_X17_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
GE1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[1]_PORT_A_data_in_reg = DFFE(GE1_q_a[1]_PORT_A_data_in, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_data_in = BUS(CB1_dout_2_1, CB1_dout_2_0);
GE1_q_a[1]_PORT_B_data_in_reg = DFFE(GE1_q_a[1]_PORT_B_data_in, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[1]_PORT_A_address_reg = DFFE(GE1_q_a[1]_PORT_A_address, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[1]_PORT_B_address_reg = DFFE(GE1_q_a[1]_PORT_B_address, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_A_write_enable = GND;
GE1_q_a[1]_PORT_A_write_enable_reg = DFFE(GE1_q_a[1]_PORT_A_write_enable, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_write_enable = WB1L2;
GE1_q_a[1]_PORT_B_write_enable_reg = DFFE(GE1_q_a[1]_PORT_B_write_enable, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[1]_PORT_A_data_out = MEMORY(GE1_q_a[1]_PORT_A_data_in_reg, GE1_q_a[1]_PORT_B_data_in_reg, GE1_q_a[1]_PORT_A_address_reg, GE1_q_a[1]_PORT_B_address_reg, GE1_q_a[1]_PORT_A_write_enable_reg, GE1_q_a[1]_PORT_B_write_enable_reg, , , GE1_q_a[1]_clock_0, , , , , );
GE1_q_a[1] = GE1_q_a[1]_PORT_A_data_out[0];
 
--GE1_q_b[1] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[1] at M4K_X17_Y10
GE1_q_b[1]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[1]_PORT_A_data_in_reg = DFFE(GE1_q_b[1]_PORT_A_data_in, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_data_in = BUS(CB1_dout_2_1, CB1_dout_2_0);
GE1_q_b[1]_PORT_B_data_in_reg = DFFE(GE1_q_b[1]_PORT_B_data_in, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[1]_PORT_A_address_reg = DFFE(GE1_q_b[1]_PORT_A_address, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[1]_PORT_B_address_reg = DFFE(GE1_q_b[1]_PORT_B_address, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_A_write_enable = GND;
GE1_q_b[1]_PORT_A_write_enable_reg = DFFE(GE1_q_b[1]_PORT_A_write_enable, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_write_enable = WB1L2;
GE1_q_b[1]_PORT_B_write_enable_reg = DFFE(GE1_q_b[1]_PORT_B_write_enable, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[1]_PORT_B_data_out = MEMORY(GE1_q_b[1]_PORT_A_data_in_reg, GE1_q_b[1]_PORT_B_data_in_reg, GE1_q_b[1]_PORT_A_address_reg, GE1_q_b[1]_PORT_B_address_reg, GE1_q_b[1]_PORT_A_write_enable_reg, GE1_q_b[1]_PORT_B_write_enable_reg, , , GE1_q_b[1]_clock_0, , , , , );
GE1_q_b[1] = GE1_q_b[1]_PORT_B_data_out[0];
 
--GE1_q_a[0] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_a[0] at M4K_X17_Y10
GE1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_a[1]_PORT_A_data_in_reg = DFFE(GE1_q_a[1]_PORT_A_data_in, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_data_in = BUS(CB1_dout_2_1, CB1_dout_2_0);
GE1_q_a[1]_PORT_B_data_in_reg = DFFE(GE1_q_a[1]_PORT_B_data_in, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_a[1]_PORT_A_address_reg = DFFE(GE1_q_a[1]_PORT_A_address, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_a[1]_PORT_B_address_reg = DFFE(GE1_q_a[1]_PORT_B_address, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_A_write_enable = GND;
GE1_q_a[1]_PORT_A_write_enable_reg = DFFE(GE1_q_a[1]_PORT_A_write_enable, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_PORT_B_write_enable = WB1L2;
GE1_q_a[1]_PORT_B_write_enable_reg = DFFE(GE1_q_a[1]_PORT_B_write_enable, GE1_q_a[1]_clock_0, , , );
GE1_q_a[1]_clock_0 = GLOBAL(E1__clk0);
GE1_q_a[1]_PORT_A_data_out = MEMORY(GE1_q_a[1]_PORT_A_data_in_reg, GE1_q_a[1]_PORT_B_data_in_reg, GE1_q_a[1]_PORT_A_address_reg, GE1_q_a[1]_PORT_B_address_reg, GE1_q_a[1]_PORT_A_write_enable_reg, GE1_q_a[1]_PORT_B_write_enable_reg, , , GE1_q_a[1]_clock_0, , , , , );
GE1_q_a[0] = GE1_q_a[1]_PORT_A_data_out[1];
 
--GE1_q_b[0] is mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|q_b[0] at M4K_X17_Y10
GE1_q_b[1]_PORT_A_data_in = BUS(~GND, ~GND);
GE1_q_b[1]_PORT_A_data_in_reg = DFFE(GE1_q_b[1]_PORT_A_data_in, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_data_in = BUS(CB1_dout_2_1, CB1_dout_2_0);
GE1_q_b[1]_PORT_B_data_in_reg = DFFE(GE1_q_b[1]_PORT_B_data_in, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
GE1_q_b[1]_PORT_A_address_reg = DFFE(GE1_q_b[1]_PORT_A_address, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
GE1_q_b[1]_PORT_B_address_reg = DFFE(GE1_q_b[1]_PORT_B_address, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_A_write_enable = GND;
GE1_q_b[1]_PORT_A_write_enable_reg = DFFE(GE1_q_b[1]_PORT_A_write_enable, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_PORT_B_write_enable = WB1L2;
GE1_q_b[1]_PORT_B_write_enable_reg = DFFE(GE1_q_b[1]_PORT_B_write_enable, GE1_q_b[1]_clock_0, , , );
GE1_q_b[1]_clock_0 = GLOBAL(E1__clk0);
GE1_q_b[1]_PORT_B_data_out = MEMORY(GE1_q_b[1]_PORT_A_data_in_reg, GE1_q_b[1]_PORT_B_data_in_reg, GE1_q_b[1]_PORT_A_address_reg, GE1_q_b[1]_PORT_B_address_reg, GE1_q_b[1]_PORT_A_write_enable_reg, GE1_q_b[1]_PORT_B_write_enable_reg, , , GE1_q_b[1]_clock_0, , , , , );
GE1_q_b[0] = GE1_q_b[1]_PORT_B_data_out[1];
 
 
--KE1_q_a[1] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[1] at M4K_X17_Y12
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KE1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[1]_PORT_A_data_in_reg = DFFE(KE1_q_a[1]_PORT_A_data_in, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_data_in = BUS(TB1_dout_1_2_1, TB1_dout_1_2_0);
KE1_q_a[1]_PORT_B_data_in_reg = DFFE(KE1_q_a[1]_PORT_B_data_in, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[1]_PORT_A_address_reg = DFFE(KE1_q_a[1]_PORT_A_address, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[1]_PORT_B_address_reg = DFFE(KE1_q_a[1]_PORT_B_address, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_A_write_enable = GND;
KE1_q_a[1]_PORT_A_write_enable_reg = DFFE(KE1_q_a[1]_PORT_A_write_enable, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_write_enable = WB4L2;
KE1_q_a[1]_PORT_B_write_enable_reg = DFFE(KE1_q_a[1]_PORT_B_write_enable, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[1]_PORT_A_data_out = MEMORY(KE1_q_a[1]_PORT_A_data_in_reg, KE1_q_a[1]_PORT_B_data_in_reg, KE1_q_a[1]_PORT_A_address_reg, KE1_q_a[1]_PORT_B_address_reg, KE1_q_a[1]_PORT_A_write_enable_reg, KE1_q_a[1]_PORT_B_write_enable_reg, , , KE1_q_a[1]_clock_0, , , , , );
KE1_q_a[1] = KE1_q_a[1]_PORT_A_data_out[0];
 
--KE1_q_b[1] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[1] at M4K_X17_Y12
KE1_q_b[1]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[1]_PORT_A_data_in_reg = DFFE(KE1_q_b[1]_PORT_A_data_in, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_data_in = BUS(TB1_dout_1_2_1, TB1_dout_1_2_0);
KE1_q_b[1]_PORT_B_data_in_reg = DFFE(KE1_q_b[1]_PORT_B_data_in, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[1]_PORT_A_address_reg = DFFE(KE1_q_b[1]_PORT_A_address, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[1]_PORT_B_address_reg = DFFE(KE1_q_b[1]_PORT_B_address, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_A_write_enable = GND;
KE1_q_b[1]_PORT_A_write_enable_reg = DFFE(KE1_q_b[1]_PORT_A_write_enable, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_write_enable = WB4L2;
KE1_q_b[1]_PORT_B_write_enable_reg = DFFE(KE1_q_b[1]_PORT_B_write_enable, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[1]_PORT_B_data_out = MEMORY(KE1_q_b[1]_PORT_A_data_in_reg, KE1_q_b[1]_PORT_B_data_in_reg, KE1_q_b[1]_PORT_A_address_reg, KE1_q_b[1]_PORT_B_address_reg, KE1_q_b[1]_PORT_A_write_enable_reg, KE1_q_b[1]_PORT_B_write_enable_reg, , , KE1_q_b[1]_clock_0, , , , , );
KE1_q_b[1] = KE1_q_b[1]_PORT_B_data_out[0];
 
--KE1_q_a[0] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[0] at M4K_X17_Y12
KE1_q_a[1]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_a[1]_PORT_A_data_in_reg = DFFE(KE1_q_a[1]_PORT_A_data_in, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_data_in = BUS(TB1_dout_1_2_1, TB1_dout_1_2_0);
KE1_q_a[1]_PORT_B_data_in_reg = DFFE(KE1_q_a[1]_PORT_B_data_in, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_a[1]_PORT_A_address_reg = DFFE(KE1_q_a[1]_PORT_A_address, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_a[1]_PORT_B_address_reg = DFFE(KE1_q_a[1]_PORT_B_address, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_A_write_enable = GND;
KE1_q_a[1]_PORT_A_write_enable_reg = DFFE(KE1_q_a[1]_PORT_A_write_enable, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_PORT_B_write_enable = WB4L2;
KE1_q_a[1]_PORT_B_write_enable_reg = DFFE(KE1_q_a[1]_PORT_B_write_enable, KE1_q_a[1]_clock_0, , , );
KE1_q_a[1]_clock_0 = GLOBAL(E1__clk0);
KE1_q_a[1]_PORT_A_data_out = MEMORY(KE1_q_a[1]_PORT_A_data_in_reg, KE1_q_a[1]_PORT_B_data_in_reg, KE1_q_a[1]_PORT_A_address_reg, KE1_q_a[1]_PORT_B_address_reg, KE1_q_a[1]_PORT_A_write_enable_reg, KE1_q_a[1]_PORT_B_write_enable_reg, , , KE1_q_a[1]_clock_0, , , , , );
KE1_q_a[0] = KE1_q_a[1]_PORT_A_data_out[1];
 
--KE1_q_b[0] is mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_b[0] at M4K_X17_Y12
KE1_q_b[1]_PORT_A_data_in = BUS(~GND, ~GND);
KE1_q_b[1]_PORT_A_data_in_reg = DFFE(KE1_q_b[1]_PORT_A_data_in, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_data_in = BUS(TB1_dout_1_2_1, TB1_dout_1_2_0);
KE1_q_b[1]_PORT_B_data_in_reg = DFFE(KE1_q_b[1]_PORT_B_data_in, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_A_address = BUS(KB1_pc_next_0_iv_2, KB1_pc_next_0_iv_3, KB1_pc_next_0_iv_4, KB1_pc_next_0_iv_5, KB1_pc_next_0_iv_6, KB1_pc_next_0_iv_7, KB1_pc_next_0_iv_8, KB1_pc_next_0_iv_9, KB1_pc_next_0_iv_10, KB1_pc_next_0_iv_11, KB1_pc_next_0_iv_12);
KE1_q_b[1]_PORT_A_address_reg = DFFE(KE1_q_b[1]_PORT_A_address, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_address = BUS(AB1_c_0, AB1_c_1, AB1_c_2, AB1_c_3, AB1_c_4, AB1_c_5, AB1_c_6, AB1_c_7, AB1_c_8, AB1_c_9, AB1_c_10);
KE1_q_b[1]_PORT_B_address_reg = DFFE(KE1_q_b[1]_PORT_B_address, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_A_write_enable = GND;
KE1_q_b[1]_PORT_A_write_enable_reg = DFFE(KE1_q_b[1]_PORT_A_write_enable, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_PORT_B_write_enable = WB4L2;
KE1_q_b[1]_PORT_B_write_enable_reg = DFFE(KE1_q_b[1]_PORT_B_write_enable, KE1_q_b[1]_clock_0, , , );
KE1_q_b[1]_clock_0 = GLOBAL(E1__clk0);
KE1_q_b[1]_PORT_B_data_out = MEMORY(KE1_q_b[1]_PORT_A_data_in_reg, KE1_q_b[1]_PORT_B_data_in_reg, KE1_q_b[1]_PORT_A_address_reg, KE1_q_b[1]_PORT_B_address_reg, KE1_q_b[1]_PORT_A_write_enable_reg, KE1_q_b[1]_PORT_B_write_enable_reg, , , KE1_q_b[1]_clock_0, , , , , );
KE1_q_b[0] = KE1_q_b[1]_PORT_B_data_out[1];
 
 
--UD1_shift_out_80_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[1] at LC_X16_Y17_N1
--operation mode is normal
 
UD1_shift_out_80_a[1] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_4 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_2;
 
 
--UD1_shift_out_82_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[1] at LC_X16_Y17_N3
--operation mode is normal
 
UD1_shift_out_82_a[1] = PD1_a_o_2 & !VD1_b_o_iv_5 # !PD1_a_o_2 & !VD1_b_o_iv_3;
 
 
--UD1_shift_out_41[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_41[1] at LC_X14_Y13_N2
--operation mode is normal
 
UD1_shift_out_41[1] = PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & UD1_shift_out_39[17];
 
 
--UD1_shift_out_74_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[1] at LC_X14_Y13_N8
--operation mode is normal
 
UD1_shift_out_74_a[1] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_79[13] # !PD1_a_o_2 & !UD1_shift_out_79[9];
 
 
--UD1_shift_out_79[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[1] at LC_X15_Y13_N7
--operation mode is normal
 
UD1_shift_out_79[1] = PD1_a_o_1 & UD1_shift_out_79_a[1] & VD1_b_o_iv_11 # !UD1_shift_out_79_a[1] & VD1_b_o_iv_12 # !PD1_a_o_1 & !UD1_shift_out_79_a[1];
 
 
--UD1_shift_out_76_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[1] at LC_X15_Y13_N3
--operation mode is normal
 
UD1_shift_out_76_a[1] = PD1_a_o_3 & !UD1_shift_out_59[1] # !PD1_a_o_3 & UD1_shift_out587 & !UD1_shift_out_79[13] # !UD1_shift_out587 & !UD1_shift_out_59[1];
 
 
--VD1_hilo_37_iv_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[1] at LC_X5_Y17_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a[1] = VD1_hilo_2_sqmuxa & !VD1_hilo[0] & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2 # !VD1_hilo_2_sqmuxa & !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2;
 
 
--VD1_hilo_37_iv_0_0[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[1] at LC_X5_Y17_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[1] = VD1_hilo_1 & VD1_hilo_37_iv_0_o5[0] # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[1] # !VD1_hilo_1 & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[1];
 
 
--VD1_hilo_37_iv_2[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[33] at LC_X8_Y7_N2
--operation mode is normal
 
VD1_hilo_37_iv_2[33] = VD1_hilo_33_i_m[33] # VD1_hilo_37_iv_2_a[33] # !VD1_hilo_22_Z[33] & VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[33] at LC_X8_Y8_N9
--operation mode is normal
 
VD1_hilo_37_iv_a[33] = RC1_alu_func_o_0 & !PD1_a_o_1 # !RC1_alu_func_o_0 & !VD1_hilo_33;
 
 
--TD1_alu_out_6_0_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_6_0_a[1] at LC_X15_Y9_N3
--operation mode is normal
 
TD1_alu_out_6_0_a[1] = RC1_alu_func_o_0 & !VD1_b_o_iv_1 & !PD1_a_o_1 # !RC1_alu_func_o_0 & VD1_b_o_iv_1 $ PD1_a_o_1;
 
 
--TB1_dout_1_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_0 at LC_X29_Y6_N0
--operation mode is normal
 
TB1_dout_1_0 = TB1_dout21 & CB1_dout_2_0 # !TB1_dout21 & TB1_dout22 & CB1_dout_2_0 # !TB1_dout22 & CB1_dout_2_16;
 
 
--VD1_hilo[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[32] at LC_X8_Y10_N4
--operation mode is normal
 
VD1_hilo[32]_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_2[32] & !VD1_hilo_37_iv_a[32] # !VD1_hilo25;
VD1_hilo[32] = DFFEAS(VD1_hilo[32]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[0] at LC_X6_Y13_N2
--operation mode is normal
 
VD1_hilo[0]_lut_out = PD1_a_o_0 & VD1_hilo_37_iv_0_a3_1[62] # VD1_addnop2109_0_a2 # !VD1_hilo_37_iv_0_a[0];
VD1_hilo[0] = DFFEAS(VD1_hilo[0]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--UD1_shift_out_79[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[0] at LC_X20_Y13_N6
--operation mode is normal
 
UD1_shift_out_79[0] = PD1_a_o_1 & UD1_shift_out_79_a[0] & VD1_b_o_iv_10 # !UD1_shift_out_79_a[0] & VD1_b_o_iv_11 # !PD1_a_o_1 & !UD1_shift_out_79_a[0];
 
 
--UD1_shift_out_76_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[0] at LC_X21_Y13_N7
--operation mode is normal
 
UD1_shift_out_76_a[0] = PD1_a_o_3 & !UD1_shift_out_79[20] # !PD1_a_o_3 & !UD1_shift_out_47[0];
 
 
--UD1_shift_out_80[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[0] at LC_X15_Y11_N2
--operation mode is normal
 
UD1_shift_out_80[0] = PD1_a_o_2 & UD1_shift_out_80_a[0] & VD1_b_o_iv_5 # !UD1_shift_out_80_a[0] & VD1_b_o_iv_7 # !PD1_a_o_2 & !UD1_shift_out_80_a[0];
 
 
--UD1_shift_out_82[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82[0] at LC_X15_Y11_N5
--operation mode is normal
 
UD1_shift_out_82[0] = PD1_a_o_1 & PD1_a_o_2 & VD1_b_o_iv_6 # !PD1_a_o_2 & !UD1_shift_out_82_a[0] # !PD1_a_o_1 & !UD1_shift_out_82_a[0];
 
 
--UD1_shift_out_86_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[0] at LC_X19_Y13_N5
--operation mode is normal
 
UD1_shift_out_86_a[0] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_79[4] # !PD1_a_o_2 & !UD1_shift_out_79[8] # !UD1_shift_out587 & !UD1_shift_out_79[4];
 
 
--UD1_shift_out_74[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[0] at LC_X19_Y13_N2
--operation mode is normal
 
UD1_shift_out_74[0] = UD1_shift_out_74_a[0] & PD1_a_o_3 & UD1_shift_out_79[16] # !UD1_shift_out_74_a[0] & UD1_shift_out_79[20] # !PD1_a_o_3;
 
 
--PD1_a_o_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[31] at LC_X19_Y3_N5
--operation mode is normal
 
PD1_a_o_a[31] = SC1_muxa_ctl_o_1 & !FB1_r32_o_31 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_31;
 
 
--PD1_a_o_3_Z[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[31] at LC_X19_Y3_N8
--operation mode is normal
 
SD1_r32_o_31_qfbk = SD1_r32_o_31;
PD1_a_o_3_Z[31] = PD1_a_o_3_s[0] & SD1_r32_o_31_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[31];
 
--SD1_r32_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_31 at LC_X19_Y3_N8
--operation mode is normal
 
SD1_r32_o_31 = DFFEAS(PD1_a_o_3_Z[31], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_31, , , VCC);
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] at LC_X22_Y16_N9
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[31] = QB1_r32_o_31 & !FB1_r32_o_31 & QD1_b_o18 # !QB1_r32_o_31 & QD1_un1_b_o18_2 # !FB1_r32_o_31 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[31] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[31] at LC_X22_Y16_N1
--operation mode is normal
 
G1_BUS15471_i_m[31] = QD1_b_o_1_sqmuxa & !FD1_wb_o_31;
 
 
--VD1_b_o_iv_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_30 at LC_X20_Y4_N8
--operation mode is normal
 
VD1_b_o_iv_30 = !G1_BUS15471_i_m[30] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] & AB1_r32_o_28 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[30] at LC_X20_Y4_N8
--operation mode is normal
 
VD1_op2_reged[30] = DFFEAS(VD1_b_o_iv_30, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--TD1_lt_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_29 at LC_X16_Y7_N3
--operation mode is arithmetic
 
TD1_lt_29_cout_0 = VD1_b_o_iv_29 & PD1_a_o_29 & !TD1_lt_28 # !VD1_b_o_iv_29 & PD1_a_o_29 # !TD1_lt_28;
TD1_lt_29 = CARRY(TD1_lt_29_cout_0);
 
--TD1L691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_29~COUT1_1 at LC_X16_Y7_N3
--operation mode is arithmetic
 
TD1L691_cout_1 = VD1_b_o_iv_29 & PD1_a_o_29 & !TD1L491 # !VD1_b_o_iv_29 & PD1_a_o_29 # !TD1L491;
TD1L691 = CARRY(TD1L691_cout_1);
 
 
--TD1_sum_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_30 at LC_X15_Y6_N4
--operation mode is arithmetic
 
TD1_sum_carry_30 = CARRY(PD1_a_o_30 & !TD1L144 # !VD1_b_o_iv_30 # !PD1_a_o_30 & !VD1_b_o_iv_30 & !TD1L144);
 
 
--N1_tx_sr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[6] at LC_X16_Y2_N0
--operation mode is normal
 
N1_tx_sr[6]_lut_out = N1_read_request_ff & Y1_q_b[6] # !N1_read_request_ff & N1_tx_sr[7];
N1_tx_sr[6] = DFFEAS(N1_tx_sr[6]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--K1_cntr_5_0[30] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[30] at LC_X32_Y5_N6
--operation mode is normal
 
K1_s_cntr_30__Z_qfbk = K1_s_cntr_30__Z;
K1_cntr_5_0[30] = F1_wr_tmr_data_0_a2 & CB1_r32_o_30 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_30__Z_qfbk;
 
--K1_s_cntr_30__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_30__Z at LC_X32_Y5_N6
--operation mode is normal
 
K1_s_cntr_30__Z = DFFEAS(K1_cntr_5_0[30], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_30, , , VCC);
 
 
--K1_cntr_5_0[31] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[31] at LC_X30_Y4_N7
--operation mode is normal
 
K1_s_cntr_31__Z_qfbk = K1_s_cntr_31__Z;
K1_cntr_5_0[31] = F1_wr_tmr_data_0_a2 & CB1_r32_o_31 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_31__Z_qfbk;
 
--K1_s_cntr_31__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_31__Z at LC_X30_Y4_N7
--operation mode is normal
 
K1_s_cntr_31__Z = DFFEAS(K1_cntr_5_0[31], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_31, , , VCC);
 
 
--K1_cntr_5_0[28] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[28] at LC_X27_Y13_N9
--operation mode is normal
 
K1_s_cntr_28__Z_qfbk = K1_s_cntr_28__Z;
K1_cntr_5_0[28] = F1_wr_tmr_data_0_a2 & CB1_r32_o_28 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_28__Z_qfbk;
 
--K1_s_cntr_28__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_28__Z at LC_X27_Y13_N9
--operation mode is normal
 
K1_s_cntr_28__Z = DFFEAS(K1_cntr_5_0[28], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_28, , , VCC);
 
 
--K1_cntr_27 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_27 at LC_X31_Y3_N1
--operation mode is arithmetic
 
K1_cntr_27_carry_eqn = (!K1_cntr_cout[25] & K1_cntr_cout[26]) # (K1_cntr_cout[25] & K1L641);
K1_cntr_27_lut_out = K1_cntr_27 $ (!K1_cntr_27_carry_eqn);
K1_cntr_27 = DFFEAS(K1_cntr_27_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[27], , , !K1_un1_ld_1);
 
--K1_cntr_cout[27] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[27] at LC_X31_Y3_N1
--operation mode is arithmetic
 
K1_cntr_cout[27]_cout_0 = !K1_cntr_27 & !K1_cntr_cout[26];
K1_cntr_cout[27] = CARRY(K1_cntr_cout[27]_cout_0);
 
--K1L841 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[27]~COUT1_22 at LC_X31_Y3_N1
--operation mode is arithmetic
 
K1L841_cout_1 = !K1_cntr_27 & !K1L641;
K1L841 = CARRY(K1L841_cout_1);
 
 
--K1_cntr_5_0[29] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[29] at LC_X32_Y5_N4
--operation mode is normal
 
K1_s_cntr_29__Z_qfbk = K1_s_cntr_29__Z;
K1_cntr_5_0[29] = F1_wr_tmr_data_0_a2 & CB1_r32_o_29 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_29__Z_qfbk;
 
--K1_s_cntr_29__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_29__Z at LC_X32_Y5_N4
--operation mode is normal
 
K1_s_cntr_29__Z = DFFEAS(K1_cntr_5_0[29], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_29, , , VCC);
 
 
--K1_cntr_18 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_18 at LC_X31_Y4_N2
--operation mode is arithmetic
 
K1_cntr_18_carry_eqn = (!K1_cntr_cout[15] & K1_cntr_cout[17]) # (K1_cntr_cout[15] & K1L031);
K1_cntr_18_lut_out = K1_cntr_18 $ (K1_cntr_18_carry_eqn);
K1_cntr_18 = DFFEAS(K1_cntr_18_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[18], , , !K1_un1_ld_1);
 
--K1_cntr_cout[18] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[18] at LC_X31_Y4_N2
--operation mode is arithmetic
 
K1_cntr_cout[18]_cout_0 = K1_cntr_18 # !K1_cntr_cout[17];
K1_cntr_cout[18] = CARRY(K1_cntr_cout[18]_cout_0);
 
--K1L231 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[18]~COUT1_15 at LC_X31_Y4_N2
--operation mode is arithmetic
 
K1L231_cout_1 = K1_cntr_18 # !K1L031;
K1L231 = CARRY(K1L231_cout_1);
 
 
--K1_cntr_19 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_19 at LC_X31_Y4_N3
--operation mode is arithmetic
 
K1_cntr_19_carry_eqn = (!K1_cntr_cout[15] & K1_cntr_cout[18]) # (K1_cntr_cout[15] & K1L231);
K1_cntr_19_lut_out = K1_cntr_19 $ !K1_cntr_19_carry_eqn;
K1_cntr_19 = DFFEAS(K1_cntr_19_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[19], , , !K1_un1_ld_1);
 
--K1_cntr_cout[19] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[19] at LC_X31_Y4_N3
--operation mode is arithmetic
 
K1_cntr_cout[19]_cout_0 = !K1_cntr_19 & !K1_cntr_cout[18];
K1_cntr_cout[19] = CARRY(K1_cntr_cout[19]_cout_0);
 
--K1L431 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[19]~COUT1_16 at LC_X31_Y4_N3
--operation mode is arithmetic
 
K1L431_cout_1 = !K1_cntr_19 & !K1L231;
K1L431 = CARRY(K1L431_cout_1);
 
 
--K1_cntr_16 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_16 at LC_X31_Y4_N0
--operation mode is arithmetic
 
K1_cntr_16_carry_eqn = K1_cntr_cout[15];
K1_cntr_16_lut_out = K1_cntr_16 $ K1_cntr_16_carry_eqn;
K1_cntr_16 = DFFEAS(K1_cntr_16_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[16], , , !K1_un1_ld_1);
 
--K1_cntr_cout[16] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[16] at LC_X31_Y4_N0
--operation mode is arithmetic
 
K1_cntr_cout[16]_cout_0 = K1_cntr_16 # !K1_cntr_cout[15];
K1_cntr_cout[16] = CARRY(K1_cntr_cout[16]_cout_0);
 
--K1L821 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[16]~COUT1_13 at LC_X31_Y4_N0
--operation mode is arithmetic
 
K1L821_cout_1 = K1_cntr_16 # !K1_cntr_cout[15];
K1L821 = CARRY(K1L821_cout_1);
 
 
--K1_cntr_17 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_17 at LC_X31_Y4_N1
--operation mode is arithmetic
 
K1_cntr_17_carry_eqn = (!K1_cntr_cout[15] & K1_cntr_cout[16]) # (K1_cntr_cout[15] & K1L821);
K1_cntr_17_lut_out = K1_cntr_17 $ (!K1_cntr_17_carry_eqn);
K1_cntr_17 = DFFEAS(K1_cntr_17_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[17], , , !K1_un1_ld_1);
 
--K1_cntr_cout[17] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[17] at LC_X31_Y4_N1
--operation mode is arithmetic
 
K1_cntr_cout[17]_cout_0 = !K1_cntr_17 & !K1_cntr_cout[16];
K1_cntr_cout[17] = CARRY(K1_cntr_cout[17]_cout_0);
 
--K1L031 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[17]~COUT1_14 at LC_X31_Y4_N1
--operation mode is arithmetic
 
K1L031_cout_1 = !K1_cntr_17 & !K1L821;
K1L031 = CARRY(K1L031_cout_1);
 
 
--K1_cntr_22 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_22 at LC_X31_Y4_N6
--operation mode is arithmetic
 
K1_cntr_22_carry_eqn = (!K1_cntr_cout[20] & K1_cntr_cout[21]) # (K1_cntr_cout[20] & K1L731);
K1_cntr_22_lut_out = K1_cntr_22 $ (K1_cntr_22_carry_eqn);
K1_cntr_22 = DFFEAS(K1_cntr_22_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[22], , , !K1_un1_ld_1);
 
--K1_cntr_cout[22] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[22] at LC_X31_Y4_N6
--operation mode is arithmetic
 
K1_cntr_cout[22]_cout_0 = K1_cntr_22 # !K1_cntr_cout[21];
K1_cntr_cout[22] = CARRY(K1_cntr_cout[22]_cout_0);
 
--K1L931 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[22]~COUT1_18 at LC_X31_Y4_N6
--operation mode is arithmetic
 
K1L931_cout_1 = K1_cntr_22 # !K1L731;
K1L931 = CARRY(K1L931_cout_1);
 
 
--K1_cntr_23 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_23 at LC_X31_Y4_N7
--operation mode is arithmetic
 
K1_cntr_23_carry_eqn = (!K1_cntr_cout[20] & K1_cntr_cout[22]) # (K1_cntr_cout[20] & K1L931);
K1_cntr_23_lut_out = K1_cntr_23 $ (!K1_cntr_23_carry_eqn);
K1_cntr_23 = DFFEAS(K1_cntr_23_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[23], , , !K1_un1_ld_1);
 
--K1_cntr_cout[23] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[23] at LC_X31_Y4_N7
--operation mode is arithmetic
 
K1_cntr_cout[23]_cout_0 = !K1_cntr_23 & !K1_cntr_cout[22];
K1_cntr_cout[23] = CARRY(K1_cntr_cout[23]_cout_0);
 
--K1L141 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[23]~COUT1_19 at LC_X31_Y4_N7
--operation mode is arithmetic
 
K1L141_cout_1 = !K1_cntr_23 & !K1L931;
K1L141 = CARRY(K1L141_cout_1);
 
 
--K1_cntr_20 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_20 at LC_X31_Y4_N4
--operation mode is arithmetic
 
K1_cntr_20_carry_eqn = (!K1_cntr_cout[15] & K1_cntr_cout[19]) # (K1_cntr_cout[15] & K1L431);
K1_cntr_20_lut_out = K1_cntr_20 $ K1_cntr_20_carry_eqn;
K1_cntr_20 = DFFEAS(K1_cntr_20_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[20], , , !K1_un1_ld_1);
 
--K1_cntr_cout[20] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[20] at LC_X31_Y4_N4
--operation mode is arithmetic
 
K1_cntr_cout[20] = CARRY(K1_cntr_20 # !K1L431);
 
 
--K1_cntr_21 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_21 at LC_X31_Y4_N5
--operation mode is arithmetic
 
K1_cntr_21_carry_eqn = K1_cntr_cout[20];
K1_cntr_21_lut_out = K1_cntr_21 $ !K1_cntr_21_carry_eqn;
K1_cntr_21 = DFFEAS(K1_cntr_21_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[21], , , !K1_un1_ld_1);
 
--K1_cntr_cout[21] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[21] at LC_X31_Y4_N5
--operation mode is arithmetic
 
K1_cntr_cout[21]_cout_0 = !K1_cntr_21 & !K1_cntr_cout[20];
K1_cntr_cout[21] = CARRY(K1_cntr_cout[21]_cout_0);
 
--K1L731 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[21]~COUT1_17 at LC_X31_Y4_N5
--operation mode is arithmetic
 
K1L731_cout_1 = !K1_cntr_21 & !K1_cntr_cout[20];
K1L731 = CARRY(K1L731_cout_1);
 
 
--K1_cntr_26 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_26 at LC_X31_Y3_N0
--operation mode is arithmetic
 
K1_cntr_26_carry_eqn = K1_cntr_cout[25];
K1_cntr_26_lut_out = K1_cntr_26 $ K1_cntr_26_carry_eqn;
K1_cntr_26 = DFFEAS(K1_cntr_26_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[26], , , !K1_un1_ld_1);
 
--K1_cntr_cout[26] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[26] at LC_X31_Y3_N0
--operation mode is arithmetic
 
K1_cntr_cout[26]_cout_0 = K1_cntr_26 # !K1_cntr_cout[25];
K1_cntr_cout[26] = CARRY(K1_cntr_cout[26]_cout_0);
 
--K1L641 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[26]~COUT1_21 at LC_X31_Y3_N0
--operation mode is arithmetic
 
K1L641_cout_1 = K1_cntr_26 # !K1_cntr_cout[25];
K1L641 = CARRY(K1L641_cout_1);
 
 
--K1_cntr_24 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_24 at LC_X31_Y4_N8
--operation mode is arithmetic
 
K1_cntr_24_carry_eqn = (!K1_cntr_cout[20] & K1_cntr_cout[23]) # (K1_cntr_cout[20] & K1L141);
K1_cntr_24_lut_out = K1_cntr_24 $ K1_cntr_24_carry_eqn;
K1_cntr_24 = DFFEAS(K1_cntr_24_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[24], , , !K1_un1_ld_1);
 
--K1_cntr_cout[24] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[24] at LC_X31_Y4_N8
--operation mode is arithmetic
 
K1_cntr_cout[24]_cout_0 = K1_cntr_24 # !K1_cntr_cout[23];
K1_cntr_cout[24] = CARRY(K1_cntr_cout[24]_cout_0);
 
--K1L341 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[24]~COUT1_20 at LC_X31_Y4_N8
--operation mode is arithmetic
 
K1L341_cout_1 = K1_cntr_24 # !K1L141;
K1L341 = CARRY(K1L341_cout_1);
 
 
--K1_cntr_25 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_25 at LC_X31_Y4_N9
--operation mode is arithmetic
 
K1_cntr_25_carry_eqn = (!K1_cntr_cout[20] & K1_cntr_cout[24]) # (K1_cntr_cout[20] & K1L341);
K1_cntr_25_lut_out = K1_cntr_25 $ (!K1_cntr_25_carry_eqn);
K1_cntr_25 = DFFEAS(K1_cntr_25_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[25], , , !K1_un1_ld_1);
 
--K1_cntr_cout[25] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[25] at LC_X31_Y4_N9
--operation mode is arithmetic
 
K1_cntr_cout[25] = CARRY(!K1_cntr_25 & !K1L341);
 
 
--K1_cntr_10 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_10 at LC_X31_Y5_N4
--operation mode is arithmetic
 
K1_cntr_10_carry_eqn = (!K1_cntr_cout[5] & K1_cntr_cout[9]) # (K1_cntr_cout[5] & K1L611);
K1_cntr_10_lut_out = K1_cntr_10 $ K1_cntr_10_carry_eqn;
K1_cntr_10 = DFFEAS(K1_cntr_10_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[10], , , !K1_un1_ld_1);
 
--K1_cntr_cout[10] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[10] at LC_X31_Y5_N4
--operation mode is arithmetic
 
K1_cntr_cout[10] = CARRY(K1_cntr_10 # !K1L611);
 
 
--K1_cntr_11 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_11 at LC_X31_Y5_N5
--operation mode is arithmetic
 
K1_cntr_11_carry_eqn = K1_cntr_cout[10];
K1_cntr_11_lut_out = K1_cntr_11 $ !K1_cntr_11_carry_eqn;
K1_cntr_11 = DFFEAS(K1_cntr_11_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[11], , , !K1_un1_ld_1);
 
--K1_cntr_cout[11] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[11] at LC_X31_Y5_N5
--operation mode is arithmetic
 
K1_cntr_cout[11]_cout_0 = !K1_cntr_11 & !K1_cntr_cout[10];
K1_cntr_cout[11] = CARRY(K1_cntr_cout[11]_cout_0);
 
--K1L911 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[11]~COUT1_9 at LC_X31_Y5_N5
--operation mode is arithmetic
 
K1L911_cout_1 = !K1_cntr_11 & !K1_cntr_cout[10];
K1L911 = CARRY(K1L911_cout_1);
 
 
--K1_cntr_8 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_8 at LC_X31_Y5_N2
--operation mode is arithmetic
 
K1_cntr_8_carry_eqn = (!K1_cntr_cout[5] & K1_cntr_cout[7]) # (K1_cntr_cout[5] & K1L211);
K1_cntr_8_lut_out = K1_cntr_8 $ (K1_cntr_8_carry_eqn);
K1_cntr_8 = DFFEAS(K1_cntr_8_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[8], , , !K1_un1_ld_1);
 
--K1_cntr_cout[8] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[8] at LC_X31_Y5_N2
--operation mode is arithmetic
 
K1_cntr_cout[8]_cout_0 = K1_cntr_8 # !K1_cntr_cout[7];
K1_cntr_cout[8] = CARRY(K1_cntr_cout[8]_cout_0);
 
--K1L411 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[8]~COUT1_7 at LC_X31_Y5_N2
--operation mode is arithmetic
 
K1L411_cout_1 = K1_cntr_8 # !K1L211;
K1L411 = CARRY(K1L411_cout_1);
 
 
--K1_cntr_9 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_9 at LC_X31_Y5_N3
--operation mode is arithmetic
 
K1_cntr_9_carry_eqn = (!K1_cntr_cout[5] & K1_cntr_cout[8]) # (K1_cntr_cout[5] & K1L411);
K1_cntr_9_lut_out = K1_cntr_9 $ !K1_cntr_9_carry_eqn;
K1_cntr_9 = DFFEAS(K1_cntr_9_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[9], , , !K1_un1_ld_1);
 
--K1_cntr_cout[9] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[9] at LC_X31_Y5_N3
--operation mode is arithmetic
 
K1_cntr_cout[9]_cout_0 = !K1_cntr_9 & !K1_cntr_cout[8];
K1_cntr_cout[9] = CARRY(K1_cntr_cout[9]_cout_0);
 
--K1L611 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[9]~COUT1_8 at LC_X31_Y5_N3
--operation mode is arithmetic
 
K1L611_cout_1 = !K1_cntr_9 & !K1L411;
K1L611 = CARRY(K1L611_cout_1);
 
 
--K1_cntr_14 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_14 at LC_X31_Y5_N8
--operation mode is arithmetic
 
K1_cntr_14_carry_eqn = (!K1_cntr_cout[10] & K1_cntr_cout[13]) # (K1_cntr_cout[10] & K1L321);
K1_cntr_14_lut_out = K1_cntr_14 $ K1_cntr_14_carry_eqn;
K1_cntr_14 = DFFEAS(K1_cntr_14_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[14], , , !K1_un1_ld_1);
 
--K1_cntr_cout[14] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[14] at LC_X31_Y5_N8
--operation mode is arithmetic
 
K1_cntr_cout[14]_cout_0 = K1_cntr_14 # !K1_cntr_cout[13];
K1_cntr_cout[14] = CARRY(K1_cntr_cout[14]_cout_0);
 
--K1L521 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[14]~COUT1_12 at LC_X31_Y5_N8
--operation mode is arithmetic
 
K1L521_cout_1 = K1_cntr_14 # !K1L321;
K1L521 = CARRY(K1L521_cout_1);
 
 
--K1_cntr_15 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_15 at LC_X31_Y5_N9
--operation mode is arithmetic
 
K1_cntr_15_carry_eqn = (!K1_cntr_cout[10] & K1_cntr_cout[14]) # (K1_cntr_cout[10] & K1L521);
K1_cntr_15_lut_out = K1_cntr_15 $ (!K1_cntr_15_carry_eqn);
K1_cntr_15 = DFFEAS(K1_cntr_15_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[15], , , !K1_un1_ld_1);
 
--K1_cntr_cout[15] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[15] at LC_X31_Y5_N9
--operation mode is arithmetic
 
K1_cntr_cout[15] = CARRY(!K1_cntr_15 & !K1L521);
 
 
--K1_cntr_12 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_12 at LC_X31_Y5_N6
--operation mode is arithmetic
 
K1_cntr_12_carry_eqn = (!K1_cntr_cout[10] & K1_cntr_cout[11]) # (K1_cntr_cout[10] & K1L911);
K1_cntr_12_lut_out = K1_cntr_12 $ (K1_cntr_12_carry_eqn);
K1_cntr_12 = DFFEAS(K1_cntr_12_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[12], , , !K1_un1_ld_1);
 
--K1_cntr_cout[12] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[12] at LC_X31_Y5_N6
--operation mode is arithmetic
 
K1_cntr_cout[12]_cout_0 = K1_cntr_12 # !K1_cntr_cout[11];
K1_cntr_cout[12] = CARRY(K1_cntr_cout[12]_cout_0);
 
--K1L121 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[12]~COUT1_10 at LC_X31_Y5_N6
--operation mode is arithmetic
 
K1L121_cout_1 = K1_cntr_12 # !K1L911;
K1L121 = CARRY(K1L121_cout_1);
 
 
--K1_cntr_13 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_13 at LC_X31_Y5_N7
--operation mode is arithmetic
 
K1_cntr_13_carry_eqn = (!K1_cntr_cout[10] & K1_cntr_cout[12]) # (K1_cntr_cout[10] & K1L121);
K1_cntr_13_lut_out = K1_cntr_13 $ (!K1_cntr_13_carry_eqn);
K1_cntr_13 = DFFEAS(K1_cntr_13_lut_out, GLOBAL(E1__clk0), VCC, , K1_cntrlde, K1_cntr_5_0[13], , , !K1_un1_ld_1);
 
--K1_cntr_cout[13] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[13] at LC_X31_Y5_N7
--operation mode is arithmetic
 
K1_cntr_cout[13]_cout_0 = !K1_cntr_13 & !K1_cntr_cout[12];
K1_cntr_cout[13] = CARRY(K1_cntr_cout[13]_cout_0);
 
--K1L321 is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_cout[13]~COUT1_11 at LC_X31_Y5_N7
--operation mode is arithmetic
 
K1L321_cout_1 = !K1_cntr_13 & !K1L121;
K1L321 = CARRY(K1L321_cout_1);
 
 
--FD1_wb_o_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_8 at LC_X32_Y6_N2
--operation mode is normal
 
FD1_wb_o_8 = TC1_wb_mux_ctl_o_0 & F1_dout_8 # DB1_r32_o_8 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_8;
 
--FD1_r_data_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_8 at LC_X32_Y6_N2
--operation mode is normal
 
FD1_r_data_8 = DFFEAS(FD1_wb_o_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_8 at LC_X20_Y5_N7
--operation mode is normal
 
ND1_dout_2_a_8 = XD1_mux_fw_1 & !AB1_r32_o_6 # !XD1_mux_fw_1 & !QB1_r32_o_8;
 
 
--M1_clk_ctr_3 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_3 at LC_X32_Y16_N5
--operation mode is arithmetic
 
M1_clk_ctr_3_carry_eqn = M1_clk_ctr_cout[2];
M1_clk_ctr_3_lut_out = M1_clk_ctr_3 $ M1_clk_ctr_3_carry_eqn;
M1_clk_ctr_3 = DFFEAS(M1_clk_ctr_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[3] at LC_X32_Y16_N5
--operation mode is arithmetic
 
M1_clk_ctr_cout[3]_cout_0 = !M1_clk_ctr_cout[2] # !M1_clk_ctr_3;
M1_clk_ctr_cout[3] = CARRY(M1_clk_ctr_cout[3]_cout_0);
 
--M1L18 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[3]~COUT1_3 at LC_X32_Y16_N5
--operation mode is arithmetic
 
M1L18_cout_1 = !M1_clk_ctr_cout[2] # !M1_clk_ctr_3;
M1L18 = CARRY(M1L18_cout_1);
 
 
--M1_clk_ctr_2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_2 at LC_X32_Y16_N4
--operation mode is arithmetic
 
M1_clk_ctr_2_lut_out = M1_clk_ctr_2 $ !M1_clk_ctr_cout[1];
M1_clk_ctr_2 = DFFEAS(M1_clk_ctr_2_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[2] at LC_X32_Y16_N4
--operation mode is arithmetic
 
M1_clk_ctr_cout[2] = CARRY(M1_clk_ctr_2 & !M1L87);
 
 
--M1_clk_ctr_0 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_0 at LC_X32_Y16_N2
--operation mode is arithmetic
 
M1_clk_ctr_0_lut_out = !M1_clk_ctr_0;
M1_clk_ctr_0 = DFFEAS(M1_clk_ctr_0_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[0] at LC_X32_Y16_N2
--operation mode is arithmetic
 
M1_clk_ctr_cout[0]_cout_0 = M1_clk_ctr_0;
M1_clk_ctr_cout[0] = CARRY(M1_clk_ctr_cout[0]_cout_0);
 
--M1L67 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[0]~COUT1_1 at LC_X32_Y16_N2
--operation mode is arithmetic
 
M1L67_cout_1 = M1_clk_ctr_0;
M1L67 = CARRY(M1L67_cout_1);
 
 
--M1_clk_ctr[15] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[15] at LC_X32_Y15_N7
--operation mode is normal
 
M1_clk_ctr[15]_carry_eqn = (!M1_clk_ctr_cout[12] & M1_clk_ctr_cout[14]) # (M1_clk_ctr_cout[12] & M1L101);
M1_clk_ctr[15]_lut_out = M1_clk_ctr[15] $ (M1_clk_ctr[15]_carry_eqn);
M1_clk_ctr[15] = DFFEAS(M1_clk_ctr[15]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
 
--M1_clk_ctr[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[14] at LC_X32_Y15_N6
--operation mode is arithmetic
 
M1_clk_ctr[14]_carry_eqn = (!M1_clk_ctr_cout[12] & M1_clk_ctr_cout[13]) # (M1_clk_ctr_cout[12] & M1L99);
M1_clk_ctr[14]_lut_out = M1_clk_ctr[14] $ (!M1_clk_ctr[14]_carry_eqn);
M1_clk_ctr[14] = DFFEAS(M1_clk_ctr[14]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[14] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[14] at LC_X32_Y15_N6
--operation mode is arithmetic
 
M1_clk_ctr_cout[14]_cout_0 = M1_clk_ctr[14] & !M1_clk_ctr_cout[13];
M1_clk_ctr_cout[14] = CARRY(M1_clk_ctr_cout[14]_cout_0);
 
--M1L101 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[14]~COUT1_12 at LC_X32_Y15_N6
--operation mode is arithmetic
 
M1L101_cout_1 = M1_clk_ctr[14] & !M1L99;
M1L101 = CARRY(M1L101_cout_1);
 
 
--M1_clk_ctr[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[13] at LC_X32_Y15_N5
--operation mode is arithmetic
 
M1_clk_ctr[13]_carry_eqn = M1_clk_ctr_cout[12];
M1_clk_ctr[13]_lut_out = M1_clk_ctr[13] $ M1_clk_ctr[13]_carry_eqn;
M1_clk_ctr[13] = DFFEAS(M1_clk_ctr[13]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[13] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[13] at LC_X32_Y15_N5
--operation mode is arithmetic
 
M1_clk_ctr_cout[13]_cout_0 = !M1_clk_ctr_cout[12] # !M1_clk_ctr[13];
M1_clk_ctr_cout[13] = CARRY(M1_clk_ctr_cout[13]_cout_0);
 
--M1L99 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[13]~COUT1_11 at LC_X32_Y15_N5
--operation mode is arithmetic
 
M1L99_cout_1 = !M1_clk_ctr_cout[12] # !M1_clk_ctr[13];
M1L99 = CARRY(M1L99_cout_1);
 
 
--M1_un1_clk_ctr_equ0_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_a at LC_X32_Y15_N8
--operation mode is normal
 
M1_un1_clk_ctr_equ0_0_a2_a = !M1_clk_ctr[6] & !M1_clk_ctr[7] & !M1_clk_ctr[12];
 
 
--M1_clk_ctr[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[5] at LC_X32_Y16_N7
--operation mode is arithmetic
 
M1_clk_ctr[5]_carry_eqn = (!M1_clk_ctr_cout[2] & M1_clk_ctr_cout[4]) # (M1_clk_ctr_cout[2] & M1L38);
M1_clk_ctr[5]_lut_out = M1_clk_ctr[5] $ (M1_clk_ctr[5]_carry_eqn);
M1_clk_ctr[5] = DFFEAS(M1_clk_ctr[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[5] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[5] at LC_X32_Y16_N7
--operation mode is arithmetic
 
M1_clk_ctr_cout[5]_cout_0 = !M1_clk_ctr_cout[4] # !M1_clk_ctr[5];
M1_clk_ctr_cout[5] = CARRY(M1_clk_ctr_cout[5]_cout_0);
 
--M1L58 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[5]~COUT1_5 at LC_X32_Y16_N7
--operation mode is arithmetic
 
M1L58_cout_1 = !M1L38 # !M1_clk_ctr[5];
M1L58 = CARRY(M1L58_cout_1);
 
 
--M1_clk_ctr[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[10] at LC_X32_Y15_N2
--operation mode is arithmetic
 
M1_clk_ctr[10]_carry_eqn = (!M1_clk_ctr_cout[7] & M1_clk_ctr_cout[9]) # (M1_clk_ctr_cout[7] & M1L29);
M1_clk_ctr[10]_lut_out = M1_clk_ctr[10] $ (!M1_clk_ctr[10]_carry_eqn);
M1_clk_ctr[10] = DFFEAS(M1_clk_ctr[10]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[10] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[10] at LC_X32_Y15_N2
--operation mode is arithmetic
 
M1_clk_ctr_cout[10]_cout_0 = M1_clk_ctr[10] & !M1_clk_ctr_cout[9];
M1_clk_ctr_cout[10] = CARRY(M1_clk_ctr_cout[10]_cout_0);
 
--M1L49 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[10]~COUT1_9 at LC_X32_Y15_N2
--operation mode is arithmetic
 
M1L49_cout_1 = M1_clk_ctr[10] & !M1L29;
M1L49 = CARRY(M1L49_cout_1);
 
 
--M1_clk_ctr[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[8] at LC_X32_Y15_N0
--operation mode is arithmetic
 
M1_clk_ctr[8]_carry_eqn = M1_clk_ctr_cout[7];
M1_clk_ctr[8]_lut_out = M1_clk_ctr[8] $ !M1_clk_ctr[8]_carry_eqn;
M1_clk_ctr[8] = DFFEAS(M1_clk_ctr[8]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[8] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[8] at LC_X32_Y15_N0
--operation mode is arithmetic
 
M1_clk_ctr_cout[8]_cout_0 = M1_clk_ctr[8] & !M1_clk_ctr_cout[7];
M1_clk_ctr_cout[8] = CARRY(M1_clk_ctr_cout[8]_cout_0);
 
--M1L09 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[8]~COUT1_7 at LC_X32_Y15_N0
--operation mode is arithmetic
 
M1L09_cout_1 = M1_clk_ctr[8] & !M1_clk_ctr_cout[7];
M1L09 = CARRY(M1L09_cout_1);
 
 
--M1_un1_clk_ctr_equ0_0_a2_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|un1_clk_ctr_equ0_0_a2_0_a at LC_X32_Y16_N1
--operation mode is normal
 
M1_un1_clk_ctr_equ0_0_a2_0_a = M1_clk_ctr[4] & !M1_clk_ctr[9] & !M1_clk_ctr[11] & !M1_clk_ctr[1];
 
 
--SB1_un1_wr_en46_4_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_4_combout at LC_X14_Y9_N5
--operation mode is normal
 
SB1_un1_wr_en46_4_combout = TB1_dout21 & !RB1_c_0_d0 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0 # !TB1_dout21 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0;
 
 
--SB1_un1_addr_i_1_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_addr_i_1_combout at LC_X14_Y9_N4
--operation mode is normal
 
QC1_dmem_ctl_o_2_qfbk = QC1_dmem_ctl_o_2;
SB1_un1_addr_i_1_combout = !RB1_c_0_d0 # !QC1_dmem_ctl_o_2_qfbk;
 
--QC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_2 at LC_X14_Y9_N4
--operation mode is normal
 
QC1_dmem_ctl_o_2 = DFFEAS(SB1_un1_addr_i_1_combout, GLOBAL(E1__clk0), VCC, , , CC1_dmem_ctl_o_2, , !AD1_NET1640_i, VCC);
 
 
--WB1L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~94 at LC_X13_Y9_N7
--operation mode is normal
 
WB1L1 = SB1_un1_wr_en46_4_combout # SB1_un1_addr_i_1_combout & !RB1_c_1 # !SB1_un1_addr_i_1_combout & !WB1L2;
 
 
--SB1_wr_en47 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|wr_en47 at LC_X13_Y9_N2
--operation mode is normal
 
SB1_wr_en47 = !QC1_dmem_ctl_o_3 & QC1_dmem_ctl_o_0 & QC1_dmem_ctl_o_2 & !QC1_dmem_ctl_o_1;
 
 
--WB1L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~95 at LC_X13_Y9_N4
--operation mode is normal
 
WB1L2 = SB1_wr_en47 # !WB1L1;
 
 
--DD1_un1_pc_next46_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0 at LC_X27_Y11_N2
--operation mode is normal
 
DD1_un1_pc_next46_0 = !AD1_CurrState_Sreg0_5 & AD1_pc_prectl_1_0_i_a2_0_a2_0 & !AD1_pc_prectl_1_0_i_a2_0_a2_1 # !AD1_pc_prectl_1_0_i_a2_0_a2_0 & !DD1_un1_pc_next46_0_a & AD1_pc_prectl_1_0_i_a2_0_a2_1;
 
 
--DD1_pc_next_0_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_2 at LC_X16_Y12_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_2 = PB1_dout_iv_2 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[2];
 
 
--DD1_un1_pc_add2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add2 at LC_X23_Y11_N6
--operation mode is arithmetic
 
DD1_un1_pc_add2_carry_eqn = (!DD1_un1_pc_carry_0 & DD1_un1_pc_carry_1) # (DD1_un1_pc_carry_0 & DD1L202);
DD1_un1_pc_add2 = KB1_r32_o_2 $ DD1_un1_pc_prectl_1_i[2] $ DD1_un1_pc_add2_carry_eqn;
 
--DD1_un1_pc_carry_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_2 at LC_X23_Y11_N6
--operation mode is arithmetic
 
DD1_un1_pc_carry_2_cout_0 = KB1_r32_o_2 & !DD1_un1_pc_carry_1 # !DD1_un1_pc_prectl_1_i[2] # !KB1_r32_o_2 & !DD1_un1_pc_prectl_1_i[2] & !DD1_un1_pc_carry_1;
DD1_un1_pc_carry_2 = CARRY(DD1_un1_pc_carry_2_cout_0);
 
--DD1L402 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_2~COUT1_1 at LC_X23_Y11_N6
--operation mode is arithmetic
 
DD1L402_cout_1 = KB1_r32_o_2 & !DD1L202 # !DD1_un1_pc_prectl_1_i[2] # !KB1_r32_o_2 & !DD1_un1_pc_prectl_1_i[2] & !DD1L202;
DD1L402 = CARRY(DD1L402_cout_1);
 
 
--DD1_pc_next_0_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_3 at LC_X16_Y13_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_3 = PB1_dout_iv_3 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[3];
 
 
--DD1_un1_pc_add3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add3 at LC_X23_Y11_N7
--operation mode is arithmetic
 
DD1_un1_pc_add3_carry_eqn = (!DD1_un1_pc_carry_0 & DD1_un1_pc_carry_2) # (DD1_un1_pc_carry_0 & DD1L402);
DD1_un1_pc_add3 = KB1_r32_o_3 $ DD1_un1_pc_prectl_1_0_a4[3] $ DD1_un1_pc_add3_carry_eqn;
 
--DD1_un1_pc_carry_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_3 at LC_X23_Y11_N7
--operation mode is arithmetic
 
DD1_un1_pc_carry_3_cout_0 = KB1_r32_o_3 & !DD1_un1_pc_prectl_1_0_a4[3] & !DD1_un1_pc_carry_2 # !KB1_r32_o_3 & !DD1_un1_pc_carry_2 # !DD1_un1_pc_prectl_1_0_a4[3];
DD1_un1_pc_carry_3 = CARRY(DD1_un1_pc_carry_3_cout_0);
 
--DD1L602 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_3~COUT1_1 at LC_X23_Y11_N7
--operation mode is arithmetic
 
DD1L602_cout_1 = KB1_r32_o_3 & !DD1_un1_pc_prectl_1_0_a4[3] & !DD1L402 # !KB1_r32_o_3 & !DD1L402 # !DD1_un1_pc_prectl_1_0_a4[3];
DD1L602 = CARRY(DD1L602_cout_1);
 
 
--DD1_pc_next_0_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_4 at LC_X16_Y11_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_4 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_4 # !DD1_pc_next_0_iv_1_a[4];
 
 
--DD1_un1_pc_add4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add4 at LC_X23_Y11_N8
--operation mode is arithmetic
 
DD1_un1_pc_add4_carry_eqn = (!DD1_un1_pc_carry_0 & DD1_un1_pc_carry_3) # (DD1_un1_pc_carry_0 & DD1L602);
DD1_un1_pc_add4 = KB1_r32_o_4 $ DD1_un1_pc_prectl_1_0_a4[4] $ !DD1_un1_pc_add4_carry_eqn;
 
--DD1_un1_pc_carry_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_4 at LC_X23_Y11_N8
--operation mode is arithmetic
 
DD1_un1_pc_carry_4_cout_0 = KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] # !DD1_un1_pc_carry_3 # !KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] & !DD1_un1_pc_carry_3;
DD1_un1_pc_carry_4 = CARRY(DD1_un1_pc_carry_4_cout_0);
 
--DD1L802 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_4~COUT1_1 at LC_X23_Y11_N8
--operation mode is arithmetic
 
DD1L802_cout_1 = KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] # !DD1L602 # !KB1_r32_o_4 & DD1_un1_pc_prectl_1_0_a4[4] & !DD1L602;
DD1L802 = CARRY(DD1L802_cout_1);
 
 
--DD1_pc_next_0_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_5 at LC_X20_Y11_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_5 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_5 # !DD1_pc_next_0_iv_1_a[5];
 
 
--DD1_un1_pc_add5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add5 at LC_X23_Y11_N9
--operation mode is arithmetic
 
DD1_un1_pc_add5_carry_eqn = (!DD1_un1_pc_carry_0 & DD1_un1_pc_carry_4) # (DD1_un1_pc_carry_0 & DD1L802);
DD1_un1_pc_add5 = DD1_un1_pc_prectl_1_0_a4[5] $ KB1_r32_o_5 $ DD1_un1_pc_add5_carry_eqn;
 
--DD1_un1_pc_carry_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_5 at LC_X23_Y11_N9
--operation mode is arithmetic
 
DD1_un1_pc_carry_5 = CARRY(DD1_un1_pc_prectl_1_0_a4[5] & !KB1_r32_o_5 & !DD1L802 # !DD1_un1_pc_prectl_1_0_a4[5] & !DD1L802 # !KB1_r32_o_5);
 
 
--DD1_pc_next_0_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_6 at LC_X19_Y11_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_6 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_6 # !DD1_pc_next_0_iv_1_a[6];
 
 
--DD1_un1_pc_add6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add6 at LC_X23_Y10_N0
--operation mode is arithmetic
 
DD1_un1_pc_add6_carry_eqn = DD1_un1_pc_carry_5;
DD1_un1_pc_add6 = DD1_un1_pc_prectl_1_0_a4[6] $ KB1_r32_o_6 $ !DD1_un1_pc_add6_carry_eqn;
 
--DD1_un1_pc_carry_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_6 at LC_X23_Y10_N0
--operation mode is arithmetic
 
DD1_un1_pc_carry_6_cout_0 = DD1_un1_pc_prectl_1_0_a4[6] & KB1_r32_o_6 # !DD1_un1_pc_carry_5 # !DD1_un1_pc_prectl_1_0_a4[6] & KB1_r32_o_6 & !DD1_un1_pc_carry_5;
DD1_un1_pc_carry_6 = CARRY(DD1_un1_pc_carry_6_cout_0);
 
--DD1L112 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_6~COUT1_1 at LC_X23_Y10_N0
--operation mode is arithmetic
 
DD1L112_cout_1 = DD1_un1_pc_prectl_1_0_a4[6] & KB1_r32_o_6 # !DD1_un1_pc_carry_5 # !DD1_un1_pc_prectl_1_0_a4[6] & KB1_r32_o_6 & !DD1_un1_pc_carry_5;
DD1L112 = CARRY(DD1L112_cout_1);
 
 
--DD1_pc_next_0_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_7 at LC_X19_Y9_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_7 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_7 # !DD1_pc_next_0_iv_1_a[7];
 
 
--DD1_un1_pc_add7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add7 at LC_X23_Y10_N1
--operation mode is arithmetic
 
DD1_un1_pc_add7_carry_eqn = (!DD1_un1_pc_carry_5 & DD1_un1_pc_carry_6) # (DD1_un1_pc_carry_5 & DD1L112);
DD1_un1_pc_add7 = KB1_r32_o_7 $ DD1_un1_pc_prectl_1_0_a4[7] $ DD1_un1_pc_add7_carry_eqn;
 
--DD1_un1_pc_carry_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_7 at LC_X23_Y10_N1
--operation mode is arithmetic
 
DD1_un1_pc_carry_7_cout_0 = KB1_r32_o_7 & !DD1_un1_pc_prectl_1_0_a4[7] & !DD1_un1_pc_carry_6 # !KB1_r32_o_7 & !DD1_un1_pc_carry_6 # !DD1_un1_pc_prectl_1_0_a4[7];
DD1_un1_pc_carry_7 = CARRY(DD1_un1_pc_carry_7_cout_0);
 
--DD1L312 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_7~COUT1_1 at LC_X23_Y10_N1
--operation mode is arithmetic
 
DD1L312_cout_1 = KB1_r32_o_7 & !DD1_un1_pc_prectl_1_0_a4[7] & !DD1L112 # !KB1_r32_o_7 & !DD1L112 # !DD1_un1_pc_prectl_1_0_a4[7];
DD1L312 = CARRY(DD1L312_cout_1);
 
 
--DD1_pc_next_0_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_8 at LC_X19_Y8_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_8 = PB1_dout_iv_8 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[8];
 
 
--DD1_un1_pc_add8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add8 at LC_X23_Y10_N2
--operation mode is arithmetic
 
DD1_un1_pc_add8_carry_eqn = (!DD1_un1_pc_carry_5 & DD1_un1_pc_carry_7) # (DD1_un1_pc_carry_5 & DD1L312);
DD1_un1_pc_add8 = KB1_r32_o_8 $ DD1_un1_pc_prectl_1_0_a4[8] $ !DD1_un1_pc_add8_carry_eqn;
 
--DD1_un1_pc_carry_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_8 at LC_X23_Y10_N2
--operation mode is arithmetic
 
DD1_un1_pc_carry_8_cout_0 = KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] # !DD1_un1_pc_carry_7 # !KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] & !DD1_un1_pc_carry_7;
DD1_un1_pc_carry_8 = CARRY(DD1_un1_pc_carry_8_cout_0);
 
--DD1L512 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_8~COUT1_1 at LC_X23_Y10_N2
--operation mode is arithmetic
 
DD1L512_cout_1 = KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] # !DD1L312 # !KB1_r32_o_8 & DD1_un1_pc_prectl_1_0_a4[8] & !DD1L312;
DD1L512 = CARRY(DD1L512_cout_1);
 
 
--DD1_pc_next_0_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_9 at LC_X19_Y10_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_9 = PB1_dout_iv_9 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[9];
 
 
--DD1_un1_pc_add9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add9 at LC_X23_Y10_N3
--operation mode is arithmetic
 
DD1_un1_pc_add9_carry_eqn = (!DD1_un1_pc_carry_5 & DD1_un1_pc_carry_8) # (DD1_un1_pc_carry_5 & DD1L512);
DD1_un1_pc_add9 = KB1_r32_o_9 $ DD1_un1_pc_prectl_1_0_a4[9] $ DD1_un1_pc_add9_carry_eqn;
 
--DD1_un1_pc_carry_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_9 at LC_X23_Y10_N3
--operation mode is arithmetic
 
DD1_un1_pc_carry_9_cout_0 = KB1_r32_o_9 & !DD1_un1_pc_prectl_1_0_a4[9] & !DD1_un1_pc_carry_8 # !KB1_r32_o_9 & !DD1_un1_pc_carry_8 # !DD1_un1_pc_prectl_1_0_a4[9];
DD1_un1_pc_carry_9 = CARRY(DD1_un1_pc_carry_9_cout_0);
 
--DD1L712 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_9~COUT1_1 at LC_X23_Y10_N3
--operation mode is arithmetic
 
DD1L712_cout_1 = KB1_r32_o_9 & !DD1_un1_pc_prectl_1_0_a4[9] & !DD1L512 # !KB1_r32_o_9 & !DD1L512 # !DD1_un1_pc_prectl_1_0_a4[9];
DD1L712 = CARRY(DD1L712_cout_1);
 
 
--DD1_pc_next_0_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_10 at LC_X19_Y12_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_10 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_10 # !DD1_pc_next_0_iv_1_a[10];
 
 
--DD1_un1_pc_add10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add10 at LC_X23_Y10_N4
--operation mode is arithmetic
 
DD1_un1_pc_add10_carry_eqn = (!DD1_un1_pc_carry_5 & DD1_un1_pc_carry_9) # (DD1_un1_pc_carry_5 & DD1L712);
DD1_un1_pc_add10 = KB1_r32_o_10 $ DD1_un1_pc_prectl_1_0_a4[10] $ !DD1_un1_pc_add10_carry_eqn;
 
--DD1_un1_pc_carry_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_10 at LC_X23_Y10_N4
--operation mode is arithmetic
 
DD1_un1_pc_carry_10 = CARRY(KB1_r32_o_10 & DD1_un1_pc_prectl_1_0_a4[10] # !DD1L712 # !KB1_r32_o_10 & DD1_un1_pc_prectl_1_0_a4[10] & !DD1L712);
 
 
--DD1_pc_next_0_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_11 at LC_X22_Y10_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_11 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_11 # !DD1_pc_next_0_iv_1_a[11];
 
 
--DD1_un1_pc_add11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add11 at LC_X23_Y10_N5
--operation mode is arithmetic
 
DD1_un1_pc_add11_carry_eqn = DD1_un1_pc_carry_10;
DD1_un1_pc_add11 = KB1_r32_o_11 $ DD1_un1_pc_prectl_1_0_a4[11] $ DD1_un1_pc_add11_carry_eqn;
 
--DD1_un1_pc_carry_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_11 at LC_X23_Y10_N5
--operation mode is arithmetic
 
DD1_un1_pc_carry_11_cout_0 = KB1_r32_o_11 & !DD1_un1_pc_prectl_1_0_a4[11] & !DD1_un1_pc_carry_10 # !KB1_r32_o_11 & !DD1_un1_pc_carry_10 # !DD1_un1_pc_prectl_1_0_a4[11];
DD1_un1_pc_carry_11 = CARRY(DD1_un1_pc_carry_11_cout_0);
 
--DD1L022 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_11~COUT1_1 at LC_X23_Y10_N5
--operation mode is arithmetic
 
DD1L022_cout_1 = KB1_r32_o_11 & !DD1_un1_pc_prectl_1_0_a4[11] & !DD1_un1_pc_carry_10 # !KB1_r32_o_11 & !DD1_un1_pc_carry_10 # !DD1_un1_pc_prectl_1_0_a4[11];
DD1L022 = CARRY(DD1L022_cout_1);
 
 
--DD1_pc_next_0_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_12 at LC_X23_Y12_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_12 = PB1_dout_iv_12 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[12];
 
 
--DD1_un1_pc_add12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add12 at LC_X23_Y10_N6
--operation mode is arithmetic
 
DD1_un1_pc_add12_carry_eqn = (!DD1_un1_pc_carry_10 & DD1_un1_pc_carry_11) # (DD1_un1_pc_carry_10 & DD1L022);
DD1_un1_pc_add12 = KB1_r32_o_12 $ DD1_un1_pc_prectl_1_0_a4[12] $ !DD1_un1_pc_add12_carry_eqn;
 
--DD1_un1_pc_carry_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_12 at LC_X23_Y10_N6
--operation mode is arithmetic
 
DD1_un1_pc_carry_12_cout_0 = KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] # !DD1_un1_pc_carry_11 # !KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] & !DD1_un1_pc_carry_11;
DD1_un1_pc_carry_12 = CARRY(DD1_un1_pc_carry_12_cout_0);
 
--DD1L222 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_12~COUT1_1 at LC_X23_Y10_N6
--operation mode is arithmetic
 
DD1L222_cout_1 = KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] # !DD1L022 # !KB1_r32_o_12 & DD1_un1_pc_prectl_1_0_a4[12] & !DD1L022;
DD1L222 = CARRY(DD1L222_cout_1);
 
 
--TB1_dout_1_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_7 at LC_X29_Y3_N6
--operation mode is normal
 
TB1_dout_1_7 = TB1_dout22 & CB1_dout_2_7 # !TB1_dout22 & TB1_dout21 & CB1_dout_2_7 # !TB1_dout21 & CB1_dout_2_23;
 
 
--UB1_dout_2_i_i_a2_2_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_2_a[7] at LC_X29_Y8_N6
--operation mode is normal
 
UB1_dout_2_i_i_a2_2_a[7] = !RB1_ctl_o_1 & !RB1_ctl_o_2;
 
 
--UB1_dout_2_i_i_a2_1_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_1_a[7] at LC_X29_Y8_N7
--operation mode is normal
 
UB1_dout_2_i_i_a2_1_a[7] = !RB1_byte_addr_o_0 & RB1_ctl_o_2 & !RB1_ctl_o_1 # !RB1_ctl_o_2 & RB1_ctl_o_1 & !RB1_ctl_o_3;
 
 
--UB1_dout_2_i_i_o2_0_a[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o2_0_a[7] at LC_X29_Y8_N3
--operation mode is normal
 
UB1_dout_2_i_i_o2_0_a[7] = RB1_ctl_o_1 & RB1_byte_addr_o_0 & !RB1_ctl_o_2 # !RB1_byte_addr_o_0 & RB1_ctl_o_3 # !RB1_ctl_o_1 & RB1_byte_addr_o_0;
 
 
--YB1_wb_mux_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_0 at LC_X27_Y16_N2
--operation mode is normal
 
YB1_wb_mux_1_0_0_0 = YB1_wb_mux_1_0_0_a3[0] # WB56L1 & YB1_alu_func_2_0_0_a2_0[1] & YB1_fsm_dly_2_0_0_o2_x[2];
 
 
--WB56L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_mux_0_|lpm_latch:U1|q[0]~56 at LC_X27_Y16_N3
--operation mode is normal
 
WB56L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_wb_mux_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB56L1;
 
--KC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10|wb_mux_ctl_o_0 at LC_X27_Y16_N3
--operation mode is normal
 
KC1_wb_mux_ctl_o_0 = DFFEAS(WB56L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--FD1_r_wraddress[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[1] at LC_X26_Y14_N0
--operation mode is normal
 
FD1_r_wraddress[1]_lut_out = NB1_r5_o_1;
FD1_r_wraddress[1] = DFFEAS(FD1_r_wraddress[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_r_wraddress[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[0] at LC_X26_Y14_N6
--operation mode is normal
 
FD1_r_wraddress[0]_lut_out = NB1_r5_o_0;
FD1_r_wraddress[0] = DFFEAS(FD1_r_wraddress[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_r_wraddress[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[3] at LC_X26_Y14_N5
--operation mode is normal
 
FD1_r_wraddress[3]_lut_out = GND;
FD1_r_wraddress[3] = DFFEAS(FD1_r_wraddress[3]_lut_out, GLOBAL(E1__clk0), VCC, , , NB1_r5_o_3, , , VCC);
 
 
--QB1_dout_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_9 at LC_X25_Y6_N4
--operation mode is normal
 
QB1_dout_iv_9 = GD1_dout_iv_1_9 # GD1_dout7_0_a2 & FD1_wb_o_9;
 
--QB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_9 at LC_X25_Y6_N4
--operation mode is normal
 
QB1_r32_o_9 = DFFEAS(QB1_dout_iv_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_9 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_9 at LC_X22_Y11_N0
--operation mode is normal
 
FB1_res_7_0_0_9 = CD1_res_7_0_0_o3_0 & ED1_r32_o_7 # CD1_res_7_0_0_a2_0 & ED1_r32_o_9 # !CD1_res_7_0_0_o3_0 & CD1_res_7_0_0_a2_0 & ED1_r32_o_9;
 
--FB1_r32_o_0_9 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_9 at LC_X22_Y11_N0
--operation mode is normal
 
FB1_r32_o_0_9 = DFFEAS(FB1_res_7_0_0_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_9 at LC_X28_Y13_N9
--operation mode is normal
 
FD1_wb_o_9 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_9 # F1_dout_9 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_9;
 
--FD1_r_data_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_9 at LC_X28_Y13_N9
--operation mode is normal
 
FD1_r_data_9 = DFFEAS(FD1_wb_o_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_b_o_iv_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_11 at LC_X20_Y15_N6
--operation mode is normal
 
VD1_b_o_iv_11 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] & !G1_BUS15471_i_m[11] & AB1_r32_o_9 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[11] at LC_X20_Y15_N6
--operation mode is normal
 
VD1_op2_reged[11] = DFFEAS(VD1_b_o_iv_11, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_13 at LC_X19_Y7_N8
--operation mode is normal
 
VD1_b_o_iv_13 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] & !G1_BUS15471_i_m[13] & AB1_r32_o_11 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[13] at LC_X19_Y7_N8
--operation mode is normal
 
VD1_op2_reged[13] = DFFEAS(VD1_b_o_iv_13, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_12 at LC_X19_Y7_N2
--operation mode is normal
 
VD1_b_o_iv_12 = !G1_BUS15471_i_m[12] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] & AB1_r32_o_10 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[12] at LC_X19_Y7_N2
--operation mode is normal
 
VD1_op2_reged[12] = DFFEAS(VD1_b_o_iv_12, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_14 at LC_X21_Y6_N4
--operation mode is normal
 
VD1_b_o_iv_14 = !G1_BUS15471_i_m[14] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] & AB1_r32_o_12 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[14] at LC_X21_Y6_N4
--operation mode is normal
 
VD1_op2_reged[14] = DFFEAS(VD1_b_o_iv_14, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_80_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[7] at LC_X10_Y15_N3
--operation mode is normal
 
UD1_shift_out_80_a[7] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !VD1_b_o_iv_8;
 
 
--FB1_res_7_0_0_6 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_6 at LC_X21_Y11_N6
--operation mode is normal
 
FB1_res_7_0_0_6 = ED1_r32_o_4 & CD1_res_7_0_0_o3_0 # ED1_r32_o_6 & CD1_res_7_0_0_a2_0 # !ED1_r32_o_4 & ED1_r32_o_6 & CD1_res_7_0_0_a2_0;
 
--FB1_r32_o_0_6 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_6 at LC_X21_Y11_N6
--operation mode is normal
 
FB1_r32_o_0_6 = DFFEAS(FB1_res_7_0_0_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UD1_shift_out_43_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43_a[31] at LC_X12_Y14_N4
--operation mode is normal
 
UD1_shift_out_43_a[31] = PD1_a_o_0 & !VD1_b_o_iv_0 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_1;
 
 
--CD1_res_7_0_0_0_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_0 at LC_X21_Y11_N5
--operation mode is normal
 
ED1_r32_o_2_qfbk = ED1_r32_o_2;
CD1_res_7_0_0_0_0 = ED1_r32_o_8 & CD1_res_7_0_0_0_a_0 # CD1_res_7_0_0_a2_0 & ED1_r32_o_2_qfbk # !ED1_r32_o_8 & CD1_res_7_0_0_a2_0 & ED1_r32_o_2_qfbk;
 
--ED1_r32_o_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_2 at LC_X21_Y11_N5
--operation mode is normal
 
ED1_r32_o_2 = DFFEAS(CD1_res_7_0_0_0_0, GLOBAL(E1__clk0), VCC, , C1_G_504, GE1_q_a[2], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--PD1_a_o_3_d_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[2] at LC_X20_Y10_N1
--operation mode is normal
 
PD1_a_o_3_d_a[2] = PD1_a_o_sn_m2 & !PB1_r32_o_2 # !PD1_a_o_sn_m2 & !AB1_r32_o_0;
 
 
--ED1_r32_o_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_7 at LC_X21_Y18_N9
--operation mode is normal
 
ED1_r32_o_7_lut_out = GE1_q_a[7];
ED1_r32_o_7 = DFFEAS(ED1_r32_o_7_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--ED1_r32_o_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_1 at LC_X22_Y17_N7
--operation mode is normal
 
ED1_r32_o_1_lut_out = GE1_q_a[1];
ED1_r32_o_1 = DFFEAS(ED1_r32_o_1_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--CD1_res_7_0_0_0_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_a_0 at LC_X22_Y16_N0
--operation mode is normal
 
CD1_res_7_0_0_0_a_0 = DC1_ext_ctl_o_0 & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2;
 
 
--DD1_pc_next_0_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_1 at LC_X20_Y9_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_1 = PB1_dout_iv_1 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[1];
 
 
--DD1_un1_pc_add1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add1 at LC_X23_Y11_N5
--operation mode is arithmetic
 
DD1_un1_pc_add1_carry_eqn = DD1_un1_pc_carry_0;
DD1_un1_pc_add1 = KB1_r32_o_1 $ DD1_un1_pc_prectl_1_0_a4[1] $ DD1_un1_pc_add1_carry_eqn;
 
--DD1_un1_pc_carry_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_1 at LC_X23_Y11_N5
--operation mode is arithmetic
 
DD1_un1_pc_carry_1_cout_0 = KB1_r32_o_1 & !DD1_un1_pc_prectl_1_0_a4[1] & !DD1_un1_pc_carry_0 # !KB1_r32_o_1 & !DD1_un1_pc_carry_0 # !DD1_un1_pc_prectl_1_0_a4[1];
DD1_un1_pc_carry_1 = CARRY(DD1_un1_pc_carry_1_cout_0);
 
--DD1L202 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_1~COUT1_1 at LC_X23_Y11_N5
--operation mode is arithmetic
 
DD1L202_cout_1 = KB1_r32_o_1 & !DD1_un1_pc_prectl_1_0_a4[1] & !DD1_un1_pc_carry_0 # !KB1_r32_o_1 & !DD1_un1_pc_carry_0 # !DD1_un1_pc_prectl_1_0_a4[1];
DD1L202 = CARRY(DD1L202_cout_1);
 
 
--PD1_a_o_3_d_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[1] at LC_X20_Y9_N1
--operation mode is normal
 
PD1_a_o_3_d_a[1] = PD1_a_o_sn_m2 & !PB1_r32_o_1 # !PD1_a_o_sn_m2 & !RB1_byte_addr_o_1;
 
 
--ED1_r32_o_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_6 at LC_X21_Y18_N5
--operation mode is normal
 
ED1_r32_o_6_lut_out = GE1_q_a[6];
ED1_r32_o_6 = DFFEAS(ED1_r32_o_6_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--DD1_pc_next_0_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_0 at LC_X27_Y10_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_0 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_0 # !DD1_pc_next_0_iv_1_a[0];
 
 
--DD1_un1_pc_add0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add0 at LC_X23_Y11_N4
--operation mode is arithmetic
 
DD1_un1_pc_add0 = KB1_r32_o_0 $ DD1_un1_pc_prectl_1_0_a4[0];
 
--DD1_un1_pc_carry_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_0 at LC_X23_Y11_N4
--operation mode is arithmetic
 
DD1_un1_pc_carry_0 = CARRY(KB1_r32_o_0 & DD1_un1_pc_prectl_1_0_a4[0]);
 
 
--PD1_a_o_3_d_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[0] at LC_X20_Y14_N6
--operation mode is normal
 
PD1_a_o_3_d_a[0] = PD1_a_o_sn_m2 & !PB1_r32_o_0 # !PD1_a_o_sn_m2 & !RB1_byte_addr_o_0;
 
 
--VD1_b_o_iv_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_21 at LC_X21_Y14_N3
--operation mode is normal
 
VD1_b_o_iv_21 = !G1_BUS15471_i_m[21] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] & AB1_r32_o_19 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[21] at LC_X21_Y14_N3
--operation mode is normal
 
VD1_op2_reged[21] = DFFEAS(VD1_b_o_iv_21, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_22 at LC_X25_Y13_N9
--operation mode is normal
 
VD1_b_o_iv_22 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] & !G1_BUS15471_i_m[22] & AB1_r32_o_20 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[22] at LC_X25_Y13_N9
--operation mode is normal
 
VD1_op2_reged[22] = DFFEAS(VD1_b_o_iv_22, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[11] at LC_X13_Y16_N6
--operation mode is normal
 
UD1_shift_out_79_a[11] = PD1_a_o_0 & !VD1_b_o_iv_20 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_19;
 
 
--VD1_b_o_iv_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_25 at LC_X20_Y12_N1
--operation mode is normal
 
VD1_b_o_iv_25 = !G1_BUS15471_i_m[25] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] & AB1_r32_o_23 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[25] at LC_X20_Y12_N1
--operation mode is normal
 
VD1_op2_reged[25] = DFFEAS(VD1_b_o_iv_25, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_26 at LC_X20_Y12_N9
--operation mode is normal
 
VD1_b_o_iv_26 = !G1_BUS15471_i_m[26] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] & AB1_r32_o_24 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[26] at LC_X20_Y12_N9
--operation mode is normal
 
VD1_op2_reged[26] = DFFEAS(VD1_b_o_iv_26, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[15] at LC_X15_Y18_N5
--operation mode is normal
 
UD1_shift_out_79_a[15] = PD1_a_o_0 & !VD1_b_o_iv_24 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_23;
 
 
--VD1_b_o_iv_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_29 at LC_X19_Y14_N6
--operation mode is normal
 
VD1_b_o_iv_29 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] & !G1_BUS15471_i_m[29] & AB1_r32_o_27 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[29] at LC_X19_Y14_N6
--operation mode is normal
 
VD1_op2_reged[29] = DFFEAS(VD1_b_o_iv_29, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[19] at LC_X14_Y10_N1
--operation mode is normal
 
UD1_shift_out_79_a[19] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_28 # !PD1_a_o_0 & !VD1_b_o_iv_27;
 
 
--VD1_b_o_iv_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_17 at LC_X21_Y16_N3
--operation mode is normal
 
VD1_b_o_iv_17 = !G1_BUS15471_i_m[17] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] & AB1_r32_o_15 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[17] at LC_X21_Y16_N3
--operation mode is normal
 
VD1_op2_reged[17] = DFFEAS(VD1_b_o_iv_17, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_18 at LC_X22_Y12_N4
--operation mode is normal
 
VD1_b_o_iv_18 = !G1_BUS15471_i_m[18] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] & AB1_r32_o_16 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[18] at LC_X22_Y12_N4
--operation mode is normal
 
VD1_op2_reged[18] = DFFEAS(VD1_b_o_iv_18, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[7] at LC_X15_Y17_N5
--operation mode is normal
 
UD1_shift_out_79_a[7] = PD1_a_o_0 & !VD1_b_o_iv_16 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_15;
 
 
--UD1_shift_out_39[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[19] at LC_X15_Y13_N6
--operation mode is normal
 
UD1_shift_out_39[19] = VD1_b_o_iv_31 & !PD1_a_o_0;
 
 
--VD1_hilo_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8 at LC_X6_Y16_N0
--operation mode is normal
 
VD1_hilo_8_lut_out = VD1_hilo_37_iv_0[8] # VD1_hilo_8_Z[8] & VD1_hilo25 # !VD1_hilo_37_iv_a[8];
VD1_hilo_8 = DFFEAS(VD1_hilo_8_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_3_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3_sqmuxa at LC_X2_Y15_N5
--operation mode is normal
 
VD1_hilo_3_sqmuxa = VD1_finish & VD1_addnop2110 & VD1_count[5];
 
 
--VD1_hilo_37_iv_0_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[7] at LC_X4_Y16_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[7] = VD1_add1 & !VD1_un134_hilo_combout[7] # !VD1_add1 & !VD1_hilo_7;
 
 
--VD1_hilo_40 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_40 at LC_X6_Y8_N9
--operation mode is normal
 
VD1_hilo_40_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_0_a[40] & !VD1_hilo_37_iv_0_5[40] & !VD1_hilo_37_iv_0_a6_3[40];
VD1_hilo_40 = DFFEAS(VD1_hilo_40_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_37_iv_0_a3_4[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_4[57] at LC_X4_Y4_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_4[57] = VD1_hilo_1_sqmuxa_1 & !VD1_sub_or_yn & VD1_hilo[0] & VD1_sign;
 
 
--VD1_un50_hilo_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add8 at LC_X10_Y4_N2
--operation mode is arithmetic
 
VD1_un50_hilo_add8_carry_eqn = (!VD1_un50_hilo_carry_5 & VD1_un50_hilo_carry_7) # (VD1_un50_hilo_carry_5 & VD1L6171);
VD1_un50_hilo_add8 = VD1_hilo_40 $ VD1_nop2_reged[8] $ !VD1_un50_hilo_add8_carry_eqn;
 
--VD1_un50_hilo_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_8 at LC_X10_Y4_N2
--operation mode is arithmetic
 
VD1_un50_hilo_carry_8_cout_0 = VD1_hilo_40 & VD1_nop2_reged[8] # !VD1_un50_hilo_carry_7 # !VD1_hilo_40 & VD1_nop2_reged[8] & !VD1_un50_hilo_carry_7;
VD1_un50_hilo_carry_8 = CARRY(VD1_un50_hilo_carry_8_cout_0);
 
--VD1L8171 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_8~COUT1_1 at LC_X10_Y4_N2
--operation mode is arithmetic
 
VD1L8171_cout_1 = VD1_hilo_40 & VD1_nop2_reged[8] # !VD1L6171 # !VD1_hilo_40 & VD1_nop2_reged[8] & !VD1L6171;
VD1L8171 = CARRY(VD1L8171_cout_1);
 
 
--VD1_un59_hilo_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add8 at LC_X9_Y5_N2
--operation mode is arithmetic
 
VD1_un59_hilo_add8_carry_eqn = (!VD1_un59_hilo_carry_5 & VD1_un59_hilo_carry_7) # (VD1_un59_hilo_carry_5 & VD1L9381);
VD1_un59_hilo_add8 = VD1_op2_reged[8] $ VD1_hilo_40 $ !VD1_un59_hilo_add8_carry_eqn;
 
--VD1_un59_hilo_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_8 at LC_X9_Y5_N2
--operation mode is arithmetic
 
VD1_un59_hilo_carry_8_cout_0 = VD1_op2_reged[8] & VD1_hilo_40 # !VD1_un59_hilo_carry_7 # !VD1_op2_reged[8] & VD1_hilo_40 & !VD1_un59_hilo_carry_7;
VD1_un59_hilo_carry_8 = CARRY(VD1_un59_hilo_carry_8_cout_0);
 
--VD1L1481 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_8~COUT1_1 at LC_X9_Y5_N2
--operation mode is arithmetic
 
VD1L1481_cout_1 = VD1_op2_reged[8] & VD1_hilo_40 # !VD1L9381 # !VD1_op2_reged[8] & VD1_hilo_40 & !VD1L9381;
VD1L1481 = CARRY(VD1L1481_cout_1);
 
 
--VD1_hilo_37_iv_0_1[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[39] at LC_X7_Y7_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_1[39] = VD1_hilo_37_iv_0_a2_1[39] # VD1_hilo_37_iv_0_a2_0[38] # !VD1_un59_hilo_add7 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--VD1_hilo_37_iv_0_4_a[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4_a[39] at LC_X7_Y7_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_4_a[39] = VD1_hilo_39 & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add7 # !VD1_hilo_39 & VD1_hilo_37_iv_0_o3_2[34] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add7;
 
 
--VD1_hilo_24_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add7 at LC_X8_Y4_N1
--operation mode is arithmetic
 
VD1_hilo_24_add7_carry_eqn = (!VD1_hilo_24_carry_5 & VD1_hilo_24_carry_6) # (VD1_hilo_24_carry_5 & VD1L884);
VD1_hilo_24_add7 = VD1_un1_op2_reged_1_combout[7] $ VD1_hilo_38 $ VD1_hilo_24_add7_carry_eqn;
 
--VD1_hilo_24_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_7 at LC_X8_Y4_N1
--operation mode is arithmetic
 
VD1_hilo_24_carry_7_cout_0 = VD1_un1_op2_reged_1_combout[7] & !VD1_hilo_38 & !VD1_hilo_24_carry_6 # !VD1_un1_op2_reged_1_combout[7] & !VD1_hilo_24_carry_6 # !VD1_hilo_38;
VD1_hilo_24_carry_7 = CARRY(VD1_hilo_24_carry_7_cout_0);
 
--VD1L094 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_7~COUT1_1 at LC_X8_Y4_N1
--operation mode is arithmetic
 
VD1L094_cout_1 = VD1_un1_op2_reged_1_combout[7] & !VD1_hilo_38 & !VD1L884 # !VD1_un1_op2_reged_1_combout[7] & !VD1L884 # !VD1_hilo_38;
VD1L094 = CARRY(VD1L094_cout_1);
 
 
--RD1_r32_o_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_7 at LC_X23_Y4_N5
--operation mode is arithmetic
 
RD1_r32_o_7_carry_eqn = RD1_r32_o_cout[5];
RD1_r32_o_7_lut_out = KB1_r32_o_7 $ (KB1_r32_o_6 & !RD1_r32_o_7_carry_eqn);
RD1_r32_o_7 = DFFEAS(RD1_r32_o_7_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[7] at LC_X23_Y4_N5
--operation mode is arithmetic
 
RD1_r32_o_cout[7]_cout_0 = KB1_r32_o_7 & KB1_r32_o_6 & !RD1_r32_o_cout[5];
RD1_r32_o_cout[7] = CARRY(RD1_r32_o_cout[7]_cout_0);
 
--RD1L37 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[7]~COUT1_12 at LC_X23_Y4_N5
--operation mode is arithmetic
 
RD1L37_cout_1 = KB1_r32_o_7 & KB1_r32_o_6 & !RD1_r32_o_cout[5];
RD1L37 = CARRY(RD1L37_cout_1);
 
 
--FB1_res_7_0_0_7 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_7 at LC_X22_Y11_N4
--operation mode is normal
 
FB1_res_7_0_0_7 = CD1_res_7_0_0_a2_0 & ED1_r32_o_7 # CD1_res_7_0_0_o3_0 & ED1_r32_o_5 # !CD1_res_7_0_0_a2_0 & CD1_res_7_0_0_o3_0 & ED1_r32_o_5;
 
--FB1_r32_o_0_7 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_7 at LC_X22_Y11_N4
--operation mode is normal
 
FB1_r32_o_0_7 = DFFEAS(FB1_res_7_0_0_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[7] at LC_X19_Y9_N2
--operation mode is normal
 
PD1_a_o_3_d[7] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_7 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[7] # !PD1_un6_a_o & !PD1_a_o_3_d_a[7];
 
 
--YB1_wb_we_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_we_1_0_0_0 at LC_X27_Y16_N9
--operation mode is normal
 
YB1_wb_we_1_0_0_0 = YB1_fsm_dly_2_0_0_o2_x[2] & YB1_alu_func_2_0_0_a2_0[1] & WB66L1 # !YB1_wb_we_1_0_0_a[0];
 
 
--WB66L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:wb_we_0_|lpm_latch:U1|q[0]~56 at LC_X27_Y16_N6
--operation mode is normal
 
WB66L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_wb_we_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB66L1;
 
--LC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11|wb_we_o_0 at LC_X27_Y16_N6
--operation mode is normal
 
LC1_wb_we_o_0 = DFFEAS(WB66L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_alu_we_1_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_0 at LC_X28_Y17_N0
--operation mode is normal
 
YB1_alu_we_1_0_0_0 = KE1_q_a[5] # YB1_alu_func_2_0_0_a3_1[1] # YB1_alu_we_1_0_0_0_Z[0] # YB1_alu_we_1_0_0_a3[0];
 
 
--WB24L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:alu_we_0_|lpm_latch:U1|q[0]~56 at LC_X28_Y17_N1
--operation mode is normal
 
WB24L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_alu_we_1_0_0_0 # !YB1_un1_muxa_ctl370_x & WB24L1;
 
--FC1_alu_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6|alu_we_o_0 at LC_X28_Y17_N1
--operation mode is normal
 
FC1_alu_we_o_0 = DFFEAS(WB24L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--SB1_un1_ctl_1_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_ctl_1_combout at LC_X13_Y9_N3
--operation mode is normal
 
QC1_dmem_ctl_o_1_qfbk = QC1_dmem_ctl_o_1;
SB1_un1_ctl_1_combout = !QC1_dmem_ctl_o_1_qfbk & QC1_dmem_ctl_o_2;
 
--QC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_1 at LC_X13_Y9_N3
--operation mode is normal
 
QC1_dmem_ctl_o_1 = DFFEAS(SB1_un1_ctl_1_combout, GLOBAL(E1__clk0), VCC, , , CC1_dmem_ctl_o_1, , !AD1_NET1640_i, VCC);
 
 
--WB3L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~84 at LC_X13_Y9_N8
--operation mode is normal
 
WB3L1 = SB1_un1_ctl_1_combout # SB1_un1_addr_i_1_combout & !RB1_c_1 # !SB1_un1_addr_i_1_combout & WB3L2;
 
 
--WB3L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~85 at LC_X13_Y9_N9
--operation mode is normal
 
WB3L2 = !SB1_un1_wr_en46_4_combout & WB3L1;
 
 
--TB1_dout21 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout21 at LC_X29_Y9_N9
--operation mode is normal
 
QC1_dmem_ctl_o_3_qfbk = QC1_dmem_ctl_o_3;
TB1_dout21 = QC1_dmem_ctl_o_0 & !QC1_dmem_ctl_o_1 & !QC1_dmem_ctl_o_3_qfbk & !QC1_dmem_ctl_o_2;
 
--QC1_dmem_ctl_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_3 at LC_X29_Y9_N9
--operation mode is normal
 
QC1_dmem_ctl_o_3 = DFFEAS(TB1_dout21, GLOBAL(E1__clk0), VCC, , , CC1_dmem_ctl_o_3, , !AD1_NET1640_i, VCC);
 
 
--TB1_dout22 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout22 at LC_X29_Y9_N4
--operation mode is normal
 
TB1_dout22 = !QC1_dmem_ctl_o_3 & QC1_dmem_ctl_o_1 & QC1_dmem_ctl_o_0 & QC1_dmem_ctl_o_2;
 
 
--CB1_dout_2_20 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_20 at LC_X22_Y14_N9
--operation mode is normal
 
CB1_dout_2_20 = ND1_dout7 & FD1_wb_o_20 # !ND1_dout7 & !ND1_dout_2_a_20;
 
--CB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_20 at LC_X22_Y14_N9
--operation mode is normal
 
CB1_r32_o_20 = DFFEAS(CB1_dout_2_20, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AD1_CurrState_Sreg0_ns_0_i_o2[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_i_o2[0] at LC_X30_Y17_N9
--operation mode is normal
 
AD1_CurrState_Sreg0_ns_0_i_o2[0] = AD1_CurrState_Sreg0_i[0] # !AD1_delay_counter_Sreg0[0] & AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 & !AD1_delay_counter_Sreg0[5];
 
 
--YB1_alu_func_2_0_0_a2_3[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_3[1] at LC_X28_Y16_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_3[1] = YB1_fsm_dly_2_0_0_a2_x[2] & YB1_cmp_ctl_2_0_0_a2_1[0] # !KE1_q_a[3] & YB1_cmp_ctl_2_0_0_a2_0[0];
 
 
--YB1_alu_func_2_0_0_3_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3_Z[1] at LC_X24_Y18_N0
--operation mode is normal
 
YB1_alu_func_2_0_0_3_Z[1] = YB1_alu_func_2_0_0_a2_x[0] & YB1_alu_func_2_0_0_a2_1[4] # YB1_alu_func_2_0_0_a2_2_x[1] # !YB1_alu_func_2_0_0_3_a[1];
 
 
--YB1_alu_func_2_0_0_a3_1[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1[1] at LC_X28_Y16_N0
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_1[1] = YB1_fsm_dly_2_0_0_a2_x[2] & YB1_alu_func_2_0_0_a2_0_x[0] # YB1_alu_func_2_0_0_a2_0[1] & YB1_alu_func_2_0_0_a2_0_x[4];
 
 
--YB1_un1_muxa_ctl370_6 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_6 at LC_X27_Y19_N8
--operation mode is normal
 
YB1_un1_muxa_ctl370_6 = !KE1_q_a[6] & YB1_un1_muxa_ctl370_6_a_x & KE1_q_a[3] $ KE1_q_a[4];
 
 
--YB1_un1_muxa_ctl370_5 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_5 at LC_X28_Y18_N8
--operation mode is normal
 
YB1_un1_muxa_ctl370_5 = KE1_q_a[6] & !KE1_q_a[2] & YB1_alu_func_2_0_0_a2_0[1] # !KE1_q_a[6] & YB1_un1_muxa_ctl370_5_a;
 
 
--YB1_un1_ins_i_22_1_a is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_22_1_a at LC_X28_Y18_N0
--operation mode is normal
 
YB1_un1_ins_i_22_1_a = KE1_q_a[4] & !KE1_q_a[2] & KE1_q_a[3] # !KE1_q_a[4] & KE1_q_a[5];
 
 
--YB1_fsm_dly_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_0 at LC_X25_Y17_N8
--operation mode is normal
 
YB1_fsm_dly_2_0_0_0 = YB1_ext_ctl_2_0_0_o3[2] # WB35L1 & YB1_ext_ctl_2_0_0_a3_1_0[2] # !YB1_fsm_dly_2_0_0_a[0];
 
 
--WB35L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1|q[0]~56 at LC_X25_Y17_N9
--operation mode is normal
 
WB35L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB35L1;
 
 
--YB1_fsm_dly_2_i_m3_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_i_m3_0[1] at LC_X28_Y17_N5
--operation mode is normal
 
YB1_fsm_dly_2_i_m3_0[1] = YB1_fsm_dly_2_0_0_a2_x[2] & GE1_q_a[3] & YB1_alu_func_2_0_0_a2_2_x[1] # !YB1_fsm_dly_2_i_m3_0_a[1];
 
 
--WB45L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y17_N6
--operation mode is normal
 
WB45L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_i_m3_0[1] # !YB1_un1_muxa_ctl370_x & WB45L1;
 
 
--YB1_fsm_dly_2_0_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0[2] at LC_X28_Y16_N3
--operation mode is normal
 
YB1_fsm_dly_2_0_0[2] = YB1_fsm_dly_2_0_0_a2_x[2] & YB1_fsm_dly_2_0_0_a2_0[2] & JE1_q_a[7] # !YB1_fsm_dly_2_0_0_a[2];
 
 
--WB55L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y16_N4
--operation mode is normal
 
WB55L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_fsm_dly_2_0_0[2] # !YB1_un1_muxa_ctl370_x & WB55L1;
 
 
--AD1_CurrState_Sreg0[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[8] at LC_X30_Y16_N0
--operation mode is normal
 
AD1_CurrState_Sreg0[8]_lut_out = AD1_CurrState_Sreg0_2 # AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] & WB55L1;
AD1_CurrState_Sreg0[8] = DFFEAS(AD1_CurrState_Sreg0[8]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--AD1_CurrState_Sreg0[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0[1] at LC_X30_Y16_N8
--operation mode is normal
 
AD1_CurrState_Sreg0[1]_lut_out = AD1_CurrState_Sreg0_ns_0_0_a2_2[1] & !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & AD1_CurrState_Sreg0_ns_0_i_o2[0] # !AD1_CurrState_Sreg0_ns_0_0_a[1];
AD1_CurrState_Sreg0[1] = DFFEAS(AD1_CurrState_Sreg0[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--YB1_alu_func_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_0 at LC_X28_Y15_N2
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_0 = YB1_alu_func_2_i_m3_0_5[2] # !KE1_q_a[4] & !GE1_q_a[3] & YB1_alu_func_2_i_m3_0_a[2];
 
 
--WB93L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~68 at LC_X28_Y15_N3
--operation mode is normal
 
WB93L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_alu_func_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB93L2;
 
 
--WB93L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1|q[0]~69 at LC_X28_Y15_N5
--operation mode is normal
 
WB93L2 = !YB1_un1_ins_i_23_2_0 & WB93L1;
 
--ZC1_alu_func_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_2 at LC_X28_Y15_N5
--operation mode is normal
 
ZC1_alu_func_o_2 = DFFEAS(WB93L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_alu_func_2_0_0_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3 at LC_X27_Y18_N3
--operation mode is normal
 
YB1_alu_func_2_0_0_3 = YB1_alu_func_2_0_0_o3[3] # YB1_alu_func_2_0_0_a3_1[3] # YB1_alu_func_2_0_0_a[3] # YB1_alu_func_2_0_0_a3_0[3];
 
 
--WB04L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~68 at LC_X27_Y18_N4
--operation mode is normal
 
WB04L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_alu_func_2_0_0_3 # !YB1_un1_muxa_ctl370_x & WB04L2;
 
 
--WB04L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1|q[0]~69 at LC_X27_Y18_N1
--operation mode is normal
 
WB04L2 = WB04L1 & !YB1_un1_ins_i_23_2_0;
 
--ZC1_alu_func_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26|alu_func_o_3 at LC_X27_Y18_N1
--operation mode is normal
 
ZC1_alu_func_o_3 = DFFEAS(WB04L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_alu_func_2_0_0_a[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[4] at LC_X29_Y18_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_a[4] = !YB1_alu_func_2_0_0_a3_1_x[4] & !KE1_q_a[4] & !KE1_q_a[3] # !KE1_q_a[5];
 
 
--YB1_alu_func_2_0_0_2[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2[4] at LC_X25_Y18_N3
--operation mode is normal
 
YB1_alu_func_2_0_0_2[4] = YB1_alu_func_2_0_0_1_Z[4] # !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[0] & !KE1_q_a[7];
 
 
--YB1_alu_func_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[0] at LC_X26_Y18_N2
--operation mode is normal
 
YB1_alu_func_2_0_0_a[0] = !YB1_cmp_ctl_2_0_0_a2_1[0] & !YB1_cmp_ctl_2_0_0_a2_0[0] # !YB1_alu_func_2_0_0_a2_0[1] # !WB73L1;
 
 
--YB1_alu_func_2_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3[0] at LC_X26_Y18_N6
--operation mode is normal
 
YB1_alu_func_2_0_0_a3[0] = !GE1_q_a[3] & GE1_q_a[0] & YB1_alu_func_2_0_0_a2_0[1] & YB1_alu_func_2_0_0_o2_0[0];
 
 
--YB1_alu_func_2_0_0_2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2_x[0] at LC_X26_Y18_N4
--operation mode is normal
 
YB1_alu_func_2_0_0_2_x[0] = YB1_alu_func_2_0_0_0_Z[0] # KE1_q_a[5] & !YB1_alu_func_2_0_0_2_a_x[0];
 
 
--YB1_alu_func_2_0_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0[0] at LC_X26_Y18_N3
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_0[0] = YB1_alu_func_2_0_0_a2_3_x[0] & !GE1_q_a[0] & YB1_alu_func_2_0_0_a2_2_x[1] # YB1_alu_func_2_0_0_a2_1[4];
 
 
--VD1_un134_hilo_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[4] at LC_X5_Y16_N4
--operation mode is arithmetic
 
VD1_un134_hilo_combout[4] = VD1_hilo_4 $ !VD1_un134_hilo_cout[2];
 
--VD1_un134_hilo_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[4] at LC_X5_Y16_N4
--operation mode is arithmetic
 
VD1_un134_hilo_cout[4] = CARRY(VD1_hilo_5 & VD1_hilo_4 & !VD1L3591);
 
 
--VD1_hilo_37_iv_0_a2_7[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[36] at LC_X6_Y8_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_7[36] = !VD1_un50_hilo_add5 & !VD1_sub_or_yn & VD1_hilo_37_iv_0_a2_7_2_1[37] & VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_5[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[36] at LC_X6_Y6_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_5[36] = VD1_hilo_37_iv_0_1[36] # VD1_hilo_37_iv_0_5_a[36] # !VD1_un59_hilo_add5 & VD1_hilo_37_iv_0_a6_1_0[40];
 
 
--XD1_un32_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un32_mux_fw at LC_X21_Y12_N5
--operation mode is normal
 
XD1_un32_mux_fw = !XD1_mux_fw_1 & WD1_un30_mux_fw # XD1_un17_mux_fw_NE # !MC1_wb_we_o_0;
 
 
--YB1_muxa_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0 at LC_X25_Y17_N7
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_0 = YB1_alu_func_2_0_0_a2_0[1] & !YB1_alu_func_2_0_0_o2_x[3] & YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_muxa_ctl_2_0_0_a[0];
 
 
--WB65L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxa_ctl_1_0_|lpm_latch:U1|q[0]~56 at LC_X25_Y17_N0
--operation mode is normal
 
WB65L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_muxa_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB65L1;
 
--GC1_muxa_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7|muxa_ctl_o_0 at LC_X25_Y17_N0
--operation mode is normal
 
GC1_muxa_ctl_o_0 = DFFEAS(WB65L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--ED1_r32_o_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_10 at LC_X22_Y17_N4
--operation mode is normal
 
ED1_r32_o_10_lut_out = HE1_q_a[2];
ED1_r32_o_10 = DFFEAS(ED1_r32_o_10_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--CD1_res_7_0_0_a2[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2[18] at LC_X22_Y16_N6
--operation mode is normal
 
CD1_res_7_0_0_a2[18] = DC1_ext_ctl_o_0 & DC1_ext_ctl_o_1 & !DC1_ext_ctl_o_2;
 
 
--WD1_un1_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE at LC_X25_Y9_N8
--operation mode is normal
 
AE1_q_4_qfbk = AE1_q_4;
WD1_un1_mux_fw_NE = WD1_un1_mux_fw_NE_1 # WD1_un1_mux_fw_NE_a # AE1_q_4_qfbk $ MB1_r5_o_4;
 
--AE1_q_4 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_4 at LC_X25_Y9_N8
--operation mode is normal
 
AE1_q_4 = DFFEAS(WD1_un1_mux_fw_NE, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_25, , , VCC);
 
 
--PB1_dout_iv_4 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_4 at LC_X16_Y11_N9
--operation mode is normal
 
PB1_dout_iv_4 = HD1_dout_iv_1_4 # HD1_dout7_0_a2 & FD1_wb_o_4;
 
--PB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_4 at LC_X16_Y11_N9
--operation mode is normal
 
PB1_r32_o_4 = DFFEAS(PB1_dout_iv_4, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_un6_a_o_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o_a at LC_X25_Y9_N7
--operation mode is normal
 
PD1_un6_a_o_a = MC1_wb_we_o_0 & !WD1_un17_mux_fw_NE & !WD1_un30_mux_fw;
 
 
--CD1_res_7_0_0_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_0 at LC_X22_Y11_N1
--operation mode is normal
 
ED1_r32_o_3_qfbk = ED1_r32_o_3;
CD1_res_7_0_0_a_0 = ED1_r32_o_9 & !CD1_res_7_0_0_0_a_0 & !ED1_r32_o_3_qfbk # !CD1_res_7_0_0_a2_0 # !ED1_r32_o_9 & !ED1_r32_o_3_qfbk # !CD1_res_7_0_0_a2_0;
 
--ED1_r32_o_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_3 at LC_X22_Y11_N1
--operation mode is normal
 
ED1_r32_o_3 = DFFEAS(CD1_res_7_0_0_a_0, GLOBAL(E1__clk0), VCC, , C1_G_504, GE1_q_a[3], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--PD1_a_o_3_d_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[3] at LC_X16_Y13_N2
--operation mode is normal
 
PD1_a_o_3_d_a[3] = PD1_a_o_sn_m2 & !PB1_r32_o_3 # !PD1_a_o_sn_m2 & !AB1_r32_o_1;
 
 
--VD1_b_o_iv_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_10 at LC_X20_Y15_N7
--operation mode is normal
 
VD1_b_o_iv_10 = !G1_BUS15471_i_m[10] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] & AB1_r32_o_8 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[10] at LC_X20_Y15_N7
--operation mode is normal
 
VD1_op2_reged[10] = DFFEAS(VD1_b_o_iv_10, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_80_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[4] at LC_X12_Y16_N1
--operation mode is normal
 
UD1_shift_out_80_a[4] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_7 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_5;
 
 
--VD1_b_o_iv_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_15 at LC_X16_Y5_N9
--operation mode is normal
 
VD1_b_o_iv_15 = !G1_BUS15471_i_m[15] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] & AB1_r32_o_13 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[15] at LC_X16_Y5_N9
--operation mode is normal
 
VD1_op2_reged[15] = DFFEAS(VD1_b_o_iv_15, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[4] at LC_X19_Y13_N7
--operation mode is normal
 
UD1_shift_out_79_a[4] = PD1_a_o_0 & !VD1_b_o_iv_13 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_12;
 
 
--VD1_b_o_iv_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_27 at LC_X21_Y15_N1
--operation mode is normal
 
VD1_b_o_iv_27 = !G1_BUS15471_i_m[27] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] & AB1_r32_o_25 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[27] at LC_X21_Y15_N1
--operation mode is normal
 
VD1_op2_reged[27] = DFFEAS(VD1_b_o_iv_27, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[16] at LC_X20_Y12_N5
--operation mode is normal
 
UD1_shift_out_79_a[16] = PD1_a_o_0 & !VD1_b_o_iv_25 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_24;
 
 
--UD1_shift_out_79_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[20] at LC_X21_Y13_N5
--operation mode is normal
 
UD1_shift_out_79_a[20] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_29 # !PD1_a_o_0 & !VD1_b_o_iv_28;
 
 
--VD1_b_o_iv_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_19 at LC_X22_Y15_N4
--operation mode is normal
 
VD1_b_o_iv_19 = !G1_BUS15471_i_m[19] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] & AB1_r32_o_17 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[19] at LC_X22_Y15_N4
--operation mode is normal
 
VD1_op2_reged[19] = DFFEAS(VD1_b_o_iv_19, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[8] at LC_X21_Y13_N0
--operation mode is normal
 
UD1_shift_out_79_a[8] = PD1_a_o_0 & !VD1_b_o_iv_17 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_16;
 
 
--VD1_b_o_iv_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_20 at LC_X22_Y14_N3
--operation mode is normal
 
VD1_b_o_iv_20 = !G1_BUS15471_i_m[20] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] & AB1_r32_o_18 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[20] at LC_X22_Y14_N3
--operation mode is normal
 
VD1_op2_reged[20] = DFFEAS(VD1_b_o_iv_20, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_47_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47_a[0] at LC_X21_Y13_N6
--operation mode is normal
 
UD1_shift_out_47_a[0] = PD1_a_o_0 & !VD1_b_o_iv_23 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_22;
 
 
--VD1_hilo_37_iv_0_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[6] at LC_X6_Y15_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[6] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_7 & !VD1_hilo_5 # !VD1_hilo_2_sqmuxa # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_5 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[6] at LC_X6_Y15_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_0[6] = VD1_hilo_6 & VD1_hilo_37_iv_0_o5[0] # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[6] # !VD1_hilo_6 & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[6];
 
 
--VD1_count[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[5] at LC_X32_Y9_N7
--operation mode is normal
 
VD1_count[5]_carry_eqn = (!VD1_count_cout[2] & VD1_count_cout[4]) # (VD1_count_cout[2] & VD1L211);
VD1_count[5]_lut_out = VD1_count[5] $ (VD1_count[5]_carry_eqn);
VD1_count[5] = DFFEAS(VD1_count[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
 
--VD1_overflow is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|overflow at LC_X8_Y13_N7
--operation mode is normal
 
VD1_overflow_lut_out = VD1_overflow & VD1_over_i[32] & !VD1_overflow_4_iv_a # !VD1_rdy_0_sqmuxa # !VD1_overflow & VD1_over_i[32] & !VD1_overflow_4_iv_a;
VD1_overflow = DFFEAS(VD1_overflow_lut_out, GLOBAL(E1__clk0), VCC, , sys_rst, , , , );
 
 
--VD1_mul is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul at LC_X9_Y14_N9
--operation mode is normal
 
VD1_mul_lut_out = !RC1_alu_func_o_4 & !RC1_alu_func_o_2 & !RC1_alu_func_o_1 & RC1_alu_func_o_3;
VD1_mul = DFFEAS(VD1_mul_lut_out, GLOBAL(E1__clk0), VCC, , VD1_mul_0_sqmuxa_i, , , , );
 
 
--VD1_addnop2110 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2110 at LC_X3_Y14_N6
--operation mode is normal
 
VD1_addnop2110 = VD1_start & !VD1_hilo25 & !VD1_rdy;
 
 
--VD1_rdy is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy at LC_X3_Y14_N0
--operation mode is normal
 
VD1_rdy_lut_out = VD1_rdy_1_i_a2_a & VD1_rdy # !VD1_rdy_1_i_a2_a & !VD1_addnop2109_0_a2 # !sys_rst;
VD1_rdy = DFFEAS(VD1_rdy_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un134_hilo_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[3] at LC_X4_Y16_N3
--operation mode is arithmetic
 
VD1_un134_hilo_combout[3] = VD1_hilo_3 $ (VD1_hilo_2 & VD1_un134_hilo_cout[1]);
 
--VD1_un134_hilo_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[3] at LC_X4_Y16_N3
--operation mode is arithmetic
 
VD1_un134_hilo_cout[3]_cout_0 = !VD1_un134_hilo_cout[1] # !VD1_hilo_3 # !VD1_hilo_2;
VD1_un134_hilo_cout[3] = CARRY(VD1_un134_hilo_cout[3]_cout_0);
 
--VD1L5591 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[3]~COUT1_2 at LC_X4_Y16_N3
--operation mode is arithmetic
 
VD1L5591_cout_1 = !VD1L1591 # !VD1_hilo_3 # !VD1_hilo_2;
VD1L5591 = CARRY(VD1L5591_cout_1);
 
 
--VD1_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1 at LC_X8_Y6_N2
--operation mode is normal
 
VD1_add1_lut_out = VD1_add1_3_sqmuxa_0_x & VD1_op2_sign_reged & !VD1_add1_14_a # !VD1_op2_sign_reged & VD1_add1_14_a & VD1_eqnop2_2_NE;
VD1_add1 = DFFEAS(VD1_add1_lut_out, GLOBAL(E1__clk0), VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
 
 
--VD1_mul_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul_0_sqmuxa_i at LC_X9_Y14_N8
--operation mode is normal
 
VD1_mul_0_sqmuxa_i = VD1_addnop2109_0_a2 # !sys_rst;
 
 
--VD1_hilo_4_sqmuxa_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_4_sqmuxa_0 at LC_X2_Y15_N0
--operation mode is normal
 
VD1_hilo_4_sqmuxa_0 = VD1_count[5] & !VD1_finish;
 
 
--C1_I_437_a_x is mips_sys:isys|I_437_a_x at LC_X3_Y14_N1
--operation mode is normal
 
C1_I_437_a_x = !VD1_rdy & sys_rst;
 
 
--VD1_eqop2_2_32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_32 at LC_X9_Y3_N9
--operation mode is normal
 
VD1_eqop2_2_32 = VD1_op2_sign_reged $ (VD1_hilo[64]);
 
 
--VD1_sub_or_yn_0_sqmuxa_1_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_i at LC_X3_Y14_N2
--operation mode is normal
 
VD1_sub_or_yn_0_sqmuxa_1_i = VD1_sub_or_yn_0_sqmuxa_1_a & VD1_un17_mul_0 # !VD1_addnop2109_0_a2 # !sys_rst;
 
 
--VD1_sign is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sign at LC_X9_Y14_N4
--operation mode is normal
 
VD1_sign_lut_out = !RC1_alu_func_o_4 & RC1_alu_func_o_3 & RC1_alu_func_o_0 & !RC1_alu_func_o_2;
VD1_sign = DFFEAS(VD1_sign_lut_out, GLOBAL(E1__clk0), VCC, , VD1_mul_0_sqmuxa_i, , , , );
 
 
--VD1_nop2_reged[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[6] at LC_X13_Y4_N5
--operation mode is arithmetic
 
VD1_nop2_reged[6]_carry_eqn = VD1_nop2_reged_cout[4];
VD1_nop2_reged[6] = VD1_op2_reged[6] $ !VD1_nop2_reged[6]_carry_eqn;
 
--VD1_nop2_reged_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[6] at LC_X13_Y4_N5
--operation mode is arithmetic
 
VD1_nop2_reged_cout[6]_cout_0 = VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[4];
VD1_nop2_reged_cout[6] = CARRY(VD1_nop2_reged_cout[6]_cout_0);
 
--VD1L1231 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[6]~COUT1_15 at LC_X13_Y4_N5
--operation mode is arithmetic
 
VD1L1231_cout_1 = VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[4];
VD1L1231 = CARRY(VD1L1231_cout_1);
 
 
--VD1_un50_hilo_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add5 at LC_X10_Y5_N9
--operation mode is arithmetic
 
VD1_un50_hilo_add5_carry_eqn = (!VD1_un50_hilo_carry_0 & VD1_un50_hilo_carry_4) # (VD1_un50_hilo_carry_0 & VD1L1171);
VD1_un50_hilo_add5 = VD1_hilo_37 $ VD1_nop2_reged[5] $ VD1_un50_hilo_add5_carry_eqn;
 
--VD1_un50_hilo_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_5 at LC_X10_Y5_N9
--operation mode is arithmetic
 
VD1_un50_hilo_carry_5 = CARRY(VD1_hilo_37 & !VD1_nop2_reged[5] & !VD1L1171 # !VD1_hilo_37 & !VD1L1171 # !VD1_nop2_reged[5]);
 
 
--VD1_un59_hilo_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add5 at LC_X9_Y6_N9
--operation mode is arithmetic
 
VD1_un59_hilo_add5_carry_eqn = (!VD1_un59_hilo_carry_0 & VD1_un59_hilo_carry_4) # (VD1_un59_hilo_carry_0 & VD1L4381);
VD1_un59_hilo_add5 = VD1_op2_reged[5] $ VD1_hilo_37 $ VD1_un59_hilo_add5_carry_eqn;
 
--VD1_un59_hilo_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_5 at LC_X9_Y6_N9
--operation mode is arithmetic
 
VD1_un59_hilo_carry_5 = CARRY(VD1_op2_reged[5] & !VD1_hilo_37 & !VD1L4381 # !VD1_op2_reged[5] & !VD1L4381 # !VD1_hilo_37);
 
 
--VD1_addop2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2 at LC_X8_Y6_N4
--operation mode is normal
 
VD1_addop2_lut_out = !VD1_mul & VD1_addnop290[0] # !VD1_addnop292[0] & VD1_un1_mul_2_a;
VD1_addop2 = DFFEAS(VD1_addop2_lut_out, GLOBAL(E1__clk0), VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
 
 
--VD1_hilo_37_iv_0_a2_7[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_7[34] at LC_X5_Y6_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_7[34] = VD1_hilo_3_sqmuxa & !VD1_addnop2;
 
 
--VD1_hilo_37_iv_0_1_a[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[37] at LC_X5_Y6_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[37] = VD1_hilo_5 & !VD1_hilo_37 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_5 & VD1_hilo_0_sqmuxa # !VD1_hilo_37 & VD1_hilo_37_iv_0_o3_2[34];
 
 
--VD1_hilo_37_iv_0_a2_6_0[37] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_6_0[37] at LC_X5_Y6_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_6_0[37] = !VD1_addop2 & VD1_hilo_3_sqmuxa & VD1_addnop2;
 
 
--VD1_hilo_24_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add5 at LC_X8_Y5_N9
--operation mode is arithmetic
 
VD1_hilo_24_add5_carry_eqn = (!VD1_hilo_24_carry_0 & VD1_hilo_24_carry_4) # (VD1_hilo_24_carry_0 & VD1L584);
VD1_hilo_24_add5 = VD1_un1_op2_reged_1_combout[5] $ VD1_hilo_36 $ VD1_hilo_24_add5_carry_eqn;
 
--VD1_hilo_24_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_5 at LC_X8_Y5_N9
--operation mode is arithmetic
 
VD1_hilo_24_carry_5 = CARRY(VD1_un1_op2_reged_1_combout[5] & !VD1_hilo_36 & !VD1L584 # !VD1_un1_op2_reged_1_combout[5] & !VD1L584 # !VD1_hilo_36);
 
 
--VD1_hilo_37_iv_0_5[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[38] at LC_X7_Y7_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_5[38] = VD1_hilo_39 & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add7 # !VD1_hilo_39 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add7;
 
 
--VD1_hilo_37_iv_0_4[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[38] at LC_X7_Y7_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_4[38] = VD1_hilo_37_iv_0_3[38] # !VD1_un59_hilo_add7 & VD1_hilo_37_iv_0_a6_1_0[40];
 
 
--VD1_hilo_37_iv_0_a[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[38] at LC_X6_Y9_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[38] = PD1_a_o_6 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add6 # !PD1_a_o_6 & VD1_hilo_37_iv_0_a3_1[0] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add6;
 
 
--VD1_un29_sign_0_o2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un29_sign_0_o2_0 at LC_X8_Y13_N5
--operation mode is normal
 
VD1_un29_sign_0_o2_0 = RC1_alu_func_o_2 # RC1_alu_func_o_4;
 
 
--PB1_dout_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_5 at LC_X20_Y11_N1
--operation mode is normal
 
PB1_dout_iv_5 = HD1_dout_iv_1_5 # FD1_wb_o_5 & HD1_dout7_0_a2;
 
--PB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_5 at LC_X20_Y11_N1
--operation mode is normal
 
PB1_r32_o_5 = DFFEAS(PB1_dout_iv_5, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UD1_shift_out_80_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[5] at LC_X15_Y19_N0
--operation mode is normal
 
UD1_shift_out_80_a[5] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_8 # !PD1_a_o_1 & !VD1_b_o_iv_6;
 
 
--VD1_b_o_iv_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_16 at LC_X21_Y5_N8
--operation mode is normal
 
VD1_b_o_iv_16 = !G1_BUS15471_i_m[16] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] & AB1_r32_o_14 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[16] at LC_X21_Y5_N8
--operation mode is normal
 
VD1_op2_reged[16] = DFFEAS(VD1_b_o_iv_16, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[5] at LC_X14_Y13_N5
--operation mode is normal
 
UD1_shift_out_79_a[5] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_13;
 
 
--VD1_b_o_iv_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_28 at LC_X19_Y14_N9
--operation mode is normal
 
VD1_b_o_iv_28 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] & !QD1_b_o_iv_1_27 & FB1_r32_o_28 # !QD1_b_o18;
 
--VD1_op2_reged[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[28] at LC_X19_Y14_N9
--operation mode is normal
 
VD1_op2_reged[28] = DFFEAS(VD1_b_o_iv_28, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[17] at LC_X15_Y13_N1
--operation mode is normal
 
UD1_shift_out_79_a[17] = PD1_a_o_0 & !PD1_a_o_1 & !VD1_b_o_iv_26 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_25;
 
 
--UD1_shift_out_39[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[17] at LC_X15_Y14_N2
--operation mode is normal
 
UD1_shift_out_39[17] = PD1_a_o_0 & VD1_b_o_iv_30 # !PD1_a_o_0 & VD1_b_o_iv_29;
 
 
--UD1_shift_out_79_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[9] at LC_X21_Y16_N0
--operation mode is normal
 
UD1_shift_out_79_a[9] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_18 # !PD1_a_o_0 & !VD1_b_o_iv_17;
 
 
--VD1_b_o_iv_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_23 at LC_X20_Y6_N2
--operation mode is normal
 
VD1_b_o_iv_23 = !G1_BUS15471_i_m[23] & !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] & AB1_r32_o_21 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[23] at LC_X20_Y6_N2
--operation mode is normal
 
VD1_op2_reged[23] = DFFEAS(VD1_b_o_iv_23, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_b_o_iv_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_24 at LC_X20_Y12_N4
--operation mode is normal
 
VD1_b_o_iv_24 = !C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] & !G1_BUS15471_i_m[24] & AB1_r32_o_22 # !QD1_b_o_0_sqmuxa;
 
--VD1_op2_reged[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged[24] at LC_X20_Y12_N4
--operation mode is normal
 
VD1_op2_reged[24] = DFFEAS(VD1_b_o_iv_24, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--UD1_shift_out_79_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[13] at LC_X21_Y14_N4
--operation mode is normal
 
UD1_shift_out_79_a[13] = PD1_a_o_0 & !PD1_a_o_1 & !VD1_b_o_iv_22 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_21;
 
 
--YB1_un1_ins_i_18_0_0_a2_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_0_0_a2_x at LC_X24_Y18_N5
--operation mode is normal
 
YB1_un1_ins_i_18_0_0_a2_x = KE1_q_a[7] & KE1_q_a[5] & !KE1_q_a[6];
 
 
--YB1_dmem_ctl_2_0_0_a3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a3[2] at LC_X28_Y18_N3
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_a3[2] = WB84L2 & YB1_alu_func_2_0_0_a2_0[1] & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
 
 
--YB1_dmem_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a[2] at LC_X28_Y18_N6
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_a[2] = KE1_q_a[7] & KE1_q_a[2] & KE1_q_a[3] & !KE1_q_a[4] # !KE1_q_a[2] & !KE1_q_a[3] & KE1_q_a[4];
 
 
--YB1_un1_ins_i_18_m_0_0_a3_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_18_m_0_0_a3_a_x at LC_X24_Y18_N7
--operation mode is normal
 
YB1_un1_ins_i_18_m_0_0_a3_a_x = KE1_q_a[4] & !KE1_q_a[3] # !KE1_q_a[4] & !KE1_q_a[5];
 
 
--UD1_shift_out_79_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[6] at LC_X19_Y18_N0
--operation mode is normal
 
UD1_shift_out_79_a[6] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_0 & !VD1_b_o_iv_14;
 
 
--UD1_shift_out_79_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[10] at LC_X13_Y16_N0
--operation mode is normal
 
UD1_shift_out_79_a[10] = PD1_a_o_0 & !VD1_b_o_iv_19 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_18;
 
 
--UD1_shift_out_79_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[18] at LC_X19_Y14_N3
--operation mode is normal
 
UD1_shift_out_79_a[18] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_27 # !PD1_a_o_0 & !VD1_b_o_iv_26;
 
 
--UD1_shift_out_79_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[2] at LC_X20_Y15_N9
--operation mode is normal
 
UD1_shift_out_79_a[2] = PD1_a_o_0 & !PD1_a_o_1 & !VD1_b_o_iv_11 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_10;
 
 
--UD1_shift_out_39[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_39[18] at LC_X19_Y17_N0
--operation mode is normal
 
UD1_shift_out_39[18] = PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
 
 
--VD1_un134_hilo_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[2] at LC_X5_Y16_N3
--operation mode is arithmetic
 
VD1_un134_hilo_combout[2] = VD1_hilo_2 $ (VD1_un134_hilo_cout[0]);
 
--VD1_un134_hilo_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[2] at LC_X5_Y16_N3
--operation mode is arithmetic
 
VD1_un134_hilo_cout[2]_cout_0 = !VD1_un134_hilo_cout[0] # !VD1_hilo_3 # !VD1_hilo_2;
VD1_un134_hilo_cout[2] = CARRY(VD1_un134_hilo_cout[2]_cout_0);
 
--VD1L3591 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[2]~COUT1_14 at LC_X5_Y16_N3
--operation mode is arithmetic
 
VD1L3591_cout_1 = !VD1L9491 # !VD1_hilo_3 # !VD1_hilo_2;
VD1L3591 = CARRY(VD1L3591_cout_1);
 
 
--VD1_un50_hilo_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add3 at LC_X10_Y5_N7
--operation mode is arithmetic
 
VD1_un50_hilo_add3_carry_eqn = (!VD1_un50_hilo_carry_0 & VD1_un50_hilo_carry_2) # (VD1_un50_hilo_carry_0 & VD1L7071);
VD1_un50_hilo_add3 = VD1_hilo_35 $ VD1_nop2_reged[3] $ VD1_un50_hilo_add3_carry_eqn;
 
--VD1_un50_hilo_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_3 at LC_X10_Y5_N7
--operation mode is arithmetic
 
VD1_un50_hilo_carry_3_cout_0 = VD1_hilo_35 & !VD1_nop2_reged[3] & !VD1_un50_hilo_carry_2 # !VD1_hilo_35 & !VD1_un50_hilo_carry_2 # !VD1_nop2_reged[3];
VD1_un50_hilo_carry_3 = CARRY(VD1_un50_hilo_carry_3_cout_0);
 
--VD1L9071 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_3~COUT1_1 at LC_X10_Y5_N7
--operation mode is arithmetic
 
VD1L9071_cout_1 = VD1_hilo_35 & !VD1_nop2_reged[3] & !VD1L7071 # !VD1_hilo_35 & !VD1L7071 # !VD1_nop2_reged[3];
VD1L9071 = CARRY(VD1L9071_cout_1);
 
 
--VD1_hilo_24_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add2 at LC_X8_Y5_N6
--operation mode is arithmetic
 
VD1_hilo_24_add2_carry_eqn = (!VD1_hilo_24_carry_0 & VD1_hilo_24_carry_1) # (VD1_hilo_24_carry_0 & VD1L974);
VD1_hilo_24_add2 = VD1_hilo_33 $ VD1_un1_op2_reged_1_combout[2] $ !VD1_hilo_24_add2_carry_eqn;
 
--VD1_hilo_24_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_2 at LC_X8_Y5_N6
--operation mode is arithmetic
 
VD1_hilo_24_carry_2_cout_0 = VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] # !VD1_hilo_24_carry_1 # !VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] & !VD1_hilo_24_carry_1;
VD1_hilo_24_carry_2 = CARRY(VD1_hilo_24_carry_2_cout_0);
 
--VD1L184 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_2~COUT1_1 at LC_X8_Y5_N6
--operation mode is arithmetic
 
VD1L184_cout_1 = VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] # !VD1L974 # !VD1_hilo_33 & VD1_un1_op2_reged_1_combout[2] & !VD1L974;
VD1L184 = CARRY(VD1L184_cout_1);
 
 
--VD1_hilo_37_iv_0_2[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[34] at LC_X6_Y7_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_2[34] = VD1_hilo_37_iv_0_a2_0[38] # VD1_hilo_37_iv_0_2_a[34] # VD1_hilo_37_iv_0_o3_2[34] & !VD1_hilo_34;
 
 
--VD1_hilo_37_iv_0_o3_1[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1[34] at LC_X3_Y9_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_1[34] = VD1_hilo_37_iv_0_o3_1_a[34] # !VD1_un59_hilo_add3 & VD1_hilo_37_iv_0_a6_1_0[40];
 
 
--VD1_hilo_37_iv_0[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[3] at LC_X6_Y16_N1
--operation mode is normal
 
VD1_hilo_37_iv_0[3] = VD1_hilo_1_sqmuxa_1 & VD1_hilo_4 # !VD1_hilo_37_iv_0_a[3] & VD1_hilo_3_sqmuxa # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_37_iv_0_a[3] & VD1_hilo_3_sqmuxa;
 
 
--VD1_hilo_8_Z[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[3] at LC_X6_Y16_N6
--operation mode is normal
 
VD1_hilo_8_Z[3] = RC1_alu_func_o_0 & VD1_hilo_3 # !RC1_alu_func_o_0 & PD1_a_o_3;
 
 
--VD1_hilo_37_iv_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[3] at LC_X6_Y16_N3
--operation mode is normal
 
VD1_hilo_37_iv_a[3] = VD1_hilo_2_sqmuxa & !VD1_hilo_2 & !VD1_addnop2109_0_a2 # !PD1_a_o_3 # !VD1_hilo_2_sqmuxa & !VD1_addnop2109_0_a2 # !PD1_a_o_3;
 
 
--VD1_hilo_37_iv_2[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[35] at LC_X3_Y6_N2
--operation mode is normal
 
VD1_hilo_37_iv_2[35] = VD1_hilo_37_iv_2_a[35] # VD1_hilo_33_i_m[35] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[35];
 
 
--VD1_hilo_37_iv_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[35] at LC_X5_Y8_N2
--operation mode is normal
 
VD1_hilo_37_iv_a[35] = RC1_alu_func_o_0 & !PD1_a_o_3 # !RC1_alu_func_o_0 & !VD1_hilo_35;
 
 
--UD1_shift_out_80_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[3] at LC_X13_Y19_N3
--operation mode is normal
 
UD1_shift_out_80_a[3] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_6 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_4;
 
 
--UD1_shift_out_79[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[3] at LC_X16_Y18_N0
--operation mode is normal
 
UD1_shift_out_79[3] = PD1_a_o_1 & UD1_shift_out_79_a[3] & VD1_b_o_iv_13 # !UD1_shift_out_79_a[3] & VD1_b_o_iv_14 # !PD1_a_o_1 & !UD1_shift_out_79_a[3];
 
 
--UD1_shift_out_76_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[3] at LC_X15_Y15_N3
--operation mode is normal
 
UD1_shift_out_76_a[3] = PD1_a_o_3 & UD1_shift_out_39[19] & !PD1_a_o_1 # !PD1_a_o_3 & UD1_shift_out_79[15];
 
 
--UD1_shift_out_74_c[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_c[3] at LC_X15_Y15_N0
--operation mode is normal
 
UD1_shift_out_74_c[3] = PD1_a_o_2 & PD1_a_o_3 # !PD1_a_o_2 & PD1_a_o_3 & UD1_shift_out_79[19] # !PD1_a_o_3 & UD1_shift_out_79[11];
 
 
--YB1_alu_func_2_0_0_a2_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0[1] at LC_X28_Y18_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_0[1] = !KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[7] & !KE1_q_a[4];
 
 
--YB1_fsm_dly_2_0_0_o2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_o2_x[2] at LC_X28_Y17_N8
--operation mode is normal
 
YB1_fsm_dly_2_0_0_o2_x[2] = YB1_cmp_ctl_2_0_0_a2_1[0] # YB1_cmp_ctl_2_0_0_a2_0[0];
 
 
--YB1_alu_func_2_0_0_a3_1_x[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1_x[4] at LC_X28_Y16_N7
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_1_x[4] = YB1_alu_func_2_0_0_a2_0[1] & !JE1_q_a[7] & YB1_fsm_dly_2_0_0_a2_0[2];
 
 
--YB1_un1_ins_i_23_2_0_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_ins_i_23_2_0_a_x at LC_X28_Y18_N9
--operation mode is normal
 
YB1_un1_ins_i_23_2_0_a_x = !KE1_q_a[6] & KE1_q_a[7] & !KE1_q_a[2];
 
 
--YB1_muxa_ctl373_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl373_a_x at LC_X29_Y18_N6
--operation mode is normal
 
YB1_muxa_ctl373_a_x = !KE1_q_a[5] # !KE1_q_a[7] # !KE1_q_a[2];
 
 
--YB1_dmem_ctl_2_0_0_a_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a_x[1] at LC_X29_Y18_N7
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_a_x[1] = !YB1_cmp_ctl_2_0_0_a2_0[0] & !YB1_cmp_ctl_2_0_0_a2_1[0];
 
 
--YB1_dmem_ctl_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1_Z[1] at LC_X29_Y18_N9
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_1_Z[1] = YB1_alu_func_2_0_0_a3_1_x[4] # !KE1_q_a[5] & !KE1_q_a[6] & YB1_dmem_ctl_2_0_0_1_a[1];
 
 
--UD1_shift_out_87_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[16] at LC_X9_Y18_N5
--operation mode is normal
 
UD1_shift_out_87_d[16] = PD1_a_o_0 & UD1_shift_out_80[16] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[16];
 
 
--UD1_shift_out_85_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[16] at LC_X9_Y18_N8
--operation mode is normal
 
UD1_shift_out_85_d[16] = PD1_a_o_2 & UD1_shift_out_52[28] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[16];
 
 
--UD1_shift_out_86_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[16] at LC_X13_Y12_N5
--operation mode is normal
 
UD1_shift_out_86_a[16] = !PD1_a_o_2 & UD1_shift_out587;
 
 
--UD1_shift_out_92_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[16] at LC_X13_Y12_N2
--operation mode is normal
 
UD1_shift_out_92_d_a[16] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_16 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[16];
 
 
--UD1_shift_out_84[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[16] at LC_X16_Y15_N2
--operation mode is normal
 
UD1_shift_out_84[16] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_92_d_a[8] # !PD1_a_o_4 & UD1_shift_out_77[16];
 
 
--VD1_hilo_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_16 at LC_X3_Y13_N2
--operation mode is normal
 
VD1_hilo_16_lut_out = VD1_hilo_37_iv_0_0[16] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_16 # !VD1_hilo_37_iv_0_a[16];
VD1_hilo_16 = DFFEAS(VD1_hilo_16_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_48 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_48 at LC_X4_Y8_N6
--operation mode is normal
 
VD1_hilo_48_lut_out = !VD1_hilo_37_iv_2[48] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[48] # !VD1_hilo25;
VD1_hilo_48 = DFFEAS(VD1_hilo_48_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_16 at LC_X25_Y4_N5
--operation mode is normal
 
PD1_a_o_16 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[16] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[16];
 
 
--TD1_m36_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m36_a at LC_X11_Y9_N9
--operation mode is normal
 
TD1_m36_a = VD1_b_o_iv_16 & PD1_a_o_16 & !TD1_m9 # !VD1_b_o_iv_16 & !PD1_a_o_16 # !TD1_m5;
 
 
--TD1_un1_a_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add16 at LC_X12_Y8_N1
--operation mode is arithmetic
 
TD1_un1_a_add16_carry_eqn = (!TD1_un1_a_carry_14 & TD1_un1_a_carry_15) # (TD1_un1_a_carry_14 & TD1L935);
TD1_un1_a_add16 = TD1_un1_b_1_combout[16] $ PD1_a_o_16 $ !TD1_un1_a_add16_carry_eqn;
 
--TD1_un1_a_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_16 at LC_X12_Y8_N1
--operation mode is arithmetic
 
TD1_un1_a_carry_16_cout_0 = TD1_un1_b_1_combout[16] & PD1_a_o_16 # !TD1_un1_a_carry_15 # !TD1_un1_b_1_combout[16] & PD1_a_o_16 & !TD1_un1_a_carry_15;
TD1_un1_a_carry_16 = CARRY(TD1_un1_a_carry_16_cout_0);
 
--TD1L145 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_16~COUT1_1 at LC_X12_Y8_N1
--operation mode is arithmetic
 
TD1L145_cout_1 = TD1_un1_b_1_combout[16] & PD1_a_o_16 # !TD1L935 # !TD1_un1_b_1_combout[16] & PD1_a_o_16 & !TD1L935;
TD1L145 = CARRY(TD1L145_cout_1);
 
 
--UD1_shift_out_87_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[17] at LC_X7_Y17_N7
--operation mode is normal
 
UD1_shift_out_87_d[17] = PD1_a_o_0 & UD1_shift_out_80[17] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[17];
 
 
--UD1_shift_out_85_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[17] at LC_X14_Y15_N0
--operation mode is normal
 
UD1_shift_out_85_d[17] = PD1_a_o_2 & UD1_shift_out_52[29] # !PD1_a_o_2 & !UD1_shift_out_77_a[23];
 
 
--UD1_shift_out_83[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[17] at LC_X14_Y12_N1
--operation mode is normal
 
UD1_shift_out_83[17] = PD1_a_o_1 & VD1_b_o_iv_31 & UD1_shift_out_83_a[17] # !PD1_a_o_1 & UD1_shift_out_39[17] & !UD1_shift_out_83_a[17];
 
 
--UD1_shift_out_92_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[17] at LC_X14_Y16_N5
--operation mode is normal
 
UD1_shift_out_92_d_a[17] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_17 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[17];
 
 
--UD1_shift_out_84[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[17] at LC_X14_Y16_N7
--operation mode is normal
 
UD1_shift_out_84[17] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[17] # !PD1_a_o_4 & UD1_shift_out_63[25];
 
 
--VD1_hilo_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_17 at LC_X3_Y16_N6
--operation mode is normal
 
VD1_hilo_17_lut_out = VD1_hilo_37_iv_0_0[17] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_17 # !VD1_hilo_37_iv_0_a[17];
VD1_hilo_17 = DFFEAS(VD1_hilo_17_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_49 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_49 at LC_X3_Y8_N8
--operation mode is normal
 
VD1_hilo_49_lut_out = !VD1_hilo_37_iv_2[49] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[49] # !VD1_hilo25;
VD1_hilo_49 = DFFEAS(VD1_hilo_49_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_17 at LC_X22_Y5_N9
--operation mode is normal
 
PD1_a_o_17 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[17] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[17];
 
 
--TD1_m41_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m41_a at LC_X9_Y12_N6
--operation mode is normal
 
TD1_m41_a = VD1_b_o_iv_17 & PD1_a_o_17 & !TD1_m9 # !VD1_b_o_iv_17 & !PD1_a_o_17 # !TD1_m5;
 
 
--TD1_un1_a_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add17 at LC_X12_Y8_N2
--operation mode is arithmetic
 
TD1_un1_a_add17_carry_eqn = (!TD1_un1_a_carry_14 & TD1_un1_a_carry_16) # (TD1_un1_a_carry_14 & TD1L145);
TD1_un1_a_add17 = PD1_a_o_17 $ TD1_un1_b_1_combout[17] $ TD1_un1_a_add17_carry_eqn;
 
--TD1_un1_a_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_17 at LC_X12_Y8_N2
--operation mode is arithmetic
 
TD1_un1_a_carry_17_cout_0 = PD1_a_o_17 & !TD1_un1_b_1_combout[17] & !TD1_un1_a_carry_16 # !PD1_a_o_17 & !TD1_un1_a_carry_16 # !TD1_un1_b_1_combout[17];
TD1_un1_a_carry_17 = CARRY(TD1_un1_a_carry_17_cout_0);
 
--TD1L345 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_17~COUT1_1 at LC_X12_Y8_N2
--operation mode is arithmetic
 
TD1L345_cout_1 = PD1_a_o_17 & !TD1_un1_b_1_combout[17] & !TD1L145 # !PD1_a_o_17 & !TD1L145 # !TD1_un1_b_1_combout[17];
TD1L345 = CARRY(TD1L345_cout_1);
 
 
--UD1_shift_out_87_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[14] at LC_X20_Y17_N3
--operation mode is normal
 
UD1_shift_out_87_d[14] = PD1_a_o_0 & UD1_shift_out_80[14] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[14];
 
 
--UD1_shift_out_85_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[14] at LC_X11_Y17_N3
--operation mode is normal
 
UD1_shift_out_85_d[14] = PD1_a_o_2 & UD1_shift_out_48[30] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[14];
 
 
--UD1_shift_out_74[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[14] at LC_X13_Y17_N6
--operation mode is normal
 
UD1_shift_out_74[14] = VD1_b_o_iv_31 $ (!PD1_a_o_0 & UD1_shift_out_74_a[14] & !PD1_a_o_1);
 
 
--UD1_shift_out_83[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[14] at LC_X13_Y17_N9
--operation mode is normal
 
UD1_shift_out_83[14] = UD1_shift_out587 & PD1_a_o_2 & UD1_shift_out_79[18] # !PD1_a_o_2 & UD1_shift_out_83_a[14] # !UD1_shift_out587 & UD1_shift_out_79[18];
 
 
--UD1_shift_out_63[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[22] at LC_X12_Y17_N5
--operation mode is normal
 
UD1_shift_out_63[22] = PD1_a_o_2 & UD1_shift_out_43[30] # !PD1_a_o_2 & UD1_shift_out_45[30];
 
 
--UD1_shift_out_92_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[14] at LC_X12_Y17_N9
--operation mode is normal
 
UD1_shift_out_92_d_a[14] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_14 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[14] # !UD1_shift_out_sn_m17_0;
 
 
--VD1_hilo_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_14 at LC_X4_Y13_N5
--operation mode is normal
 
VD1_hilo_14_lut_out = VD1_hilo_37_iv_0_0[14] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_14 # !VD1_hilo_37_iv_0_a[14];
VD1_hilo_14 = DFFEAS(VD1_hilo_14_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_46 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_46 at LC_X4_Y8_N9
--operation mode is normal
 
VD1_hilo_46_lut_out = !VD1_hilo_37_iv_2[46] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[46] # !VD1_hilo25;
VD1_hilo_46 = DFFEAS(VD1_hilo_46_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_14 at LC_X25_Y11_N9
--operation mode is normal
 
PD1_a_o_14 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[14] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[14];
 
 
--TD1_m26_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m26_a at LC_X9_Y12_N4
--operation mode is normal
 
TD1_m26_a = VD1_b_o_iv_14 & PD1_a_o_14 & !TD1_m9 # !VD1_b_o_iv_14 & !TD1_m5 # !PD1_a_o_14;
 
 
--TD1_un1_a_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add14 at LC_X12_Y9_N9
--operation mode is arithmetic
 
TD1_un1_a_add14_carry_eqn = (!TD1_un1_a_carry_9 & TD1_un1_a_carry_13) # (TD1_un1_a_carry_9 & TD1L635);
TD1_un1_a_add14 = PD1_a_o_14 $ TD1_un1_b_1_combout[14] $ !TD1_un1_a_add14_carry_eqn;
 
--TD1_un1_a_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_14 at LC_X12_Y9_N9
--operation mode is arithmetic
 
TD1_un1_a_carry_14 = CARRY(PD1_a_o_14 & TD1_un1_b_1_combout[14] # !TD1L635 # !PD1_a_o_14 & TD1_un1_b_1_combout[14] & !TD1L635);
 
 
--UD1_shift_out_87_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[15] at LC_X13_Y16_N5
--operation mode is normal
 
UD1_shift_out_87_d[15] = PD1_a_o_0 & UD1_shift_out_80[15] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[15];
 
 
--UD1_shift_out_85_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[15] at LC_X11_Y12_N6
--operation mode is normal
 
UD1_shift_out_85_d[15] = PD1_a_o_2 & UD1_shift_out_48[31] # !PD1_a_o_2 & !UD1_shift_out_77_a[21];
 
 
--UD1_shift_out_83[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[15] at LC_X14_Y17_N6
--operation mode is normal
 
UD1_shift_out_83[15] = PD1_a_o_2 & UD1_shift_out_79[19] # !PD1_a_o_2 & UD1_shift_out587 & UD1_shift_out_83_a[15] # !UD1_shift_out587 & UD1_shift_out_79[19];
 
 
--UD1_shift_out_63[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[23] at LC_X12_Y14_N6
--operation mode is normal
 
UD1_shift_out_63[23] = PD1_a_o_2 & UD1_shift_out_43[31] # !PD1_a_o_2 & UD1_shift_out_45[31];
 
 
--UD1_shift_out_92_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[15] at LC_X14_Y17_N2
--operation mode is normal
 
UD1_shift_out_92_d_a[15] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_15 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[15] # !UD1_shift_out_sn_m17_0;
 
 
--VD1_hilo_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15 at LC_X3_Y13_N8
--operation mode is normal
 
VD1_hilo_15_lut_out = VD1_hilo_37_iv_0_0[15] # PD1_a_o_15 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[15];
VD1_hilo_15 = DFFEAS(VD1_hilo_15_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_47 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_47 at LC_X4_Y8_N7
--operation mode is normal
 
VD1_hilo_47_lut_out = !VD1_hilo_37_iv_2[47] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[47] # !VD1_hilo25;
VD1_hilo_47 = DFFEAS(VD1_hilo_47_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_15 at LC_X19_Y6_N8
--operation mode is normal
 
PD1_a_o_15 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[15] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[15];
 
 
--TD1_m31_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m31_a at LC_X9_Y12_N1
--operation mode is normal
 
TD1_m31_a = PD1_a_o_15 & VD1_b_o_iv_15 & !TD1_m9 # !VD1_b_o_iv_15 & !TD1_m5 # !PD1_a_o_15 & !VD1_b_o_iv_15;
 
 
--TD1_un1_a_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add15 at LC_X12_Y8_N0
--operation mode is arithmetic
 
TD1_un1_a_add15_carry_eqn = TD1_un1_a_carry_14;
TD1_un1_a_add15 = TD1_un1_b_1_combout[15] $ PD1_a_o_15 $ TD1_un1_a_add15_carry_eqn;
 
--TD1_un1_a_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_15 at LC_X12_Y8_N0
--operation mode is arithmetic
 
TD1_un1_a_carry_15_cout_0 = TD1_un1_b_1_combout[15] & !PD1_a_o_15 & !TD1_un1_a_carry_14 # !TD1_un1_b_1_combout[15] & !TD1_un1_a_carry_14 # !PD1_a_o_15;
TD1_un1_a_carry_15 = CARRY(TD1_un1_a_carry_15_cout_0);
 
--TD1L935 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_15~COUT1_1 at LC_X12_Y8_N0
--operation mode is arithmetic
 
TD1L935_cout_1 = TD1_un1_b_1_combout[15] & !PD1_a_o_15 & !TD1_un1_a_carry_14 # !TD1_un1_b_1_combout[15] & !TD1_un1_a_carry_14 # !PD1_a_o_15;
TD1L935 = CARRY(TD1L935_cout_1);
 
 
--UD1_shift_out_68[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[27] at LC_X11_Y14_N6
--operation mode is normal
 
UD1_shift_out_68[27] = PD1_a_o_0 & VD1_b_o_iv_24 # !PD1_a_o_0 & VD1_b_o_iv_25;
 
 
--UD1_shift_out_68[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[29] at LC_X11_Y14_N1
--operation mode is normal
 
UD1_shift_out_68[29] = PD1_a_o_0 & VD1_b_o_iv_26 # !PD1_a_o_0 & VD1_b_o_iv_27;
 
 
--UD1_shift_out_85_c[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[31] at LC_X11_Y14_N2
--operation mode is normal
 
UD1_shift_out_85_c[31] = PD1_a_o_2 & PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_68[31] # !PD1_a_o_1 & VD1_b_o_iv_30;
 
 
--UD1_shift_out_92_d_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[31] at LC_X11_Y10_N7
--operation mode is normal
 
UD1_shift_out_92_d_a[31] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_31 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[31] at LC_X11_Y10_N6
--operation mode is normal
 
UD1_shift_out_84[31] = PD1_a_o_4 & UD1_shift_out_75[31] # !PD1_a_o_4 & UD1_shift_out_77[31];
 
 
--VD1_hilo_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_31 at LC_X6_Y13_N8
--operation mode is normal
 
VD1_hilo_31_lut_out = PD1_a_o_31 & VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_37_iv_0_a[31];
VD1_hilo_31 = DFFEAS(VD1_hilo_31_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_63 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_63 at LC_X8_Y8_N2
--operation mode is normal
 
VD1_hilo_63_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_2[63] & !VD1_hilo25 # !VD1_hilo_37_iv_a[63];
VD1_hilo_63 = DFFEAS(VD1_hilo_63_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--TD1_m101_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m101_a at LC_X12_Y6_N9
--operation mode is normal
 
TD1_m101_a = PD1_a_o_31 & !TD1_m5 & !VD1_b_o_iv_31 # !PD1_a_o_31 & VD1_b_o_iv_31 # !TD1_m4;
 
 
--TD1_un1_a_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add31 at LC_X12_Y7_N6
--operation mode is normal
 
TD1_un1_a_add31_carry_eqn = (!TD1_un1_a_carry_29 & TD1_un1_a_carry_30) # (TD1_un1_a_carry_29 & TD1L665);
TD1_un1_a_add31 = PD1_a_o_31 $ (TD1_un1_a_add31_carry_eqn $ TD1_un1_b_1_combout[31]);
 
 
--UD1_shift_out_87[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[8] at LC_X11_Y17_N9
--operation mode is normal
 
UD1_shift_out_87[8] = PD1_a_o_0 & UD1_shift_out_87_d[8] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[8] # !PD1_a_o_2 & VD1_b_o_iv_10;
 
 
--UD1_shift_out_89_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[8] at LC_X11_Y18_N5
--operation mode is normal
 
UD1_shift_out_89_a[8] = PD1_a_o_2 & !UD1_shift_out_85_d[8] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[8] # !PD1_a_o_1 & !VD1_b_o_iv_7;
 
 
--UD1_shift_out_86_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_8 at LC_X16_Y14_N7
--operation mode is normal
 
UD1_shift_out_86_8 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[8] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[8];
 
 
--UD1_shift_out_92_d_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_0 at LC_X16_Y15_N6
--operation mode is normal
 
UD1_shift_out_92_d_0 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[8] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_92_d_a[8];
 
 
--MD1_c_0_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[8] at LC_X10_Y8_N2
--operation mode is normal
 
MD1_c_0_a[8] = VD1_un24_res & !VD1_hilo_40 # !VD1_un24_res & !VD1_hilo_8 # !VD1_un11_res;
 
 
--TD1_m16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m16 at LC_X13_Y14_N0
--operation mode is normal
 
TD1_m16 = TD1_m16_a & PD1_a_o_8 # !TD1_m4 # !TD1_m16_a & TD1_m7 & !PD1_a_o_8;
 
 
--TD1_m13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m13 at LC_X16_Y15_N1
--operation mode is normal
 
TD1_m13 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add8;
 
 
--UD1_shift_out_87[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[9] at LC_X12_Y18_N2
--operation mode is normal
 
UD1_shift_out_87[9] = PD1_a_o_2 & UD1_shift_out_87_d[9] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[9] # !PD1_a_o_0 & VD1_b_o_iv_11;
 
 
--UD1_shift_out_89_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[9] at LC_X14_Y19_N8
--operation mode is normal
 
UD1_shift_out_89_a[9] = PD1_a_o_1 & !UD1_shift_out_85_d[9] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[9] # !PD1_a_o_2 & !VD1_b_o_iv_8;
 
 
--UD1_shift_out_86_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_9 at LC_X14_Y13_N6
--operation mode is normal
 
UD1_shift_out_86_9 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[9] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[9];
 
 
--UD1_shift_out_92_d_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_1 at LC_X13_Y13_N1
--operation mode is normal
 
UD1_shift_out_92_d_1 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[9] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_63_a[17] & UD1_shift_out_92_d_a[9];
 
 
--MD1_c_0_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[9] at LC_X7_Y8_N4
--operation mode is normal
 
MD1_c_0_a[9] = VD1_un24_res & !VD1_hilo_41 # !VD1_un24_res & !VD1_hilo_9 # !VD1_un11_res;
 
 
--TD1_m117 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m117 at LC_X13_Y14_N3
--operation mode is normal
 
TD1_m117 = PD1_a_o_9 & TD1_m117_a # !PD1_a_o_9 & TD1_m117_a & !TD1_m4 # !TD1_m117_a & TD1_m7;
 
 
--TD1_m114 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m114 at LC_X13_Y13_N3
--operation mode is normal
 
TD1_m114 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add9;
 
 
--MD1_c_1_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_a[10] at LC_X7_Y14_N1
--operation mode is normal
 
MD1_c_1_a[10] = VD1_un24_res & !VD1_hilo_42 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_10;
 
 
--TD1_alu_out_0_a2_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_4 at LC_X7_Y14_N3
--operation mode is normal
 
TD1_alu_out_0_a2_4 = TD1_alu_out_sn_m14_0_0 & PD1_a_o_10 & !TD1_alu_out_0_a2_a[10] # !PD1_a_o_10 & TD1_alu_out_7_0_0_m4_0[10];
 
 
--PD1_a_o_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_10 at LC_X19_Y12_N8
--operation mode is normal
 
PD1_a_o_10 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[10] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[10];
 
 
--TD1_un1_b_1_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[10] at LC_X13_Y8_N0
--operation mode is normal
 
TD1_un1_b_1_combout[10] = TD1_sum13_0_a2 $ !VD1_b_o_iv_10;
 
 
--TD1_un1_a_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add9 at LC_X12_Y9_N4
--operation mode is arithmetic
 
TD1_un1_a_add9_carry_eqn = (!TD1_un1_a_carry_4 & TD1_un1_a_carry_8) # (TD1_un1_a_carry_4 & TD1L725);
TD1_un1_a_add9 = PD1_a_o_9 $ TD1_un1_b_1_combout[9] $ TD1_un1_a_add9_carry_eqn;
 
--TD1_un1_a_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_9 at LC_X12_Y9_N4
--operation mode is arithmetic
 
TD1_un1_a_carry_9 = CARRY(PD1_a_o_9 & !TD1_un1_b_1_combout[9] & !TD1L725 # !PD1_a_o_9 & !TD1L725 # !TD1_un1_b_1_combout[9]);
 
 
--UD1_shift_out_89[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[10] at LC_X19_Y16_N6
--operation mode is normal
 
UD1_shift_out_89[10] = UD1_shift_out586 & !UD1_shift_out_89_a[10] # !UD1_shift_out586 & UD1_shift_out_87[10];
 
 
--UD1_shift_out_92[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92[10] at LC_X19_Y16_N5
--operation mode is normal
 
UD1_shift_out_92[10] = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[10] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_a[10];
 
 
--UD1_shift_out_87[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[11] at LC_X13_Y18_N9
--operation mode is normal
 
UD1_shift_out_87[11] = PD1_a_o_2 & UD1_shift_out_87_d[11] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[11] # !PD1_a_o_0 & VD1_b_o_iv_13;
 
 
--UD1_shift_out_89_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[11] at LC_X11_Y16_N1
--operation mode is normal
 
UD1_shift_out_89_a[11] = PD1_a_o_2 & !UD1_shift_out_85_d[11] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[11] # !PD1_a_o_1 & !VD1_b_o_iv_10;
 
 
--UD1_shift_out_86_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_11 at LC_X15_Y17_N1
--operation mode is normal
 
UD1_shift_out_86_11 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[11] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[11];
 
 
--UD1_shift_out_92_d_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_3 at LC_X15_Y16_N3
--operation mode is normal
 
UD1_shift_out_92_d_3 = UD1_shift_out_sn_m25_0 & UD1_shift_out_91[11] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_77[11];
 
 
--MD1_c_0_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[11] at LC_X10_Y8_N4
--operation mode is normal
 
MD1_c_0_a[11] = VD1_un24_res & !VD1_hilo_43 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_11;
 
 
--TD1_m21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m21 at LC_X13_Y14_N1
--operation mode is normal
 
TD1_m21 = PD1_a_o_11 & TD1_m21_a # !PD1_a_o_11 & TD1_m21_a & !TD1_m4 # !TD1_m21_a & TD1_m7;
 
 
--TD1_m18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m18 at LC_X15_Y16_N8
--operation mode is normal
 
TD1_m18 = TD1_un1_a_add11 & TD1_alu_out_sn_m14_0_0;
 
 
--UD1_shift_out_87_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[21] at LC_X7_Y18_N3
--operation mode is normal
 
UD1_shift_out_87_d[21] = PD1_a_o_0 & UD1_shift_out_80[21] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[21];
 
 
--UD1_shift_out_85_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[21] at LC_X14_Y12_N6
--operation mode is normal
 
UD1_shift_out_85_d[21] = PD1_a_o_2 & UD1_shift_out_54[29] # !PD1_a_o_2 & !UD1_shift_out_77_a[27];
 
 
--UD1_shift_out_92_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[21] at LC_X14_Y10_N5
--operation mode is normal
 
UD1_shift_out_92_d_a[21] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_21 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[21];
 
 
--UD1_shift_out_84[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[21] at LC_X14_Y11_N2
--operation mode is normal
 
UD1_shift_out_84[21] = PD1_a_o_4 & UD1_shift_out_63[21] & !PD1_a_o_3 # !PD1_a_o_4 & UD1_shift_out_77[21];
 
 
--VD1_hilo_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_21 at LC_X4_Y14_N6
--operation mode is normal
 
VD1_hilo_21_lut_out = VD1_hilo_37_iv_0_0[21] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_21 # !VD1_hilo_37_iv_0_a[21];
VD1_hilo_21 = DFFEAS(VD1_hilo_21_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_53 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_53 at LC_X5_Y8_N6
--operation mode is normal
 
VD1_hilo_53_lut_out = !VD1_hilo_37_iv_2[53] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[53] # !VD1_hilo25;
VD1_hilo_53 = DFFEAS(VD1_hilo_53_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_21 at LC_X22_Y9_N9
--operation mode is normal
 
PD1_a_o_21 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[21] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[21];
 
 
--TD1_m132_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m132_a at LC_X9_Y8_N5
--operation mode is normal
 
TD1_m132_a = PD1_a_o_21 & VD1_b_o_iv_21 & !TD1_m9 # !VD1_b_o_iv_21 & !TD1_m5 # !PD1_a_o_21 & !VD1_b_o_iv_21;
 
 
--TD1_un1_a_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add21 at LC_X12_Y8_N6
--operation mode is arithmetic
 
TD1_un1_a_add21_carry_eqn = (!TD1_un1_a_carry_19 & TD1_un1_a_carry_20) # (TD1_un1_a_carry_19 & TD1L845);
TD1_un1_a_add21 = PD1_a_o_21 $ TD1_un1_b_1_combout[21] $ TD1_un1_a_add21_carry_eqn;
 
--TD1_un1_a_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_21 at LC_X12_Y8_N6
--operation mode is arithmetic
 
TD1_un1_a_carry_21_cout_0 = PD1_a_o_21 & !TD1_un1_b_1_combout[21] & !TD1_un1_a_carry_20 # !PD1_a_o_21 & !TD1_un1_a_carry_20 # !TD1_un1_b_1_combout[21];
TD1_un1_a_carry_21 = CARRY(TD1_un1_a_carry_21_cout_0);
 
--TD1L055 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_21~COUT1_1 at LC_X12_Y8_N6
--operation mode is arithmetic
 
TD1L055_cout_1 = PD1_a_o_21 & !TD1_un1_b_1_combout[21] & !TD1L845 # !PD1_a_o_21 & !TD1L845 # !TD1_un1_b_1_combout[21];
TD1L055 = CARRY(TD1L055_cout_1);
 
 
--UD1_shift_out_87_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[20] at LC_X6_Y18_N2
--operation mode is normal
 
UD1_shift_out_87_d[20] = PD1_a_o_0 & UD1_shift_out_80[20] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[20];
 
 
--UD1_shift_out_85_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[20] at LC_X10_Y18_N0
--operation mode is normal
 
UD1_shift_out_85_d[20] = PD1_a_o_2 & UD1_shift_out_54[28] # !PD1_a_o_2 & !UD1_shift_out_77_a[26];
 
 
--VD1_hilo_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_20 at LC_X4_Y14_N9
--operation mode is normal
 
VD1_hilo_20_lut_out = VD1_hilo_37_iv_0_0[20] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_20 # !VD1_hilo_37_iv_0_a[20];
VD1_hilo_20 = DFFEAS(VD1_hilo_20_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_52 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_52 at LC_X5_Y5_N4
--operation mode is normal
 
VD1_hilo_52_lut_out = VD1_hilo_37_iv_0_a[52] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_20 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_52 = DFFEAS(VD1_hilo_52_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_20 at LC_X22_Y13_N4
--operation mode is normal
 
PD1_a_o_20 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[20] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[20];
 
 
--TD1_m56_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m56_a at LC_X10_Y14_N5
--operation mode is normal
 
TD1_m56_a = VD1_b_o_iv_20 & !TD1_m9 & PD1_a_o_20 # !VD1_b_o_iv_20 & !PD1_a_o_20 # !TD1_m5;
 
 
--TD1_un1_a_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add20 at LC_X12_Y8_N5
--operation mode is arithmetic
 
TD1_un1_a_add20_carry_eqn = TD1_un1_a_carry_19;
TD1_un1_a_add20 = PD1_a_o_20 $ TD1_un1_b_1_combout[20] $ !TD1_un1_a_add20_carry_eqn;
 
--TD1_un1_a_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_20 at LC_X12_Y8_N5
--operation mode is arithmetic
 
TD1_un1_a_carry_20_cout_0 = PD1_a_o_20 & TD1_un1_b_1_combout[20] # !TD1_un1_a_carry_19 # !PD1_a_o_20 & TD1_un1_b_1_combout[20] & !TD1_un1_a_carry_19;
TD1_un1_a_carry_20 = CARRY(TD1_un1_a_carry_20_cout_0);
 
--TD1L845 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_20~COUT1_1 at LC_X12_Y8_N5
--operation mode is arithmetic
 
TD1L845_cout_1 = PD1_a_o_20 & TD1_un1_b_1_combout[20] # !TD1_un1_a_carry_19 # !PD1_a_o_20 & TD1_un1_b_1_combout[20] & !TD1_un1_a_carry_19;
TD1L845 = CARRY(TD1L845_cout_1);
 
 
--UD1_shift_out_92_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[20] at LC_X10_Y17_N5
--operation mode is normal
 
UD1_shift_out_92_d_a[20] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_20 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[20];
 
 
--UD1_shift_out_84[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[20] at LC_X10_Y17_N8
--operation mode is normal
 
UD1_shift_out_84[20] = PD1_a_o_4 & !PD1_a_o_3 & !UD1_shift_out_84_a[20] # !PD1_a_o_4 & UD1_shift_out_63[28];
 
 
--UD1_shift_out_87[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[19] at LC_X10_Y9_N4
--operation mode is normal
 
UD1_shift_out_87[19] = PD1_a_o_2 & UD1_shift_out_87_d[19] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[19] # !PD1_a_o_0 & VD1_b_o_iv_21;
 
 
--UD1_shift_out_89_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[19] at LC_X14_Y12_N8
--operation mode is normal
 
UD1_shift_out_89_a[19] = PD1_a_o_1 & !UD1_shift_out_85_d[19] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[19] # !PD1_a_o_2 & !VD1_b_o_iv_18;
 
 
--MD1_c_0_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[19] at LC_X10_Y7_N8
--operation mode is normal
 
MD1_c_0_a[19] = VD1_un24_res & !VD1_hilo_51 # !VD1_un24_res & !VD1_hilo_19 # !VD1_un11_res;
 
 
--TD1_m51 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m51 at LC_X10_Y7_N5
--operation mode is normal
 
TD1_m51 = PD1_a_o_19 & TD1_m51_a # !PD1_a_o_19 & TD1_m51_a & !TD1_m4 # !TD1_m51_a & TD1_m7;
 
 
--TD1_m48 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m48 at LC_X10_Y7_N2
--operation mode is normal
 
TD1_m48 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add19;
 
 
--UD1_shift_out_92_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[19] at LC_X14_Y8_N5
--operation mode is normal
 
UD1_shift_out_92_a[19] = !PD1_a_o_0 & !PD1_a_o_1 & PD1_a_o_2 # !UD1_shift_out587;
 
 
--UD1_shift_out_92_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[19] at LC_X15_Y12_N7
--operation mode is normal
 
UD1_shift_out_92_d[19] = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[19] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[19];
 
 
--UD1_shift_out_87[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[18] at LC_X10_Y16_N5
--operation mode is normal
 
UD1_shift_out_87[18] = PD1_a_o_2 & UD1_shift_out_87_d[18] # !PD1_a_o_2 & PD1_a_o_0 & UD1_shift_out_87_d[18] # !PD1_a_o_0 & VD1_b_o_iv_20;
 
 
--UD1_shift_out_89_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[18] at LC_X10_Y18_N1
--operation mode is normal
 
UD1_shift_out_89_a[18] = PD1_a_o_2 & !UD1_shift_out_85_d[18] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[18] # !PD1_a_o_1 & !VD1_b_o_iv_17;
 
 
--UD1_shift_out_92_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[18] at LC_X13_Y17_N3
--operation mode is normal
 
UD1_shift_out_92_a[18] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_83[18] # !UD1_shift_out_sn_b9_0 & !VD1_b_o_iv_31;
 
 
--UD1_shift_out_92_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[18] at LC_X11_Y15_N8
--operation mode is normal
 
UD1_shift_out_92_d[18] = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[18] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[18];
 
 
--MD1_c_0_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[18] at LC_X5_Y14_N0
--operation mode is normal
 
MD1_c_0_a[18] = VD1_un24_res & !VD1_hilo_50 # !VD1_un24_res & !VD1_hilo_18 # !VD1_un11_res;
 
 
--TD1_m46 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m46 at LC_X5_Y14_N4
--operation mode is normal
 
TD1_m46 = PD1_a_o_18 & TD1_m46_a # !PD1_a_o_18 & TD1_m46_a & !TD1_m4 # !TD1_m46_a & TD1_m7;
 
 
--TD1_m43 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m43 at LC_X5_Y14_N6
--operation mode is normal
 
TD1_m43 = TD1_un1_a_add18 & TD1_alu_out_sn_m14_0_0;
 
 
--UD1_shift_out_89_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[26] at LC_X8_Y15_N5
--operation mode is normal
 
UD1_shift_out_89_a[26] = PD1_a_o_0 & !UD1_shift_out_87_d[26] # !PD1_a_o_0 & PD1_a_o_2 & !UD1_shift_out_87_d[26] # !PD1_a_o_2 & !VD1_b_o_iv_28;
 
 
--UD1_shift_out_85[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[26] at LC_X8_Y17_N2
--operation mode is normal
 
UD1_shift_out_85[26] = PD1_a_o_2 & UD1_shift_out_85_a[26] & UD1_shift_out_68[24] # !UD1_shift_out_85_a[26] & UD1_shift_out_68[22] # !PD1_a_o_2 & !UD1_shift_out_85_a[26];
 
 
--UD1_shift_out_92_d_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_18 at LC_X11_Y15_N5
--operation mode is normal
 
UD1_shift_out_92_d_18 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[26] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[26];
 
 
--MD1_c_0_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[26] at LC_X6_Y14_N2
--operation mode is normal
 
MD1_c_0_a[26] = VD1_un24_res & !VD1_hilo_58 # !VD1_un24_res & !VD1_hilo_26 # !VD1_un11_res;
 
 
--TD1_m81 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m81 at LC_X6_Y14_N5
--operation mode is normal
 
TD1_m81 = PD1_a_o_26 & TD1_m81_a # !PD1_a_o_26 & TD1_m81_a & !TD1_m4 # !TD1_m81_a & TD1_m7;
 
 
--TD1_m78 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m78 at LC_X6_Y14_N7
--operation mode is normal
 
TD1_m78 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add26;
 
 
--UD1_shift_out_85[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[27] at LC_X11_Y14_N0
--operation mode is normal
 
UD1_shift_out_85[27] = PD1_a_o_2 & UD1_shift_out_85_a[27] & UD1_shift_out_68[25] # !UD1_shift_out_85_a[27] & UD1_shift_out_68[23] # !PD1_a_o_2 & !UD1_shift_out_85_a[27];
 
 
--UD1_shift_out_89_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[27] at LC_X11_Y7_N9
--operation mode is normal
 
UD1_shift_out_89_a[27] = PD1_a_o_2 & !UD1_shift_out_87_d[27] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[27] # !PD1_a_o_0 & !VD1_b_o_iv_29;
 
 
--UD1_shift_out_92_d_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_19 at LC_X12_Y13_N3
--operation mode is normal
 
UD1_shift_out_92_d_19 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[27] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[27];
 
 
--MD1_c_0_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[27] at LC_X11_Y7_N1
--operation mode is normal
 
MD1_c_0_a[27] = VD1_un24_res & !VD1_hilo_59 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_27;
 
 
--TD1_m86 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m86 at LC_X13_Y14_N9
--operation mode is normal
 
TD1_m86 = PD1_a_o_27 & TD1_m86_a # !PD1_a_o_27 & TD1_m86_a & !TD1_m4 # !TD1_m86_a & TD1_m7;
 
 
--TD1_m83 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m83 at LC_X11_Y7_N4
--operation mode is normal
 
TD1_m83 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add27;
 
 
--UD1_shift_out_87[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[28] at LC_X8_Y16_N8
--operation mode is normal
 
UD1_shift_out_87[28] = PD1_a_o_1 & PD1_a_o_0 & !UD1_shift_out_87_a[28] # !PD1_a_o_0 & UD1_shift_out_87_d[28] # !PD1_a_o_1 & UD1_shift_out_87_d[28];
 
 
--UD1_shift_out_85[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[28] at LC_X8_Y17_N9
--operation mode is normal
 
UD1_shift_out_85[28] = PD1_a_o_2 & UD1_shift_out_85_a[28] & UD1_shift_out_68[26] # !UD1_shift_out_85_a[28] & UD1_shift_out_68[24] # !PD1_a_o_2 & !UD1_shift_out_85_a[28];
 
 
--TD1_alu_out_0_a2_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_22 at LC_X9_Y15_N2
--operation mode is normal
 
TD1_alu_out_0_a2_22 = !PD1_a_o_28 & TD1_alu_out_0_a2_a[28] & VD1_b_o_iv_28 $ RC1_alu_func_o_0;
 
 
--MD1_c_2[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2[28] at LC_X7_Y15_N8
--operation mode is normal
 
MD1_c_2[28] = TD1_alu_out_0_a2_3_0 # MD1_c_0_Z[28] # MD1_c_2_a[28] & PD1_a_o_28;
 
 
--TD1_un1_a_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add28 at LC_X12_Y7_N3
--operation mode is arithmetic
 
TD1_un1_a_add28_carry_eqn = (!TD1_un1_a_carry_24 & TD1_un1_a_carry_27) # (TD1_un1_a_carry_24 & TD1L165);
TD1_un1_a_add28 = PD1_a_o_28 $ TD1_un1_b_1_combout[28] $ !TD1_un1_a_add28_carry_eqn;
 
--TD1_un1_a_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_28 at LC_X12_Y7_N3
--operation mode is arithmetic
 
TD1_un1_a_carry_28_cout_0 = PD1_a_o_28 & TD1_un1_b_1_combout[28] # !TD1_un1_a_carry_27 # !PD1_a_o_28 & TD1_un1_b_1_combout[28] & !TD1_un1_a_carry_27;
TD1_un1_a_carry_28 = CARRY(TD1_un1_a_carry_28_cout_0);
 
--TD1L365 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_28~COUT1_1 at LC_X12_Y7_N3
--operation mode is arithmetic
 
TD1L365_cout_1 = PD1_a_o_28 & TD1_un1_b_1_combout[28] # !TD1L165 # !PD1_a_o_28 & TD1_un1_b_1_combout[28] & !TD1L165;
TD1L365 = CARRY(TD1L365_cout_1);
 
 
--UD1_shift_out_92_d_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_20 at LC_X9_Y16_N4
--operation mode is normal
 
UD1_shift_out_92_d_20 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[28] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[28];
 
 
--UD1_shift_out_87[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[29] at LC_X8_Y15_N1
--operation mode is normal
 
UD1_shift_out_87[29] = PD1_a_o_0 & !UD1_shift_out_87_a[29] # !PD1_a_o_0 & PD1_a_o_2 & !UD1_shift_out_87_a[29] # !PD1_a_o_2 & VD1_b_o_iv_31;
 
 
--UD1_shift_out_85[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[29] at LC_X11_Y14_N8
--operation mode is normal
 
UD1_shift_out_85[29] = PD1_a_o_2 & UD1_shift_out_85_c[29] & UD1_shift_out_68[25] # !UD1_shift_out_85_c[29] & UD1_shift_out_68[27] # !PD1_a_o_2 & UD1_shift_out_85_c[29];
 
 
--UD1_shift_out_92_d_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_21 at LC_X12_Y13_N5
--operation mode is normal
 
UD1_shift_out_92_d_21 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[29] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[29];
 
 
--MD1_c_0_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[29] at LC_X9_Y10_N8
--operation mode is normal
 
MD1_c_0_a[29] = VD1_un24_res & !VD1_hilo_61 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_29;
 
 
--TD1_m91 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m91 at LC_X9_Y10_N7
--operation mode is normal
 
TD1_m91 = PD1_a_o_29 & TD1_m91_a # !PD1_a_o_29 & TD1_m91_a & !TD1_m4 # !TD1_m91_a & TD1_m7;
 
 
--TD1_m88 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m88 at LC_X9_Y10_N3
--operation mode is normal
 
TD1_m88 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add29;
 
 
--UD1_shift_out_87_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[13] at LC_X13_Y18_N7
--operation mode is normal
 
UD1_shift_out_87_d[13] = PD1_a_o_0 & UD1_shift_out_80[13] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[13];
 
 
--UD1_shift_out_85_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[13] at LC_X14_Y15_N8
--operation mode is normal
 
UD1_shift_out_85_d[13] = PD1_a_o_2 & UD1_shift_out_48[29] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[13];
 
 
--UD1_shift_out_86_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[13] at LC_X15_Y14_N5
--operation mode is normal
 
UD1_shift_out_86_a[13] = UD1_shift_out_sn_b9_0 & UD1_shift_out587 & !PD1_a_o_2 # !UD1_shift_out_sn_b9_0 & !UD1_shift_out_74[13];
 
 
--UD1_shift_out_63[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[21] at LC_X14_Y19_N4
--operation mode is normal
 
UD1_shift_out_63[21] = PD1_a_o_2 & !PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_2 & UD1_shift_out_45[29];
 
 
--UD1_shift_out_92_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[13] at LC_X14_Y14_N3
--operation mode is normal
 
UD1_shift_out_92_d_a[13] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_13 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[13] # !UD1_shift_out_sn_m17_0;
 
 
--VD1_hilo_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_13 at LC_X4_Y13_N8
--operation mode is normal
 
VD1_hilo_13_lut_out = VD1_hilo_37_iv_0_0[13] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_13 # !VD1_hilo_37_iv_0_a[13];
VD1_hilo_13 = DFFEAS(VD1_hilo_13_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_45 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_45 at LC_X9_Y9_N3
--operation mode is normal
 
VD1_hilo_45_lut_out = !VD1_hilo_37_iv_2[45] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[45] # !VD1_hilo25;
VD1_hilo_45 = DFFEAS(VD1_hilo_45_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_13 at LC_X24_Y9_N7
--operation mode is normal
 
PD1_a_o_13 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[13] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[13];
 
 
--TD1_m127_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m127_a at LC_X11_Y11_N2
--operation mode is normal
 
TD1_m127_a = PD1_a_o_13 & VD1_b_o_iv_13 & !TD1_m9 # !VD1_b_o_iv_13 & !TD1_m5 # !PD1_a_o_13 & !VD1_b_o_iv_13;
 
 
--TD1_un1_a_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add13 at LC_X12_Y9_N8
--operation mode is arithmetic
 
TD1_un1_a_add13_carry_eqn = (!TD1_un1_a_carry_9 & TD1_un1_a_carry_12) # (TD1_un1_a_carry_9 & TD1L435);
TD1_un1_a_add13 = PD1_a_o_13 $ TD1_un1_b_1_combout[13] $ TD1_un1_a_add13_carry_eqn;
 
--TD1_un1_a_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_13 at LC_X12_Y9_N8
--operation mode is arithmetic
 
TD1_un1_a_carry_13_cout_0 = PD1_a_o_13 & !TD1_un1_b_1_combout[13] & !TD1_un1_a_carry_12 # !PD1_a_o_13 & !TD1_un1_a_carry_12 # !TD1_un1_b_1_combout[13];
TD1_un1_a_carry_13 = CARRY(TD1_un1_a_carry_13_cout_0);
 
--TD1L635 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_13~COUT1_1 at LC_X12_Y9_N8
--operation mode is arithmetic
 
TD1L635_cout_1 = PD1_a_o_13 & !TD1_un1_b_1_combout[13] & !TD1L435 # !PD1_a_o_13 & !TD1L435 # !TD1_un1_b_1_combout[13];
TD1L635 = CARRY(TD1L635_cout_1);
 
 
--VD1_hilo_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_29 at LC_X3_Y17_N4
--operation mode is normal
 
VD1_hilo_29_lut_out = VD1_hilo_37_iv_0_0[29] # PD1_a_o_29 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[29];
VD1_hilo_29 = DFFEAS(VD1_hilo_29_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_un134_hilo_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[30] at LC_X5_Y15_N7
--operation mode is normal
 
VD1_un134_hilo_combout[30]_carry_eqn = (!VD1_un134_hilo_cout[24] & VD1_un134_hilo_cout[28]) # (VD1_un134_hilo_cout[24] & VD1L9991);
VD1_un134_hilo_combout[30] = VD1_un134_hilo_combout[30]_carry_eqn $ VD1_hilo_30;
 
 
--PD1_a_o_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[30] at LC_X20_Y4_N9
--operation mode is normal
 
PD1_a_o_a[30] = SC1_muxa_ctl_o_1 & !FB1_r32_o_30 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_30;
 
 
--PD1_a_o_3_Z[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[30] at LC_X24_Y3_N8
--operation mode is normal
 
SD1_r32_o_30_qfbk = SD1_r32_o_30;
PD1_a_o_3_Z[30] = PD1_a_o_3_s[0] & SD1_r32_o_30_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[30];
 
--SD1_r32_o_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_30 at LC_X24_Y3_N8
--operation mode is normal
 
SD1_r32_o_30 = DFFEAS(PD1_a_o_3_Z[30], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_30, , , VCC);
 
 
--VD1_hilo_37_iv_0_a3_4[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_4[62] at LC_X8_Y9_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_4[62] = !VD1_hilo_33_1[64] & VD1_hilo_3_sqmuxa;
 
 
--VD1_hilo_37_iv_0_a[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[62] at LC_X9_Y2_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a[62] = !VD1_hilo_37_iv_0_2[62] & !VD1_hilo_37_iv_0_o5[62] & VD1_hilo_24_add30 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_o5_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0[62] at LC_X8_Y8_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_o5_0[62] = VD1_hilo_37_iv_0_o5_0_a[62] # VD1_hilo_37_iv_0_a3[57] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add31;
 
 
--UD1_shift_out_92_d[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d[30] at LC_X12_Y17_N1
--operation mode is normal
 
UD1_shift_out_92_d[30] = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[30] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[30];
 
 
--UD1_shift_out_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[30] at LC_X11_Y13_N7
--operation mode is normal
 
UD1_shift_out_a[30] = UD1_shift_out_sn_m31_i & !UD1_shift_out_sn_m25_0 & !UD1_shift_out586 # !UD1_shift_out_sn_m31_i & !UD1_shift_out_89[30];
 
 
--TD1_m96_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m96_a at LC_X13_Y14_N6
--operation mode is normal
 
TD1_m96_a = VD1_b_o_iv_30 & !TD1_m9 & PD1_a_o_30 # !VD1_b_o_iv_30 & !PD1_a_o_30 # !TD1_m5;
 
 
--TD1_un1_b_1_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[30] at LC_X15_Y5_N4
--operation mode is normal
 
TD1_un1_b_1_combout[30] = VD1_b_o_iv_30 $ !TD1_sum13_0_a2;
 
 
--TD1_un1_a_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add29 at LC_X12_Y7_N4
--operation mode is arithmetic
 
TD1_un1_a_add29_carry_eqn = (!TD1_un1_a_carry_24 & TD1_un1_a_carry_28) # (TD1_un1_a_carry_24 & TD1L365);
TD1_un1_a_add29 = TD1_un1_b_1_combout[29] $ PD1_a_o_29 $ TD1_un1_a_add29_carry_eqn;
 
--TD1_un1_a_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_29 at LC_X12_Y7_N4
--operation mode is arithmetic
 
TD1_un1_a_carry_29 = CARRY(TD1_un1_b_1_combout[29] & !PD1_a_o_29 & !TD1L365 # !TD1_un1_b_1_combout[29] & !TD1L365 # !PD1_a_o_29);
 
 
--UD1_shift_out_87[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[12] at LC_X19_Y18_N2
--operation mode is normal
 
UD1_shift_out_87[12] = PD1_a_o_0 & UD1_shift_out_87_d[12] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[12] # !PD1_a_o_2 & VD1_b_o_iv_14;
 
 
--UD1_shift_out_89_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[12] at LC_X11_Y18_N6
--operation mode is normal
 
UD1_shift_out_89_a[12] = PD1_a_o_1 & !UD1_shift_out_85_d[12] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[12] # !PD1_a_o_2 & !VD1_b_o_iv_11;
 
 
--UD1_shift_out_86_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_12 at LC_X16_Y14_N0
--operation mode is normal
 
UD1_shift_out_86_12 = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[12] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[12];
 
 
--UD1_shift_out_92_d_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_4 at LC_X10_Y17_N4
--operation mode is normal
 
UD1_shift_out_92_d_4 = UD1_shift_out_sn_m25_0 & !UD1_shift_out_92_d_a[12] # !UD1_shift_out_sn_m25_0 & !PD1_a_o_4 & UD1_shift_out_63[20];
 
 
--MD1_c_0_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[12] at LC_X8_Y12_N3
--operation mode is normal
 
MD1_c_0_a[12] = VD1_un24_res & !VD1_hilo_44 # !VD1_un24_res & !VD1_hilo_12 # !VD1_un11_res;
 
 
--TD1_m122 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m122 at LC_X11_Y11_N9
--operation mode is normal
 
TD1_m122 = PD1_a_o_12 & TD1_m122_a # !PD1_a_o_12 & TD1_m122_a & !TD1_m4 # !TD1_m122_a & TD1_m7;
 
 
--TD1_m119 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m119 at LC_X16_Y14_N5
--operation mode is normal
 
TD1_m119 = TD1_un1_a_add12 & TD1_alu_out_sn_m14_0_0;
 
 
--UD1_shift_out_89_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[24] at LC_X8_Y18_N9
--operation mode is normal
 
UD1_shift_out_89_a[24] = PD1_a_o_0 & !UD1_shift_out_87_d[24] # !PD1_a_o_0 & PD1_a_o_2 & !UD1_shift_out_87_d[24] # !PD1_a_o_2 & !VD1_b_o_iv_26;
 
 
--UD1_shift_out_85[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[24] at LC_X8_Y18_N7
--operation mode is normal
 
UD1_shift_out_85[24] = PD1_a_o_2 & UD1_shift_out_85_a[24] & UD1_shift_out_68[22] # !UD1_shift_out_85_a[24] & UD1_shift_out_68[20] # !PD1_a_o_2 & !UD1_shift_out_85_a[24];
 
 
--UD1_shift_out_92_d_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_16 at LC_X9_Y17_N4
--operation mode is normal
 
UD1_shift_out_92_d_16 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[24] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[24];
 
 
--MD1_c_0_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[24] at LC_X9_Y13_N2
--operation mode is normal
 
MD1_c_0_a[24] = VD1_un24_res & !VD1_hilo_56 # !VD1_un24_res & !VD1_hilo_24 # !VD1_un11_res;
 
 
--TD1_m71 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m71 at LC_X13_Y6_N9
--operation mode is normal
 
TD1_m71 = PD1_a_o_24 & TD1_m71_a # !PD1_a_o_24 & TD1_m71_a & !TD1_m4 # !TD1_m71_a & TD1_m7;
 
 
--TD1_m68 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m68 at LC_X9_Y13_N7
--operation mode is normal
 
TD1_m68 = TD1_un1_a_add24 & TD1_alu_out_sn_m14_0_0;
 
 
--UD1_shift_out_89_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[25] at LC_X13_Y10_N3
--operation mode is normal
 
UD1_shift_out_89_a[25] = PD1_a_o_2 & !UD1_shift_out_87_d[25] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[25] # !PD1_a_o_0 & !VD1_b_o_iv_27;
 
 
--UD1_shift_out_85[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[25] at LC_X8_Y10_N9
--operation mode is normal
 
UD1_shift_out_85[25] = PD1_a_o_2 & UD1_shift_out_85_a[25] & UD1_shift_out_68[23] # !UD1_shift_out_85_a[25] & UD1_shift_out_68[21] # !PD1_a_o_2 & !UD1_shift_out_85_a[25];
 
 
--UD1_shift_out_92_d_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_17 at LC_X14_Y15_N6
--operation mode is normal
 
UD1_shift_out_92_d_17 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & !UD1_shift_out_92_d_a[25] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_84[25];
 
 
--MD1_c_0_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[25] at LC_X10_Y8_N6
--operation mode is normal
 
MD1_c_0_a[25] = VD1_un24_res & !VD1_hilo_57 # !VD1_un24_res & !VD1_hilo_25 # !VD1_un11_res;
 
 
--TD1_m76 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m76 at LC_X13_Y6_N6
--operation mode is normal
 
TD1_m76 = PD1_a_o_25 & TD1_m76_a # !PD1_a_o_25 & TD1_m76_a & !TD1_m4 # !TD1_m76_a & TD1_m7;
 
 
--TD1_m73 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m73 at LC_X13_Y10_N9
--operation mode is normal
 
TD1_m73 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add25;
 
 
--UD1_shift_out_87[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[22] at LC_X6_Y17_N8
--operation mode is normal
 
UD1_shift_out_87[22] = PD1_a_o_0 & UD1_shift_out_87_d[22] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[22] # !PD1_a_o_2 & VD1_b_o_iv_24;
 
 
--UD1_shift_out_85[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[22] at LC_X8_Y17_N8
--operation mode is normal
 
UD1_shift_out_85[22] = PD1_a_o_1 & UD1_shift_out_85_d[22] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[22] # !PD1_a_o_2 & VD1_b_o_iv_21;
 
 
--UD1_shift_out_92_d_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_14 at LC_X12_Y13_N1
--operation mode is normal
 
UD1_shift_out_92_d_14 = UD1_shift_out_sn_m25_0 & UD1_shift_out_88[22] & UD1_shift_out_sn_m17_0 # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d_a[22];
 
 
--MD1_c_0_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[22] at LC_X5_Y13_N2
--operation mode is normal
 
MD1_c_0_a[22] = VD1_un24_res & !VD1_hilo_54 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_22;
 
 
--TD1_m61 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m61 at LC_X5_Y13_N7
--operation mode is normal
 
TD1_m61 = TD1_m61_a & PD1_a_o_22 # !TD1_m4 # !TD1_m61_a & TD1_m7 & !PD1_a_o_22;
 
 
--TD1_m58 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m58 at LC_X5_Y13_N5
--operation mode is normal
 
TD1_m58 = TD1_alu_out_sn_m14_0_0 & TD1_un1_a_add22;
 
 
--UD1_shift_out_89_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[23] at LC_X14_Y7_N6
--operation mode is normal
 
UD1_shift_out_89_a[23] = PD1_a_o_2 & !UD1_shift_out_87_d[23] # !PD1_a_o_2 & PD1_a_o_0 & !UD1_shift_out_87_d[23] # !PD1_a_o_0 & !VD1_b_o_iv_25;
 
 
--UD1_shift_out_85[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[23] at LC_X14_Y7_N4
--operation mode is normal
 
UD1_shift_out_85[23] = PD1_a_o_2 & !UD1_shift_out_85_a[23] # !PD1_a_o_2 & UD1_shift_out_85_a[23] & VD1_b_o_iv_22 # !UD1_shift_out_85_a[23] & UD1_shift_out_68[23];
 
 
--UD1_shift_out_92_d_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_15 at LC_X12_Y12_N7
--operation mode is normal
 
UD1_shift_out_92_d_15 = UD1_shift_out_sn_m25_0 & UD1_shift_out_sn_m17_0 & UD1_shift_out_88[23] # !UD1_shift_out_sn_m25_0 & UD1_shift_out_92_d_a[23];
 
 
--MD1_c_0_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[23] at LC_X10_Y8_N5
--operation mode is normal
 
MD1_c_0_a[23] = VD1_un24_res & !VD1_hilo_55 # !VD1_un24_res & !VD1_un11_res # !VD1_hilo_23;
 
 
--TD1_m66 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m66 at LC_X13_Y6_N4
--operation mode is normal
 
TD1_m66 = PD1_a_o_23 & TD1_m66_a # !PD1_a_o_23 & TD1_m66_a & !TD1_m4 # !TD1_m66_a & TD1_m7;
 
 
--TD1_m63 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m63 at LC_X14_Y7_N7
--operation mode is normal
 
TD1_m63 = TD1_un1_a_add23 & TD1_alu_out_sn_m14_0_0;
 
 
--CB1_dout_2_22 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_22 at LC_X25_Y13_N5
--operation mode is normal
 
CB1_dout_2_22 = ND1_dout7 & FD1_wb_o_22 # !ND1_dout7 & !ND1_dout_2_a_22;
 
--CB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_22 at LC_X25_Y13_N5
--operation mode is normal
 
CB1_r32_o_22 = DFFEAS(CB1_dout_2_22, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_o2_0_a[3] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_o2_0_a[3] at LC_X31_Y9_N0
--operation mode is normal
 
UB1_dout_2_i_o2_0_a[3] = RB1_ctl_o_2 & !RB1_ctl_o_1 # !RB1_ctl_o_2 & RB1_ctl_o_1 & !RB1_ctl_o_3 # !RB1_byte_addr_o_1;
 
 
--TB1_dout_1_x_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_6 at LC_X20_Y4_N5
--operation mode is normal
 
TB1_dout_1_x_6 = TB1_dout21 & CB1_dout_2_6 # !TB1_dout21 & CB1_dout_2_14;
 
 
--TB1_dout_1_2_6 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_6 at LC_X20_Y4_N6
--operation mode is normal
 
TB1_dout_1_2_6 = TB1_dout21 & TB1_dout22 & !TB1_dout_1_2_a_x[30] # !TB1_dout22 & CB1_dout_2_6 # !TB1_dout21 & !TB1_dout_1_2_a_x[30];
 
 
--UB1_dout_2_i_i_o3[7] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_o3[7] at LC_X31_Y9_N5
--operation mode is normal
 
UB1_dout_2_i_i_o3[7] = RB1_ctl_o_1 & !RB1_ctl_o_3 & !RB1_ctl_o_2 # !RB1_ctl_o_1 & RB1_ctl_o_2;
 
 
--QB1_dout_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_8 at LC_X23_Y6_N8
--operation mode is normal
 
QB1_dout_iv_8 = GD1_dout_iv_1_8 # FD1_wb_o_8 & GD1_dout7_0_a2;
 
--QB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_8 at LC_X23_Y6_N8
--operation mode is normal
 
QB1_r32_o_8 = DFFEAS(QB1_dout_iv_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_8 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_8 at LC_X21_Y11_N1
--operation mode is normal
 
FB1_res_7_0_0_8 = ED1_r32_o_8 & CD1_res_7_0_0_a2_0 # CD1_res_7_0_0_o3_0 & ED1_r32_o_6 # !ED1_r32_o_8 & CD1_res_7_0_0_o3_0 & ED1_r32_o_6;
 
--FB1_r32_o_0_8 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_8 at LC_X21_Y11_N1
--operation mode is normal
 
FB1_r32_o_0_8 = DFFEAS(FB1_res_7_0_0_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UD1_shift_out_80_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[6] at LC_X12_Y15_N1
--operation mode is normal
 
UD1_shift_out_80_a[6] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_9 # !PD1_a_o_1 & !VD1_b_o_iv_7;
 
 
--UD1_shift_out_43_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43_a[30] at LC_X14_Y18_N5
--operation mode is normal
 
UD1_shift_out_43_a[30] = PD1_a_o_1 & !VD1_b_o_iv_0 # !PD1_a_o_1 & !VD1_b_o_iv_2;
 
 
--RD1_r32_o_0_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_6 at LC_X21_Y4_N5
--operation mode is arithmetic
 
RD1_r32_o_0_6_carry_eqn = RD1_r32_o_cout[4];
RD1_r32_o_0_6_lut_out = KB1_r32_o_6 $ (!RD1_r32_o_0_6_carry_eqn);
RD1_r32_o_0_6 = DFFEAS(RD1_r32_o_0_6_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[6] at LC_X21_Y4_N5
--operation mode is arithmetic
 
RD1_r32_o_cout[6]_cout_0 = KB1_r32_o_6 & KB1_r32_o_7 & !RD1_r32_o_cout[4];
RD1_r32_o_cout[6] = CARRY(RD1_r32_o_cout[6]_cout_0);
 
--RD1L17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[6]~COUT1_1 at LC_X21_Y4_N5
--operation mode is arithmetic
 
RD1L17_cout_1 = KB1_r32_o_6 & KB1_r32_o_7 & !RD1_r32_o_cout[4];
RD1L17 = CARRY(RD1L17_cout_1);
 
 
--PD1_a_o_3_d[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[6] at LC_X19_Y11_N4
--operation mode is normal
 
PD1_a_o_3_d[6] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_6 # !PD1_un6_a_o & !PD1_a_o_3_d_a[6] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[6];
 
 
--UD1_shift_out_47_a[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_47_a[2] at LC_X15_Y18_N8
--operation mode is normal
 
UD1_shift_out_47_a[2] = PD1_a_o_0 & !VD1_b_o_iv_25 & PD1_a_o_1 # !PD1_a_o_0 & !VD1_b_o_iv_24 # !PD1_a_o_1;
 
 
--UD1_shift_out_63_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63_a[17] at LC_X13_Y13_N8
--operation mode is normal
 
UD1_shift_out_63_a[17] = !PD1_a_o_2 & !PD1_a_o_1;
 
 
--CB1_dout_2_21 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_21 at LC_X21_Y14_N8
--operation mode is normal
 
CB1_dout_2_21 = ND1_dout7 & FD1_wb_o_21 # !ND1_dout7 & !ND1_dout_2_a_21;
 
--CB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_21 at LC_X21_Y14_N8
--operation mode is normal
 
CB1_r32_o_21 = DFFEAS(CB1_dout_2_21, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_x_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_5 at LC_X21_Y14_N0
--operation mode is normal
 
TB1_dout_1_x_5 = TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & CB1_dout_2_13;
 
 
--TB1_dout_1_2_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_5 at LC_X21_Y9_N8
--operation mode is normal
 
TB1_dout_1_2_5 = TB1_dout22 & !TB1_dout_1_2_a_x[29] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_5 # !TB1_dout21 & !TB1_dout_1_2_a_x[29];
 
 
--TB1_dout_1_2_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_4 at LC_X27_Y13_N6
--operation mode is normal
 
TB1_dout_1_2_4 = TB1_dout22 & !TB1_dout_1_2_a_x[28] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & !TB1_dout_1_2_a_x[28];
 
 
--TB1_dout_1_x_4 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_4 at LC_X27_Y13_N5
--operation mode is normal
 
TB1_dout_1_x_4 = TB1_dout21 & CB1_dout_2_4 # !TB1_dout21 & CB1_dout_2_12;
 
 
--M1_ua_state[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[2] at LC_X33_Y15_N6
--operation mode is normal
 
M1_ua_state[2]_lut_out = M1_clk_ctr_equ15_0_a2 & M1_ua_state[1] # M1_ua_state[2] & M1_ua_state_ns_0_a[2] # !M1_clk_ctr_equ15_0_a2 & M1_ua_state[2];
M1_ua_state[2] = DFFEAS(M1_ua_state[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--M1_ua_state_ns_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_ns_0_a[2] at LC_X33_Y14_N5
--operation mode is normal
 
M1_ua_state_ns_0_a[2] = !M1_bit_ctr[0] # !M1_bit_ctr[1] # !M1_bit_ctr[2];
 
 
--M1_clk_ctr_equ15_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_equ15_0_a2_a at LC_X33_Y16_N6
--operation mode is normal
 
M1_clk_ctr_equ15_0_a2_a = !M1_clk_ctr_3 & M1_clk_ctr_2;
 
 
--CB1_dout_2_19 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_19 at LC_X22_Y15_N2
--operation mode is normal
 
CB1_dout_2_19 = ND1_dout7 & FD1_wb_o_19 # !ND1_dout7 & !ND1_dout_2_a_19;
 
--CB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_19 at LC_X22_Y15_N2
--operation mode is normal
 
CB1_r32_o_19 = DFFEAS(CB1_dout_2_19, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_x_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_3 at LC_X21_Y15_N8
--operation mode is normal
 
TB1_dout_1_x_3 = TB1_dout21 & CB1_dout_2_3 # !TB1_dout21 & CB1_dout_2_11;
 
 
--TB1_dout_1_2_3 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_3 at LC_X21_Y15_N3
--operation mode is normal
 
TB1_dout_1_2_3 = TB1_dout21 & TB1_dout22 & !TB1_dout_1_2_a_x[27] # !TB1_dout22 & CB1_dout_2_3 # !TB1_dout21 & !TB1_dout_1_2_a_x[27];
 
 
--CB1_dout_2_18 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_18 at LC_X22_Y12_N3
--operation mode is normal
 
CB1_dout_2_18 = ND1_dout7 & FD1_wb_o_18 # !ND1_dout7 & !ND1_dout_2_a_18;
 
--CB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_18 at LC_X22_Y12_N3
--operation mode is normal
 
CB1_r32_o_18 = DFFEAS(CB1_dout_2_18, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_2_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_2 at LC_X29_Y6_N8
--operation mode is normal
 
TB1_dout_1_2_2 = TB1_dout22 & !TB1_dout_1_2_a_x[26] # !TB1_dout22 & TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & !TB1_dout_1_2_a_x[26];
 
 
--TB1_dout_1_x_2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_2 at LC_X29_Y6_N6
--operation mode is normal
 
TB1_dout_1_x_2 = TB1_dout21 & CB1_dout_2_2 # !TB1_dout21 & CB1_dout_2_10;
 
 
--CB1_dout_2_17 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_17 at LC_X21_Y16_N1
--operation mode is normal
 
CB1_dout_2_17 = ND1_dout7 & FD1_wb_o_17 # !ND1_dout7 & !ND1_dout_2_a_17;
 
--CB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_17 at LC_X21_Y16_N1
--operation mode is normal
 
CB1_r32_o_17 = DFFEAS(CB1_dout_2_17, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_2_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_1 at LC_X25_Y3_N2
--operation mode is normal
 
TB1_dout_1_2_1 = TB1_dout21 & TB1_dout22 & !TB1_dout_1_2_a_x[25] # !TB1_dout22 & CB1_dout_2_1 # !TB1_dout21 & !TB1_dout_1_2_a_x[25];
 
 
--TB1_dout_1_x_1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_1 at LC_X25_Y3_N9
--operation mode is normal
 
TB1_dout_1_x_1 = TB1_dout21 & CB1_dout_2_1 # !TB1_dout21 & CB1_dout_2_9;
 
 
--UD1_shift_out_79_a[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[1] at LC_X15_Y13_N5
--operation mode is normal
 
UD1_shift_out_79_a[1] = PD1_a_o_0 & !VD1_b_o_iv_10 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_9;
 
 
--UD1_shift_out_59[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_59[1] at LC_X15_Y13_N4
--operation mode is normal
 
UD1_shift_out_59[1] = UD1_shift_out587 & PD1_a_o_1 & UD1_shift_out_39[19] # !PD1_a_o_1 & UD1_shift_out_39[17];
 
 
--VD1_un134_hilo_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[1] at LC_X4_Y16_N2
--operation mode is arithmetic
 
VD1_un134_hilo_combout[1] = VD1_hilo_1 $ VD1_hilo[0];
 
--VD1_un134_hilo_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[1] at LC_X4_Y16_N2
--operation mode is arithmetic
 
VD1_un134_hilo_cout[1]_cout_0 = VD1_hilo_1 & VD1_hilo[0];
VD1_un134_hilo_cout[1] = CARRY(VD1_un134_hilo_cout[1]_cout_0);
 
--VD1L1591 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[1]~COUT1_1 at LC_X4_Y16_N2
--operation mode is arithmetic
 
VD1L1591_cout_1 = VD1_hilo_1 & VD1_hilo[0];
VD1L1591 = CARRY(VD1L1591_cout_1);
 
 
--VD1_hilo_33_i_m[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[33] at LC_X8_Y7_N7
--operation mode is normal
 
VD1_hilo_33_i_m[33] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[33] # !VD1_hilo_33_1[64] & !VD1_hilo_33;
 
 
--VD1_hilo_37_iv_2_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[33] at LC_X8_Y7_N0
--operation mode is normal
 
VD1_hilo_37_iv_2_a[33] = VD1_hilo_1 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add1 # !VD1_hilo_1 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add1;
 
 
--VD1_hilo_22_Z[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[33] at LC_X7_Y4_N6
--operation mode is normal
 
VD1_hilo_22_Z[33] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[33] # !VD1_sign & !VD1_hilo_22_a[33] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[33];
 
 
--CB1_dout_2_16 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_16 at LC_X29_Y6_N1
--operation mode is normal
 
CB1_dout_2_16 = ND1_dout7 & FD1_wb_o_16 # !ND1_dout7 & !ND1_dout_2_a_16;
 
--CB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_16 at LC_X29_Y6_N1
--operation mode is normal
 
CB1_r32_o_16 = DFFEAS(CB1_dout_2_16, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_x_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_0 at LC_X29_Y5_N4
--operation mode is normal
 
TB1_dout_1_x_0 = TB1_dout21 & CB1_dout_2_0 # !TB1_dout21 & CB1_dout_2_8;
 
 
--TB1_dout_1_2_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_0 at LC_X29_Y5_N9
--operation mode is normal
 
TB1_dout_1_2_0 = TB1_dout21 & TB1_dout22 & !TB1_dout_1_2_a_x[24] # !TB1_dout22 & CB1_dout_2_0 # !TB1_dout21 & !TB1_dout_1_2_a_x[24];
 
 
--VD1_hilo_37_iv_2[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[32] at LC_X8_Y7_N6
--operation mode is normal
 
VD1_hilo_37_iv_2[32] = VD1_hilo_33_i_m[32] # VD1_hilo_37_iv_2_a[32] # !VD1_hilo_24_add0 & VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[32] at LC_X8_Y10_N3
--operation mode is normal
 
VD1_hilo_37_iv_a[32] = RC1_alu_func_o_0 & !PD1_a_o_0 # !RC1_alu_func_o_0 & !VD1_hilo[32];
 
 
--VD1_hilo_37_iv_0_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[0] at LC_X6_Y13_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a[0] = !VD1_hilo_37_iv_0_1[0] & VD1_hilo_24_add32 $ VD1_op2_sign_reged # !VD1_hilo_2_sqmuxa;
 
 
--UD1_shift_out_79_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[0] at LC_X20_Y13_N5
--operation mode is normal
 
UD1_shift_out_79_a[0] = PD1_a_o_0 & !VD1_b_o_iv_9 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_8;
 
 
--UD1_shift_out_80_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[0] at LC_X15_Y11_N1
--operation mode is normal
 
UD1_shift_out_80_a[0] = PD1_a_o_1 & !VD1_b_o_iv_3 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_1;
 
 
--UD1_shift_out_82_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_82_a[0] at LC_X15_Y11_N4
--operation mode is normal
 
UD1_shift_out_82_a[0] = PD1_a_o_2 & !VD1_b_o_iv_4 # !PD1_a_o_2 & !VD1_b_o_iv_2;
 
 
--UD1_shift_out_74_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[0] at LC_X21_Y13_N3
--operation mode is normal
 
UD1_shift_out_74_a[0] = PD1_a_o_3 & !PD1_a_o_2 # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_47[0] # !PD1_a_o_2 & !UD1_shift_out_79[8];
 
 
--RD1_r32_o_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_31 at LC_X23_Y3_N7
--operation mode is normal
 
RD1_r32_o_31_carry_eqn = (!RD1_r32_o_cout[25] & RD1_r32_o_cout[29]) # (RD1_r32_o_cout[25] & RD1L311);
RD1_r32_o_31_lut_out = KB1_r32_o_31 $ (KB1_r32_o_30 & !RD1_r32_o_31_carry_eqn);
RD1_r32_o_31 = DFFEAS(RD1_r32_o_31_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_31 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_31 at LC_X22_Y16_N4
--operation mode is normal
 
FB1_res_7_0_0_31 = ED1_r32_o_15 & DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_0 # !DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_0;
 
--FB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_31 at LC_X22_Y16_N4
--operation mode is normal
 
FB1_r32_o_31 = DFFEAS(FB1_res_7_0_0_31, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[31] at LC_X19_Y3_N7
--operation mode is normal
 
PD1_a_o_3_d[31] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_31 # !PD1_un6_a_o & !PD1_a_o_3_d_a[31] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[31];
 
 
--QB1_dout_iv_31 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_31 at LC_X24_Y4_N9
--operation mode is normal
 
QB1_dout_iv_31 = GD1_dout_iv_1_31 # FD1_wb_o_31 & GD1_dout7_0_a2;
 
--QB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_31 at LC_X24_Y4_N9
--operation mode is normal
 
QB1_r32_o_31 = DFFEAS(QB1_dout_iv_31, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_31 at LC_X27_Y4_N8
--operation mode is normal
 
FD1_wb_o_31 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_31 # F1_dout_31 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_31;
 
--FD1_r_data_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_31 at LC_X27_Y4_N8
--operation mode is normal
 
FD1_r_data_31 = DFFEAS(FD1_wb_o_31, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] at LC_X20_Y4_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[30] = QD1_b_o18 & !QB1_r32_o_30 & QD1_un1_b_o18_2 # !FB1_r32_o_30 # !QD1_b_o18 & !QB1_r32_o_30 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[30] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[30] at LC_X20_Y4_N7
--operation mode is normal
 
G1_BUS15471_i_m[30] = QD1_b_o_1_sqmuxa & !FD1_wb_o_30;
 
 
--PD1_a_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_29 at LC_X15_Y6_N8
--operation mode is normal
 
PD1_a_o_29 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[29] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[29];
 
 
--TD1_lt_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_28 at LC_X16_Y7_N2
--operation mode is arithmetic
 
TD1_lt_28_cout_0 = PD1_a_o_28 & VD1_b_o_iv_28 & !TD1_lt_27 # !PD1_a_o_28 & VD1_b_o_iv_28 # !TD1_lt_27;
TD1_lt_28 = CARRY(TD1_lt_28_cout_0);
 
--TD1L491 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_28~COUT1_1 at LC_X16_Y7_N2
--operation mode is arithmetic
 
TD1L491_cout_1 = PD1_a_o_28 & VD1_b_o_iv_28 & !TD1L291 # !PD1_a_o_28 & VD1_b_o_iv_28 # !TD1L291;
TD1L491 = CARRY(TD1L491_cout_1);
 
 
--TD1_sum_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_29 at LC_X15_Y6_N3
--operation mode is arithmetic
 
TD1_sum_carry_29_cout_0 = VD1_b_o_iv_29 & !TD1_sum_carry_28 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !TD1_sum_carry_28;
TD1_sum_carry_29 = CARRY(TD1_sum_carry_29_cout_0);
 
--TD1L144 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_29~COUT1_1 at LC_X15_Y6_N3
--operation mode is arithmetic
 
TD1L144_cout_1 = VD1_b_o_iv_29 & !TD1L934 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !TD1L934;
TD1L144 = CARRY(TD1L144_cout_1);
 
 
--N1_tx_sr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[7] at LC_X16_Y2_N5
--operation mode is normal
 
N1_tx_sr[7]_lut_out = Y1_q_b[7] & N1_read_request_ff;
N1_tx_sr[7] = DFFEAS(N1_tx_sr[7]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_586, , , !sys_rst, );
 
 
--CB1_dout_2_30 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_30 at LC_X20_Y4_N2
--operation mode is normal
 
CB1_dout_2_30 = ND1_dout7 & FD1_wb_o_30 # !ND1_dout7 & !ND1_dout_2_a_30;
 
--CB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_30 at LC_X20_Y4_N2
--operation mode is normal
 
CB1_r32_o_30 = DFFEAS(CB1_dout_2_30, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_31 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_31 at LC_X27_Y4_N5
--operation mode is normal
 
CB1_dout_2_31 = ND1_dout7 & FD1_wb_o_31 # !ND1_dout7 & !ND1_dout_2_a_31;
 
--CB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_31 at LC_X27_Y4_N5
--operation mode is normal
 
CB1_r32_o_31 = DFFEAS(CB1_dout_2_31, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_28 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_28 at LC_X27_Y13_N1
--operation mode is normal
 
CB1_dout_2_28 = ND1_dout7 & FD1_wb_o_28 # !ND1_dout7 & !ND1_dout_2_a_28;
 
--CB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_28 at LC_X27_Y13_N1
--operation mode is normal
 
CB1_r32_o_28 = DFFEAS(CB1_dout_2_28, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--K1_cntr_5_0[27] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[27] at LC_X30_Y4_N6
--operation mode is normal
 
K1_s_cntr_27__Z_qfbk = K1_s_cntr_27__Z;
K1_cntr_5_0[27] = F1_wr_tmr_data_0_a2 & CB1_r32_o_27 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_27__Z_qfbk;
 
--K1_s_cntr_27__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_27__Z at LC_X30_Y4_N6
--operation mode is normal
 
K1_s_cntr_27__Z = DFFEAS(K1_cntr_5_0[27], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_27, , , VCC);
 
 
--CB1_dout_2_29 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_29 at LC_X21_Y9_N9
--operation mode is normal
 
CB1_dout_2_29 = ND1_dout7 & FD1_wb_o_29 # !ND1_dout7 & !ND1_dout_2_a_29;
 
--CB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_29 at LC_X21_Y9_N9
--operation mode is normal
 
CB1_r32_o_29 = DFFEAS(CB1_dout_2_29, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--K1_cntr_5_0[18] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[18] at LC_X32_Y5_N3
--operation mode is normal
 
K1_s_cntr_18__Z_qfbk = K1_s_cntr_18__Z;
K1_cntr_5_0[18] = F1_wr_tmr_data_0_a2 & CB1_r32_o_18 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_18__Z_qfbk;
 
--K1_s_cntr_18__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_18__Z at LC_X32_Y5_N3
--operation mode is normal
 
K1_s_cntr_18__Z = DFFEAS(K1_cntr_5_0[18], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_18, , , VCC);
 
 
--K1_cntr_5_0[19] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[19] at LC_X30_Y4_N0
--operation mode is normal
 
K1_s_cntr_19__Z_qfbk = K1_s_cntr_19__Z;
K1_cntr_5_0[19] = F1_wr_tmr_data_0_a2 & CB1_r32_o_19 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_19__Z_qfbk;
 
--K1_s_cntr_19__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_19__Z at LC_X30_Y4_N0
--operation mode is normal
 
K1_s_cntr_19__Z = DFFEAS(K1_cntr_5_0[19], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_19, , , VCC);
 
 
--K1_cntr_5_0[16] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[16] at LC_X29_Y6_N5
--operation mode is normal
 
K1_s_cntr_16__Z_qfbk = K1_s_cntr_16__Z;
K1_cntr_5_0[16] = F1_wr_tmr_data_0_a2 & CB1_r32_o_16 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_16__Z_qfbk;
 
--K1_s_cntr_16__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_16__Z at LC_X29_Y6_N5
--operation mode is normal
 
K1_s_cntr_16__Z = DFFEAS(K1_cntr_5_0[16], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_16, , , VCC);
 
 
--K1_cntr_5_0[17] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[17] at LC_X30_Y4_N8
--operation mode is normal
 
K1_s_cntr_17__Z_qfbk = K1_s_cntr_17__Z;
K1_cntr_5_0[17] = F1_wr_tmr_data_0_a2 & CB1_r32_o_17 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_17__Z_qfbk;
 
--K1_s_cntr_17__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_17__Z at LC_X30_Y4_N8
--operation mode is normal
 
K1_s_cntr_17__Z = DFFEAS(K1_cntr_5_0[17], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_17, , , VCC);
 
 
--K1_cntr_5_0[22] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[22] at LC_X30_Y4_N3
--operation mode is normal
 
K1_s_cntr_22__Z_qfbk = K1_s_cntr_22__Z;
K1_cntr_5_0[22] = F1_wr_tmr_data_0_a2 & CB1_r32_o_22 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_22__Z_qfbk;
 
--K1_s_cntr_22__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_22__Z at LC_X30_Y4_N3
--operation mode is normal
 
K1_s_cntr_22__Z = DFFEAS(K1_cntr_5_0[22], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_22, , , VCC);
 
 
--K1_cntr_5_0[23] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[23] at LC_X29_Y3_N2
--operation mode is normal
 
K1_s_cntr_23__Z_qfbk = K1_s_cntr_23__Z;
K1_cntr_5_0[23] = F1_wr_tmr_data_0_a2 & CB1_r32_o_23 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_23__Z_qfbk;
 
--K1_s_cntr_23__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_23__Z at LC_X29_Y3_N2
--operation mode is normal
 
K1_s_cntr_23__Z = DFFEAS(K1_cntr_5_0[23], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_23, , , VCC);
 
 
--K1_cntr_5_0[20] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[20] at LC_X32_Y5_N8
--operation mode is normal
 
K1_s_cntr_20__Z_qfbk = K1_s_cntr_20__Z;
K1_cntr_5_0[20] = F1_wr_tmr_data_0_a2 & CB1_r32_o_20 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_20__Z_qfbk;
 
--K1_s_cntr_20__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_20__Z at LC_X32_Y5_N8
--operation mode is normal
 
K1_s_cntr_20__Z = DFFEAS(K1_cntr_5_0[20], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_20, , , VCC);
 
 
--K1_cntr_5_0[21] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[21] at LC_X32_Y5_N1
--operation mode is normal
 
K1_s_cntr_21__Z_qfbk = K1_s_cntr_21__Z;
K1_cntr_5_0[21] = F1_wr_tmr_data_0_a2 & CB1_r32_o_21 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_21__Z_qfbk;
 
--K1_s_cntr_21__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_21__Z at LC_X32_Y5_N1
--operation mode is normal
 
K1_s_cntr_21__Z = DFFEAS(K1_cntr_5_0[21], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_21, , , VCC);
 
 
--K1_cntr_5_0[26] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[26] at LC_X29_Y6_N9
--operation mode is normal
 
K1_s_cntr_26__Z_qfbk = K1_s_cntr_26__Z;
K1_cntr_5_0[26] = F1_wr_tmr_data_0_a2 & CB1_r32_o_26 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_26__Z_qfbk;
 
--K1_s_cntr_26__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_26__Z at LC_X29_Y6_N9
--operation mode is normal
 
K1_s_cntr_26__Z = DFFEAS(K1_cntr_5_0[26], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_26, , , VCC);
 
 
--K1_cntr_5_0[24] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[24] at LC_X32_Y5_N9
--operation mode is normal
 
K1_s_cntr_24__Z_qfbk = K1_s_cntr_24__Z;
K1_cntr_5_0[24] = F1_wr_tmr_data_0_a2 & CB1_r32_o_24 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_24__Z_qfbk;
 
--K1_s_cntr_24__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_24__Z at LC_X32_Y5_N9
--operation mode is normal
 
K1_s_cntr_24__Z = DFFEAS(K1_cntr_5_0[24], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_24, , , VCC);
 
 
--K1_cntr_5_0[25] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[25] at LC_X25_Y3_N4
--operation mode is normal
 
K1_s_cntr_25__Z_qfbk = K1_s_cntr_25__Z;
K1_cntr_5_0[25] = F1_wr_tmr_data_0_a2 & CB1_r32_o_25 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_25__Z_qfbk;
 
--K1_s_cntr_25__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_25__Z at LC_X25_Y3_N4
--operation mode is normal
 
K1_s_cntr_25__Z = DFFEAS(K1_cntr_5_0[25], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_25, , , VCC);
 
 
--K1_cntr_5_0[10] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[10] at LC_X29_Y15_N5
--operation mode is normal
 
K1_s_cntr_10__Z_qfbk = K1_s_cntr_10__Z;
K1_cntr_5_0[10] = F1_wr_tmr_data_0_a2 & CB1_r32_o_10 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_10__Z_qfbk;
 
--K1_s_cntr_10__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_10__Z at LC_X29_Y15_N5
--operation mode is normal
 
K1_s_cntr_10__Z = DFFEAS(K1_cntr_5_0[10], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_10, , , VCC);
 
 
--K1_cntr_5_0[11] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[11] at LC_X30_Y4_N5
--operation mode is normal
 
K1_s_cntr_11__Z_qfbk = K1_s_cntr_11__Z;
K1_cntr_5_0[11] = F1_wr_tmr_data_0_a2 & CB1_r32_o_11 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_11__Z_qfbk;
 
--K1_s_cntr_11__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_11__Z at LC_X30_Y4_N5
--operation mode is normal
 
K1_s_cntr_11__Z = DFFEAS(K1_cntr_5_0[11], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_11, , , VCC);
 
 
--K1_cntr_5_0[8] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[8] at LC_X32_Y5_N7
--operation mode is normal
 
K1_s_cntr_8__Z_qfbk = K1_s_cntr_8__Z;
K1_cntr_5_0[8] = F1_wr_tmr_data_0_a2 & CB1_r32_o_8 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_8__Z_qfbk;
 
--K1_s_cntr_8__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_8__Z at LC_X32_Y5_N7
--operation mode is normal
 
K1_s_cntr_8__Z = DFFEAS(K1_cntr_5_0[8], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_8, , , VCC);
 
 
--K1_cntr_5_0[9] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[9] at LC_X25_Y3_N8
--operation mode is normal
 
K1_s_cntr_9__Z_qfbk = K1_s_cntr_9__Z;
K1_cntr_5_0[9] = F1_wr_tmr_data_0_a2 & CB1_r32_o_9 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_9__Z_qfbk;
 
--K1_s_cntr_9__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_9__Z at LC_X25_Y3_N8
--operation mode is normal
 
K1_s_cntr_9__Z = DFFEAS(K1_cntr_5_0[9], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_9, , , VCC);
 
 
--K1_cntr_5_0[14] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[14] at LC_X28_Y4_N5
--operation mode is normal
 
K1_s_cntr_14__Z_qfbk = K1_s_cntr_14__Z;
K1_cntr_5_0[14] = F1_wr_tmr_data_0_a2 & CB1_r32_o_14 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_14__Z_qfbk;
 
--K1_s_cntr_14__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_14__Z at LC_X28_Y4_N5
--operation mode is normal
 
K1_s_cntr_14__Z = DFFEAS(K1_cntr_5_0[14], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_14, , , VCC);
 
 
--K1_cntr_5_0[15] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[15] at LC_X27_Y3_N4
--operation mode is normal
 
K1_s_cntr_15__Z_qfbk = K1_s_cntr_15__Z;
K1_cntr_5_0[15] = F1_wr_tmr_data_0_a2 & CB1_r32_o_15 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_15__Z_qfbk;
 
--K1_s_cntr_15__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_15__Z at LC_X27_Y3_N4
--operation mode is normal
 
K1_s_cntr_15__Z = DFFEAS(K1_cntr_5_0[15], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_15, , , VCC);
 
 
--K1_cntr_5_0[12] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[12] at LC_X27_Y13_N7
--operation mode is normal
 
K1_s_cntr_12__Z_qfbk = K1_s_cntr_12__Z;
K1_cntr_5_0[12] = F1_wr_tmr_data_0_a2 & CB1_r32_o_12 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_12__Z_qfbk;
 
--K1_s_cntr_12__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_12__Z at LC_X27_Y13_N7
--operation mode is normal
 
K1_s_cntr_12__Z = DFFEAS(K1_cntr_5_0[12], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_12, , , VCC);
 
 
--K1_cntr_5_0[13] is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntr_5_0[13] at LC_X30_Y4_N1
--operation mode is normal
 
K1_s_cntr_13__Z_qfbk = K1_s_cntr_13__Z;
K1_cntr_5_0[13] = F1_wr_tmr_data_0_a2 & CB1_r32_o_13 # !F1_wr_tmr_data_0_a2 & K1_s_cntr_13__Z_qfbk;
 
--K1_s_cntr_13__Z is mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|s_cntr_13__Z at LC_X30_Y4_N1
--operation mode is normal
 
K1_s_cntr_13__Z = DFFEAS(K1_cntr_5_0[13], GLOBAL(E1__clk0), VCC, , F1_wr_tmr_data_0_a2, CB1_r32_o_13, , , VCC);
 
 
--F1_dout_8 is mips_sys:isys|mips_dvc:imips_dvc|dout_8 at LC_X32_Y6_N9
--operation mode is normal
 
F1_dout_8_lut_out = F1_dout_0_0_a3_4[0] & K1_cntr_8 # F1_dout_0_0_a3_3[0] & F1_cmd[8] # !F1_dout_0_0_a3_4[0] & F1_dout_0_0_a3_3[0] & F1_cmd[8];
F1_dout_8 = DFFEAS(F1_dout_8_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_8 at LC_X32_Y6_N5
--operation mode is normal
 
BB1_r32_o_8_lut_out = AB1_r32_o_6;
BB1_r32_o_8 = DFFEAS(BB1_r32_o_8_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_clk_ctr27_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_i at LC_X33_Y15_N4
--operation mode is normal
 
M1_clk_ctr27_i_i = M1_ua_state_i[0] & M1_clk_ctr27_i_0_a & sys_rst & !M1_ua_state[4];
 
 
--M1_clk_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[1] at LC_X32_Y16_N3
--operation mode is arithmetic
 
M1_clk_ctr[1]_lut_out = M1_clk_ctr[1] $ M1_clk_ctr_cout[0];
M1_clk_ctr[1] = DFFEAS(M1_clk_ctr[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[1] at LC_X32_Y16_N3
--operation mode is arithmetic
 
M1_clk_ctr_cout[1]_cout_0 = !M1_clk_ctr_cout[0] # !M1_clk_ctr[1];
M1_clk_ctr_cout[1] = CARRY(M1_clk_ctr_cout[1]_cout_0);
 
--M1L87 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[1]~COUT1_2 at LC_X32_Y16_N3
--operation mode is arithmetic
 
M1L87_cout_1 = !M1L67 # !M1_clk_ctr[1];
M1L87 = CARRY(M1L87_cout_1);
 
 
--M1_clk_ctr[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[12] at LC_X32_Y15_N4
--operation mode is arithmetic
 
M1_clk_ctr[12]_carry_eqn = (!M1_clk_ctr_cout[7] & M1_clk_ctr_cout[11]) # (M1_clk_ctr_cout[7] & M1L69);
M1_clk_ctr[12]_lut_out = M1_clk_ctr[12] $ !M1_clk_ctr[12]_carry_eqn;
M1_clk_ctr[12] = DFFEAS(M1_clk_ctr[12]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[12] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[12] at LC_X32_Y15_N4
--operation mode is arithmetic
 
M1_clk_ctr_cout[12] = CARRY(M1_clk_ctr[12] & !M1L69);
 
 
--M1_clk_ctr[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[6] at LC_X32_Y16_N8
--operation mode is arithmetic
 
M1_clk_ctr[6]_carry_eqn = (!M1_clk_ctr_cout[2] & M1_clk_ctr_cout[5]) # (M1_clk_ctr_cout[2] & M1L58);
M1_clk_ctr[6]_lut_out = M1_clk_ctr[6] $ !M1_clk_ctr[6]_carry_eqn;
M1_clk_ctr[6] = DFFEAS(M1_clk_ctr[6]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[6] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[6] at LC_X32_Y16_N8
--operation mode is arithmetic
 
M1_clk_ctr_cout[6]_cout_0 = M1_clk_ctr[6] & !M1_clk_ctr_cout[5];
M1_clk_ctr_cout[6] = CARRY(M1_clk_ctr_cout[6]_cout_0);
 
--M1L78 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[6]~COUT1_6 at LC_X32_Y16_N8
--operation mode is arithmetic
 
M1L78_cout_1 = M1_clk_ctr[6] & !M1L58;
M1L78 = CARRY(M1L78_cout_1);
 
 
--M1_clk_ctr[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[7] at LC_X32_Y16_N9
--operation mode is arithmetic
 
M1_clk_ctr[7]_carry_eqn = (!M1_clk_ctr_cout[2] & M1_clk_ctr_cout[6]) # (M1_clk_ctr_cout[2] & M1L78);
M1_clk_ctr[7]_lut_out = M1_clk_ctr[7] $ (M1_clk_ctr[7]_carry_eqn);
M1_clk_ctr[7] = DFFEAS(M1_clk_ctr[7]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[7] at LC_X32_Y16_N9
--operation mode is arithmetic
 
M1_clk_ctr_cout[7] = CARRY(!M1L78 # !M1_clk_ctr[7]);
 
 
--M1_clk_ctr[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[4] at LC_X32_Y16_N6
--operation mode is arithmetic
 
M1_clk_ctr[4]_carry_eqn = (!M1_clk_ctr_cout[2] & M1_clk_ctr_cout[3]) # (M1_clk_ctr_cout[2] & M1L18);
M1_clk_ctr[4]_lut_out = M1_clk_ctr[4] $ (!M1_clk_ctr[4]_carry_eqn);
M1_clk_ctr[4] = DFFEAS(M1_clk_ctr[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[4] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[4] at LC_X32_Y16_N6
--operation mode is arithmetic
 
M1_clk_ctr_cout[4]_cout_0 = M1_clk_ctr[4] & !M1_clk_ctr_cout[3];
M1_clk_ctr_cout[4] = CARRY(M1_clk_ctr_cout[4]_cout_0);
 
--M1L38 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[4]~COUT1_4 at LC_X32_Y16_N6
--operation mode is arithmetic
 
M1L38_cout_1 = M1_clk_ctr[4] & !M1L18;
M1L38 = CARRY(M1L38_cout_1);
 
 
--M1_clk_ctr[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[9] at LC_X32_Y15_N1
--operation mode is arithmetic
 
M1_clk_ctr[9]_carry_eqn = (!M1_clk_ctr_cout[7] & M1_clk_ctr_cout[8]) # (M1_clk_ctr_cout[7] & M1L09);
M1_clk_ctr[9]_lut_out = M1_clk_ctr[9] $ (M1_clk_ctr[9]_carry_eqn);
M1_clk_ctr[9] = DFFEAS(M1_clk_ctr[9]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[9] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[9] at LC_X32_Y15_N1
--operation mode is arithmetic
 
M1_clk_ctr_cout[9]_cout_0 = !M1_clk_ctr_cout[8] # !M1_clk_ctr[9];
M1_clk_ctr_cout[9] = CARRY(M1_clk_ctr_cout[9]_cout_0);
 
--M1L29 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[9]~COUT1_8 at LC_X32_Y15_N1
--operation mode is arithmetic
 
M1L29_cout_1 = !M1L09 # !M1_clk_ctr[9];
M1L29 = CARRY(M1L29_cout_1);
 
 
--M1_clk_ctr[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr[11] at LC_X32_Y15_N3
--operation mode is arithmetic
 
M1_clk_ctr[11]_carry_eqn = (!M1_clk_ctr_cout[7] & M1_clk_ctr_cout[10]) # (M1_clk_ctr_cout[7] & M1L49);
M1_clk_ctr[11]_lut_out = M1_clk_ctr[11] $ M1_clk_ctr[11]_carry_eqn;
M1_clk_ctr[11] = DFFEAS(M1_clk_ctr[11]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_clk_ctr27_i_i, );
 
--M1_clk_ctr_cout[11] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[11] at LC_X32_Y15_N3
--operation mode is arithmetic
 
M1_clk_ctr_cout[11]_cout_0 = !M1_clk_ctr_cout[10] # !M1_clk_ctr[11];
M1_clk_ctr_cout[11] = CARRY(M1_clk_ctr_cout[11]_cout_0);
 
--M1L69 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr_cout[11]~COUT1_10 at LC_X32_Y15_N3
--operation mode is arithmetic
 
M1L69_cout_1 = !M1L49 # !M1_clk_ctr[11];
M1L69 = CARRY(M1L69_cout_1);
 
 
--SB1_wr_en46_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|wr_en46_0 at LC_X29_Y9_N7
--operation mode is normal
 
QC1_dmem_ctl_o_0_qfbk = QC1_dmem_ctl_o_0;
SB1_wr_en46_0 = QC1_dmem_ctl_o_0_qfbk & QC1_dmem_ctl_o_2;
 
--QC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15|dmem_ctl_o_0 at LC_X29_Y9_N7
--operation mode is normal
 
QC1_dmem_ctl_o_0 = DFFEAS(SB1_wr_en46_0, GLOBAL(E1__clk0), VCC, , , CC1_dmem_ctl_o_0, , !AD1_NET1640_i, VCC);
 
 
--DD1_un1_pc_next46_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0_a at LC_X27_Y11_N8
--operation mode is normal
 
DD1_un1_pc_next46_0_a = HC1_pc_gen_ctl_o_1 & !HC1_pc_gen_ctl_o_0 # !HC1_pc_gen_ctl_o_1 & !HC1_pc_gen_ctl_o_2 & HC1_pc_gen_ctl_o_0;
 
 
--AD1_pc_prectl_1_0_i_a2_0_a2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|pc_prectl_1_0_i_a2_0_a2_0 at LC_X27_Y11_N9
--operation mode is normal
 
AD1_pc_prectl_1_0_i_a2_0_a2_0 = !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & !AD1_CurrState_Sreg0_3;
 
 
--AD1_pc_prectl_1_0_i_a2_0_a2_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|pc_prectl_1_0_i_a2_0_a2_1 at LC_X27_Y14_N1
--operation mode is normal
 
AD1_pc_prectl_1_0_i_a2_0_a2_1 = !AD1_CurrState_Sreg0[2] & !AD1_CurrState_Sreg0_2 & AD1_CurrState_Sreg0_i[0] & !AD1_CurrState_Sreg0[7];
 
 
--DD1_pc_next_2_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_0_a4 at LC_X27_Y11_N3
--operation mode is normal
 
DD1_pc_next_2_sqmuxa_0_a4 = DD1_pc_next_2_sqmuxa_1_i_a2 & !HC1_pc_gen_ctl_o_2 & HC1_pc_gen_ctl_o_1 & !HC1_pc_gen_ctl_o_0;
 
 
--DD1_pc_next_0_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[2] at LC_X16_Y12_N1
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[2] = SD1_r32_o_2 & !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_2 # !DD1_pc_next_1_sqmuxa_0_a4 # !SD1_r32_o_2 & !FB1_res_7_0_0_2 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--PB1_dout_iv_2 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_2 at LC_X20_Y10_N4
--operation mode is normal
 
PB1_dout_iv_2 = HD1_dout_iv_1_2 # HD1_dout7_0_a2 & FD1_wb_o_2;
 
--PB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_2 at LC_X20_Y10_N4
--operation mode is normal
 
PB1_r32_o_2 = DFFEAS(PB1_dout_iv_2, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_i[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_i[2] at LC_X27_Y11_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_i[2] = AD1_pc_prectl_1_0_i_a2_0_a2_0 # DD1_un1_pc_prectl_1_i_a[2] & !FB1_res_7_0_0_2 & BD1_res_7_0;
 
 
--DD1_pc_next_0_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[3] at LC_X16_Y13_N8
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[3] = SD1_r32_o_3 & !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_3 # !DD1_pc_next_1_sqmuxa_0_a4 # !SD1_r32_o_3 & !FB1_res_7_0_0_3 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--PB1_dout_iv_3 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_3 at LC_X26_Y7_N4
--operation mode is normal
 
PB1_dout_iv_3 = HD1_dout_iv_1_3 # HD1_dout7_0_a2 & FD1_wb_o_3;
 
--PB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_3 at LC_X26_Y7_N4
--operation mode is normal
 
PB1_r32_o_3 = DFFEAS(PB1_dout_iv_3, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[3] at LC_X22_Y11_N7
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[3] = FB1_res_7_0_0_3 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[4] at LC_X27_Y10_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[4] = SD1_r32_o_4 & !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_4 # !DD1_pc_next_1_sqmuxa_0_a4 # !SD1_r32_o_4 & !FB1_res_7_0_0_4 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[4] at LC_X21_Y11_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[4] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_0_2 # CD1_res_7_0_0_o3_0 & ED1_r32_o_2;
 
 
--DD1_pc_next_0_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[5] at LC_X22_Y11_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[5] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_5 & !SD1_r32_o_5 # !DD1_pc_next_0_sqmuxa_0_a4 # !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_5 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[5] at LC_X22_Y11_N9
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[5] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_5;
 
 
--DD1_pc_next_0_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[6] at LC_X19_Y11_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[6] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_6 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_6 # !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_6;
 
 
--PB1_dout_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_6 at LC_X19_Y11_N8
--operation mode is normal
 
PB1_dout_iv_6 = HD1_dout_iv_1_6 # HD1_dout7_0_a2 & FD1_wb_o_6;
 
--PB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_6 at LC_X19_Y11_N8
--operation mode is normal
 
PB1_r32_o_6 = DFFEAS(PB1_dout_iv_6, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[6] at LC_X24_Y12_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[6] = FB1_res_7_0_0_6 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[7] at LC_X19_Y9_N9
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[7] = FB1_res_7_0_0_7 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_7 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_7 & !SD1_r32_o_7 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--PB1_dout_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_7 at LC_X19_Y9_N4
--operation mode is normal
 
PB1_dout_iv_7 = HD1_dout_iv_1_7 # FD1_wb_o_7 & HD1_dout7_0_a2;
 
--PB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_7 at LC_X19_Y9_N4
--operation mode is normal
 
PB1_r32_o_7 = DFFEAS(PB1_dout_iv_7, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[7] at LC_X24_Y10_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[7] = FB1_res_7_0_0_7 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[8] at LC_X24_Y12_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[8] = FB1_res_7_0_0_8 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_8 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_8 & !SD1_r32_o_8 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--PB1_dout_iv_8 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_8 at LC_X19_Y8_N9
--operation mode is normal
 
PB1_dout_iv_8 = HD1_dout_iv_1_8 # FD1_wb_o_8 & HD1_dout7_0_a2;
 
--PB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_8 at LC_X19_Y8_N9
--operation mode is normal
 
PB1_r32_o_8 = DFFEAS(PB1_dout_iv_8, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[8] at LC_X24_Y12_N2
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[8] = FB1_res_7_0_0_8 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[9] at LC_X24_Y14_N3
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[9] = FB1_res_7_0_0_9 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_9 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_9 & !SD1_r32_o_9 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--PB1_dout_iv_9 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_9 at LC_X19_Y10_N5
--operation mode is normal
 
PB1_dout_iv_9 = HD1_dout_iv_1_9 # FD1_wb_o_9 & HD1_dout7_0_a2;
 
--PB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_9 at LC_X19_Y10_N5
--operation mode is normal
 
PB1_r32_o_9 = DFFEAS(PB1_dout_iv_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[9] at LC_X24_Y14_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[9] = FB1_res_7_0_0_9 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[10] at LC_X24_Y10_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[10] = SD1_r32_o_10 & !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_10 # !DD1_pc_next_1_sqmuxa_0_a4 # !SD1_r32_o_10 & !FB1_res_7_0_0_10 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--PB1_dout_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_10 at LC_X19_Y12_N4
--operation mode is normal
 
PB1_dout_iv_10 = HD1_dout_iv_1_10 # FD1_wb_o_10 & HD1_dout7_0_a2;
 
--PB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_10 at LC_X19_Y12_N4
--operation mode is normal
 
PB1_r32_o_10 = DFFEAS(PB1_dout_iv_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[10] at LC_X24_Y10_N5
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[10] = FB1_res_7_0_0_10 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[11] at LC_X22_Y10_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[11] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_11 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_11 # !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_11;
 
 
--PB1_dout_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_11 at LC_X22_Y10_N0
--operation mode is normal
 
PB1_dout_iv_11 = HD1_dout_iv_1_11 # FD1_wb_o_11 & HD1_dout7_0_a2;
 
--PB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_11 at LC_X22_Y10_N0
--operation mode is normal
 
PB1_r32_o_11 = DFFEAS(PB1_dout_iv_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[11] at LC_X23_Y13_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[11] = FB1_res_7_0_0_11 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[12] at LC_X23_Y12_N3
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[12] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_12 & !FB1_res_7_0_0_12 # !DD1_pc_next_1_sqmuxa_0_a4 # !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_12 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--PB1_dout_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_12 at LC_X23_Y12_N5
--operation mode is normal
 
PB1_dout_iv_12 = HD1_dout_iv_1_12 # FD1_wb_o_12 & HD1_dout7_0_a2;
 
--PB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_12 at LC_X23_Y12_N5
--operation mode is normal
 
PB1_r32_o_12 = DFFEAS(PB1_dout_iv_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[12] at LC_X23_Y13_N2
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[12] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_12;
 
 
--CB1_dout_2_23 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_23 at LC_X29_Y3_N5
--operation mode is normal
 
CB1_dout_2_23 = ND1_dout7 & FD1_wb_o_23 # !ND1_dout7 & !ND1_dout_2_a_23;
 
--CB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_23 at LC_X29_Y3_N5
--operation mode is normal
 
CB1_r32_o_23 = DFFEAS(CB1_dout_2_23, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_x_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_x_7 at LC_X27_Y3_N0
--operation mode is normal
 
TB1_dout_1_x_7 = TB1_dout21 & CB1_dout_2_7 # !TB1_dout21 & CB1_dout_2_15;
 
 
--TB1_dout_1_2_7 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_7 at LC_X27_Y3_N6
--operation mode is normal
 
TB1_dout_1_2_7 = TB1_dout21 & TB1_dout22 & !TB1_dout_1_2_a_x[31] # !TB1_dout22 & CB1_dout_2_7 # !TB1_dout21 & !TB1_dout_1_2_a_x[31];
 
 
--YB1_wb_mux_1_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_a3[0] at LC_X24_Y19_N9
--operation mode is normal
 
YB1_wb_mux_1_0_0_a3[0] = KE1_q_a[7] & !KE1_q_a[5] & !KE1_q_a[6] & YB1_wb_mux_1_0_0_a3_a_x[0];
 
 
--GD1_dout_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_9 at LC_X25_Y6_N3
--operation mode is normal
 
GD1_dout_iv_1_9 = FD1_N_20_i_0_s3 & LD1_q_b[9] # !GD1_dout_iv_1_a[9];
 
 
--ED1_r32_o_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_9 at LC_X22_Y17_N3
--operation mode is normal
 
ED1_r32_o_9_lut_out = HE1_q_a[1];
ED1_r32_o_9 = DFFEAS(ED1_r32_o_9_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--F1_dout_9 is mips_sys:isys|mips_dvc:imips_dvc|dout_9 at LC_X28_Y13_N4
--operation mode is normal
 
F1_dout_9_lut_out = F1_dout_0_0_a3_3[0] & F1_cmd[9] # F1_dout_0_0_a3_4[0] & K1_cntr_9 # !F1_dout_0_0_a3_3[0] & F1_dout_0_0_a3_4[0] & K1_cntr_9;
F1_dout_9 = DFFEAS(F1_dout_9_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_9 at LC_X28_Y13_N5
--operation mode is normal
 
BB1_r32_o_9_lut_out = AB1_r32_o_7;
BB1_r32_o_9 = DFFEAS(BB1_r32_o_9_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] at LC_X20_Y15_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[11] = QD1_b_o18 & !QB1_r32_o_11 & QD1_un1_b_o18_2 # !FB1_r32_o_0_11 # !QD1_b_o18 & !QB1_r32_o_11 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[11] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[11] at LC_X20_Y15_N1
--operation mode is normal
 
G1_BUS15471_i_m[11] = !FD1_wb_o_11 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] at LC_X19_Y7_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[13] = QB1_r32_o_13 & !FB1_r32_o_0_13 & QD1_b_o18 # !QB1_r32_o_13 & QD1_un1_b_o18_2 # !FB1_r32_o_0_13 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[13] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[13] at LC_X19_Y7_N5
--operation mode is normal
 
G1_BUS15471_i_m[13] = QD1_b_o_1_sqmuxa & !FD1_wb_o_13;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] at LC_X19_Y7_N6
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[12] = QB1_r32_o_12 & !FB1_r32_o_0_12 & QD1_b_o18 # !QB1_r32_o_12 & QD1_un1_b_o18_2 # !FB1_r32_o_0_12 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[12] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[12] at LC_X19_Y7_N7
--operation mode is normal
 
G1_BUS15471_i_m[12] = QD1_b_o_1_sqmuxa & !FD1_wb_o_12;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] at LC_X21_Y6_N8
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[14] = FB1_r32_o_0_14 & !QB1_r32_o_14 & QD1_un1_b_o18_2 # !FB1_r32_o_0_14 & QD1_b_o18 # !QB1_r32_o_14 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[14] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[14] at LC_X21_Y6_N5
--operation mode is normal
 
G1_BUS15471_i_m[14] = QD1_b_o_1_sqmuxa & !FD1_wb_o_14;
 
 
--ED1_r32_o_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_8 at LC_X23_Y17_N3
--operation mode is normal
 
ED1_r32_o_8_lut_out = HE1_q_a[0];
ED1_r32_o_8 = DFFEAS(ED1_r32_o_8_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--DD1_pc_next_0_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[1] at LC_X20_Y9_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[1] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_1 & !SD1_r32_o_1 # !DD1_pc_next_0_sqmuxa_0_a4 # !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_1 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--PB1_dout_iv_1 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_1 at LC_X25_Y7_N7
--operation mode is normal
 
PB1_dout_iv_1 = HD1_dout_iv_1_1 # HD1_dout7_0_a2 & FD1_wb_o_1;
 
--PB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_1 at LC_X25_Y7_N7
--operation mode is normal
 
PB1_r32_o_1 = DFFEAS(PB1_dout_iv_1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[1] at LC_X23_Y11_N3
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[1] = FB1_res_7_0_0_1 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[0] at LC_X27_Y10_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[0] = FB1_res_7_0_0_0_d0 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_0 # !FB1_res_7_0_0_0_d0 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_0;
 
 
--PB1_dout_iv_0 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_0 at LC_X26_Y4_N9
--operation mode is normal
 
PB1_dout_iv_0 = HD1_dout_iv_1_0 # FD1_wb_o_0 & HD1_dout7_0_a2;
 
--PB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_0 at LC_X26_Y4_N9
--operation mode is normal
 
PB1_r32_o_0 = DFFEAS(PB1_dout_iv_0, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[0] at LC_X23_Y11_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[0] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_0_d0;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] at LC_X21_Y14_N2
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[21] = QB1_r32_o_21 & QD1_b_o18 & !FB1_r32_o_21 # !QB1_r32_o_21 & QD1_un1_b_o18_2 # QD1_b_o18 & !FB1_r32_o_21;
 
 
--G1_BUS15471_i_m[21] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[21] at LC_X21_Y14_N6
--operation mode is normal
 
G1_BUS15471_i_m[21] = QD1_b_o_1_sqmuxa & !FD1_wb_o_21;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] at LC_X21_Y12_N1
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[22] = FB1_r32_o_22 & !QB1_r32_o_22 & QD1_un1_b_o18_2 # !FB1_r32_o_22 & QD1_b_o18 # !QB1_r32_o_22 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[22] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[22] at LC_X25_Y13_N8
--operation mode is normal
 
G1_BUS15471_i_m[22] = !FD1_wb_o_22 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] at LC_X20_Y12_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[25] = QB1_r32_o_25 & !FB1_r32_o_25 & QD1_b_o18 # !QB1_r32_o_25 & QD1_un1_b_o18_2 # !FB1_r32_o_25 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[25] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[25] at LC_X20_Y12_N6
--operation mode is normal
 
G1_BUS15471_i_m[25] = QD1_b_o_1_sqmuxa & !FD1_wb_o_25;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] at LC_X20_Y12_N8
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[26] = FB1_r32_o_26 & !QB1_r32_o_26 & QD1_un1_b_o18_2 # !FB1_r32_o_26 & QD1_b_o18 # !QB1_r32_o_26 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[26] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[26] at LC_X20_Y12_N2
--operation mode is normal
 
G1_BUS15471_i_m[26] = !FD1_wb_o_26 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] at LC_X19_Y14_N7
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[29] = QB1_r32_o_29 & QD1_b_o18 & !FB1_r32_o_29 # !QB1_r32_o_29 & QD1_un1_b_o18_2 # QD1_b_o18 & !FB1_r32_o_29;
 
 
--G1_BUS15471_i_m[29] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[29] at LC_X19_Y14_N5
--operation mode is normal
 
G1_BUS15471_i_m[29] = QD1_b_o_1_sqmuxa & !FD1_wb_o_29;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] at LC_X21_Y16_N2
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[17] = QB1_r32_o_17 & QD1_b_o18 & !FB1_r32_o_17 # !QB1_r32_o_17 & QD1_un1_b_o18_2 # QD1_b_o18 & !FB1_r32_o_17;
 
 
--G1_BUS15471_i_m[17] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[17] at LC_X21_Y16_N9
--operation mode is normal
 
G1_BUS15471_i_m[17] = !FD1_wb_o_17 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] at LC_X22_Y12_N8
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[18] = QD1_b_o18 & !QB1_r32_o_18 & QD1_un1_b_o18_2 # !FB1_r32_o_18 # !QD1_b_o18 & !QB1_r32_o_18 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[18] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[18] at LC_X22_Y12_N9
--operation mode is normal
 
G1_BUS15471_i_m[18] = !FD1_wb_o_18 & QD1_b_o_1_sqmuxa;
 
 
--VD1_hilo_37_iv_0[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[8] at LC_X6_Y16_N2
--operation mode is normal
 
VD1_hilo_37_iv_0[8] = VD1_hilo_1_sqmuxa_1 & VD1_hilo_9 # !VD1_hilo_37_iv_0_a[8] & VD1_hilo_3_sqmuxa # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_37_iv_0_a[8] & VD1_hilo_3_sqmuxa;
 
 
--VD1_hilo_8_Z[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[8] at LC_X6_Y16_N7
--operation mode is normal
 
VD1_hilo_8_Z[8] = RC1_alu_func_o_0 & VD1_hilo_8 # !RC1_alu_func_o_0 & PD1_a_o_8;
 
 
--VD1_hilo_37_iv_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[8] at LC_X6_Y16_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[8] = VD1_hilo_7 & !VD1_hilo_2_sqmuxa & !PD1_a_o_8 # !VD1_addnop2109_0_a2 # !VD1_hilo_7 & !PD1_a_o_8 # !VD1_addnop2109_0_a2;
 
 
--VD1_finish is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish at LC_X2_Y15_N1
--operation mode is normal
 
VD1_finish_lut_out = !VD1_rdy;
VD1_finish = DFFEAS(VD1_finish_lut_out, GLOBAL(E1__clk0), VCC, , VD1_finish_0_sqmuxa_i, , , !sys_rst, );
 
 
--VD1_un134_hilo_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[7] at LC_X4_Y16_N5
--operation mode is arithmetic
 
VD1_un134_hilo_combout[7]_carry_eqn = VD1_un134_hilo_cout[5];
VD1_un134_hilo_combout[7] = VD1_hilo_7 $ (VD1_hilo_6 & VD1_un134_hilo_combout[7]_carry_eqn);
 
--VD1_un134_hilo_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[7] at LC_X4_Y16_N5
--operation mode is arithmetic
 
VD1_un134_hilo_cout[7]_cout_0 = !VD1_un134_hilo_cout[5] # !VD1_hilo_7 # !VD1_hilo_6;
VD1_un134_hilo_cout[7] = CARRY(VD1_un134_hilo_cout[7]_cout_0);
 
--VD1L1691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[7]~COUT1_3 at LC_X4_Y16_N5
--operation mode is arithmetic
 
VD1L1691_cout_1 = !VD1_un134_hilo_cout[5] # !VD1_hilo_7 # !VD1_hilo_6;
VD1L1691 = CARRY(VD1L1691_cout_1);
 
 
--VD1_hilo_37_iv_0_a6_3[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a6_3[40] at LC_X6_Y8_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a6_3[40] = VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add9 & VD1_hilo_37_iv_0_a2_7_2_1[37] & !VD1_sub_or_yn;
 
 
--VD1_hilo_37_iv_0_5[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[40] at LC_X7_Y3_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_5[40] = VD1_hilo_37_iv_0_1[40] # VD1_hilo_37_iv_0_5_a[40] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add9;
 
 
--VD1_hilo_37_iv_0_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[40] at LC_X6_Y8_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_a[40] = VD1_hilo_37_iv_0_a6_0_1[40] & !PD1_a_o_8 & VD1_hilo_37_iv_0_a3_1[0] # !VD1_hilo_41 # !VD1_hilo_37_iv_0_a6_0_1[40] & !PD1_a_o_8 & VD1_hilo_37_iv_0_a3_1[0];
 
 
--VD1_nop2_reged[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[8] at LC_X13_Y4_N6
--operation mode is arithmetic
 
VD1_nop2_reged[8]_carry_eqn = (!VD1_nop2_reged_cout[4] & VD1_nop2_reged_cout[6]) # (VD1_nop2_reged_cout[4] & VD1L1231);
VD1_nop2_reged[8] = VD1_op2_reged[8] $ VD1_nop2_reged[8]_carry_eqn;
 
--VD1_nop2_reged_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[8] at LC_X13_Y4_N6
--operation mode is arithmetic
 
VD1_nop2_reged_cout[8]_cout_0 = !VD1_op2_reged[9] & !VD1_op2_reged[8] & !VD1_nop2_reged_cout[6];
VD1_nop2_reged_cout[8] = CARRY(VD1_nop2_reged_cout[8]_cout_0);
 
--VD1L5231 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[8]~COUT1_16 at LC_X13_Y4_N6
--operation mode is arithmetic
 
VD1L5231_cout_1 = !VD1_op2_reged[9] & !VD1_op2_reged[8] & !VD1L1231;
VD1L5231 = CARRY(VD1L5231_cout_1);
 
 
--VD1_un50_hilo_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add7 at LC_X10_Y4_N1
--operation mode is arithmetic
 
VD1_un50_hilo_add7_carry_eqn = (!VD1_un50_hilo_carry_5 & VD1_un50_hilo_carry_6) # (VD1_un50_hilo_carry_5 & VD1L4171);
VD1_un50_hilo_add7 = VD1_nop2_reged[7] $ VD1_hilo_39 $ VD1_un50_hilo_add7_carry_eqn;
 
--VD1_un50_hilo_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_7 at LC_X10_Y4_N1
--operation mode is arithmetic
 
VD1_un50_hilo_carry_7_cout_0 = VD1_nop2_reged[7] & !VD1_hilo_39 & !VD1_un50_hilo_carry_6 # !VD1_nop2_reged[7] & !VD1_un50_hilo_carry_6 # !VD1_hilo_39;
VD1_un50_hilo_carry_7 = CARRY(VD1_un50_hilo_carry_7_cout_0);
 
--VD1L6171 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_7~COUT1_1 at LC_X10_Y4_N1
--operation mode is arithmetic
 
VD1L6171_cout_1 = VD1_nop2_reged[7] & !VD1_hilo_39 & !VD1L4171 # !VD1_nop2_reged[7] & !VD1L4171 # !VD1_hilo_39;
VD1L6171 = CARRY(VD1L6171_cout_1);
 
 
--VD1_un59_hilo_add7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add7 at LC_X9_Y5_N1
--operation mode is arithmetic
 
VD1_un59_hilo_add7_carry_eqn = (!VD1_un59_hilo_carry_5 & VD1_un59_hilo_carry_6) # (VD1_un59_hilo_carry_5 & VD1L7381);
VD1_un59_hilo_add7 = VD1_hilo_39 $ VD1_op2_reged[7] $ VD1_un59_hilo_add7_carry_eqn;
 
--VD1_un59_hilo_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_7 at LC_X9_Y5_N1
--operation mode is arithmetic
 
VD1_un59_hilo_carry_7_cout_0 = VD1_hilo_39 & !VD1_op2_reged[7] & !VD1_un59_hilo_carry_6 # !VD1_hilo_39 & !VD1_un59_hilo_carry_6 # !VD1_op2_reged[7];
VD1_un59_hilo_carry_7 = CARRY(VD1_un59_hilo_carry_7_cout_0);
 
--VD1L9381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_7~COUT1_1 at LC_X9_Y5_N1
--operation mode is arithmetic
 
VD1L9381_cout_1 = VD1_hilo_39 & !VD1_op2_reged[7] & !VD1L7381 # !VD1_hilo_39 & !VD1L7381 # !VD1_op2_reged[7];
VD1L9381 = CARRY(VD1L9381_cout_1);
 
 
--VD1_hilo_37_iv_0_a2_0[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_0[38] at LC_X6_Y7_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_0[38] = !RC1_alu_func_o_0 & VD1_addnop2109_0_a2;
 
 
--VD1_hilo_37_iv_0_a2_1[39] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a2_1[39] at LC_X7_Y7_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a2_1[39] = VD1_hilo_0_sqmuxa & !VD1_hilo_7;
 
 
--VD1_hilo_37_iv_0_a3_2[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_2[62] at LC_X5_Y6_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_2[62] = VD1_addop2 & VD1_hilo_3_sqmuxa & !VD1_addnop2;
 
 
--VD1_hilo_37_iv_0_o3_2[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_2[34] at LC_X6_Y3_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_2[34] = VD1_hilo_37_iv_0_a3_1[62] # !VD1_hilo_33_1[64] & VD1_hilo_3_sqmuxa;
 
 
--VD1_un1_op2_reged_1_combout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[7] at LC_X15_Y4_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[7] = VD1_eqop2_2_32 & VD1_op2_reged[7] # !VD1_eqop2_2_32 & VD1_nop2_reged[7];
 
 
--VD1_hilo_24_add6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add6 at LC_X8_Y4_N0
--operation mode is arithmetic
 
VD1_hilo_24_add6_carry_eqn = VD1_hilo_24_carry_5;
VD1_hilo_24_add6 = VD1_un1_op2_reged_1_combout[6] $ VD1_hilo_37 $ !VD1_hilo_24_add6_carry_eqn;
 
--VD1_hilo_24_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_6 at LC_X8_Y4_N0
--operation mode is arithmetic
 
VD1_hilo_24_carry_6_cout_0 = VD1_un1_op2_reged_1_combout[6] & VD1_hilo_37 # !VD1_hilo_24_carry_5 # !VD1_un1_op2_reged_1_combout[6] & VD1_hilo_37 & !VD1_hilo_24_carry_5;
VD1_hilo_24_carry_6 = CARRY(VD1_hilo_24_carry_6_cout_0);
 
--VD1L884 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_6~COUT1_1 at LC_X8_Y4_N0
--operation mode is arithmetic
 
VD1L884_cout_1 = VD1_un1_op2_reged_1_combout[6] & VD1_hilo_37 # !VD1_hilo_24_carry_5 # !VD1_un1_op2_reged_1_combout[6] & VD1_hilo_37 & !VD1_hilo_24_carry_5;
VD1L884 = CARRY(VD1L884_cout_1);
 
 
--PD1_a_o_3_d_a[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[7] at LC_X19_Y9_N1
--operation mode is normal
 
PD1_a_o_3_d_a[7] = PD1_a_o_sn_m2 & !PB1_r32_o_7 # !PD1_a_o_sn_m2 & !AB1_r32_o_5;
 
 
--YB1_rd_sel_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0 at LC_X25_Y17_N5
--operation mode is normal
 
YB1_rd_sel_2_0_0_0 = YB1_alu_func_2_0_0_a3_1[1] # WB36L1 & YB1_alu_func_2_0_0_a2_3[1] # !YB1_rd_sel_2_0_0_a[0];
 
 
--WB36L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:rd_sel_1_0_|lpm_latch:U1|q[0]~56 at LC_X25_Y17_N1
--operation mode is normal
 
WB36L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_rd_sel_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB36L1;
 
--EC1_rd_sel_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5|rd_sel_o_0 at LC_X25_Y17_N1
--operation mode is normal
 
EC1_rd_sel_o_0 = DFFEAS(WB36L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_rd_sel_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_1 at LC_X29_Y17_N0
--operation mode is normal
 
YB1_rd_sel_2_0_0_1 = YB1_rd_sel_2_0_0_0_Z[1] # !KE1_q_a[7] & WB46L2 & YB1_rd_sel_2_0_0_a[1];
 
 
--WB46L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~68 at LC_X29_Y17_N1
--operation mode is normal
 
WB46L1 = YB1_muxa_ctl373 # YB1_un1_muxa_ctl370_x & YB1_rd_sel_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB46L2;
 
 
--WB46L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1|q[0]~69 at LC_X29_Y17_N2
--operation mode is normal
 
WB46L2 = !YB1_un1_ins_i_22_u_x & WB46L1;
 
--EC1_rd_sel_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5|rd_sel_o_1 at LC_X29_Y17_N2
--operation mode is normal
 
EC1_rd_sel_o_1 = DFFEAS(WB46L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_wb_we_1_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_we_1_0_0_a[0] at LC_X24_Y19_N7
--operation mode is normal
 
YB1_wb_we_1_0_0_a[0] = !YB1_wb_mux_1_0_0_a3[0] & YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x # !KE1_q_a[5] # !KE1_q_a[4];
 
 
--YB1_alu_we_1_0_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_0_Z[0] at LC_X28_Y17_N2
--operation mode is normal
 
YB1_alu_we_1_0_0_0_Z[0] = YB1_alu_we_1_0_0_a3_1[0] # YB1_rd_sel_2_0_0_a[1] & !KE1_q_a[7] & WB24L1;
 
 
--YB1_alu_we_1_0_0_a3[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3[0] at LC_X25_Y19_N8
--operation mode is normal
 
YB1_alu_we_1_0_0_a3[0] = !GE1_q_a[3] & YB1_alu_we_1_0_0_a3_a_x[0] & YB1_alu_func_2_i_m3_0_a2_0_x[2] # YB1_alu_func_2_0_0_a2_2_x[0];
 
 
--FD1_wb_o_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_20 at LC_X29_Y7_N9
--operation mode is normal
 
FD1_wb_o_20 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_20 # F1_dout_20 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_20;
 
--FD1_r_data_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_20 at LC_X29_Y7_N9
--operation mode is normal
 
FD1_r_data_20 = DFFEAS(FD1_wb_o_20, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_20 at LC_X22_Y14_N8
--operation mode is normal
 
ND1_dout_2_a_20 = XD1_mux_fw_1 & !AB1_r32_o_18 # !XD1_mux_fw_1 & !QB1_r32_o_20;
 
 
--AD1_delay_counter_Sreg0[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[5] at LC_X31_Y17_N9
--operation mode is normal
 
AD1_delay_counter_Sreg0[5]_lut_out = WB27L1 # !sys_rst;
AD1_delay_counter_Sreg0[5] = DFFEAS(AD1_delay_counter_Sreg0[5]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 at LC_X31_Y17_N5
--operation mode is normal
 
AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0 = !AD1_delay_counter_Sreg0[4] & !AD1_delay_counter_Sreg0[2] & !AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[3];
 
 
--YB1_cmp_ctl_2_0_0_a2_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_0[0] at LC_X26_Y9_N2
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a2_0[0] = KE1_q_a[6] & !KE1_q_a[2] & KE1_q_a[1] # !YB1_fsm_dly_2_0_0_a2_0_a_x[2];
 
 
--YB1_cmp_ctl_2_0_0_a2_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_1[0] at LC_X26_Y13_N6
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a2_1[0] = KE1_q_a[2] & YB1_alu_we_1s_1_o2_0_x[0] # JE1_q_a[4] & JE1_q_a[0];
 
 
--YB1_fsm_dly_2_0_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_x[2] at LC_X24_Y17_N5
--operation mode is normal
 
YB1_fsm_dly_2_0_0_a2_x[2] = !KE1_q_a[7] & !KE1_q_a[5] & !KE1_q_a[4];
 
 
--YB1_alu_func_2_0_0_a2_2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2_x[1] at LC_X27_Y17_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_2_x[1] = GE1_q_a[4] & !GE1_q_a[5] & YB1_alu_func_2_0_0_a2_0_x[3];
 
 
--YB1_alu_func_2_0_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_x[0] at LC_X25_Y18_N4
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_x[0] = !GE1_q_a[3] & YB1_alu_func_2_0_0_a2_0[1];
 
 
--YB1_alu_func_2_0_0_a2_1[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_1[4] at LC_X26_Y18_N7
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_1[4] = YB1_alu_func_2_0_0_a2_0_x[3] & !GE1_q_a[4] & GE1_q_a[5] & GE1_q_a[1];
 
 
--YB1_alu_func_2_0_0_3_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_3_a[1] at LC_X24_Y18_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_3_a[1] = !YB1_alu_func_2_0_0_1_Z[1] & !YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x # !KE1_q_a[5] # !KE1_q_a[4];
 
 
--YB1_alu_func_2_0_0_a2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[0] at LC_X24_Y19_N2
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_0_x[0] = KE1_q_a[3] & KE1_q_a[2];
 
 
--YB1_alu_func_2_0_0_a2_0_x[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[4] at LC_X28_Y16_N6
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_0_x[4] = !JE1_q_a[7] & YB1_fsm_dly_2_0_0_a2_0[2];
 
 
--YB1_un1_muxa_ctl370_6_a_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_6_a_x at LC_X27_Y19_N5
--operation mode is normal
 
YB1_un1_muxa_ctl370_6_a_x = !KE1_q_a[5] & KE1_q_a[7];
 
 
--YB1_un1_muxa_ctl370_5_a is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|un1_muxa_ctl370_5_a at LC_X28_Y18_N1
--operation mode is normal
 
YB1_un1_muxa_ctl370_5_a = !KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[4] # !KE1_q_a[7];
 
 
--YB1_ext_ctl_2_0_0_a3_1_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a3_1_0[2] at LC_X24_Y19_N5
--operation mode is normal
 
YB1_ext_ctl_2_0_0_a3_1_0[2] = !KE1_q_a[7] & !KE1_q_a[5] & !KE1_q_a[3] & YB1_ext_ctl_2_0_0_o2[2];
 
 
--YB1_ext_ctl_2_0_0_o3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_o3[2] at LC_X25_Y16_N1
--operation mode is normal
 
YB1_ext_ctl_2_0_0_o3[2] = YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] & YB1_cmp_ctl_2_0_0_a2_x[0] # YB1_ext_ctl_2_0_0_a2_0_x[2] & YB1_cmp_ctl_2_0_0_a2_x[2] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] & YB1_ext_ctl_2_0_0_a2_0_x[2] & YB1_cmp_ctl_2_0_0_a2_x[2];
 
 
--YB1_fsm_dly_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a[0] at LC_X26_Y17_N8
--operation mode is normal
 
YB1_fsm_dly_2_0_0_a[0] = !YB1_ext_ctl_2_0_0_a2_0_x[2] # !YB1_pc_gen_ctl_2_0_0_a2_x[1] # !GE1_q_a[3] # !YB1_alu_func_2_0_0_a2_2_x[0];
 
 
--YB1_fsm_dly_2_i_m3_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_i_m3_0_a[1] at LC_X28_Y17_N4
--operation mode is normal
 
YB1_fsm_dly_2_i_m3_0_a[1] = !KE1_q_a[3] & !YB1_cmp_ctl_2_0_0_a2_1[0] & !YB1_cmp_ctl_2_0_0_a2_0[0] # !WB45L1;
 
 
--YB1_fsm_dly_2_0_0_a2_0[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_0[2] at LC_X26_Y9_N7
--operation mode is normal
 
YB1_fsm_dly_2_0_0_a2_0[2] = KE1_q_a[6] & !KE1_q_a[2] & !KE1_q_a[1] & YB1_fsm_dly_2_0_0_a2_0_a_x[2];
 
 
--YB1_fsm_dly_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a[2] at LC_X28_Y16_N5
--operation mode is normal
 
YB1_fsm_dly_2_0_0_a[2] = !KE1_q_a[3] & !YB1_cmp_ctl_2_0_0_a2_1[0] & !YB1_cmp_ctl_2_0_0_a2_0[0] # !WB55L1;
 
 
--AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_0_a_x[8] at LC_X30_Y16_N4
--operation mode is normal
 
AD1_CurrState_Sreg0_ns_0_0_0_a_x[8] = WB45L1 & !WB35L1;
 
 
--AD1_CurrState_Sreg0_ns_0_0_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_a[1] at LC_X30_Y16_N9
--operation mode is normal
 
AD1_CurrState_Sreg0_ns_0_0_a[1] = WB35L1 & !WB45L1 # !WB35L1 & WB45L1 # WB55L1 # !AD1_CurrState_Sreg0_i[0];
 
 
--AD1_CurrState_Sreg0_ns_0_0_a2_2[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_ns_0_0_a2_2[1] at LC_X30_Y16_N5
--operation mode is normal
 
AD1_CurrState_Sreg0_ns_0_0_a2_2[1] = !AD1_CurrState_Sreg0_2 & !AD1_CurrState_Sreg0[2];
 
 
--YB1_alu_func_2_i_m3_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a[2] at LC_X26_Y19_N5
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_a[2] = !KE1_q_a[3] & YB1_alu_func_2_0_0_o2_0[0] # YB1_alu_func_2_0_0_a2_1_x[3] & YB1_alu_func_2_0_0_a2_0_x[3];
 
 
--YB1_alu_func_2_i_m3_0_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_5[2] at LC_X28_Y15_N9
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_5[2] = YB1_alu_func_2_i_m3_0_a3_5[2] # YB1_alu_func_2_i_m3_0_2[2] # !KE1_q_a[4] & YB1_alu_func_2_i_m3_0_5_a[2];
 
 
--YB1_alu_func_2_0_0_a3_0[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0[3] at LC_X27_Y18_N2
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_0[3] = !KE1_q_a[4] & YB1_alu_func_2_0_0_a3_0_a_x[3] & !KE1_q_a[7] & WB04L2;
 
 
--YB1_alu_func_2_0_0_a3_1[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1[3] at LC_X26_Y19_N2
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_1[3] = YB1_alu_func_2_0_0_a2_1_x[3] & !GE1_q_a[3] & !KE1_q_a[4] & YB1_alu_func_2_0_0_a3_1_a[3];
 
 
--YB1_alu_func_2_0_0_o3[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o3[3] at LC_X24_Y19_N4
--operation mode is normal
 
YB1_alu_func_2_0_0_o3[3] = YB1_wb_mux_1_0_0_a3[0] # !KE1_q_a[4] & !KE1_q_a[3] & KE1_q_a[5];
 
 
--YB1_alu_func_2_0_0_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a[3] at LC_X27_Y18_N8
--operation mode is normal
 
YB1_alu_func_2_0_0_a[3] = !KE1_q_a[4] & !KE1_q_a[3] & YB1_alu_func_2_0_0_o2_x[3] & YB1_alu_func_2_0_0_a2_2_x[1];
 
 
--YB1_alu_func_2_0_0_1_Z[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_Z[4] at LC_X25_Y18_N2
--operation mode is normal
 
YB1_alu_func_2_0_0_1_Z[4] = YB1_alu_func_2_0_0_1_a[4] & YB1_alu_func_2_0_0_a2_1[4] & YB1_alu_func_2_0_0_a2_3_x[0] # !YB1_alu_func_2_0_0_1_a[4] & YB1_alu_func_2_0_0_a2_x[0] # YB1_alu_func_2_0_0_a2_1[4] & YB1_alu_func_2_0_0_a2_3_x[0];
 
 
--YB1_alu_func_2_0_0_o2_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_0[0] at LC_X26_Y18_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_o2_0[0] = YB1_alu_func_2_0_0_a2_2_x[1] # YB1_alu_func_2_0_0_o2_0_a_x[0] & !GE1_q_a[4] & GE1_q_a[1];
 
 
--YB1_alu_func_2_0_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0_Z[0] at LC_X26_Y18_N1
--operation mode is normal
 
YB1_alu_func_2_0_0_0_Z[0] = !GE1_q_a[3] & !GE1_q_a[0] & YB1_alu_func_2_0_0_a2_0[1] & YB1_alu_func_2_0_0_0_a[0];
 
 
--YB1_alu_func_2_0_0_2_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_2_a_x[0] at LC_X24_Y19_N6
--operation mode is normal
 
YB1_alu_func_2_0_0_2_a_x[0] = KE1_q_a[2] & !KE1_q_a[4] # !KE1_q_a[3] # !KE1_q_a[2] & KE1_q_a[3] $ !KE1_q_a[4];
 
 
--YB1_alu_func_2_0_0_a2_3_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_3_x[0] at LC_X26_Y17_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_3_x[0] = GE1_q_a[3] & YB1_alu_func_2_0_0_a2_0[1];
 
 
--VD1_hilo_37_iv_0_1[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[36] at LC_X6_Y6_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_1[36] = VD1_hilo_37_iv_0_1_a[36] # VD1_addop2 & VD1_hilo_37_iv_0_a2_7[34] & !VD1_un59_hilo_add4;
 
 
--VD1_hilo_37_iv_0_5_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[36] at LC_X6_Y6_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_5_a[36] = VD1_un50_hilo_add4 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add4 # !VD1_un50_hilo_add4 & VD1_hilo_37_iv_0_a2_6_0[37] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add4;
 
 
--YB1_alu_func_2_0_0_o2_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_x[3] at LC_X24_Y17_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_o2_x[3] = GE1_q_a[3] # GE1_q_a[0] & !GE1_q_a[1];
 
 
--YB1_ext_ctl_2_0_0_a2_2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a2_2_x[2] at LC_X25_Y19_N2
--operation mode is normal
 
YB1_ext_ctl_2_0_0_a2_2_x[2] = !GE1_q_a[5] & !GE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[3];
 
 
--YB1_muxa_ctl_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a[0] at LC_X25_Y17_N6
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_a[0] = YB1_alu_func_2_0_0_a2_0_x[0] & !YB1_fsm_dly_2_0_0_a2_x[2] & !WB65L1 # !YB1_alu_func_2_0_0_a2_3[1] # !YB1_alu_func_2_0_0_a2_0_x[0] & !WB65L1 # !YB1_alu_func_2_0_0_a2_3[1];
 
 
--YB1_muxa_ctl_2_0_0_x_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_x_0 at LC_X29_Y17_N8
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_x_0 = KE1_q_a[5] # YB1_muxa_ctl_2_0_0_2[1];
 
 
--WB75L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~68 at LC_X28_Y15_N6
--operation mode is normal
 
WB75L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_muxa_ctl_2_0_0_x_0 # !YB1_un1_muxa_ctl370_x & WB75L2;
 
 
--WB75L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1|q[0]~69 at LC_X28_Y15_N4
--operation mode is normal
 
WB75L2 = !YB1_un1_ins_i_23_2_0 & WB75L1;
 
--GC1_muxa_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7|muxa_ctl_o_1 at LC_X28_Y15_N4
--operation mode is normal
 
GC1_muxa_ctl_o_1 = DFFEAS(WB75L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--WD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE_1 at LC_X27_Y9_N6
--operation mode is normal
 
AE1_q_1_qfbk = AE1_q_1;
WD1_un1_mux_fw_NE_1 = AE1_q_0 & AE1_q_1_qfbk $ MB1_r5_o_1 # !MB1_r5_o_0 # !AE1_q_0 & MB1_r5_o_0 # AE1_q_1_qfbk $ MB1_r5_o_1;
 
--AE1_q_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_1 at LC_X27_Y9_N6
--operation mode is normal
 
AE1_q_1 = DFFEAS(WD1_un1_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_22, , , VCC);
 
 
--WD1_un1_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un1_mux_fw_NE_a at LC_X25_Y9_N4
--operation mode is normal
 
AE1_q_2_qfbk = AE1_q_2;
WD1_un1_mux_fw_NE_a = MB1_r5_o_2 & MB1_r5_o_3 $ AE1_q_3 # !AE1_q_2_qfbk # !MB1_r5_o_2 & AE1_q_2_qfbk # MB1_r5_o_3 $ AE1_q_3;
 
--AE1_q_2 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_2 at LC_X25_Y9_N4
--operation mode is normal
 
AE1_q_2 = DFFEAS(WD1_un1_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_23, , , VCC);
 
 
--HD1_dout_iv_1_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_4 at LC_X16_Y11_N8
--operation mode is normal
 
HD1_dout_iv_1_4 = FD1_N_18_i_0_s3 & LD2_q_b[4] # !HD1_dout_iv_1_a[4];
 
 
--HD1_dout7_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout7_0_a2 at LC_X22_Y8_N3
--operation mode is normal
 
HD1_dout7_0_a2 = MC1_wb_we_o_0 & !YD1_mux_fw_1 & !YD1_un17_mux_fw_NE & !WD1_un30_mux_fw;
 
 
--WD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE at LC_X25_Y9_N2
--operation mode is normal
 
WD1_un17_mux_fw_NE = WD1_un17_mux_fw_NE_1 # WD1_un17_mux_fw_NE_a # NB1_r5_o_4 $ AE1_q_4;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] at LC_X20_Y15_N3
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[10] = QB1_r32_o_10 & !FB1_r32_o_0_10 & QD1_b_o18 # !QB1_r32_o_10 & QD1_un1_b_o18_2 # !FB1_r32_o_0_10 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[10] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[10] at LC_X20_Y15_N2
--operation mode is normal
 
G1_BUS15471_i_m[10] = !FD1_wb_o_10 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] at LC_X16_Y5_N8
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[15] = QD1_b_o18 & !QB1_r32_o_15 & QD1_un1_b_o18_2 # !FB1_r32_o_0_15 # !QD1_b_o18 & !QB1_r32_o_15 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[15] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[15] at LC_X16_Y5_N3
--operation mode is normal
 
G1_BUS15471_i_m[15] = QD1_b_o_1_sqmuxa & !FD1_wb_o_15;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] at LC_X21_Y15_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[27] = QD1_b_o18 & !QB1_r32_o_27 & QD1_un1_b_o18_2 # !FB1_r32_o_27 # !QD1_b_o18 & !QB1_r32_o_27 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[27] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[27] at LC_X21_Y15_N2
--operation mode is normal
 
G1_BUS15471_i_m[27] = QD1_b_o_1_sqmuxa & !FD1_wb_o_27;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] at LC_X22_Y15_N3
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[19] = QB1_r32_o_19 & !FB1_r32_o_19 & QD1_b_o18 # !QB1_r32_o_19 & QD1_un1_b_o18_2 # !FB1_r32_o_19 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[19] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[19] at LC_X22_Y15_N0
--operation mode is normal
 
G1_BUS15471_i_m[19] = !FD1_wb_o_19 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] at LC_X22_Y14_N2
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[20] = FB1_r32_o_20 & !QB1_r32_o_20 & QD1_un1_b_o18_2 # !FB1_r32_o_20 & QD1_b_o18 # !QB1_r32_o_20 & QD1_un1_b_o18_2;
 
 
--G1_BUS15471_i_m[20] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[20] at LC_X22_Y14_N5
--operation mode is normal
 
G1_BUS15471_i_m[20] = QD1_b_o_1_sqmuxa & !FD1_wb_o_20;
 
 
--VD1_un134_hilo_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[6] at LC_X5_Y16_N5
--operation mode is arithmetic
 
VD1_un134_hilo_combout[6]_carry_eqn = VD1_un134_hilo_cout[4];
VD1_un134_hilo_combout[6] = VD1_hilo_6 $ VD1_un134_hilo_combout[6]_carry_eqn;
 
--VD1_un134_hilo_cout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[6] at LC_X5_Y16_N5
--operation mode is arithmetic
 
VD1_un134_hilo_cout[6]_cout_0 = !VD1_un134_hilo_cout[4] # !VD1_hilo_6 # !VD1_hilo_7;
VD1_un134_hilo_cout[6] = CARRY(VD1_un134_hilo_cout[6]_cout_0);
 
--VD1L9591 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[6]~COUT1_15 at LC_X5_Y16_N5
--operation mode is arithmetic
 
VD1L9591_cout_1 = !VD1_un134_hilo_cout[4] # !VD1_hilo_6 # !VD1_hilo_7;
VD1L9591 = CARRY(VD1L9591_cout_1);
 
 
--VD1_hilo_1_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_i at LC_X32_Y9_N0
--operation mode is normal
 
VD1_hilo_1_sqmuxa_i = !VD1_rdy_0_sqmuxa # !sys_rst;
 
 
--VD1_count[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[4] at LC_X32_Y9_N6
--operation mode is arithmetic
 
VD1_count[4]_carry_eqn = (!VD1_count_cout[2] & VD1_count_cout[3]) # (VD1_count_cout[2] & VD1L011);
VD1_count[4]_lut_out = VD1_count[4] $ (!VD1_count[4]_carry_eqn);
VD1_count[4] = DFFEAS(VD1_count[4]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
--VD1_count_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[4] at LC_X32_Y9_N6
--operation mode is arithmetic
 
VD1_count_cout[4]_cout_0 = VD1_count[4] & !VD1_count_cout[3];
VD1_count_cout[4] = CARRY(VD1_count_cout[4]_cout_0);
 
--VD1L211 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[4]~COUT1_4 at LC_X32_Y9_N6
--operation mode is arithmetic
 
VD1L211_cout_1 = VD1_count[4] & !VD1L011;
VD1L211 = CARRY(VD1L211_cout_1);
 
 
--VD1_overflow_4_iv_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|overflow_4_iv_a at LC_X8_Y13_N0
--operation mode is normal
 
VD1_overflow_4_iv_a = !VD1_un3_overflow_m_0 # !PD1_a_o_31 # !VD1_op2_reged_3[32] # !VD1_addnop2109_0_a2;
 
 
--VD1_over_i[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_i[32] at LC_X10_Y10_N6
--operation mode is normal
 
VD1_over_i[32]_carry_eqn = (!VD1_over_carry_30 & VD1_over_add31_cout) # (VD1_over_carry_30 & VD1L2741);
VD1_over_i[32] = !VD1_over_i[32]_carry_eqn;
 
 
--VD1_rdy_1_i_a2_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|rdy_1_i_a2_a at LC_X2_Y15_N6
--operation mode is normal
 
VD1_rdy_1_i_a2_a = !VD1_hilo25 & !VD1_rdy_0_sqmuxa & !VD1_un1_overflow_1 # !VD1_addnop2110;
 
 
--VD1_op2_reged_3[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_reged_3[32] at LC_X8_Y13_N8
--operation mode is normal
 
VD1_op2_reged_3[32] = VD1_b_o_iv_31 & RC1_alu_func_o_0;
 
--VD1_op2_sign_reged is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op2_sign_reged at LC_X8_Y13_N8
--operation mode is normal
 
VD1_op2_sign_reged = DFFEAS(VD1_op2_reged_3[32], GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_add1_3_sqmuxa_0_x is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1_3_sqmuxa_0_x at LC_X8_Y6_N1
--operation mode is normal
 
VD1_add1_3_sqmuxa_0_x = sys_rst & !VD1_mul;
 
 
--VD1_add1_14_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|add1_14_a at LC_X8_Y6_N8
--operation mode is normal
 
VD1_add1_14_a = !VD1_eqz_2 & VD1_op1_sign_reged & VD1_eqop2_2_NE # !VD1_op2_sign_reged;
 
 
--VD1_eqnop2_2_NE is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE at LC_X13_Y2_N2
--operation mode is normal
 
VD1_eqnop2_2_NE = VD1_eqnop2_2_NE_7 # VD1_eqnop2_2_NE_9 # VD1_eqnop2_2_NE_10 # !VD1_eqnop2_2_NE_a;
 
 
--VD1_addop2_0_sqmuxa_1_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2_0_sqmuxa_1_i at LC_X2_Y15_N9
--operation mode is normal
 
VD1_addop2_0_sqmuxa_1_i = VD1_count[5] & VD1_addnop2110 & !VD1_finish # !sys_rst;
 
 
--VD1_hilo[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo[64] at LC_X7_Y9_N4
--operation mode is normal
 
VD1_hilo[64]_lut_out = !VD1_hilo_37_iv_1[64] & VD1_hilo_37_iv_a[64] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_33_i_m[64];
VD1_hilo[64] = DFFEAS(VD1_hilo[64]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_sub_or_yn_0_sqmuxa_1_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_a at LC_X3_Y14_N9
--operation mode is normal
 
VD1_sub_or_yn_0_sqmuxa_1_a = !VD1_hilo25 & VD1_rdy # !VD1_un1_addnop2104_1 & VD1_start;
 
 
--VD1_nop2_reged[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[4] at LC_X13_Y4_N4
--operation mode is arithmetic
 
VD1_nop2_reged[4] = VD1_op2_reged[4] $ VD1_nop2_reged_cout[2];
 
--VD1_nop2_reged_cout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[4] at LC_X13_Y4_N4
--operation mode is arithmetic
 
VD1_nop2_reged_cout[4] = CARRY(!VD1_op2_reged[5] & !VD1_op2_reged[4] & !VD1L5131);
 
 
--VD1_nop2_reged[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[5] at LC_X12_Y4_N4
--operation mode is arithmetic
 
VD1_nop2_reged[5] = VD1_op2_reged[5] $ (VD1_op2_reged[4] # VD1_nop2_reged_cout[3]);
 
--VD1_nop2_reged_cout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[5] at LC_X12_Y4_N4
--operation mode is arithmetic
 
VD1_nop2_reged_cout[5] = CARRY(!VD1_op2_reged[5] & !VD1_op2_reged[4] & !VD1L7131);
 
 
--VD1_un50_hilo_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add4 at LC_X10_Y5_N8
--operation mode is arithmetic
 
VD1_un50_hilo_add4_carry_eqn = (!VD1_un50_hilo_carry_0 & VD1_un50_hilo_carry_3) # (VD1_un50_hilo_carry_0 & VD1L9071);
VD1_un50_hilo_add4 = VD1_hilo_36 $ VD1_nop2_reged[4] $ !VD1_un50_hilo_add4_carry_eqn;
 
--VD1_un50_hilo_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_4 at LC_X10_Y5_N8
--operation mode is arithmetic
 
VD1_un50_hilo_carry_4_cout_0 = VD1_hilo_36 & VD1_nop2_reged[4] # !VD1_un50_hilo_carry_3 # !VD1_hilo_36 & VD1_nop2_reged[4] & !VD1_un50_hilo_carry_3;
VD1_un50_hilo_carry_4 = CARRY(VD1_un50_hilo_carry_4_cout_0);
 
--VD1L1171 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_4~COUT1_1 at LC_X10_Y5_N8
--operation mode is arithmetic
 
VD1L1171_cout_1 = VD1_hilo_36 & VD1_nop2_reged[4] # !VD1L9071 # !VD1_hilo_36 & VD1_nop2_reged[4] & !VD1L9071;
VD1L1171 = CARRY(VD1L1171_cout_1);
 
 
--VD1_un59_hilo_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add4 at LC_X9_Y6_N8
--operation mode is arithmetic
 
VD1_un59_hilo_add4_carry_eqn = (!VD1_un59_hilo_carry_0 & VD1_un59_hilo_carry_3) # (VD1_un59_hilo_carry_0 & VD1L2381);
VD1_un59_hilo_add4 = VD1_hilo_36 $ VD1_op2_reged[4] $ !VD1_un59_hilo_add4_carry_eqn;
 
--VD1_un59_hilo_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_4 at LC_X9_Y6_N8
--operation mode is arithmetic
 
VD1_un59_hilo_carry_4_cout_0 = VD1_hilo_36 & VD1_op2_reged[4] # !VD1_un59_hilo_carry_3 # !VD1_hilo_36 & VD1_op2_reged[4] & !VD1_un59_hilo_carry_3;
VD1_un59_hilo_carry_4 = CARRY(VD1_un59_hilo_carry_4_cout_0);
 
--VD1L4381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_4~COUT1_1 at LC_X9_Y6_N8
--operation mode is arithmetic
 
VD1L4381_cout_1 = VD1_hilo_36 & VD1_op2_reged[4] # !VD1L2381 # !VD1_hilo_36 & VD1_op2_reged[4] & !VD1L2381;
VD1L4381 = CARRY(VD1L4381_cout_1);
 
 
--VD1_un1_mul_2_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_mul_2_a at LC_X8_Y6_N0
--operation mode is normal
 
VD1_un1_mul_2_a = VD1_op2_sign_reged & !VD1_hilo[64] & !VD1_eqz_2 & VD1_op1_sign_reged # !VD1_op2_sign_reged & VD1_hilo[64] & !VD1_op1_sign_reged;
 
 
--VD1_addnop292[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop292[0] at LC_X8_Y6_N5
--operation mode is normal
 
VD1_addnop292[0] = VD1_op2_sign_reged & !VD1_eqz_2 & !VD1_eqop2_2_NE & VD1_op1_sign_reged;
 
 
--VD1_addnop290[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop290[0] at LC_X8_Y6_N7
--operation mode is normal
 
VD1_addnop290[0] = !VD1_op2_sign_reged & !VD1_eqz_2 & !VD1_eqnop2_2_NE & VD1_op1_sign_reged;
 
 
--VD1_addnop2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addnop2 at LC_X8_Y6_N9
--operation mode is normal
 
VD1_addnop2_lut_out = !VD1_mul & VD1_addnop292[0] # !VD1_addnop290[0] & VD1_un1_mul_3_a;
VD1_addnop2 = DFFEAS(VD1_addnop2_lut_out, GLOBAL(E1__clk0), VCC, , VD1_addop2_0_sqmuxa_1_i, , , , );
 
 
--VD1_hilo_0_sqmuxa is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_0_sqmuxa at LC_X3_Y14_N3
--operation mode is normal
 
VD1_hilo_0_sqmuxa = VD1_overflow & !VD1_hilo25 & VD1_start & !VD1_rdy;
 
 
--VD1_un1_op2_reged_1_combout[5] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[5] at LC_X12_Y4_N1
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[5] = VD1_eqop2_2_32 & VD1_op2_reged[5] # !VD1_eqop2_2_32 & VD1_nop2_reged[5];
 
 
--VD1_hilo_24_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add4 at LC_X8_Y5_N8
--operation mode is arithmetic
 
VD1_hilo_24_add4_carry_eqn = (!VD1_hilo_24_carry_0 & VD1_hilo_24_carry_3) # (VD1_hilo_24_carry_0 & VD1L384);
VD1_hilo_24_add4 = VD1_un1_op2_reged_1_combout[4] $ VD1_hilo_35 $ !VD1_hilo_24_add4_carry_eqn;
 
--VD1_hilo_24_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_4 at LC_X8_Y5_N8
--operation mode is arithmetic
 
VD1_hilo_24_carry_4_cout_0 = VD1_un1_op2_reged_1_combout[4] & VD1_hilo_35 # !VD1_hilo_24_carry_3 # !VD1_un1_op2_reged_1_combout[4] & VD1_hilo_35 & !VD1_hilo_24_carry_3;
VD1_hilo_24_carry_4 = CARRY(VD1_hilo_24_carry_4_cout_0);
 
--VD1L584 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_4~COUT1_1 at LC_X8_Y5_N8
--operation mode is arithmetic
 
VD1L584_cout_1 = VD1_un1_op2_reged_1_combout[4] & VD1_hilo_35 # !VD1L384 # !VD1_un1_op2_reged_1_combout[4] & VD1_hilo_35 & !VD1L384;
VD1L584 = CARRY(VD1L584_cout_1);
 
 
--VD1_hilo_37_iv_0_3[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[38] at LC_X7_Y7_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_3[38] = VD1_hilo_37_iv_0_a2_0[38] # !VD1_hilo_38 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_37_iv_0_3_a[38];
 
 
--HD1_dout_iv_1_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_5 at LC_X20_Y11_N8
--operation mode is normal
 
HD1_dout_iv_1_5 = FD1_N_18_i_0_s3 & LD2_q_b[5] # !HD1_dout_iv_1_a[5];
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] at LC_X21_Y5_N7
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[16] = QB1_r32_o_16 & QD1_b_o18 & !FB1_r32_o_16 # !QB1_r32_o_16 & QD1_un1_b_o18_2 # QD1_b_o18 & !FB1_r32_o_16;
 
 
--G1_BUS15471_i_m[16] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[16] at LC_X21_Y5_N9
--operation mode is normal
 
G1_BUS15471_i_m[16] = QD1_b_o_1_sqmuxa & !FD1_wb_o_16;
 
 
--FB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_28 at LC_X23_Y16_N2
--operation mode is normal
 
FB1_r32_o_28_lut_out = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_12;
FB1_r32_o_28 = DFFEAS(FB1_r32_o_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] at LC_X19_Y14_N2
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[28] = QD1_un1_b_o18_2 & !QB1_r32_o_28;
 
 
--QD1_b_o_iv_1_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_iv_1_27 at LC_X19_Y14_N8
--operation mode is normal
 
QD1_b_o_iv_1_27 = QD1_b_o_0_sqmuxa & !FD1_wb_o_28 & QD1_b_o_1_sqmuxa # !AB1_r32_o_26 # !QD1_b_o_0_sqmuxa & !FD1_wb_o_28 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] at LC_X20_Y6_N0
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[23] = QB1_r32_o_23 & !FB1_r32_o_23 & QD1_b_o18 # !QB1_r32_o_23 & QD1_un1_b_o18_2 # !FB1_r32_o_23 & QD1_b_o18;
 
 
--G1_BUS15471_i_m[23] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[23] at LC_X20_Y6_N9
--operation mode is normal
 
G1_BUS15471_i_m[23] = !FD1_wb_o_23 & QD1_b_o_1_sqmuxa;
 
 
--C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] is mips_sys:isys|sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] at LC_X21_Y12_N7
--operation mode is normal
 
C1_sclrsclrmips_core_iexec_stage_i_alu_muxb_b_o_iv_a[24] = QD1_un1_b_o18_2 & QD1_b_o18 & !FB1_r32_o_24 # !QB1_r32_o_24 # !QD1_un1_b_o18_2 & QD1_b_o18 & !FB1_r32_o_24;
 
 
--G1_BUS15471_i_m[24] is mips_sys:isys|mips_core:mips_core|BUS15471_i_m[24] at LC_X20_Y12_N3
--operation mode is normal
 
G1_BUS15471_i_m[24] = QD1_b_o_1_sqmuxa & !FD1_wb_o_24;
 
 
--VD1_un134_hilo_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[0] at LC_X5_Y16_N2
--operation mode is arithmetic
 
VD1_un134_hilo_cout[0]_cout_0 = VD1_hilo_1 & VD1_hilo[0];
VD1_un134_hilo_cout[0] = CARRY(VD1_un134_hilo_cout[0]_cout_0);
 
--VD1L9491 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[0]~COUT1_13 at LC_X5_Y16_N2
--operation mode is arithmetic
 
VD1L9491_cout_1 = VD1_hilo_1 & VD1_hilo[0];
VD1L9491 = CARRY(VD1L9491_cout_1);
 
 
--VD1_nop2_reged[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[3] at LC_X12_Y4_N3
--operation mode is arithmetic
 
VD1_nop2_reged[3] = VD1_op2_reged[3] $ (VD1_op2_reged[2] # !VD1_nop2_reged_cout[1]);
 
--VD1_nop2_reged_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[3] at LC_X12_Y4_N3
--operation mode is arithmetic
 
VD1_nop2_reged_cout[3]_cout_0 = VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1_nop2_reged_cout[1];
VD1_nop2_reged_cout[3] = CARRY(VD1_nop2_reged_cout[3]_cout_0);
 
--VD1L7131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[3]~COUT1_2 at LC_X12_Y4_N3
--operation mode is arithmetic
 
VD1L7131_cout_1 = VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1L3131;
VD1L7131 = CARRY(VD1L7131_cout_1);
 
 
--VD1_un50_hilo_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add2 at LC_X10_Y5_N6
--operation mode is arithmetic
 
VD1_un50_hilo_add2_carry_eqn = (!VD1_un50_hilo_carry_0 & VD1_un50_hilo_carry_1) # (VD1_un50_hilo_carry_0 & VD1L5071);
VD1_un50_hilo_add2 = VD1_nop2_reged[2] $ VD1_hilo_34 $ !VD1_un50_hilo_add2_carry_eqn;
 
--VD1_un50_hilo_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_2 at LC_X10_Y5_N6
--operation mode is arithmetic
 
VD1_un50_hilo_carry_2_cout_0 = VD1_nop2_reged[2] & VD1_hilo_34 # !VD1_un50_hilo_carry_1 # !VD1_nop2_reged[2] & VD1_hilo_34 & !VD1_un50_hilo_carry_1;
VD1_un50_hilo_carry_2 = CARRY(VD1_un50_hilo_carry_2_cout_0);
 
--VD1L7071 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_2~COUT1_1 at LC_X10_Y5_N6
--operation mode is arithmetic
 
VD1L7071_cout_1 = VD1_nop2_reged[2] & VD1_hilo_34 # !VD1L5071 # !VD1_nop2_reged[2] & VD1_hilo_34 & !VD1L5071;
VD1L7071 = CARRY(VD1L7071_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[2] at LC_X13_Y4_N1
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[2] = VD1_eqop2_2_32 & VD1_op2_reged[2] # !VD1_eqop2_2_32 & VD1_nop2_reged[2];
 
 
--VD1_hilo_24_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add1 at LC_X8_Y5_N5
--operation mode is arithmetic
 
VD1_hilo_24_add1_carry_eqn = VD1_hilo_24_carry_0;
VD1_hilo_24_add1 = VD1_hilo[32] $ VD1_un1_op2_reged_1_combout[1] $ VD1_hilo_24_add1_carry_eqn;
 
--VD1_hilo_24_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_1 at LC_X8_Y5_N5
--operation mode is arithmetic
 
VD1_hilo_24_carry_1_cout_0 = VD1_hilo[32] & !VD1_un1_op2_reged_1_combout[1] & !VD1_hilo_24_carry_0 # !VD1_hilo[32] & !VD1_hilo_24_carry_0 # !VD1_un1_op2_reged_1_combout[1];
VD1_hilo_24_carry_1 = CARRY(VD1_hilo_24_carry_1_cout_0);
 
--VD1L974 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_1~COUT1_1 at LC_X8_Y5_N5
--operation mode is arithmetic
 
VD1L974_cout_1 = VD1_hilo[32] & !VD1_un1_op2_reged_1_combout[1] & !VD1_hilo_24_carry_0 # !VD1_hilo[32] & !VD1_hilo_24_carry_0 # !VD1_un1_op2_reged_1_combout[1];
VD1L974 = CARRY(VD1L974_cout_1);
 
 
--VD1_hilo_37_iv_0_2_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[34] at LC_X6_Y7_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_2_a[34] = VD1_un50_hilo_add2 & !VD1_un59_hilo_add2 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_un50_hilo_add2 & VD1_hilo_37_iv_0_a2_6_0[37] # !VD1_un59_hilo_add2 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--VD1_un59_hilo_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add3 at LC_X9_Y6_N7
--operation mode is arithmetic
 
VD1_un59_hilo_add3_carry_eqn = (!VD1_un59_hilo_carry_0 & VD1_un59_hilo_carry_2) # (VD1_un59_hilo_carry_0 & VD1L0381);
VD1_un59_hilo_add3 = VD1_op2_reged[3] $ VD1_hilo_35 $ VD1_un59_hilo_add3_carry_eqn;
 
--VD1_un59_hilo_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_3 at LC_X9_Y6_N7
--operation mode is arithmetic
 
VD1_un59_hilo_carry_3_cout_0 = VD1_op2_reged[3] & !VD1_hilo_35 & !VD1_un59_hilo_carry_2 # !VD1_op2_reged[3] & !VD1_un59_hilo_carry_2 # !VD1_hilo_35;
VD1_un59_hilo_carry_3 = CARRY(VD1_un59_hilo_carry_3_cout_0);
 
--VD1L2381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_3~COUT1_1 at LC_X9_Y6_N7
--operation mode is arithmetic
 
VD1L2381_cout_1 = VD1_op2_reged[3] & !VD1_hilo_35 & !VD1L0381 # !VD1_op2_reged[3] & !VD1L0381 # !VD1_hilo_35;
VD1L2381 = CARRY(VD1L2381_cout_1);
 
 
--VD1_hilo_37_iv_0_o3_1_a[34] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_a[34] at LC_X3_Y9_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_1_a[34] = VD1_hilo_35 & VD1_hilo_0_sqmuxa & !VD1_hilo_2 # !VD1_hilo_35 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_0_sqmuxa & !VD1_hilo_2;
 
 
--VD1_hilo_37_iv_0_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[3] at LC_X6_Y16_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_a[3] = VD1_add1 & !VD1_un134_hilo_combout[3] # !VD1_add1 & !VD1_hilo_3;
 
 
--VD1_hilo_33_i_m[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[35] at LC_X3_Y6_N1
--operation mode is normal
 
VD1_hilo_33_i_m[35] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[35] # !VD1_hilo_33_1[64] & !VD1_hilo_35;
 
 
--VD1_hilo_37_iv_2_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[35] at LC_X8_Y5_N1
--operation mode is normal
 
VD1_hilo_37_iv_2_a[35] = VD1_hilo_24_add3 & VD1_hilo_0_sqmuxa & !VD1_hilo_3 # !VD1_hilo_24_add3 & VD1_hilo_2_sqmuxa # VD1_hilo_0_sqmuxa & !VD1_hilo_3;
 
 
--VD1_hilo_22_Z[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[35] at LC_X6_Y6_N9
--operation mode is normal
 
VD1_hilo_22_Z[35] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[35] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[35] # !VD1_sign & !VD1_hilo_22_a[35];
 
 
--UD1_shift_out_79_a[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[3] at LC_X16_Y18_N5
--operation mode is normal
 
UD1_shift_out_79_a[3] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_11;
 
 
--YB1_dmem_ctl_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_1_a[1] at LC_X29_Y18_N8
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_1_a[1] = KE1_q_a[7] & KE1_q_a[4] & !KE1_q_a[3] & KE1_q_a[2] # !KE1_q_a[4] & KE1_q_a[3] $ !KE1_q_a[2];
 
 
--UD1_shift_out_87_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[16] at LC_X9_Y18_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[16] = PD1_a_o_1 & !VD1_b_o_iv_22 # !PD1_a_o_1 & !VD1_b_o_iv_20;
 
 
--UD1_shift_out_80[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[16] at LC_X9_Y18_N2
--operation mode is normal
 
UD1_shift_out_80[16] = PD1_a_o_2 & UD1_shift_out_80_a[16] & VD1_b_o_iv_21 # !UD1_shift_out_80_a[16] & VD1_b_o_iv_23 # !PD1_a_o_2 & !UD1_shift_out_80_a[16];
 
 
--UD1_shift_out_85_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[16] at LC_X9_Y18_N7
--operation mode is normal
 
UD1_shift_out_85_d_a[16] = PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_0 & !VD1_b_o_iv_14;
 
 
--UD1_shift_out_52[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[28] at LC_X11_Y17_N2
--operation mode is normal
 
UD1_shift_out_52[28] = PD1_a_o_1 & !UD1_shift_out_52_a[28] # !PD1_a_o_1 & UD1_shift_out_52_a[28] & VD1_b_o_iv_12 # !UD1_shift_out_52_a[28] & VD1_b_o_iv_11;
 
 
--UD1_shift_out_92_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[8] at LC_X14_Y18_N9
--operation mode is normal
 
UD1_shift_out_92_d_a[8] = VD1_b_o_iv_0 & !PD1_a_o_0 & !PD1_a_o_1 & !PD1_a_o_2;
 
 
--UD1_shift_out_77[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[16] at LC_X11_Y18_N4
--operation mode is normal
 
UD1_shift_out_77[16] = PD1_a_o_1 & UD1_shift_out_85_d[8] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[8] # !PD1_a_o_2 & !UD1_shift_out_77_a[16];
 
 
--VD1_hilo_37_iv_0_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[16] at LC_X3_Y13_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_a[16] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_17 & !VD1_hilo_2_sqmuxa # !VD1_hilo_15 # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_15;
 
 
--VD1_hilo_37_iv_0_0[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[16] at LC_X3_Y13_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_0[16] = VD1_hilo_16 & VD1_hilo_37_iv_0_o5[0] # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[16] # !VD1_hilo_16 & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[16];
 
 
--VD1_hilo_37_iv_2[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[48] at LC_X3_Y4_N5
--operation mode is normal
 
VD1_hilo_37_iv_2[48] = VD1_hilo_37_iv_2_a[48] # VD1_hilo_33_i_m[48] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[48];
 
 
--VD1_hilo_37_iv_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[48] at LC_X4_Y8_N3
--operation mode is normal
 
VD1_hilo_37_iv_a[48] = RC1_alu_func_o_0 & !PD1_a_o_16 # !RC1_alu_func_o_0 & !VD1_hilo_48;
 
 
--PD1_a_o_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[16] at LC_X21_Y3_N9
--operation mode is normal
 
PD1_a_o_a[16] = SC1_muxa_ctl_o_1 & !FB1_r32_o_16 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_16;
 
 
--PD1_a_o_3_Z[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[16] at LC_X25_Y4_N9
--operation mode is normal
 
SD1_r32_o_16_qfbk = SD1_r32_o_16;
PD1_a_o_3_Z[16] = PD1_a_o_3_s[0] & SD1_r32_o_16_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[16];
 
--SD1_r32_o_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_16 at LC_X25_Y4_N9
--operation mode is normal
 
SD1_r32_o_16 = DFFEAS(PD1_a_o_3_Z[16], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_16, , , VCC);
 
 
--TD1_un1_b_1_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[16] at LC_X15_Y5_N5
--operation mode is normal
 
TD1_un1_b_1_combout[16] = TD1_sum13_0_a2 $ !VD1_b_o_iv_16;
 
 
--UD1_shift_out_87_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[17] at LC_X7_Y17_N2
--operation mode is normal
 
UD1_shift_out_87_d_a[17] = PD1_a_o_1 & !VD1_b_o_iv_23 # !PD1_a_o_1 & !VD1_b_o_iv_21;
 
 
--UD1_shift_out_80[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[17] at LC_X7_Y17_N6
--operation mode is normal
 
UD1_shift_out_80[17] = PD1_a_o_2 & UD1_shift_out_80_a[17] & VD1_b_o_iv_22 # !UD1_shift_out_80_a[17] & VD1_b_o_iv_24 # !PD1_a_o_2 & !UD1_shift_out_80_a[17];
 
 
--UD1_shift_out_77_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[23] at LC_X11_Y12_N2
--operation mode is normal
 
UD1_shift_out_77_a[23] = PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_15;
 
 
--UD1_shift_out_52[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[29] at LC_X20_Y15_N4
--operation mode is normal
 
UD1_shift_out_52[29] = PD1_a_o_1 & !UD1_shift_out_52_a[29] # !PD1_a_o_1 & UD1_shift_out_52_a[29] & VD1_b_o_iv_13 # !UD1_shift_out_52_a[29] & VD1_b_o_iv_12;
 
 
--UD1_shift_out_83_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[17] at LC_X14_Y12_N0
--operation mode is normal
 
UD1_shift_out_83_a[17] = PD1_a_o_2 & PD1_a_o_1 & !PD1_a_o_0 # !UD1_shift_out587 # !PD1_a_o_2 & PD1_a_o_1 $ UD1_shift_out587;
 
 
--UD1_shift_out_63[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[17] at LC_X14_Y18_N4
--operation mode is normal
 
UD1_shift_out_63[17] = UD1_shift_out_63_a[17] & PD1_a_o_0 & VD1_b_o_iv_0 # !PD1_a_o_0 & VD1_b_o_iv_1;
 
 
--UD1_shift_out_63[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[25] at LC_X14_Y16_N3
--operation mode is normal
 
UD1_shift_out_63[25] = PD1_a_o_2 & UD1_shift_out_45[29] # !PD1_a_o_2 & UD1_shift_out_48[29];
 
 
--VD1_hilo_37_iv_0_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[17] at LC_X3_Y16_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[17] = VD1_hilo_2_sqmuxa & !VD1_hilo_16 & !VD1_hilo_18 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2_sqmuxa & !VD1_hilo_18 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[17] at LC_X3_Y16_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[17] = VD1_hilo_17 & VD1_hilo_37_iv_0_o5[0] # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[17] # !VD1_hilo_17 & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[17];
 
 
--VD1_hilo_37_iv_2[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[49] at LC_X3_Y8_N5
--operation mode is normal
 
VD1_hilo_37_iv_2[49] = VD1_hilo_33_i_m[49] # VD1_hilo_37_iv_2_a[49] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[49];
 
 
--VD1_hilo_37_iv_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[49] at LC_X3_Y8_N7
--operation mode is normal
 
VD1_hilo_37_iv_a[49] = RC1_alu_func_o_0 & !PD1_a_o_17 # !RC1_alu_func_o_0 & !VD1_hilo_49;
 
 
--PD1_a_o_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[17] at LC_X22_Y5_N1
--operation mode is normal
 
PD1_a_o_a[17] = SC1_muxa_ctl_o_1 & !FB1_r32_o_17 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_17;
 
 
--PD1_a_o_3_Z[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[17] at LC_X22_Y5_N8
--operation mode is normal
 
SD1_r32_o_17_qfbk = SD1_r32_o_17;
PD1_a_o_3_Z[17] = PD1_a_o_3_s[0] & SD1_r32_o_17_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[17];
 
--SD1_r32_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_17 at LC_X22_Y5_N8
--operation mode is normal
 
SD1_r32_o_17 = DFFEAS(PD1_a_o_3_Z[17], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_17, , , VCC);
 
 
--TD1_un1_b_1_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[17] at LC_X13_Y8_N5
--operation mode is normal
 
TD1_un1_b_1_combout[17] = VD1_b_o_iv_17 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[14] at LC_X20_Y17_N4
--operation mode is normal
 
UD1_shift_out_87_d_a[14] = PD1_a_o_1 & !VD1_b_o_iv_20 # !PD1_a_o_1 & !VD1_b_o_iv_18;
 
 
--UD1_shift_out_80[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[14] at LC_X20_Y17_N9
--operation mode is normal
 
UD1_shift_out_80[14] = PD1_a_o_2 & UD1_shift_out_80_a[14] & VD1_b_o_iv_19 # !UD1_shift_out_80_a[14] & VD1_b_o_iv_21 # !PD1_a_o_2 & !UD1_shift_out_80_a[14];
 
 
--UD1_shift_out_85_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[14] at LC_X11_Y17_N6
--operation mode is normal
 
UD1_shift_out_85_d_a[14] = PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_0 & !VD1_b_o_iv_12;
 
 
--UD1_shift_out_48[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[30] at LC_X16_Y17_N9
--operation mode is normal
 
UD1_shift_out_48[30] = PD1_a_o_1 & !UD1_shift_out_48_a[30] # !PD1_a_o_1 & UD1_shift_out_48_a[30] & VD1_b_o_iv_10 # !UD1_shift_out_48_a[30] & VD1_b_o_iv_9;
 
 
--UD1_shift_out_74_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[14] at LC_X13_Y17_N7
--operation mode is normal
 
UD1_shift_out_74_a[14] = !PD1_a_o_3 & !PD1_a_o_2 & VD1_b_o_iv_30 $ VD1_b_o_iv_31;
 
 
--UD1_shift_out_83_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[14] at LC_X13_Y17_N8
--operation mode is normal
 
UD1_shift_out_83_a[14] = !PD1_a_o_1 & PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
 
 
--UD1_shift_out_45[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[30] at LC_X12_Y16_N0
--operation mode is normal
 
UD1_shift_out_45[30] = PD1_a_o_1 & !UD1_shift_out_45_a[30] # !PD1_a_o_1 & UD1_shift_out_45_a[30] & VD1_b_o_iv_6 # !UD1_shift_out_45_a[30] & VD1_b_o_iv_5;
 
 
--UD1_shift_out_79[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[14] at LC_X15_Y18_N0
--operation mode is normal
 
UD1_shift_out_79[14] = PD1_a_o_1 & UD1_shift_out_79_a[14] & VD1_b_o_iv_24 # !UD1_shift_out_79_a[14] & VD1_b_o_iv_25 # !PD1_a_o_1 & !UD1_shift_out_79_a[14];
 
 
--VD1_hilo_37_iv_0_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[14] at LC_X4_Y13_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_a[14] = VD1_hilo_15 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_13 # !VD1_hilo_2_sqmuxa # !VD1_hilo_15 & !VD1_hilo_13 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[14] at LC_X4_Y13_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_0[14] = VD1_hilo_14 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[14] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_14 & VD1_un134_hilo_combout[14] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_2[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[46] at LC_X3_Y7_N5
--operation mode is normal
 
VD1_hilo_37_iv_2[46] = VD1_hilo_37_iv_2_a[46] # VD1_hilo_33_i_m[46] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[46];
 
 
--VD1_hilo_37_iv_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[46] at LC_X4_Y8_N8
--operation mode is normal
 
VD1_hilo_37_iv_a[46] = RC1_alu_func_o_0 & !PD1_a_o_14 # !RC1_alu_func_o_0 & !VD1_hilo_46;
 
 
--PD1_a_o_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[14] at LC_X25_Y11_N5
--operation mode is normal
 
PD1_a_o_a[14] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_14 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_14;
 
 
--PD1_a_o_3_Z[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[14] at LC_X25_Y11_N8
--operation mode is normal
 
SD1_r32_o_14_qfbk = SD1_r32_o_14;
PD1_a_o_3_Z[14] = PD1_a_o_3_s[0] & SD1_r32_o_14_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[14];
 
--SD1_r32_o_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_14 at LC_X25_Y11_N8
--operation mode is normal
 
SD1_r32_o_14 = DFFEAS(PD1_a_o_3_Z[14], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_14, , , VCC);
 
 
--TD1_un1_b_1_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[14] at LC_X14_Y5_N5
--operation mode is normal
 
TD1_un1_b_1_combout[14] = VD1_b_o_iv_14 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[15] at LC_X13_Y16_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[15] = PD1_a_o_1 & !VD1_b_o_iv_21 # !PD1_a_o_1 & !VD1_b_o_iv_19;
 
 
--UD1_shift_out_80[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[15] at LC_X13_Y16_N3
--operation mode is normal
 
UD1_shift_out_80[15] = PD1_a_o_2 & UD1_shift_out_80_a[15] & VD1_b_o_iv_20 # !UD1_shift_out_80_a[15] & VD1_b_o_iv_22 # !PD1_a_o_2 & !UD1_shift_out_80_a[15];
 
 
--UD1_shift_out_77_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[21] at LC_X19_Y7_N9
--operation mode is normal
 
UD1_shift_out_77_a[21] = PD1_a_o_0 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_13;
 
 
--UD1_shift_out_48[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[31] at LC_X11_Y16_N7
--operation mode is normal
 
UD1_shift_out_48[31] = PD1_a_o_1 & !UD1_shift_out_48_a[31] # !PD1_a_o_1 & UD1_shift_out_48_a[31] & VD1_b_o_iv_11 # !UD1_shift_out_48_a[31] & VD1_b_o_iv_10;
 
 
--UD1_shift_out_83_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[15] at LC_X14_Y17_N1
--operation mode is normal
 
UD1_shift_out_83_a[15] = VD1_b_o_iv_31 & !PD1_a_o_0 & !PD1_a_o_1;
 
 
--UD1_shift_out_45[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[31] at LC_X12_Y16_N9
--operation mode is normal
 
UD1_shift_out_45[31] = PD1_a_o_1 & !UD1_shift_out_45_a[31] # !PD1_a_o_1 & UD1_shift_out_45_a[31] & VD1_b_o_iv_7 # !UD1_shift_out_45_a[31] & VD1_b_o_iv_6;
 
 
--VD1_hilo_37_iv_0_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[15] at LC_X3_Y13_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a[15] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_16 & !VD1_hilo_2_sqmuxa # !VD1_hilo_14 # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_14;
 
 
--VD1_hilo_37_iv_0_0[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[15] at LC_X3_Y13_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_0[15] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_15 # VD1_un134_hilo_combout[15] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_37_iv_0_o5[0] & VD1_un134_hilo_combout[15] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_2[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[47] at LC_X2_Y7_N5
--operation mode is normal
 
VD1_hilo_37_iv_2[47] = VD1_hilo_37_iv_2_a[47] # VD1_hilo_33_i_m[47] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[47];
 
 
--VD1_hilo_37_iv_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[47] at LC_X4_Y8_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[47] = RC1_alu_func_o_0 & !PD1_a_o_15 # !RC1_alu_func_o_0 & !VD1_hilo_47;
 
 
--PD1_a_o_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[15] at LC_X19_Y6_N2
--operation mode is normal
 
PD1_a_o_a[15] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_15 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_15;
 
 
--PD1_a_o_3_Z[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[15] at LC_X19_Y6_N7
--operation mode is normal
 
SD1_r32_o_15_qfbk = SD1_r32_o_15;
PD1_a_o_3_Z[15] = PD1_a_o_3_s[0] & SD1_r32_o_15_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[15];
 
--SD1_r32_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_15 at LC_X19_Y6_N7
--operation mode is normal
 
SD1_r32_o_15 = DFFEAS(PD1_a_o_3_Z[15], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_15, , , VCC);
 
 
--TD1_un1_b_1_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[15] at LC_X11_Y8_N3
--operation mode is normal
 
TD1_un1_b_1_combout[15] = TD1_sum13_0_a2 $ !VD1_b_o_iv_15;
 
 
--UD1_shift_out_68[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[31] at LC_X11_Y14_N3
--operation mode is normal
 
UD1_shift_out_68[31] = PD1_a_o_0 & VD1_b_o_iv_28 # !PD1_a_o_0 & VD1_b_o_iv_29;
 
 
--UD1_shift_out_75[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[31] at LC_X12_Y14_N3
--operation mode is normal
 
UD1_shift_out_75[31] = PD1_a_o_3 & !UD1_shift_out_75_a[31] # !PD1_a_o_3 & UD1_shift_out_75_a[31] & UD1_shift_out_52[31] # !UD1_shift_out_75_a[31] & UD1_shift_out_48[31];
 
 
--UD1_shift_out_77[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[31] at LC_X11_Y14_N9
--operation mode is normal
 
UD1_shift_out_77[31] = PD1_a_o_2 & !UD1_shift_out_85_a[23] # !PD1_a_o_2 & UD1_shift_out_85_a[23] & UD1_shift_out_68[25] # !UD1_shift_out_85_a[23] & UD1_shift_out_68[23];
 
 
--VD1_hilo_37_iv_0_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[31] at LC_X6_Y13_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a[31] = !VD1_hilo_37_iv_0_2[31] & !VD1_hilo_37_iv_0_1[31] & !VD1_hilo_30 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_2[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[63] at LC_X8_Y8_N6
--operation mode is normal
 
VD1_hilo_37_iv_2[63] = VD1_hilo_22_i_m[63] # VD1_hilo_37_iv_2_a[63] # VD1_hilo_3_sqmuxa & !VD1_hilo_33_3[63];
 
 
--VD1_hilo_37_iv_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[63] at LC_X8_Y8_N7
--operation mode is normal
 
VD1_hilo_37_iv_a[63] = RC1_alu_func_o_0 & !PD1_a_o_31 # !RC1_alu_func_o_0 & !VD1_hilo_63;
 
 
--TD1_un1_b_1_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[31] at LC_X12_Y6_N5
--operation mode is normal
 
TD1_un1_b_1_combout[31] = VD1_b_o_iv_31 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[8] at LC_X11_Y17_N1
--operation mode is normal
 
UD1_shift_out_87_d[8] = PD1_a_o_0 & UD1_shift_out_80[8] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[8];
 
 
--UD1_shift_out_85_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[8] at LC_X11_Y18_N0
--operation mode is normal
 
UD1_shift_out_85_d[8] = PD1_a_o_2 & UD1_shift_out_45[28] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[8];
 
 
--UD1_shift_out_86_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[8] at LC_X16_Y14_N8
--operation mode is normal
 
UD1_shift_out_86_a[8] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_47[0] # !PD1_a_o_2 & !UD1_shift_out_79[16] # !UD1_shift_out587 & !UD1_shift_out_47[0];
 
 
--UD1_shift_out_74[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[8] at LC_X16_Y14_N9
--operation mode is normal
 
UD1_shift_out_74[8] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[16] # !UD1_shift_out_74_a[7] & UD1_shift_out_79[20];
 
 
--UD1_shift_out_91[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[8] at LC_X16_Y15_N8
--operation mode is normal
 
UD1_shift_out_91[8] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[8] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[8];
 
 
--PD1_a_o_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_8 at LC_X19_Y8_N8
--operation mode is normal
 
PD1_a_o_8 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[8] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[8];
 
 
--TD1_m16_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m16_a at LC_X13_Y14_N2
--operation mode is normal
 
TD1_m16_a = VD1_b_o_iv_8 & PD1_a_o_8 & !TD1_m9 # !VD1_b_o_iv_8 & !PD1_a_o_8 # !TD1_m5;
 
 
--TD1_un1_a_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add8 at LC_X12_Y9_N3
--operation mode is arithmetic
 
TD1_un1_a_add8_carry_eqn = (!TD1_un1_a_carry_4 & TD1_un1_a_carry_7) # (TD1_un1_a_carry_4 & TD1L525);
TD1_un1_a_add8 = PD1_a_o_8 $ TD1_un1_b_1_combout[8] $ !TD1_un1_a_add8_carry_eqn;
 
--TD1_un1_a_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_8 at LC_X12_Y9_N3
--operation mode is arithmetic
 
TD1_un1_a_carry_8_cout_0 = PD1_a_o_8 & TD1_un1_b_1_combout[8] # !TD1_un1_a_carry_7 # !PD1_a_o_8 & TD1_un1_b_1_combout[8] & !TD1_un1_a_carry_7;
TD1_un1_a_carry_8 = CARRY(TD1_un1_a_carry_8_cout_0);
 
--TD1L725 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_8~COUT1_1 at LC_X12_Y9_N3
--operation mode is arithmetic
 
TD1L725_cout_1 = PD1_a_o_8 & TD1_un1_b_1_combout[8] # !TD1L525 # !PD1_a_o_8 & TD1_un1_b_1_combout[8] & !TD1L525;
TD1L725 = CARRY(TD1L725_cout_1);
 
 
--UD1_shift_out_87_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[9] at LC_X12_Y18_N1
--operation mode is normal
 
UD1_shift_out_87_d[9] = PD1_a_o_0 & UD1_shift_out_80[9] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[9];
 
 
--UD1_shift_out_85_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[9] at LC_X14_Y19_N5
--operation mode is normal
 
UD1_shift_out_85_d[9] = PD1_a_o_2 & UD1_shift_out_45[29] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[9];
 
 
--UD1_shift_out_74[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[9] at LC_X14_Y13_N3
--operation mode is normal
 
UD1_shift_out_74[9] = PD1_a_o_3 & !UD1_shift_out_74_a[9] # !PD1_a_o_3 & PD1_a_o_2 & !UD1_shift_out_74_a[9] # !PD1_a_o_2 & UD1_shift_out_79[17];
 
 
--UD1_shift_out_86_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[9] at LC_X14_Y13_N7
--operation mode is normal
 
UD1_shift_out_86_a[9] = PD1_a_o_2 & !UD1_shift_out_79[13] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[17] # !UD1_shift_out587 & !UD1_shift_out_79[13];
 
 
--UD1_shift_out_92_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[9] at LC_X14_Y18_N8
--operation mode is normal
 
UD1_shift_out_92_d_a[9] = !PD1_a_o_4 & PD1_a_o_0 & VD1_b_o_iv_0 # !PD1_a_o_0 & VD1_b_o_iv_1;
 
 
--UD1_shift_out_91[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[9] at LC_X13_Y13_N2
--operation mode is normal
 
UD1_shift_out_91[9] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[9] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[9];
 
 
--VD1_hilo_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_9 at LC_X4_Y17_N6
--operation mode is normal
 
VD1_hilo_9_lut_out = VD1_hilo_37_iv_0_0[9] # PD1_a_o_9 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[9];
VD1_hilo_9 = DFFEAS(VD1_hilo_9_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_41 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_41 at LC_X9_Y9_N4
--operation mode is normal
 
VD1_hilo_41_lut_out = !VD1_hilo_37_iv_2[41] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[41] # !VD1_hilo25;
VD1_hilo_41 = DFFEAS(VD1_hilo_41_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_9 at LC_X19_Y10_N4
--operation mode is normal
 
PD1_a_o_9 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[9] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[9];
 
 
--TD1_m117_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m117_a at LC_X13_Y14_N7
--operation mode is normal
 
TD1_m117_a = PD1_a_o_9 & VD1_b_o_iv_9 & !TD1_m9 # !VD1_b_o_iv_9 & !TD1_m5 # !PD1_a_o_9 & !VD1_b_o_iv_9;
 
 
--VD1_hilo_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_10 at LC_X4_Y17_N9
--operation mode is normal
 
VD1_hilo_10_lut_out = VD1_hilo_37_iv_0_0[10] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_10 # !VD1_hilo_37_iv_0_a[10];
VD1_hilo_10 = DFFEAS(VD1_hilo_10_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_42 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_42 at LC_X9_Y9_N9
--operation mode is normal
 
VD1_hilo_42_lut_out = !VD1_hilo_37_iv_2[42] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[42] # !VD1_hilo25;
VD1_hilo_42 = DFFEAS(VD1_hilo_42_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--TD1_alu_out_7_0_0_m4_0[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_7_0_0_m4_0[10] at LC_X8_Y14_N2
--operation mode is normal
 
TD1_alu_out_7_0_0_m4_0[10] = VD1_b_o_iv_10 & TD1_alu_out_7_0_0_o3_0 & TD1_alu_out_0_a3[28] # !VD1_b_o_iv_10 & TD1_alu_out_7_0_0_m4_0_a[3];
 
 
--TD1_alu_out_0_a2_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[10] at LC_X7_Y14_N2
--operation mode is normal
 
TD1_alu_out_0_a2_a[10] = VD1_b_o_iv_10 & !TD1_m107 # !VD1_b_o_iv_10 & !TD1_alu_out_0_a3[28];
 
 
--PD1_a_o_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[10] at LC_X19_Y4_N5
--operation mode is normal
 
PD1_a_o_a[10] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_10 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_10;
 
 
--PD1_a_o_3_Z[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[10] at LC_X19_Y12_N1
--operation mode is normal
 
SD1_r32_o_10_qfbk = SD1_r32_o_10;
PD1_a_o_3_Z[10] = PD1_a_o_3_s[0] & SD1_r32_o_10_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[10];
 
--SD1_r32_o_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_10 at LC_X19_Y12_N1
--operation mode is normal
 
SD1_r32_o_10 = DFFEAS(PD1_a_o_3_Z[10], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_10, , , VCC);
 
 
--TD1_un1_b_1_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[9] at LC_X12_Y15_N8
--operation mode is normal
 
TD1_un1_b_1_combout[9] = VD1_b_o_iv_9 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87[10] at LC_X16_Y18_N9
--operation mode is normal
 
UD1_shift_out_87[10] = PD1_a_o_0 & UD1_shift_out_87_d[10] # !PD1_a_o_0 & PD1_a_o_2 & UD1_shift_out_87_d[10] # !PD1_a_o_2 & VD1_b_o_iv_12;
 
 
--UD1_shift_out_89_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[10] at LC_X11_Y18_N1
--operation mode is normal
 
UD1_shift_out_89_a[10] = PD1_a_o_2 & !UD1_shift_out_85_d[10] # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d[10] # !PD1_a_o_1 & !VD1_b_o_iv_9;
 
 
--UD1_shift_out_91[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[10] at LC_X14_Y17_N3
--operation mode is normal
 
UD1_shift_out_91[10] = UD1_shift_out_sn_m17_0 & !UD1_shift_out_91_a[10] # !UD1_shift_out_sn_m17_0 & UD1_shift_out_76[10];
 
 
--UD1_shift_out_92_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_a[10] at LC_X19_Y16_N4
--operation mode is normal
 
UD1_shift_out_92_a[10] = UD1_shift_out586 & UD1_shift_out_77[10] & !PD1_a_o_4 # !UD1_shift_out586 & UD1_shift_out_86[10];
 
 
--UD1_shift_out_87_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[11] at LC_X13_Y18_N8
--operation mode is normal
 
UD1_shift_out_87_d[11] = PD1_a_o_0 & UD1_shift_out_80[11] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[11];
 
 
--UD1_shift_out_85_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[11] at LC_X11_Y16_N3
--operation mode is normal
 
UD1_shift_out_85_d[11] = PD1_a_o_2 & UD1_shift_out_45[31] # !PD1_a_o_2 & !UD1_shift_out_85_d_a[11];
 
 
--UD1_shift_out_74[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[11] at LC_X15_Y17_N6
--operation mode is normal
 
UD1_shift_out_74[11] = PD1_a_o_3 & VD1_b_o_iv_31 # !PD1_a_o_3 & PD1_a_o_2 & VD1_b_o_iv_31 # !PD1_a_o_2 & UD1_shift_out_79[19];
 
 
--UD1_shift_out_86_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[11] at LC_X15_Y17_N4
--operation mode is normal
 
UD1_shift_out_86_a[11] = PD1_a_o_2 & !UD1_shift_out_79[15] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[19] # !UD1_shift_out587 & !UD1_shift_out_79[15];
 
 
--UD1_shift_out_77[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[11] at LC_X15_Y19_N5
--operation mode is normal
 
UD1_shift_out_77[11] = !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_85_d_a[5] # !PD1_a_o_1 & UD1_shift_out_68[5];
 
 
--UD1_shift_out_91[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91[11] at LC_X15_Y16_N2
--operation mode is normal
 
UD1_shift_out_91[11] = UD1_shift_out_sn_m17_0 & UD1_shift_out_88[11] # !UD1_shift_out_sn_m17_0 & UD1_shift_out587 & UD1_shift_out_91_a[11];
 
 
--VD1_hilo_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_11 at LC_X4_Y17_N2
--operation mode is normal
 
VD1_hilo_11_lut_out = VD1_hilo_37_iv_0_0[11] # PD1_a_o_11 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[11];
VD1_hilo_11 = DFFEAS(VD1_hilo_11_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_43 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_43 at LC_X4_Y8_N2
--operation mode is normal
 
VD1_hilo_43_lut_out = !VD1_hilo_37_iv_2[43] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[43] # !VD1_hilo25;
VD1_hilo_43 = DFFEAS(VD1_hilo_43_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_11 at LC_X22_Y10_N9
--operation mode is normal
 
PD1_a_o_11 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[11] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[11];
 
 
--TD1_m21_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m21_a at LC_X13_Y14_N8
--operation mode is normal
 
TD1_m21_a = VD1_b_o_iv_11 & PD1_a_o_11 & !TD1_m9 # !VD1_b_o_iv_11 & !TD1_m5 # !PD1_a_o_11;
 
 
--TD1_un1_a_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add11 at LC_X12_Y9_N6
--operation mode is arithmetic
 
TD1_un1_a_add11_carry_eqn = (!TD1_un1_a_carry_9 & TD1_un1_a_carry_10) # (TD1_un1_a_carry_9 & TD1L035);
TD1_un1_a_add11 = PD1_a_o_11 $ TD1_un1_b_1_combout[11] $ TD1_un1_a_add11_carry_eqn;
 
--TD1_un1_a_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_11 at LC_X12_Y9_N6
--operation mode is arithmetic
 
TD1_un1_a_carry_11_cout_0 = PD1_a_o_11 & !TD1_un1_b_1_combout[11] & !TD1_un1_a_carry_10 # !PD1_a_o_11 & !TD1_un1_a_carry_10 # !TD1_un1_b_1_combout[11];
TD1_un1_a_carry_11 = CARRY(TD1_un1_a_carry_11_cout_0);
 
--TD1L235 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_11~COUT1_1 at LC_X12_Y9_N6
--operation mode is arithmetic
 
TD1L235_cout_1 = PD1_a_o_11 & !TD1_un1_b_1_combout[11] & !TD1L035 # !PD1_a_o_11 & !TD1L035 # !TD1_un1_b_1_combout[11];
TD1L235 = CARRY(TD1L235_cout_1);
 
 
--UD1_shift_out_87_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[21] at LC_X7_Y18_N2
--operation mode is normal
 
UD1_shift_out_87_d_a[21] = PD1_a_o_1 & !VD1_b_o_iv_27 # !PD1_a_o_1 & !VD1_b_o_iv_25;
 
 
--UD1_shift_out_80[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[21] at LC_X7_Y18_N8
--operation mode is normal
 
UD1_shift_out_80[21] = UD1_shift_out_80_a[21] & PD1_a_o_2 & VD1_b_o_iv_26 # !UD1_shift_out_80_a[21] & VD1_b_o_iv_28 # !PD1_a_o_2;
 
 
--UD1_shift_out_77_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[27] at LC_X14_Y12_N9
--operation mode is normal
 
UD1_shift_out_77_a[27] = PD1_a_o_0 & !VD1_b_o_iv_18 # !PD1_a_o_0 & !VD1_b_o_iv_19;
 
 
--UD1_shift_out_54[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[29] at LC_X19_Y18_N9
--operation mode is normal
 
UD1_shift_out_54[29] = PD1_a_o_1 & !UD1_shift_out_54_a[29] # !PD1_a_o_1 & UD1_shift_out_54_a[29] & VD1_b_o_iv_17 # !UD1_shift_out_54_a[29] & VD1_b_o_iv_16;
 
 
--UD1_shift_out_79[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[21] at LC_X14_Y10_N0
--operation mode is normal
 
UD1_shift_out_79[21] = PD1_a_o_1 & UD1_shift_out_79_a[21] & VD1_b_o_iv_31 # !UD1_shift_out_79_a[21] & UD1_shift_out_36_0 # !PD1_a_o_1 & !UD1_shift_out_79_a[21];
 
 
--UD1_shift_out_77[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[21] at LC_X14_Y11_N7
--operation mode is normal
 
UD1_shift_out_77[21] = PD1_a_o_1 & UD1_shift_out_85_d[13] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[13] # !PD1_a_o_2 & !UD1_shift_out_77_a[21];
 
 
--VD1_hilo_37_iv_0_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[21] at LC_X4_Y14_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[21] = VD1_hilo_20 & !VD1_hilo_2_sqmuxa & !VD1_hilo_22 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_20 & !VD1_hilo_22 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[21] at LC_X4_Y15_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_0[21] = VD1_un134_hilo_combout[21] & VD1_hilo_37_iv_0_a3_0[0] # VD1_hilo_37_iv_0_o5[0] & VD1_hilo_21 # !VD1_un134_hilo_combout[21] & VD1_hilo_37_iv_0_o5[0] & VD1_hilo_21;
 
 
--VD1_hilo_37_iv_2[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[53] at LC_X6_Y4_N8
--operation mode is normal
 
VD1_hilo_37_iv_2[53] = VD1_hilo_37_iv_2_a[53] # VD1_hilo_33_i_m[53] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[53];
 
 
--VD1_hilo_37_iv_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[53] at LC_X5_Y8_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[53] = RC1_alu_func_o_0 & !PD1_a_o_21 # !RC1_alu_func_o_0 & !VD1_hilo_53;
 
 
--PD1_a_o_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[21] at LC_X22_Y9_N3
--operation mode is normal
 
PD1_a_o_a[21] = SC1_muxa_ctl_o_1 & !FB1_r32_o_21 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_21;
 
 
--PD1_a_o_3_Z[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[21] at LC_X22_Y9_N7
--operation mode is normal
 
SD1_r32_o_21_qfbk = SD1_r32_o_21;
PD1_a_o_3_Z[21] = PD1_a_o_3_s[0] & SD1_r32_o_21_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[21];
 
--SD1_r32_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_21 at LC_X22_Y9_N7
--operation mode is normal
 
SD1_r32_o_21 = DFFEAS(PD1_a_o_3_Z[21], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_21, , , VCC);
 
 
--TD1_un1_b_1_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[21] at LC_X11_Y8_N2
--operation mode is normal
 
TD1_un1_b_1_combout[21] = TD1_sum13_0_a2 $ !VD1_b_o_iv_21;
 
 
--UD1_shift_out_87_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[20] at LC_X6_Y18_N5
--operation mode is normal
 
UD1_shift_out_87_d_a[20] = PD1_a_o_1 & !VD1_b_o_iv_26 # !PD1_a_o_1 & !VD1_b_o_iv_24;
 
 
--UD1_shift_out_80[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[20] at LC_X6_Y18_N3
--operation mode is normal
 
UD1_shift_out_80[20] = PD1_a_o_2 & UD1_shift_out_80_a[20] & VD1_b_o_iv_25 # !UD1_shift_out_80_a[20] & VD1_b_o_iv_27 # !PD1_a_o_2 & !UD1_shift_out_80_a[20];
 
 
--UD1_shift_out_77_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[26] at LC_X21_Y16_N7
--operation mode is normal
 
UD1_shift_out_77_a[26] = PD1_a_o_0 & !VD1_b_o_iv_17 # !PD1_a_o_0 & !VD1_b_o_iv_18;
 
 
--UD1_shift_out_54[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[28] at LC_X10_Y18_N7
--operation mode is normal
 
UD1_shift_out_54[28] = UD1_shift_out_54_a[28] & VD1_b_o_iv_16 & !PD1_a_o_1 # !UD1_shift_out_54_a[28] & VD1_b_o_iv_15 # PD1_a_o_1;
 
 
--VD1_hilo_37_iv_0_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[20] at LC_X4_Y14_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_a[20] = VD1_hilo_21 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_19 # !VD1_hilo_2_sqmuxa # !VD1_hilo_21 & !VD1_hilo_19 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[20] at LC_X4_Y14_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_0[20] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_20 # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[20] # !VD1_hilo_37_iv_0_o5[0] & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[20];
 
 
--VD1_hilo_37_iv_0_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[52] at LC_X6_Y4_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a[52] = !VD1_hilo_37_iv_0_4[52] & !VD1_hilo_37_iv_0_3[52] & VD1_hilo_24_add20 # !VD1_hilo_2_sqmuxa;
 
 
--PD1_a_o_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[20] at LC_X22_Y14_N0
--operation mode is normal
 
PD1_a_o_a[20] = SC1_muxa_ctl_o_1 & !FB1_r32_o_20 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_20;
 
 
--PD1_a_o_3_Z[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[20] at LC_X22_Y13_N3
--operation mode is normal
 
SD1_r32_o_20_qfbk = SD1_r32_o_20;
PD1_a_o_3_Z[20] = PD1_a_o_3_s[0] & SD1_r32_o_20_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[20];
 
--SD1_r32_o_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_20 at LC_X22_Y13_N3
--operation mode is normal
 
SD1_r32_o_20 = DFFEAS(PD1_a_o_3_Z[20], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_20, , , VCC);
 
 
--TD1_un1_b_1_combout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[20] at LC_X13_Y8_N4
--operation mode is normal
 
TD1_un1_b_1_combout[20] = TD1_sum13_0_a2 $ !VD1_b_o_iv_20;
 
 
--TD1_un1_a_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add19 at LC_X12_Y8_N4
--operation mode is arithmetic
 
TD1_un1_a_add19_carry_eqn = (!TD1_un1_a_carry_14 & TD1_un1_a_carry_18) # (TD1_un1_a_carry_14 & TD1L545);
TD1_un1_a_add19 = PD1_a_o_19 $ TD1_un1_b_1_combout[19] $ TD1_un1_a_add19_carry_eqn;
 
--TD1_un1_a_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_19 at LC_X12_Y8_N4
--operation mode is arithmetic
 
TD1_un1_a_carry_19 = CARRY(PD1_a_o_19 & !TD1_un1_b_1_combout[19] & !TD1L545 # !PD1_a_o_19 & !TD1L545 # !TD1_un1_b_1_combout[19]);
 
 
--UD1_shift_out_84_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[20] at LC_X10_Y17_N7
--operation mode is normal
 
UD1_shift_out_84_a[20] = PD1_a_o_2 & !UD1_shift_out_43[28] # !PD1_a_o_2 & !UD1_shift_out_45[28];
 
 
--UD1_shift_out_63[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[28] at LC_X10_Y17_N9
--operation mode is normal
 
UD1_shift_out_63[28] = PD1_a_o_2 & UD1_shift_out_48[28] # !PD1_a_o_2 & UD1_shift_out_52[28];
 
 
--UD1_shift_out_87_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[19] at LC_X10_Y9_N5
--operation mode is normal
 
UD1_shift_out_87_d[19] = PD1_a_o_0 & UD1_shift_out_80[19] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[19];
 
 
--UD1_shift_out_85_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[19] at LC_X14_Y12_N5
--operation mode is normal
 
UD1_shift_out_85_d[19] = PD1_a_o_2 & UD1_shift_out_52[31] # !PD1_a_o_2 & !UD1_shift_out_77_a[25];
 
 
--VD1_hilo_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_19 at LC_X4_Y14_N3
--operation mode is normal
 
VD1_hilo_19_lut_out = VD1_hilo_37_iv_0_0[19] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_19 # !VD1_hilo_37_iv_0_a[19];
VD1_hilo_19 = DFFEAS(VD1_hilo_19_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_51 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_51 at LC_X5_Y5_N7
--operation mode is normal
 
VD1_hilo_51_lut_out = !VD1_hilo_37_iv_0_8[51] & !VD1_hilo_37_iv_0_a3[57];
VD1_hilo_51 = DFFEAS(VD1_hilo_51_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_19 at LC_X22_Y6_N9
--operation mode is normal
 
PD1_a_o_19 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[19] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[19];
 
 
--TD1_m51_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m51_a at LC_X10_Y7_N4
--operation mode is normal
 
TD1_m51_a = PD1_a_o_19 & VD1_b_o_iv_19 & !TD1_m9 # !VD1_b_o_iv_19 & !TD1_m5 # !PD1_a_o_19 & !VD1_b_o_iv_19;
 
 
--UD1_shift_out_92_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[19] at LC_X15_Y12_N3
--operation mode is normal
 
UD1_shift_out_92_d_a[19] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_19 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[19];
 
 
--UD1_shift_out_84[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[19] at LC_X15_Y12_N8
--operation mode is normal
 
UD1_shift_out_84[19] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_77[11] # !PD1_a_o_4 & !UD1_shift_out_84_a[19];
 
 
--UD1_shift_out_87_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[18] at LC_X7_Y18_N6
--operation mode is normal
 
UD1_shift_out_87_d[18] = PD1_a_o_0 & UD1_shift_out_80[18] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[18];
 
 
--UD1_shift_out_85_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[18] at LC_X10_Y18_N9
--operation mode is normal
 
UD1_shift_out_85_d[18] = PD1_a_o_2 & UD1_shift_out_52[30] # !PD1_a_o_2 & !UD1_shift_out_77_a[24];
 
 
--UD1_shift_out_83[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83[18] at LC_X13_Y17_N2
--operation mode is normal
 
UD1_shift_out_83[18] = !UD1_shift_out_83_a[18] & PD1_a_o_2 & !PD1_a_o_1 # !UD1_shift_out587;
 
 
--UD1_shift_out_92_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[18] at LC_X11_Y15_N3
--operation mode is normal
 
UD1_shift_out_92_d_a[18] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_18 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[18];
 
 
--UD1_shift_out_84[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[18] at LC_X11_Y15_N9
--operation mode is normal
 
UD1_shift_out_84[18] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_77[10] # !PD1_a_o_4 & UD1_shift_out_77[18];
 
 
--VD1_hilo_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_18 at LC_X5_Y14_N8
--operation mode is normal
 
VD1_hilo_18_lut_out = VD1_hilo_37_iv_1[18] # PD1_a_o_18 & VD1_addnop2109_0_a2 # !VD1_hilo_37_iv_a[18];
VD1_hilo_18 = DFFEAS(VD1_hilo_18_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_50 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_50 at LC_X6_Y5_N6
--operation mode is normal
 
VD1_hilo_50_lut_out = !VD1_hilo_37_iv_0_5[50] & !VD1_hilo_37_iv_0_a[50] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_0_4[50];
VD1_hilo_50 = DFFEAS(VD1_hilo_50_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_18 at LC_X19_Y5_N4
--operation mode is normal
 
PD1_a_o_18 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[18] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[18];
 
 
--TD1_m46_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m46_a at LC_X5_Y14_N3
--operation mode is normal
 
TD1_m46_a = VD1_b_o_iv_18 & !TD1_m9 & PD1_a_o_18 # !VD1_b_o_iv_18 & !PD1_a_o_18 # !TD1_m5;
 
 
--TD1_un1_a_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add18 at LC_X12_Y8_N3
--operation mode is arithmetic
 
TD1_un1_a_add18_carry_eqn = (!TD1_un1_a_carry_14 & TD1_un1_a_carry_17) # (TD1_un1_a_carry_14 & TD1L345);
TD1_un1_a_add18 = TD1_un1_b_1_combout[18] $ PD1_a_o_18 $ !TD1_un1_a_add18_carry_eqn;
 
--TD1_un1_a_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_18 at LC_X12_Y8_N3
--operation mode is arithmetic
 
TD1_un1_a_carry_18_cout_0 = TD1_un1_b_1_combout[18] & PD1_a_o_18 # !TD1_un1_a_carry_17 # !TD1_un1_b_1_combout[18] & PD1_a_o_18 & !TD1_un1_a_carry_17;
TD1_un1_a_carry_18 = CARRY(TD1_un1_a_carry_18_cout_0);
 
--TD1L545 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_18~COUT1_1 at LC_X12_Y8_N3
--operation mode is arithmetic
 
TD1L545_cout_1 = TD1_un1_b_1_combout[18] & PD1_a_o_18 # !TD1L345 # !TD1_un1_b_1_combout[18] & PD1_a_o_18 & !TD1L345;
TD1L545 = CARRY(TD1L545_cout_1);
 
 
--UD1_shift_out_87_d[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[26] at LC_X8_Y15_N4
--operation mode is normal
 
UD1_shift_out_87_d[26] = PD1_a_o_0 & UD1_shift_out_80[26] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[26];
 
 
--UD1_shift_out_68[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[22] at LC_X9_Y18_N9
--operation mode is normal
 
UD1_shift_out_68[22] = PD1_a_o_0 & VD1_b_o_iv_19 # !PD1_a_o_0 & VD1_b_o_iv_20;
 
 
--UD1_shift_out_68[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[24] at LC_X7_Y18_N0
--operation mode is normal
 
UD1_shift_out_68[24] = PD1_a_o_0 & VD1_b_o_iv_21 # !PD1_a_o_0 & VD1_b_o_iv_22;
 
 
--UD1_shift_out_85_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[26] at LC_X8_Y17_N1
--operation mode is normal
 
UD1_shift_out_85_a[26] = PD1_a_o_1 & !PD1_a_o_2 & !UD1_shift_out_68[26] # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_25;
 
 
--UD1_shift_out_92_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[26] at LC_X11_Y15_N2
--operation mode is normal
 
UD1_shift_out_92_d_a[26] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_26 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[26] at LC_X11_Y15_N4
--operation mode is normal
 
UD1_shift_out_84[26] = PD1_a_o_4 & PD1_a_o_3 & !UD1_shift_out_84_a[26] # !PD1_a_o_3 & UD1_shift_out_77[18] # !PD1_a_o_4 & !UD1_shift_out_84_a[26];
 
 
--VD1_hilo_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_26 at LC_X3_Y15_N7
--operation mode is normal
 
VD1_hilo_26_lut_out = VD1_hilo_37_iv_0_0[26] # PD1_a_o_26 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[26];
VD1_hilo_26 = DFFEAS(VD1_hilo_26_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_58 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_58 at LC_X5_Y3_N8
--operation mode is normal
 
VD1_hilo_58_lut_out = !VD1_hilo_37_iv_0_o3_1_0_1[58] & !VD1_hilo_37_iv_0_1[58] & !VD1_hilo_37_iv_0_o3[58] # !VD1_hilo_3_sqmuxa;
VD1_hilo_58 = DFFEAS(VD1_hilo_58_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_26 at LC_X21_Y10_N4
--operation mode is normal
 
PD1_a_o_26 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[26] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[26];
 
 
--TD1_m81_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m81_a at LC_X6_Y14_N4
--operation mode is normal
 
TD1_m81_a = PD1_a_o_26 & VD1_b_o_iv_26 & !TD1_m9 # !VD1_b_o_iv_26 & !TD1_m5 # !PD1_a_o_26 & !VD1_b_o_iv_26;
 
 
--TD1_un1_a_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add26 at LC_X12_Y7_N1
--operation mode is arithmetic
 
TD1_un1_a_add26_carry_eqn = (!TD1_un1_a_carry_24 & TD1_un1_a_carry_25) # (TD1_un1_a_carry_24 & TD1L755);
TD1_un1_a_add26 = TD1_un1_b_1_combout[26] $ PD1_a_o_26 $ !TD1_un1_a_add26_carry_eqn;
 
--TD1_un1_a_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_26 at LC_X12_Y7_N1
--operation mode is arithmetic
 
TD1_un1_a_carry_26_cout_0 = TD1_un1_b_1_combout[26] & PD1_a_o_26 # !TD1_un1_a_carry_25 # !TD1_un1_b_1_combout[26] & PD1_a_o_26 & !TD1_un1_a_carry_25;
TD1_un1_a_carry_26 = CARRY(TD1_un1_a_carry_26_cout_0);
 
--TD1L955 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_26~COUT1_1 at LC_X12_Y7_N1
--operation mode is arithmetic
 
TD1L955_cout_1 = TD1_un1_b_1_combout[26] & PD1_a_o_26 # !TD1L755 # !TD1_un1_b_1_combout[26] & PD1_a_o_26 & !TD1L755;
TD1L955 = CARRY(TD1L955_cout_1);
 
 
--UD1_shift_out_68[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[25] at LC_X7_Y17_N9
--operation mode is normal
 
UD1_shift_out_68[25] = PD1_a_o_0 & VD1_b_o_iv_22 # !PD1_a_o_0 & VD1_b_o_iv_23;
 
 
--UD1_shift_out_68[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[23] at LC_X13_Y16_N9
--operation mode is normal
 
UD1_shift_out_68[23] = PD1_a_o_0 & VD1_b_o_iv_20 # !PD1_a_o_0 & VD1_b_o_iv_21;
 
 
--UD1_shift_out_85_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[27] at LC_X11_Y14_N4
--operation mode is normal
 
UD1_shift_out_85_a[27] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[27] # !PD1_a_o_1 & !VD1_b_o_iv_26;
 
 
--UD1_shift_out_87_d[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[27] at LC_X11_Y7_N8
--operation mode is normal
 
UD1_shift_out_87_d[27] = PD1_a_o_0 & UD1_shift_out_80[27] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[27];
 
 
--UD1_shift_out_92_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[27] at LC_X12_Y13_N2
--operation mode is normal
 
UD1_shift_out_92_d_a[27] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_27 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[27] at LC_X15_Y12_N9
--operation mode is normal
 
UD1_shift_out_84[27] = PD1_a_o_4 & UD1_shift_out_75[27] # !PD1_a_o_4 & UD1_shift_out_77[27];
 
 
--VD1_hilo_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_27 at LC_X3_Y15_N6
--operation mode is normal
 
VD1_hilo_27_lut_out = VD1_hilo_37_iv_0[27] # VD1_hilo25 & VD1_hilo_8_Z[27] # !VD1_hilo_37_iv_a[27];
VD1_hilo_27 = DFFEAS(VD1_hilo_27_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_59 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_59 at LC_X5_Y3_N2
--operation mode is normal
 
VD1_hilo_59_lut_out = VD1_hilo_37_iv_0_a[59] & !VD1_hilo_37_iv_0_a3[57] & PD1_a_o_27 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_59 = DFFEAS(VD1_hilo_59_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_27 at LC_X22_Y4_N6
--operation mode is normal
 
PD1_a_o_27 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[27] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[27];
 
 
--TD1_m86_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m86_a at LC_X13_Y14_N4
--operation mode is normal
 
TD1_m86_a = PD1_a_o_27 & VD1_b_o_iv_27 & !TD1_m9 # !VD1_b_o_iv_27 & !TD1_m5 # !PD1_a_o_27 & !VD1_b_o_iv_27;
 
 
--TD1_un1_a_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add27 at LC_X12_Y7_N2
--operation mode is arithmetic
 
TD1_un1_a_add27_carry_eqn = (!TD1_un1_a_carry_24 & TD1_un1_a_carry_26) # (TD1_un1_a_carry_24 & TD1L955);
TD1_un1_a_add27 = PD1_a_o_27 $ TD1_un1_b_1_combout[27] $ TD1_un1_a_add27_carry_eqn;
 
--TD1_un1_a_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_27 at LC_X12_Y7_N2
--operation mode is arithmetic
 
TD1_un1_a_carry_27_cout_0 = PD1_a_o_27 & !TD1_un1_b_1_combout[27] & !TD1_un1_a_carry_26 # !PD1_a_o_27 & !TD1_un1_a_carry_26 # !TD1_un1_b_1_combout[27];
TD1_un1_a_carry_27 = CARRY(TD1_un1_a_carry_27_cout_0);
 
--TD1L165 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_27~COUT1_1 at LC_X12_Y7_N2
--operation mode is arithmetic
 
TD1L165_cout_1 = PD1_a_o_27 & !TD1_un1_b_1_combout[27] & !TD1L955 # !PD1_a_o_27 & !TD1L955 # !TD1_un1_b_1_combout[27];
TD1L165 = CARRY(TD1L165_cout_1);
 
 
--UD1_shift_out_87_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_a[28] at LC_X8_Y16_N7
--operation mode is normal
 
UD1_shift_out_87_a[28] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_31;
 
 
--UD1_shift_out_87_d[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[28] at LC_X8_Y16_N6
--operation mode is normal
 
UD1_shift_out_87_d[28] = PD1_a_o_0 & !UD1_shift_out_87_d_a[28] # !PD1_a_o_0 & PD1_a_o_2 & !UD1_shift_out_87_d_a[28] # !PD1_a_o_2 & VD1_b_o_iv_30;
 
 
--UD1_shift_out_68[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[26] at LC_X7_Y17_N4
--operation mode is normal
 
UD1_shift_out_68[26] = PD1_a_o_0 & VD1_b_o_iv_23 # !PD1_a_o_0 & VD1_b_o_iv_24;
 
 
--UD1_shift_out_85_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[28] at LC_X8_Y17_N3
--operation mode is normal
 
UD1_shift_out_85_a[28] = PD1_a_o_1 & !UD1_shift_out_68[28] & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_27;
 
 
--TD1_alu_out_0_a2_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_a[28] at LC_X9_Y14_N6
--operation mode is normal
 
TD1_alu_out_0_a2_a[28] = RC1_alu_func_o_4 & RC1_alu_func_o_2 & !RC1_alu_func_o_1 & !RC1_alu_func_o_3;
 
 
--PD1_a_o_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_28 at LC_X16_Y7_N9
--operation mode is normal
 
PD1_a_o_28 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[28] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[28];
 
 
--MD1_c_0_Z[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_Z[28] at LC_X7_Y15_N7
--operation mode is normal
 
MD1_c_0_Z[28] = VD1_b_o_iv_28 & TD1_alu_out_9_a2_1_1_0 # !MD1_c_0_a[28];
 
 
--MD1_c_2_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_a[28] at LC_X7_Y15_N6
--operation mode is normal
 
MD1_c_2_a[28] = TD1_m107 & !RC1_alu_func_o_3 & VD1_b_o_iv_28 # !RC1_alu_func_o_0;
 
 
--TD1_alu_out_0_a2_3_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_0_a2_3_0 at LC_X7_Y15_N9
--operation mode is normal
 
TD1_alu_out_0_a2_3_0 = !VD1_b_o_iv_28 & UD1_shift_out588_0 & TD1_alu_out_0_a3[28] & PD1_a_o_28;
 
 
--TD1_un1_b_1_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[28] at LC_X12_Y11_N2
--operation mode is normal
 
TD1_un1_b_1_combout[28] = VD1_b_o_iv_28 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_92_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[28] at LC_X9_Y16_N3
--operation mode is normal
 
UD1_shift_out_92_d_a[28] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_28 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[28] at LC_X10_Y17_N0
--operation mode is normal
 
UD1_shift_out_84[28] = PD1_a_o_4 & UD1_shift_out_75[28] # !PD1_a_o_4 & UD1_shift_out_77[28];
 
 
--UD1_shift_out_87_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_a[29] at LC_X8_Y15_N7
--operation mode is normal
 
UD1_shift_out_87_a[29] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_30;
 
 
--UD1_shift_out_85_c[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[29] at LC_X11_Y14_N7
--operation mode is normal
 
UD1_shift_out_85_c[29] = PD1_a_o_2 & PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_68[29] # !PD1_a_o_1 & VD1_b_o_iv_28;
 
 
--UD1_shift_out_92_d_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[29] at LC_X12_Y13_N6
--operation mode is normal
 
UD1_shift_out_92_d_a[29] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_29 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[29] at LC_X14_Y11_N3
--operation mode is normal
 
UD1_shift_out_84[29] = PD1_a_o_4 & UD1_shift_out_75[29] # !PD1_a_o_4 & !UD1_shift_out_84_a[29];
 
 
--VD1_hilo_61 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_61 at LC_X9_Y2_N2
--operation mode is normal
 
VD1_hilo_61_lut_out = !VD1_hilo_37_iv_0_a3[57] & VD1_hilo_37_iv_0_a[61] & PD1_a_o_29 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_61 = DFFEAS(VD1_hilo_61_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--TD1_m91_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m91_a at LC_X9_Y10_N5
--operation mode is normal
 
TD1_m91_a = PD1_a_o_29 & VD1_b_o_iv_29 & !TD1_m9 # !VD1_b_o_iv_29 & !TD1_m5 # !PD1_a_o_29 & !VD1_b_o_iv_29;
 
 
--UD1_shift_out_87_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[13] at LC_X13_Y18_N6
--operation mode is normal
 
UD1_shift_out_87_d_a[13] = PD1_a_o_1 & !VD1_b_o_iv_19 # !PD1_a_o_1 & !VD1_b_o_iv_17;
 
 
--UD1_shift_out_80[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[13] at LC_X13_Y18_N2
--operation mode is normal
 
UD1_shift_out_80[13] = PD1_a_o_2 & UD1_shift_out_80_a[13] & VD1_b_o_iv_18 # !UD1_shift_out_80_a[13] & VD1_b_o_iv_20 # !PD1_a_o_2 & !UD1_shift_out_80_a[13];
 
 
--UD1_shift_out_85_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[13] at LC_X14_Y15_N9
--operation mode is normal
 
UD1_shift_out_85_d_a[13] = PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_0 & !VD1_b_o_iv_11;
 
 
--UD1_shift_out_48[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[29] at LC_X15_Y11_N9
--operation mode is normal
 
UD1_shift_out_48[29] = PD1_a_o_1 & !UD1_shift_out_48_a[29] # !PD1_a_o_1 & UD1_shift_out_48_a[29] & VD1_b_o_iv_9 # !UD1_shift_out_48_a[29] & VD1_b_o_iv_8;
 
 
--UD1_shift_out_74[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[13] at LC_X15_Y14_N0
--operation mode is normal
 
UD1_shift_out_74[13] = PD1_a_o_1 & VD1_b_o_iv_31 # !PD1_a_o_1 & UD1_shift_out_sn_m25_0_o2 & VD1_b_o_iv_31 # !UD1_shift_out_sn_m25_0_o2 & UD1_shift_out_39[17];
 
 
--UD1_shift_out_45[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[29] at LC_X14_Y19_N3
--operation mode is normal
 
UD1_shift_out_45[29] = PD1_a_o_1 & !UD1_shift_out_45_a[29] # !PD1_a_o_1 & UD1_shift_out_45_a[29] & VD1_b_o_iv_5 # !UD1_shift_out_45_a[29] & VD1_b_o_iv_4;
 
 
--VD1_hilo_37_iv_0_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[13] at LC_X4_Y13_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a[13] = VD1_hilo_14 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_12 # !VD1_hilo_2_sqmuxa # !VD1_hilo_14 & !VD1_hilo_12 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[13] at LC_X4_Y13_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_0[13] = VD1_hilo_13 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[13] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_13 & VD1_un134_hilo_combout[13] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_2[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[45] at LC_X8_Y9_N9
--operation mode is normal
 
VD1_hilo_37_iv_2[45] = VD1_hilo_33_i_m[45] # VD1_hilo_37_iv_2_a[45] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[45];
 
 
--VD1_hilo_37_iv_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[45] at LC_X9_Y9_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[45] = RC1_alu_func_o_0 & !PD1_a_o_13 # !RC1_alu_func_o_0 & !VD1_hilo_45;
 
 
--PD1_a_o_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[13] at LC_X24_Y9_N6
--operation mode is normal
 
PD1_a_o_a[13] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_13 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_13;
 
 
--PD1_a_o_3_Z[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[13] at LC_X24_Y9_N8
--operation mode is normal
 
SD1_r32_o_13_qfbk = SD1_r32_o_13;
PD1_a_o_3_Z[13] = PD1_a_o_3_s[0] & SD1_r32_o_13_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[13];
 
--SD1_r32_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_13 at LC_X24_Y9_N8
--operation mode is normal
 
SD1_r32_o_13 = DFFEAS(PD1_a_o_3_Z[13], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_13, , , VCC);
 
 
--TD1_un1_b_1_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[13] at LC_X13_Y7_N4
--operation mode is normal
 
TD1_un1_b_1_combout[13] = VD1_b_o_iv_13 $ !TD1_sum13_0_a2;
 
 
--TD1_un1_a_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add12 at LC_X12_Y9_N7
--operation mode is arithmetic
 
TD1_un1_a_add12_carry_eqn = (!TD1_un1_a_carry_9 & TD1_un1_a_carry_11) # (TD1_un1_a_carry_9 & TD1L235);
TD1_un1_a_add12 = TD1_un1_b_1_combout[12] $ PD1_a_o_12 $ !TD1_un1_a_add12_carry_eqn;
 
--TD1_un1_a_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_12 at LC_X12_Y9_N7
--operation mode is arithmetic
 
TD1_un1_a_carry_12_cout_0 = TD1_un1_b_1_combout[12] & PD1_a_o_12 # !TD1_un1_a_carry_11 # !TD1_un1_b_1_combout[12] & PD1_a_o_12 & !TD1_un1_a_carry_11;
TD1_un1_a_carry_12 = CARRY(TD1_un1_a_carry_12_cout_0);
 
--TD1L435 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_12~COUT1_1 at LC_X12_Y9_N7
--operation mode is arithmetic
 
TD1L435_cout_1 = TD1_un1_b_1_combout[12] & PD1_a_o_12 # !TD1L235 # !TD1_un1_b_1_combout[12] & PD1_a_o_12 & !TD1L235;
TD1L435 = CARRY(TD1L435_cout_1);
 
 
--VD1_hilo_37_iv_0_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[29] at LC_X3_Y17_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[29] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_30 & !VD1_hilo_2_sqmuxa # !VD1_hilo_28 # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_28;
 
 
--VD1_hilo_37_iv_0_0[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[29] at LC_X3_Y17_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_0[29] = VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[29] # VD1_hilo_29 & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo_37_iv_0_a3_0[0] & VD1_hilo_29 & VD1_hilo_37_iv_0_o5[0];
 
 
--VD1_un134_hilo_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[28] at LC_X5_Y15_N6
--operation mode is arithmetic
 
VD1_un134_hilo_combout[28]_carry_eqn = (!VD1_un134_hilo_cout[24] & VD1_un134_hilo_cout[26]) # (VD1_un134_hilo_cout[24] & VD1L5991);
VD1_un134_hilo_combout[28] = VD1_hilo_28 $ (!VD1_un134_hilo_combout[28]_carry_eqn);
 
--VD1_un134_hilo_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[28] at LC_X5_Y15_N6
--operation mode is arithmetic
 
VD1_un134_hilo_cout[28]_cout_0 = VD1_hilo_28 & VD1_hilo_29 & !VD1_un134_hilo_cout[26];
VD1_un134_hilo_cout[28] = CARRY(VD1_un134_hilo_cout[28]_cout_0);
 
--VD1L9991 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[28]~COUT1_24 at LC_X5_Y15_N6
--operation mode is arithmetic
 
VD1L9991_cout_1 = VD1_hilo_28 & VD1_hilo_29 & !VD1L5991;
VD1L9991 = CARRY(VD1L9991_cout_1);
 
 
--RD1_r32_o_0_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_30 at LC_X21_Y3_N7
--operation mode is normal
 
RD1_r32_o_0_30_carry_eqn = (!RD1_r32_o_cout[24] & RD1_r32_o_cout[28]) # (RD1_r32_o_cout[24] & RD1L111);
RD1_r32_o_0_30_lut_out = RD1_r32_o_0_30_carry_eqn $ !KB1_r32_o_30;
RD1_r32_o_0_30 = DFFEAS(RD1_r32_o_0_30_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_30 at LC_X20_Y4_N3
--operation mode is normal
 
FB1_r32_o_30_lut_out = CD1_res_7_0_0_a3_0 # ED1_r32_o_14 & CD1_res_7_0_0_a2_16;
FB1_r32_o_30 = DFFEAS(FB1_r32_o_30_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[30] at LC_X24_Y3_N0
--operation mode is normal
 
PD1_a_o_3_d[30] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_30 # !PD1_un6_a_o & !PD1_a_o_3_d_a[30] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[30];
 
 
--VD1_hilo_33_1[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_1[64] at LC_X5_Y4_N2
--operation mode is normal
 
VD1_hilo_33_1[64] = VD1_addnop2 $ VD1_addop2;
 
 
--VD1_hilo_24_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add30 at LC_X8_Y2_N4
--operation mode is arithmetic
 
VD1_hilo_24_add30_carry_eqn = (!VD1_hilo_24_carry_25 & VD1_hilo_24_carry_29) # (VD1_hilo_24_carry_25 & VD1L035);
VD1_hilo_24_add30 = VD1_un1_op2_reged_1_combout[30] $ VD1_hilo_61 $ !VD1_hilo_24_add30_carry_eqn;
 
--VD1_hilo_24_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_30 at LC_X8_Y2_N4
--operation mode is arithmetic
 
VD1_hilo_24_carry_30 = CARRY(VD1_un1_op2_reged_1_combout[30] & VD1_hilo_61 # !VD1L035 # !VD1_un1_op2_reged_1_combout[30] & VD1_hilo_61 & !VD1L035);
 
 
--VD1_hilo_37_iv_0_2[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[62] at LC_X7_Y3_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_2[62] = VD1_hilo_37_iv_0_0[62] # VD1_hilo_37_iv_0_a5_0[62] # !VD1_un50_hilo_add30 & VD1_hilo_37_iv_0_a2_6_0[37];
 
 
--VD1_hilo_37_iv_0_o5[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[62] at LC_X9_Y2_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_o5[62] = VD1_hilo_37_iv_0_a3_4[57] & !PD1_a_o_30 & VD1_hilo_37_iv_0_a3_1[0] # !VD1_un50_hilo_add31 # !VD1_hilo_37_iv_0_a3_4[57] & !PD1_a_o_30 & VD1_hilo_37_iv_0_a3_1[0];
 
 
--VD1_un59_hilo_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add31 at LC_X9_Y3_N5
--operation mode is arithmetic
 
VD1_un59_hilo_add31_carry_eqn = VD1_un59_hilo_carry_30;
VD1_un59_hilo_add31 = VD1_op2_reged[31] $ VD1_hilo_63 $ VD1_un59_hilo_add31_carry_eqn;
 
--VD1_un59_hilo_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_31 at LC_X9_Y3_N5
--operation mode is arithmetic
 
VD1_un59_hilo_carry_31_cout_0 = VD1_op2_reged[31] & !VD1_hilo_63 & !VD1_un59_hilo_carry_30 # !VD1_op2_reged[31] & !VD1_un59_hilo_carry_30 # !VD1_hilo_63;
VD1_un59_hilo_carry_31 = CARRY(VD1_un59_hilo_carry_31_cout_0);
 
--VD1L2881 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_31~COUT1_1 at LC_X9_Y3_N5
--operation mode is arithmetic
 
VD1L2881_cout_1 = VD1_op2_reged[31] & !VD1_hilo_63 & !VD1_un59_hilo_carry_30 # !VD1_op2_reged[31] & !VD1_un59_hilo_carry_30 # !VD1_hilo_63;
VD1L2881 = CARRY(VD1L2881_cout_1);
 
 
--VD1_hilo_37_iv_0_o5_0_a[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0_a[62] at LC_X8_Y8_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_o5_0_a[62] = !VD1_hilo_63 & VD1_hilo_37_iv_0_a6_0_1[40];
 
 
--UD1_shift_out_92_d_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[30] at LC_X12_Y17_N0
--operation mode is normal
 
UD1_shift_out_92_d_a[30] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_30 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[30] at LC_X12_Y17_N4
--operation mode is normal
 
UD1_shift_out_84[30] = PD1_a_o_4 & !UD1_shift_out_84_a[30] # !PD1_a_o_4 & UD1_shift_out_77[30];
 
 
--UD1_shift_out_89[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89[30] at LC_X11_Y13_N6
--operation mode is normal
 
UD1_shift_out_89[30] = UD1_shift_out586 & UD1_shift_out_85[30] # !UD1_shift_out586 & !UD1_shift_out_89_a[30];
 
 
--TD1_un1_b_1_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[29] at LC_X14_Y6_N4
--operation mode is normal
 
TD1_un1_b_1_combout[29] = TD1_sum13_0_a2 $ !VD1_b_o_iv_29;
 
 
--UD1_shift_out_87_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[12] at LC_X19_Y18_N1
--operation mode is normal
 
UD1_shift_out_87_d[12] = PD1_a_o_0 & UD1_shift_out_80[12] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[12];
 
 
--UD1_shift_out_85_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[12] at LC_X11_Y18_N9
--operation mode is normal
 
UD1_shift_out_85_d[12] = PD1_a_o_2 & UD1_shift_out_48[28] # !PD1_a_o_2 & !UD1_shift_out_77_a[18];
 
 
--UD1_shift_out_74[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[12] at LC_X16_Y14_N1
--operation mode is normal
 
UD1_shift_out_74[12] = PD1_a_o_2 & VD1_b_o_iv_31 # !PD1_a_o_2 & PD1_a_o_3 & VD1_b_o_iv_31 # !PD1_a_o_3 & UD1_shift_out_79[20];
 
 
--UD1_shift_out_86_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[12] at LC_X16_Y14_N2
--operation mode is normal
 
UD1_shift_out_86_a[12] = PD1_a_o_2 & !UD1_shift_out_79[16] # !PD1_a_o_2 & UD1_shift_out587 & !UD1_shift_out_79[20] # !UD1_shift_out587 & !UD1_shift_out_79[16];
 
 
--UD1_shift_out_63[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[20] at LC_X10_Y17_N3
--operation mode is normal
 
UD1_shift_out_63[20] = PD1_a_o_2 & UD1_shift_out_43[28] # !PD1_a_o_2 & UD1_shift_out_45[28];
 
 
--UD1_shift_out_92_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[12] at LC_X15_Y18_N4
--operation mode is normal
 
UD1_shift_out_92_d_a[12] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_12 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[12] # !UD1_shift_out_sn_m17_0;
 
 
--VD1_hilo_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_12 at LC_X4_Y18_N4
--operation mode is normal
 
VD1_hilo_12_lut_out = VD1_hilo_37_iv_0_0[12] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_12 # !VD1_hilo_37_iv_0_a[12];
VD1_hilo_12 = DFFEAS(VD1_hilo_12_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_44 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_44 at LC_X9_Y7_N2
--operation mode is normal
 
VD1_hilo_44_lut_out = VD1_hilo_37_iv_0_a[44] & !VD1_hilo_37_iv_0_o3[44] & !VD1_hilo_37_iv_0_o3[34] # !VD1_hilo_37_iv_0_o2_3_0[44];
VD1_hilo_44 = DFFEAS(VD1_hilo_44_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_12 at LC_X23_Y12_N8
--operation mode is normal
 
PD1_a_o_12 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[12] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[12];
 
 
--TD1_m122_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m122_a at LC_X11_Y11_N8
--operation mode is normal
 
TD1_m122_a = PD1_a_o_12 & VD1_b_o_iv_12 & !TD1_m9 # !VD1_b_o_iv_12 & !TD1_m5 # !PD1_a_o_12 & !VD1_b_o_iv_12;
 
 
--YB1_dmem_ctl_2_0_0_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_3 at LC_X29_Y16_N1
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_3 = YB1_dmem_ctl_2_0_0_a[3] # YB1_fsm_dly_2_0_0_o2_x[2] & YB1_alu_func_2_0_0_a2_0[1] & WB94L1;
 
 
--WB94L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:dmem_ctl_1_3_|lpm_latch:U1|q[0]~56 at LC_X29_Y16_N4
--operation mode is normal
 
WB94L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_dmem_ctl_2_0_0_3 # !YB1_un1_muxa_ctl370_x & WB94L1;
 
--CC1_dmem_ctl_o_3 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3|dmem_ctl_o_3 at LC_X29_Y16_N4
--operation mode is normal
 
CC1_dmem_ctl_o_3 = DFFEAS(WB94L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--UD1_shift_out_87_d[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[24] at LC_X8_Y18_N5
--operation mode is normal
 
UD1_shift_out_87_d[24] = PD1_a_o_0 & UD1_shift_out_80[24] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[24];
 
 
--UD1_shift_out_68[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[20] at LC_X8_Y18_N6
--operation mode is normal
 
UD1_shift_out_68[20] = PD1_a_o_0 & VD1_b_o_iv_17 # !PD1_a_o_0 & VD1_b_o_iv_18;
 
 
--UD1_shift_out_85_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[24] at LC_X8_Y18_N0
--operation mode is normal
 
UD1_shift_out_85_a[24] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[24] # !PD1_a_o_1 & !VD1_b_o_iv_23;
 
 
--UD1_shift_out_92_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[24] at LC_X9_Y17_N6
--operation mode is normal
 
UD1_shift_out_92_d_a[24] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_24 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[24] at LC_X9_Y17_N2
--operation mode is normal
 
UD1_shift_out_84[24] = PD1_a_o_4 & PD1_a_o_3 & UD1_shift_out_84_a[24] # !PD1_a_o_3 & UD1_shift_out_77[16] # !PD1_a_o_4 & !UD1_shift_out_84_a[24];
 
 
--VD1_hilo_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24 at LC_X4_Y9_N4
--operation mode is normal
 
VD1_hilo_24_lut_out = VD1_hilo_37_iv_1[24] # PD1_a_o_24 & VD1_addnop2109_0_a2 # !VD1_hilo_37_iv_a[24];
VD1_hilo_24 = DFFEAS(VD1_hilo_24_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_56 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_56 at LC_X4_Y9_N5
--operation mode is normal
 
VD1_hilo_56_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_2[56] & !VD1_hilo25 # !VD1_hilo_37_iv_a[56];
VD1_hilo_56 = DFFEAS(VD1_hilo_56_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_24 at LC_X20_Y3_N4
--operation mode is normal
 
PD1_a_o_24 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[24] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[24];
 
 
--TD1_m71_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m71_a at LC_X13_Y6_N5
--operation mode is normal
 
TD1_m71_a = VD1_b_o_iv_24 & PD1_a_o_24 & !TD1_m9 # !VD1_b_o_iv_24 & !PD1_a_o_24 # !TD1_m5;
 
 
--TD1_un1_a_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add24 at LC_X12_Y8_N9
--operation mode is arithmetic
 
TD1_un1_a_add24_carry_eqn = (!TD1_un1_a_carry_19 & TD1_un1_a_carry_23) # (TD1_un1_a_carry_19 & TD1L455);
TD1_un1_a_add24 = PD1_a_o_24 $ TD1_un1_b_1_combout[24] $ !TD1_un1_a_add24_carry_eqn;
 
--TD1_un1_a_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_24 at LC_X12_Y8_N9
--operation mode is arithmetic
 
TD1_un1_a_carry_24 = CARRY(PD1_a_o_24 & TD1_un1_b_1_combout[24] # !TD1L455 # !PD1_a_o_24 & TD1_un1_b_1_combout[24] & !TD1L455);
 
 
--UD1_shift_out_87_d[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[25] at LC_X13_Y10_N2
--operation mode is normal
 
UD1_shift_out_87_d[25] = PD1_a_o_0 & UD1_shift_out_80[25] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[25];
 
 
--UD1_shift_out_68[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[21] at LC_X8_Y10_N8
--operation mode is normal
 
UD1_shift_out_68[21] = PD1_a_o_0 & VD1_b_o_iv_18 # !PD1_a_o_0 & VD1_b_o_iv_19;
 
 
--UD1_shift_out_85_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[25] at LC_X8_Y10_N7
--operation mode is normal
 
UD1_shift_out_85_a[25] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !UD1_shift_out_68[25] # !PD1_a_o_1 & !VD1_b_o_iv_24;
 
 
--UD1_shift_out_92_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[25] at LC_X9_Y16_N6
--operation mode is normal
 
UD1_shift_out_92_d_a[25] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_25 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_84[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84[25] at LC_X14_Y15_N5
--operation mode is normal
 
UD1_shift_out_84[25] = PD1_a_o_4 & UD1_shift_out_75[25] # !PD1_a_o_4 & UD1_shift_out_77[25];
 
 
--VD1_hilo_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_25 at LC_X4_Y13_N6
--operation mode is normal
 
VD1_hilo_25_lut_out = VD1_hilo_37_iv_0_0[25] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_25 # !VD1_hilo_37_iv_0_a[25];
VD1_hilo_25 = DFFEAS(VD1_hilo_25_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_57 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_57 at LC_X5_Y8_N4
--operation mode is normal
 
VD1_hilo_57_lut_out = !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_0_8[57];
VD1_hilo_57 = DFFEAS(VD1_hilo_57_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_25 at LC_X24_Y6_N4
--operation mode is normal
 
PD1_a_o_25 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[25] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[25];
 
 
--TD1_m76_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m76_a at LC_X13_Y6_N0
--operation mode is normal
 
TD1_m76_a = VD1_b_o_iv_25 & PD1_a_o_25 & !TD1_m9 # !VD1_b_o_iv_25 & !PD1_a_o_25 # !TD1_m5;
 
 
--TD1_un1_a_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add25 at LC_X12_Y7_N0
--operation mode is arithmetic
 
TD1_un1_a_add25_carry_eqn = TD1_un1_a_carry_24;
TD1_un1_a_add25 = PD1_a_o_25 $ TD1_un1_b_1_combout[25] $ TD1_un1_a_add25_carry_eqn;
 
--TD1_un1_a_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_25 at LC_X12_Y7_N0
--operation mode is arithmetic
 
TD1_un1_a_carry_25_cout_0 = PD1_a_o_25 & !TD1_un1_b_1_combout[25] & !TD1_un1_a_carry_24 # !PD1_a_o_25 & !TD1_un1_a_carry_24 # !TD1_un1_b_1_combout[25];
TD1_un1_a_carry_25 = CARRY(TD1_un1_a_carry_25_cout_0);
 
--TD1L755 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_25~COUT1_1 at LC_X12_Y7_N0
--operation mode is arithmetic
 
TD1L755_cout_1 = PD1_a_o_25 & !TD1_un1_b_1_combout[25] & !TD1_un1_a_carry_24 # !PD1_a_o_25 & !TD1_un1_a_carry_24 # !TD1_un1_b_1_combout[25];
TD1L755 = CARRY(TD1L755_cout_1);
 
 
--UD1_shift_out_87_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[22] at LC_X6_Y17_N7
--operation mode is normal
 
UD1_shift_out_87_d[22] = PD1_a_o_0 & UD1_shift_out_80[22] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[22];
 
 
--UD1_shift_out_85_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[22] at LC_X8_Y17_N6
--operation mode is normal
 
UD1_shift_out_85_d[22] = PD1_a_o_2 & UD1_shift_out_54[30] # !PD1_a_o_2 & UD1_shift_out_68[22];
 
 
--UD1_shift_out_88[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[22] at LC_X12_Y12_N2
--operation mode is normal
 
UD1_shift_out_88[22] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_22 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[22];
 
 
--UD1_shift_out_92_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[22] at LC_X12_Y17_N7
--operation mode is normal
 
UD1_shift_out_92_d_a[22] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[22] # !PD1_a_o_4 & UD1_shift_out_63[30];
 
 
--VD1_hilo_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22 at LC_X5_Y13_N9
--operation mode is normal
 
VD1_hilo_22_lut_out = VD1_hilo_37_iv_0_0[22] # VD1_hilo_37_iv_0_o5_0[0] & PD1_a_o_22 # !VD1_hilo_37_iv_0_a[22];
VD1_hilo_22 = DFFEAS(VD1_hilo_22_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_54 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_54 at LC_X5_Y4_N4
--operation mode is normal
 
VD1_hilo_54_lut_out = !VD1_hilo_37_iv_0_3[54] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_0_o5[54] & VD1_hilo_37_iv_0_a[54];
VD1_hilo_54 = DFFEAS(VD1_hilo_54_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_22 at LC_X24_Y5_N8
--operation mode is normal
 
PD1_a_o_22 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[22] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[22];
 
 
--TD1_m61_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m61_a at LC_X5_Y13_N4
--operation mode is normal
 
TD1_m61_a = PD1_a_o_22 & VD1_b_o_iv_22 & !TD1_m9 # !VD1_b_o_iv_22 & !TD1_m5 # !PD1_a_o_22 & !VD1_b_o_iv_22;
 
 
--TD1_un1_a_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add22 at LC_X12_Y8_N7
--operation mode is arithmetic
 
TD1_un1_a_add22_carry_eqn = (!TD1_un1_a_carry_19 & TD1_un1_a_carry_21) # (TD1_un1_a_carry_19 & TD1L055);
TD1_un1_a_add22 = PD1_a_o_22 $ TD1_un1_b_1_combout[22] $ !TD1_un1_a_add22_carry_eqn;
 
--TD1_un1_a_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_22 at LC_X12_Y8_N7
--operation mode is arithmetic
 
TD1_un1_a_carry_22_cout_0 = PD1_a_o_22 & TD1_un1_b_1_combout[22] # !TD1_un1_a_carry_21 # !PD1_a_o_22 & TD1_un1_b_1_combout[22] & !TD1_un1_a_carry_21;
TD1_un1_a_carry_22 = CARRY(TD1_un1_a_carry_22_cout_0);
 
--TD1L255 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_22~COUT1_1 at LC_X12_Y8_N7
--operation mode is arithmetic
 
TD1L255_cout_1 = PD1_a_o_22 & TD1_un1_b_1_combout[22] # !TD1L055 # !PD1_a_o_22 & TD1_un1_b_1_combout[22] & !TD1L055;
TD1L255 = CARRY(TD1L255_cout_1);
 
 
--UD1_shift_out_87_d[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[23] at LC_X14_Y7_N5
--operation mode is normal
 
UD1_shift_out_87_d[23] = PD1_a_o_0 & UD1_shift_out_80[23] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[23];
 
 
--UD1_shift_out_85_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_a[23] at LC_X20_Y17_N7
--operation mode is normal
 
UD1_shift_out_85_a[23] = PD1_a_o_2 & !UD1_shift_out_54[31] # !PD1_a_o_2 & !PD1_a_o_1;
 
 
--UD1_shift_out_88[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[23] at LC_X12_Y12_N6
--operation mode is normal
 
UD1_shift_out_88[23] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_23 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_88_a[23];
 
 
--UD1_shift_out_92_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_92_d_a[23] at LC_X12_Y12_N5
--operation mode is normal
 
UD1_shift_out_92_d_a[23] = PD1_a_o_4 & !PD1_a_o_3 & UD1_shift_out_63[23] # !PD1_a_o_4 & UD1_shift_out_77[23];
 
 
--VD1_hilo_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_23 at LC_X5_Y9_N8
--operation mode is normal
 
VD1_hilo_23_lut_out = VD1_hilo_37_iv_0[23] # VD1_hilo_8_Z[23] & VD1_hilo25 # !VD1_hilo_37_iv_a[23];
VD1_hilo_23 = DFFEAS(VD1_hilo_23_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_hilo_55 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_55 at LC_X9_Y9_N2
--operation mode is normal
 
VD1_hilo_55_lut_out = !VD1_hilo_37_iv_2[55] & !VD1_hilo_37_iv_0_a3[57] & !VD1_hilo_37_iv_a[55] # !VD1_hilo25;
VD1_hilo_55 = DFFEAS(VD1_hilo_55_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--PD1_a_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_23 at LC_X22_Y3_N8
--operation mode is normal
 
PD1_a_o_23 = SC1_muxa_ctl_o_0 & !PD1_a_o_a[23] # !SC1_muxa_ctl_o_0 & PD1_a_o_3_Z[23];
 
 
--TD1_m66_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|m66_a at LC_X13_Y6_N2
--operation mode is normal
 
TD1_m66_a = PD1_a_o_23 & VD1_b_o_iv_23 & !TD1_m9 # !VD1_b_o_iv_23 & !TD1_m5 # !PD1_a_o_23 & !VD1_b_o_iv_23;
 
 
--TD1_un1_a_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add23 at LC_X12_Y8_N8
--operation mode is arithmetic
 
TD1_un1_a_add23_carry_eqn = (!TD1_un1_a_carry_19 & TD1_un1_a_carry_22) # (TD1_un1_a_carry_19 & TD1L255);
TD1_un1_a_add23 = PD1_a_o_23 $ TD1_un1_b_1_combout[23] $ TD1_un1_a_add23_carry_eqn;
 
--TD1_un1_a_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_23 at LC_X12_Y8_N8
--operation mode is arithmetic
 
TD1_un1_a_carry_23_cout_0 = PD1_a_o_23 & !TD1_un1_b_1_combout[23] & !TD1_un1_a_carry_22 # !PD1_a_o_23 & !TD1_un1_a_carry_22 # !TD1_un1_b_1_combout[23];
TD1_un1_a_carry_23 = CARRY(TD1_un1_a_carry_23_cout_0);
 
--TD1L455 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_23~COUT1_1 at LC_X12_Y8_N8
--operation mode is arithmetic
 
TD1L455_cout_1 = PD1_a_o_23 & !TD1_un1_b_1_combout[23] & !TD1L255 # !PD1_a_o_23 & !TD1L255 # !TD1_un1_b_1_combout[23];
TD1L455 = CARRY(TD1L455_cout_1);
 
 
--FD1_wb_o_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_22 at LC_X25_Y13_N7
--operation mode is normal
 
FD1_wb_o_22 = TC1_wb_mux_ctl_o_0 & F1_dout_22 # DB1_r32_o_22 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_22;
 
--FD1_r_data_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_22 at LC_X25_Y13_N7
--operation mode is normal
 
FD1_r_data_22 = DFFEAS(FD1_wb_o_22, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_22 at LC_X25_Y13_N4
--operation mode is normal
 
ND1_dout_2_a_22 = XD1_mux_fw_1 & !AB1_r32_o_20 # !XD1_mux_fw_1 & !QB1_r32_o_22;
 
 
--SB1_un1_wr_en46_3_combout is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_3_combout at LC_X14_Y9_N6
--operation mode is normal
 
SB1_un1_wr_en46_3_combout = TB1_dout21 & RB1_c_0_d0 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0 # !TB1_dout21 & QC1_dmem_ctl_o_3 # !SB1_wr_en46_0;
 
 
--WB2L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~94 at LC_X13_Y9_N6
--operation mode is normal
 
WB2L1 = SB1_un1_wr_en46_3_combout # RB1_c_0_d0 & !WB2L2 # !RB1_c_0_d0 & !RB1_c_1;
 
 
--WB2L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95 at LC_X13_Y9_N5
--operation mode is normal
 
WB2L2 = SB1_wr_en47 # !WB2L1;
 
 
--CB1_dout_2_14 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_14 at LC_X28_Y4_N4
--operation mode is normal
 
CB1_dout_2_14 = ND1_dout7 & FD1_wb_o_14 # !ND1_dout7 & !ND1_dout_2_a_14;
 
--CB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_14 at LC_X28_Y4_N4
--operation mode is normal
 
CB1_r32_o_14 = DFFEAS(CB1_dout_2_14, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--WB4L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~84 at LC_X14_Y9_N0
--operation mode is normal
 
WB4L1 = SB1_un1_ctl_1_combout # RB1_c_0_d0 & WB4L2 # !RB1_c_0_d0 & !RB1_c_1;
 
 
--WB4L2 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~85 at LC_X14_Y9_N1
--operation mode is normal
 
WB4L2 = !SB1_un1_wr_en46_3_combout & WB4L1;
 
 
--TB1_dout_1_2_a_x[30] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[30] at LC_X20_Y4_N4
--operation mode is normal
 
TB1_dout_1_2_a_x[30] = TB1_dout22 & !CB1_dout_2_14 # !TB1_dout22 & !CB1_dout_2_30;
 
 
--GD1_dout_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_8 at LC_X23_Y6_N7
--operation mode is normal
 
GD1_dout_iv_1_8 = LD1_q_b[8] & FD1_N_20_i_0_s3 # !GD1_dout_iv_1_a[8];
 
 
--PD1_a_o_3_d_a[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[6] at LC_X19_Y11_N3
--operation mode is normal
 
PD1_a_o_3_d_a[6] = PD1_a_o_sn_m2 & !PB1_r32_o_6 # !PD1_a_o_sn_m2 & !AB1_r32_o_4;
 
 
--FD1_wb_o_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_21 at LC_X30_Y5_N5
--operation mode is normal
 
FD1_wb_o_21 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_21 # F1_dout_21 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_21;
 
--FD1_r_data_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_21 at LC_X30_Y5_N5
--operation mode is normal
 
FD1_r_data_21 = DFFEAS(FD1_wb_o_21, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_21 at LC_X21_Y14_N7
--operation mode is normal
 
ND1_dout_2_a_21 = XD1_mux_fw_1 & !AB1_r32_o_19 # !XD1_mux_fw_1 & !QB1_r32_o_21;
 
 
--CB1_dout_2_13 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_13 at LC_X21_Y9_N5
--operation mode is normal
 
CB1_dout_2_13 = ND1_dout7 & FD1_wb_o_13 # !ND1_dout7 & !ND1_dout_2_a_13;
 
--CB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_13 at LC_X21_Y9_N5
--operation mode is normal
 
CB1_r32_o_13 = DFFEAS(CB1_dout_2_13, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_2_a_x[29] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[29] at LC_X21_Y9_N6
--operation mode is normal
 
TB1_dout_1_2_a_x[29] = TB1_dout22 & !CB1_dout_2_13 # !TB1_dout22 & !CB1_dout_2_29;
 
 
--TB1_dout_1_2_a_x[28] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[28] at LC_X27_Y13_N4
--operation mode is normal
 
TB1_dout_1_2_a_x[28] = TB1_dout22 & !CB1_dout_2_12 # !TB1_dout22 & !CB1_dout_2_28;
 
 
--CB1_dout_2_12 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_12 at LC_X27_Y13_N3
--operation mode is normal
 
CB1_dout_2_12 = ND1_dout7 & FD1_wb_o_12 # !ND1_dout7 & !ND1_dout_2_a_12;
 
--CB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_12 at LC_X27_Y13_N3
--operation mode is normal
 
CB1_r32_o_12 = DFFEAS(CB1_dout_2_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_ua_state[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state[1] at LC_X33_Y15_N8
--operation mode is normal
 
M1_ua_state[1]_lut_out = M1_ua_state_i[0] & M1_ua_state[1] & !M1_clk_ctr_equ15_0_a2 # !M1_ua_state_i[0] & M1_ua_state[1] & !M1_clk_ctr_equ15_0_a2 # !M1_rxq1;
M1_ua_state[1] = DFFEAS(M1_ua_state[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--M1_bit_ctr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[1] at LC_X33_Y14_N7
--operation mode is arithmetic
 
M1_bit_ctr[1]_lut_out = M1_bit_ctr[1] $ (M1_bit_ctr_cout[0]);
M1_bit_ctr[1] = DFFEAS(M1_bit_ctr[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_bit_ctr23_i_i, );
 
--M1_bit_ctr_cout[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[1] at LC_X33_Y14_N7
--operation mode is arithmetic
 
M1_bit_ctr_cout[1]_cout_0 = !M1_bit_ctr_cout[0] # !M1_bit_ctr[1];
M1_bit_ctr_cout[1] = CARRY(M1_bit_ctr_cout[1]_cout_0);
 
--M1L41 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[1]~COUT1_1 at LC_X33_Y14_N7
--operation mode is arithmetic
 
M1L41_cout_1 = !M1L21 # !M1_bit_ctr[1];
M1L41 = CARRY(M1L41_cout_1);
 
 
--M1_bit_ctr[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[2] at LC_X33_Y14_N8
--operation mode is normal
 
M1_bit_ctr[2]_lut_out = M1_bit_ctr[2] $ !M1_bit_ctr_cout[1];
M1_bit_ctr[2] = DFFEAS(M1_bit_ctr[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_bit_ctr23_i_i, );
 
 
--M1_bit_ctr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr[0] at LC_X33_Y14_N6
--operation mode is arithmetic
 
M1_bit_ctr[0]_lut_out = M1_bit_ctr[0] $ M1_clk_ctr_equ15_0_a2;
M1_bit_ctr[0] = DFFEAS(M1_bit_ctr[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !M1_bit_ctr23_i_i, );
 
--M1_bit_ctr_cout[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[0] at LC_X33_Y14_N6
--operation mode is arithmetic
 
M1_bit_ctr_cout[0]_cout_0 = M1_bit_ctr[0] & M1_clk_ctr_equ15_0_a2;
M1_bit_ctr_cout[0] = CARRY(M1_bit_ctr_cout[0]_cout_0);
 
--M1L21 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr_cout[0]~COUT1 at LC_X33_Y14_N6
--operation mode is arithmetic
 
M1L21_cout_1 = M1_bit_ctr[0] & M1_clk_ctr_equ15_0_a2;
M1L21 = CARRY(M1L21_cout_1);
 
 
--FD1_wb_o_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_19 at LC_X30_Y15_N4
--operation mode is normal
 
FD1_wb_o_19 = TC1_wb_mux_ctl_o_0 & F1_dout_19 # DB1_r32_o_19 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_19;
 
--FD1_r_data_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_19 at LC_X30_Y15_N4
--operation mode is normal
 
FD1_r_data_19 = DFFEAS(FD1_wb_o_19, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_19 at LC_X22_Y15_N1
--operation mode is normal
 
ND1_dout_2_a_19 = XD1_mux_fw_1 & !AB1_r32_o_17 # !XD1_mux_fw_1 & !QB1_r32_o_19;
 
 
--CB1_dout_2_11 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_11 at LC_X21_Y15_N5
--operation mode is normal
 
CB1_dout_2_11 = ND1_dout7 & FD1_wb_o_11 # !ND1_dout7 & !ND1_dout_2_a_11;
 
--CB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_11 at LC_X21_Y15_N5
--operation mode is normal
 
CB1_r32_o_11 = DFFEAS(CB1_dout_2_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TB1_dout_1_2_a_x[27] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[27] at LC_X21_Y15_N6
--operation mode is normal
 
TB1_dout_1_2_a_x[27] = TB1_dout22 & !CB1_dout_2_11 # !TB1_dout22 & !CB1_dout_2_27;
 
 
--FD1_wb_o_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_18 at LC_X30_Y9_N7
--operation mode is normal
 
FD1_wb_o_18 = TC1_wb_mux_ctl_o_0 & F1_dout_18 # DB1_r32_o_18 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_18;
 
--FD1_r_data_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_18 at LC_X30_Y9_N7
--operation mode is normal
 
FD1_r_data_18 = DFFEAS(FD1_wb_o_18, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_18 at LC_X22_Y12_N0
--operation mode is normal
 
ND1_dout_2_a_18 = XD1_mux_fw_1 & !AB1_r32_o_16 # !XD1_mux_fw_1 & !QB1_r32_o_18;
 
 
--TB1_dout_1_2_a_x[26] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[26] at LC_X29_Y6_N7
--operation mode is normal
 
TB1_dout_1_2_a_x[26] = TB1_dout22 & !CB1_dout_2_10 # !TB1_dout22 & !CB1_dout_2_26;
 
 
--CB1_dout_2_10 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_10 at LC_X29_Y15_N9
--operation mode is normal
 
CB1_dout_2_10 = ND1_dout7 & FD1_wb_o_10 # !ND1_dout7 & !ND1_dout_2_a_10;
 
--CB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_10 at LC_X29_Y15_N9
--operation mode is normal
 
CB1_r32_o_10 = DFFEAS(CB1_dout_2_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_17 at LC_X26_Y6_N6
--operation mode is normal
 
FD1_wb_o_17 = TC1_wb_mux_ctl_o_0 & F1_dout_17 # DB1_r32_o_17 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_17;
 
--FD1_r_data_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_17 at LC_X26_Y6_N6
--operation mode is normal
 
FD1_r_data_17 = DFFEAS(FD1_wb_o_17, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_17 at LC_X21_Y16_N5
--operation mode is normal
 
ND1_dout_2_a_17 = XD1_mux_fw_1 & !AB1_r32_o_15 # !XD1_mux_fw_1 & !QB1_r32_o_17;
 
 
--TB1_dout_1_2_a_x[25] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[25] at LC_X25_Y3_N5
--operation mode is normal
 
TB1_dout_1_2_a_x[25] = TB1_dout22 & !CB1_dout_2_9 # !TB1_dout22 & !CB1_dout_2_25;
 
 
--CB1_dout_2_9 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_9 at LC_X25_Y3_N3
--operation mode is normal
 
CB1_dout_2_9 = ND1_dout7 & FD1_wb_o_9 # !ND1_dout7 & !ND1_dout_2_a_9;
 
--CB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_9 at LC_X25_Y3_N3
--operation mode is normal
 
CB1_r32_o_9 = DFFEAS(CB1_dout_2_9, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_33_i_m_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[33] at LC_X8_Y7_N1
--operation mode is normal
 
VD1_hilo_33_i_m_a[33] = VD1_addnop2 & !VD1_un50_hilo_add1 # !VD1_addnop2 & !VD1_un59_hilo_add1;
 
 
--VD1_hilo_15_1[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_1[56] at LC_X7_Y4_N4
--operation mode is normal
 
VD1_hilo_15_1[56] = VD1_hilo[0] $ (VD1_sub_or_yn);
 
 
--VD1_hilo_22_a[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[33] at LC_X7_Y4_N2
--operation mode is normal
 
VD1_hilo_22_a[33] = VD1_hilo[0] & VD1_sign & !VD1_hilo_34 # !VD1_sign & !VD1_un59_hilo_add2 # !VD1_hilo[0] & !VD1_hilo_34;
 
 
--VD1_hilo_15_2[33] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[33] at LC_X7_Y4_N0
--operation mode is normal
 
VD1_hilo_15_2[33] = VD1_sub_or_yn & VD1_un59_hilo_add2 # !VD1_sub_or_yn & VD1_un50_hilo_add2;
 
 
--FD1_wb_o_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_16 at LC_X25_Y4_N2
--operation mode is normal
 
FD1_wb_o_16 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_16 # F1_dout_16 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_16;
 
--FD1_r_data_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_16 at LC_X25_Y4_N2
--operation mode is normal
 
FD1_r_data_16 = DFFEAS(FD1_wb_o_16, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_16 at LC_X21_Y5_N1
--operation mode is normal
 
ND1_dout_2_a_16 = XD1_mux_fw_1 & !AB1_r32_o_14 # !XD1_mux_fw_1 & !QB1_r32_o_16;
 
 
--TB1_dout_1_2_a_x[24] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[24] at LC_X29_Y5_N8
--operation mode is normal
 
TB1_dout_1_2_a_x[24] = TB1_dout22 & !CB1_dout_2_8 # !TB1_dout22 & !CB1_dout_2_24;
 
 
--VD1_hilo_24_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add0 at LC_X8_Y5_N4
--operation mode is arithmetic
 
VD1_hilo_24_add0 = VD1_hilo_31 $ VD1_op2_reged[0];
 
--VD1_hilo_24_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_0 at LC_X8_Y5_N4
--operation mode is arithmetic
 
VD1_hilo_24_carry_0 = CARRY(VD1_hilo_31 & VD1_op2_reged[0]);
 
 
--VD1_hilo_33_i_m[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[32] at LC_X8_Y7_N3
--operation mode is normal
 
VD1_hilo_33_i_m[32] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[32] # !VD1_hilo_33_1[64] & !VD1_hilo[32];
 
 
--VD1_hilo_37_iv_2_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[32] at LC_X8_Y7_N5
--operation mode is normal
 
VD1_hilo_37_iv_2_a[32] = VD1_hilo[0] & VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[32] # !VD1_hilo[0] & VD1_hilo_0_sqmuxa # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[32];
 
 
--VD1_hilo_37_iv_0_1[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[0] at LC_X6_Y13_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_1[0] = VD1_hilo[0] & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo[0] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_37_iv_0_1_a[0];
 
 
--VD1_hilo_24_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add32 at LC_X8_Y2_N6
--operation mode is normal
 
VD1_hilo_24_add32_carry_eqn = (!VD1_hilo_24_carry_30 & VD1_hilo_24_carry_31) # (VD1_hilo_24_carry_30 & VD1L335);
VD1_hilo_24_add32 = VD1_hilo_63 $ VD1_hilo_24_add32_carry_eqn $ !VD1_un1_op2_reged_1_combout[32];
 
 
--KB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_30 at LC_X23_Y8_N7
--operation mode is normal
 
KB1_r32_o_30_lut_out = DD1_pc_next_0_iv_1_30 # DD1_un1_pc_next46_0 & DD1_un1_pc_add30;
KB1_r32_o_30 = DFFEAS(KB1_r32_o_30_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_31 at LC_X23_Y8_N8
--operation mode is normal
 
KB1_r32_o_31_lut_out = G1_BUS24839_m[31] # DD1_un1_pc_next46_0 & DD1_un1_pc_add31 # !DD1_pc_next_0_iv_a_0;
KB1_r32_o_31 = DFFEAS(KB1_r32_o_31_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RD1_r32_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_29 at LC_X23_Y3_N6
--operation mode is arithmetic
 
RD1_r32_o_29_carry_eqn = (!RD1_r32_o_cout[25] & RD1_r32_o_cout[27]) # (RD1_r32_o_cout[25] & RD1L901);
RD1_r32_o_29_lut_out = KB1_r32_o_29 $ (KB1_r32_o_28 & RD1_r32_o_29_carry_eqn);
RD1_r32_o_29 = DFFEAS(RD1_r32_o_29_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[29] at LC_X23_Y3_N6
--operation mode is arithmetic
 
RD1_r32_o_cout[29]_cout_0 = !RD1_r32_o_cout[27] # !KB1_r32_o_28 # !KB1_r32_o_29;
RD1_r32_o_cout[29] = CARRY(RD1_r32_o_cout[29]_cout_0);
 
--RD1L311 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[29]~COUT1_21 at LC_X23_Y3_N6
--operation mode is arithmetic
 
RD1L311_cout_1 = !RD1L901 # !KB1_r32_o_28 # !KB1_r32_o_29;
RD1L311 = CARRY(RD1L311_cout_1);
 
 
--PD1_a_o_3_d_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[31] at LC_X19_Y3_N6
--operation mode is normal
 
PD1_a_o_3_d_a[31] = PD1_a_o_sn_m2 & !PB1_r32_o_31 # !PD1_a_o_sn_m2 & !AB1_r32_o_29;
 
 
--GD1_dout_iv_1_31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_31 at LC_X24_Y4_N8
--operation mode is normal
 
GD1_dout_iv_1_31 = FD1_N_20_i_0_s3 & LD1_q_b[31] # !GD1_dout_iv_1_a[31];
 
 
--F1_dout_31 is mips_sys:isys|mips_dvc:imips_dvc|dout_31 at LC_X27_Y4_N6
--operation mode is normal
 
F1_dout_31_lut_out = K1_cntr_31 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[31] # !K1_cntr_31 & F1_dout_0_0_a3_3[0] & F1_cmd[31];
F1_dout_31 = DFFEAS(F1_dout_31_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_31 at LC_X27_Y4_N9
--operation mode is normal
 
BB1_r32_o_31_lut_out = AB1_r32_o_29;
BB1_r32_o_31 = DFFEAS(BB1_r32_o_31_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_30 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_30 at LC_X22_Y8_N4
--operation mode is normal
 
QB1_dout_iv_30 = GD1_dout_iv_1_30 # GD1_dout7_0_a2 & FD1_wb_o_30;
 
--QB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_30 at LC_X22_Y8_N4
--operation mode is normal
 
QB1_r32_o_30 = DFFEAS(QB1_dout_iv_30, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_30 at LC_X32_Y13_N2
--operation mode is normal
 
FD1_wb_o_30 = TC1_wb_mux_ctl_o_0 & F1_dout_30 # DB1_r32_o_30 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_30;
 
--FD1_r_data_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_30 at LC_X32_Y13_N2
--operation mode is normal
 
FD1_r_data_30 = DFFEAS(FD1_wb_o_30, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[29] at LC_X15_Y6_N7
--operation mode is normal
 
PD1_a_o_a[29] = SC1_muxa_ctl_o_1 & !FB1_r32_o_29 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_29;
 
 
--PD1_a_o_3_Z[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[29] at LC_X22_Y6_N6
--operation mode is normal
 
SD1_r32_o_29_qfbk = SD1_r32_o_29;
PD1_a_o_3_Z[29] = PD1_a_o_3_s[0] & SD1_r32_o_29_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[29];
 
--SD1_r32_o_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_29 at LC_X22_Y6_N6
--operation mode is normal
 
SD1_r32_o_29 = DFFEAS(PD1_a_o_3_Z[29], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_29, , , VCC);
 
 
--TD1_lt_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_27 at LC_X16_Y7_N1
--operation mode is arithmetic
 
TD1_lt_27_cout_0 = VD1_b_o_iv_27 & PD1_a_o_27 & !TD1_lt_26 # !VD1_b_o_iv_27 & PD1_a_o_27 # !TD1_lt_26;
TD1_lt_27 = CARRY(TD1_lt_27_cout_0);
 
--TD1L291 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_27~COUT1_1 at LC_X16_Y7_N1
--operation mode is arithmetic
 
TD1L291_cout_1 = VD1_b_o_iv_27 & PD1_a_o_27 & !TD1L091 # !VD1_b_o_iv_27 & PD1_a_o_27 # !TD1L091;
TD1L291 = CARRY(TD1L291_cout_1);
 
 
--TD1_sum_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_28 at LC_X15_Y6_N2
--operation mode is arithmetic
 
TD1_sum_carry_28_cout_0 = VD1_b_o_iv_28 & PD1_a_o_28 & !TD1_sum_carry_27 # !VD1_b_o_iv_28 & PD1_a_o_28 # !TD1_sum_carry_27;
TD1_sum_carry_28 = CARRY(TD1_sum_carry_28_cout_0);
 
--TD1L934 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_28~COUT1_1 at LC_X15_Y6_N2
--operation mode is arithmetic
 
TD1L934_cout_1 = VD1_b_o_iv_28 & PD1_a_o_28 & !TD1L734 # !VD1_b_o_iv_28 & PD1_a_o_28 # !TD1L734;
TD1L934 = CARRY(TD1L934_cout_1);
 
 
--ND1_dout_2_a_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_30 at LC_X20_Y4_N1
--operation mode is normal
 
ND1_dout_2_a_30 = XD1_mux_fw_1 & !AB1_r32_o_28 # !XD1_mux_fw_1 & !QB1_r32_o_30;
 
 
--ND1_dout_2_a_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_31 at LC_X27_Y4_N4
--operation mode is normal
 
ND1_dout_2_a_31 = XD1_mux_fw_1 & !AB1_r32_o_29 # !XD1_mux_fw_1 & !QB1_r32_o_31;
 
 
--FD1_wb_o_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_28 at LC_X26_Y8_N9
--operation mode is normal
 
FD1_wb_o_28 = TC1_wb_mux_ctl_o_0 & F1_dout_28 # DB1_r32_o_28 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_28;
 
--FD1_r_data_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_28 at LC_X26_Y8_N9
--operation mode is normal
 
FD1_r_data_28 = DFFEAS(FD1_wb_o_28, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_28 at LC_X26_Y8_N8
--operation mode is normal
 
ND1_dout_2_a_28 = XD1_mux_fw_1 & !AB1_r32_o_26 # !XD1_mux_fw_1 & !QB1_r32_o_28;
 
 
--CB1_dout_2_27 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_27 at LC_X21_Y15_N9
--operation mode is normal
 
CB1_dout_2_27 = ND1_dout7 & FD1_wb_o_27 # !ND1_dout7 & !ND1_dout_2_a_27;
 
--CB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_27 at LC_X21_Y15_N9
--operation mode is normal
 
CB1_r32_o_27 = DFFEAS(CB1_dout_2_27, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_29 at LC_X26_Y5_N8
--operation mode is normal
 
FD1_wb_o_29 = TC1_wb_mux_ctl_o_0 & F1_dout_29 # DB1_r32_o_29 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_29;
 
--FD1_r_data_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_29 at LC_X26_Y5_N8
--operation mode is normal
 
FD1_r_data_29 = DFFEAS(FD1_wb_o_29, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_29 at LC_X21_Y9_N7
--operation mode is normal
 
ND1_dout_2_a_29 = XD1_mux_fw_1 & !AB1_r32_o_27 # !XD1_mux_fw_1 & !QB1_r32_o_29;
 
 
--CB1_dout_2_26 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_26 at LC_X29_Y6_N3
--operation mode is normal
 
CB1_dout_2_26 = ND1_dout7 & FD1_wb_o_26 # !ND1_dout7 & !ND1_dout_2_a_26;
 
--CB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_26 at LC_X29_Y6_N3
--operation mode is normal
 
CB1_r32_o_26 = DFFEAS(CB1_dout_2_26, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_24 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_24 at LC_X29_Y5_N7
--operation mode is normal
 
CB1_dout_2_24 = ND1_dout7 & FD1_wb_o_24 # !ND1_dout7 & !ND1_dout_2_a_24;
 
--CB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_24 at LC_X29_Y5_N7
--operation mode is normal
 
CB1_r32_o_24 = DFFEAS(CB1_dout_2_24, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_25 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_25 at LC_X25_Y3_N7
--operation mode is normal
 
CB1_dout_2_25 = ND1_dout7 & FD1_wb_o_25 # !ND1_dout7 & !ND1_dout_2_a_25;
 
--CB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_25 at LC_X25_Y3_N7
--operation mode is normal
 
CB1_r32_o_25 = DFFEAS(CB1_dout_2_25, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CB1_dout_2_15 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_15 at LC_X27_Y3_N2
--operation mode is normal
 
CB1_dout_2_15 = ND1_dout7 & FD1_wb_o_15 # !ND1_dout7 & !ND1_dout_2_a_15;
 
--CB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_15 at LC_X27_Y3_N2
--operation mode is normal
 
CB1_r32_o_15 = DFFEAS(CB1_dout_2_15, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_ua_state_i[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|ua_state_i[0] at LC_X33_Y15_N2
--operation mode is normal
 
M1_ua_state_i[0]_lut_out = !M1_ua_state[4] & M1_ua_state_i[0] # !M1_rxq1;
M1_ua_state_i[0] = DFFEAS(M1_ua_state_i[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--M1_clk_ctr27_i_0_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a at LC_X33_Y16_N2
--operation mode is normal
 
M1_clk_ctr27_i_0_a = !M1_clk_ctr_0 # !M1_un1_clk_ctr_equ0_0_a2 # !M1_clk_ctr27_i_0_a5_5 # !M1_clk_ctr27_i_0_a5_4;
 
 
--AD1_CurrState_Sreg0_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_3 at LC_X30_Y16_N3
--operation mode is normal
 
AD1_CurrState_Sreg0_3_lut_out = AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & !WB35L1 & !WB45L1 & WB55L1;
AD1_CurrState_Sreg0_3 = DFFEAS(AD1_CurrState_Sreg0_3_lut_out, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--DD1_pc_next_2_sqmuxa_1_i_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_1_i_a2 at LC_X27_Y11_N6
--operation mode is normal
 
DD1_pc_next_2_sqmuxa_1_i_a2 = !AD1_CurrState_Sreg0_5 & AD1_pc_prectl_1_0_i_a2_0_a2_1 & AD1_CurrState_Sreg0_3 # AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
 
 
--DD1_pc_next_1_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_1_sqmuxa_0_a4 at LC_X27_Y11_N5
--operation mode is normal
 
DD1_pc_next_1_sqmuxa_0_a4 = !HC1_pc_gen_ctl_o_2 & HC1_pc_gen_ctl_o_0 & !HC1_pc_gen_ctl_o_1 & DD1_pc_next_2_sqmuxa_1_i_a2;
 
 
--DD1_pc_next_0_sqmuxa_0_a4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_sqmuxa_0_a4 at LC_X27_Y11_N7
--operation mode is normal
 
DD1_pc_next_0_sqmuxa_0_a4 = HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_0 & HC1_pc_gen_ctl_o_1 & DD1_pc_next_2_sqmuxa_1_i_a2;
 
 
--HD1_dout_iv_1_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_2 at LC_X20_Y10_N3
--operation mode is normal
 
HD1_dout_iv_1_2 = LD2_q_b[2] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[2];
 
 
--DD1_un1_pc_prectl_1_i_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_i_a[2] at LC_X27_Y11_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_i_a[2] = AD1_pc_prectl_1_0_i_a2_0_a2_1 & !AD1_CurrState_Sreg0_5 & HC1_pc_gen_ctl_o_2 & !HC1_pc_gen_ctl_o_0;
 
 
--BD1_res_7_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_7_0 at LC_X23_Y11_N1
--operation mode is normal
 
BC1_cmp_ctl_o_0_qfbk = BC1_cmp_ctl_o_0;
BD1_res_7_0 = BC1_cmp_ctl_o_0_qfbk & BD1_res_7_0_a # !BC1_cmp_ctl_o_0_qfbk & BD1_res_3_0;
 
--BC1_cmp_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_0 at LC_X23_Y11_N1
--operation mode is normal
 
BC1_cmp_ctl_o_0 = DFFEAS(BD1_res_7_0, GLOBAL(E1__clk0), VCC, , C1_G_504, WB34L1, , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--HD1_dout_iv_1_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_3 at LC_X26_Y7_N3
--operation mode is normal
 
HD1_dout_iv_1_3 = FD1_N_18_i_0_s3 & LD2_q_b[3] # !HD1_dout_iv_1_a[3];
 
 
--DD1_un1_pc_prectl_1_0_a3[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a3[0] at LC_X23_Y11_N2
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a3[0] = !HC1_pc_gen_ctl_o_0 & AD1_pc_prectl_1_0_i_a2_0_a2_1 & DD1_un1_pc_prectl_1_0_a3_a[0] & BD1_res_7_0;
 
 
--HD1_dout_iv_1_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_6 at LC_X19_Y11_N1
--operation mode is normal
 
HD1_dout_iv_1_6 = LD2_q_b[6] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[6];
 
 
--HD1_dout_iv_1_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_7 at LC_X19_Y9_N3
--operation mode is normal
 
HD1_dout_iv_1_7 = FD1_N_18_i_0_s3 & LD2_q_b[7] # !HD1_dout_iv_1_a[7];
 
 
--HD1_dout_iv_1_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_8 at LC_X19_Y8_N6
--operation mode is normal
 
HD1_dout_iv_1_8 = FD1_N_18_i_0_s3 & LD2_q_b[8] # !HD1_dout_iv_1_a[8];
 
 
--HD1_dout_iv_1_9 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_9 at LC_X19_Y10_N8
--operation mode is normal
 
HD1_dout_iv_1_9 = LD2_q_b[9] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[9];
 
 
--FB1_res_7_0_0_10 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_10 at LC_X21_Y11_N8
--operation mode is normal
 
FB1_res_7_0_0_10 = ED1_r32_o_8 & CD1_res_7_0_0_o3_0 # CD1_res_7_0_0_a2_0 & ED1_r32_o_10 # !ED1_r32_o_8 & CD1_res_7_0_0_a2_0 & ED1_r32_o_10;
 
--FB1_r32_o_0_10 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_10 at LC_X21_Y11_N8
--operation mode is normal
 
FB1_r32_o_0_10 = DFFEAS(FB1_res_7_0_0_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_10 at LC_X28_Y14_N2
--operation mode is normal
 
FD1_wb_o_10 = TC1_wb_mux_ctl_o_0 & F1_dout_10 # DB1_r32_o_10 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_10;
 
--FD1_r_data_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_10 at LC_X28_Y14_N2
--operation mode is normal
 
FD1_r_data_10 = DFFEAS(FD1_wb_o_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_10 at LC_X19_Y12_N3
--operation mode is normal
 
HD1_dout_iv_1_10 = LD2_q_b[10] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[10];
 
 
--FB1_res_7_0_0_11 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_11 at LC_X22_Y11_N6
--operation mode is normal
 
FB1_res_7_0_0_11 = CD1_res_7_0_0_o3_0 & ED1_r32_o_9 # CD1_res_7_0_0_a2_0 & ED1_r32_o_11 # !CD1_res_7_0_0_o3_0 & CD1_res_7_0_0_a2_0 & ED1_r32_o_11;
 
--FB1_r32_o_0_11 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_11 at LC_X22_Y11_N6
--operation mode is normal
 
FB1_r32_o_0_11 = DFFEAS(FB1_res_7_0_0_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_11 at LC_X28_Y14_N8
--operation mode is normal
 
FD1_wb_o_11 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_11 # F1_dout_11 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_11;
 
--FD1_r_data_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_11 at LC_X28_Y14_N8
--operation mode is normal
 
FD1_r_data_11 = DFFEAS(FD1_wb_o_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_11 at LC_X22_Y10_N6
--operation mode is normal
 
HD1_dout_iv_1_11 = FD1_N_18_i_0_s3 & LD2_q_b[11] # !HD1_dout_iv_1_a[11];
 
 
--FB1_res_7_0_0_12 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_12 at LC_X21_Y11_N2
--operation mode is normal
 
FB1_res_7_0_0_12 = ED1_r32_o_12 & CD1_res_7_0_0_a2_0 # CD1_res_7_0_0_o3_0 & ED1_r32_o_10 # !ED1_r32_o_12 & CD1_res_7_0_0_o3_0 & ED1_r32_o_10;
 
--FB1_r32_o_0_12 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_12 at LC_X21_Y11_N2
--operation mode is normal
 
FB1_r32_o_0_12 = DFFEAS(FB1_res_7_0_0_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_12 at LC_X27_Y8_N4
--operation mode is normal
 
FD1_wb_o_12 = TC1_wb_mux_ctl_o_0 & F1_dout_12 # DB1_r32_o_12 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_12;
 
--FD1_r_data_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_12 at LC_X27_Y8_N4
--operation mode is normal
 
FD1_r_data_12 = DFFEAS(FD1_wb_o_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_12 at LC_X23_Y12_N1
--operation mode is normal
 
HD1_dout_iv_1_12 = FD1_N_18_i_0_s3 & LD2_q_b[12] # !HD1_dout_iv_1_a[12];
 
 
--FD1_wb_o_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_23 at LC_X29_Y4_N6
--operation mode is normal
 
FD1_wb_o_23 = TC1_wb_mux_ctl_o_0 & F1_dout_23 # DB1_r32_o_23 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_23;
 
--FD1_r_data_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_23 at LC_X29_Y4_N6
--operation mode is normal
 
FD1_r_data_23 = DFFEAS(FD1_wb_o_23, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_23 at LC_X29_Y3_N8
--operation mode is normal
 
ND1_dout_2_a_23 = XD1_mux_fw_1 & !AB1_r32_o_21 # !XD1_mux_fw_1 & !QB1_r32_o_23;
 
 
--TB1_dout_1_2_a_x[31] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl|dout_1_2_a_x[31] at LC_X27_Y3_N1
--operation mode is normal
 
TB1_dout_1_2_a_x[31] = TB1_dout22 & !CB1_dout_2_15 # !TB1_dout22 & !CB1_dout_2_31;
 
 
--YB1_wb_mux_1_0_0_a3_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|wb_mux_1_0_0_a3_a_x[0] at LC_X24_Y19_N8
--operation mode is normal
 
YB1_wb_mux_1_0_0_a3_a_x[0] = KE1_q_a[2] & !KE1_q_a[4] # !KE1_q_a[3];
 
 
--GD1_dout_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[9] at LC_X25_Y6_N2
--operation mode is normal
 
GD1_dout_iv_1_a[9] = FD1_r_data_9 & !FD1_N_16_i_0_s2 & !AB1_r32_o_7 # !ZD1_mux_fw_1 # !FD1_r_data_9 & !AB1_r32_o_7 # !ZD1_mux_fw_1;
 
 
--F1_cmd[9] is mips_sys:isys|mips_dvc:imips_dvc|cmd[9] at LC_X28_Y13_N8
--operation mode is normal
 
F1_cmd[9]_lut_out = CB1_r32_o_9;
F1_cmd[9] = DFFEAS(F1_cmd[9]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--QB1_dout_iv_11 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_11 at LC_X22_Y7_N7
--operation mode is normal
 
QB1_dout_iv_11 = GD1_dout_iv_1_11 # FD1_wb_o_11 & GD1_dout7_0_a2;
 
--QB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_11 at LC_X22_Y7_N7
--operation mode is normal
 
QB1_r32_o_11 = DFFEAS(QB1_dout_iv_11, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_13 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_13 at LC_X27_Y6_N9
--operation mode is normal
 
QB1_dout_iv_13 = GD1_dout_iv_1_13 # GD1_dout7_0_a2 & FD1_wb_o_13;
 
--QB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_13 at LC_X27_Y6_N9
--operation mode is normal
 
QB1_r32_o_13 = DFFEAS(QB1_dout_iv_13, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_13 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_13 at LC_X25_Y10_N8
--operation mode is normal
 
FB1_res_7_0_0_13 = CD1_res_7_0_0_a2_0 & ED1_r32_o_13 # ED1_r32_o_11 & CD1_res_7_0_0_o3_0 # !CD1_res_7_0_0_a2_0 & ED1_r32_o_11 & CD1_res_7_0_0_o3_0;
 
--FB1_r32_o_0_13 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_13 at LC_X25_Y10_N8
--operation mode is normal
 
FB1_r32_o_0_13 = DFFEAS(FB1_res_7_0_0_13, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_13 at LC_X27_Y6_N2
--operation mode is normal
 
FD1_wb_o_13 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_13 # F1_dout_13 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_13;
 
--FD1_r_data_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_13 at LC_X27_Y6_N2
--operation mode is normal
 
FD1_r_data_13 = DFFEAS(FD1_wb_o_13, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_12 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_12 at LC_X26_Y11_N7
--operation mode is normal
 
QB1_dout_iv_12 = GD1_dout_iv_1_12 # GD1_dout7_0_a2 & FD1_wb_o_12;
 
--QB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_12 at LC_X26_Y11_N7
--operation mode is normal
 
QB1_r32_o_12 = DFFEAS(QB1_dout_iv_12, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_14 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_14 at LC_X22_Y8_N2
--operation mode is normal
 
QB1_dout_iv_14 = GD1_dout_iv_1_14 # FD1_wb_o_14 & GD1_dout7_0_a2;
 
--QB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_14 at LC_X22_Y8_N2
--operation mode is normal
 
QB1_r32_o_14 = DFFEAS(QB1_dout_iv_14, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_14 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_14 at LC_X25_Y10_N5
--operation mode is normal
 
FB1_res_7_0_0_14 = CD1_res_7_0_0_a2_0 & ED1_r32_o_14 # ED1_r32_o_12 & CD1_res_7_0_0_o3_0 # !CD1_res_7_0_0_a2_0 & ED1_r32_o_12 & CD1_res_7_0_0_o3_0;
 
--FB1_r32_o_0_14 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_14 at LC_X25_Y10_N5
--operation mode is normal
 
FB1_r32_o_0_14 = DFFEAS(FB1_res_7_0_0_14, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_14 at LC_X21_Y6_N3
--operation mode is normal
 
FD1_wb_o_14 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_14 # F1_dout_14 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_14;
 
--FD1_r_data_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_14 at LC_X21_Y6_N3
--operation mode is normal
 
FD1_r_data_14 = DFFEAS(FD1_wb_o_14, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_1 at LC_X25_Y7_N2
--operation mode is normal
 
HD1_dout_iv_1_1 = FD1_N_18_i_0_s3 & LD2_q_b[1] # !HD1_dout_iv_1_a[1];
 
 
--HD1_dout_iv_1_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_0 at LC_X26_Y4_N8
--operation mode is normal
 
HD1_dout_iv_1_0 = FD1_N_18_i_0_s3 & LD2_q_b[0] # !HD1_dout_iv_1_a[0];
 
 
--QB1_dout_iv_21 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_21 at LC_X20_Y7_N3
--operation mode is normal
 
QB1_dout_iv_21 = GD1_dout_iv_1_21 # FD1_wb_o_21 & GD1_dout7_0_a2;
 
--QB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_21 at LC_X20_Y7_N3
--operation mode is normal
 
QB1_r32_o_21 = DFFEAS(QB1_dout_iv_21, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_21 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_21 at LC_X22_Y9_N2
--operation mode is normal
 
FB1_res_7_0_0_21 = CD1_res_7_0_0_a3_0 # ED1_r32_o_5 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_18;
 
--FB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_21 at LC_X22_Y9_N2
--operation mode is normal
 
FB1_r32_o_21 = DFFEAS(FB1_res_7_0_0_21, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_22 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_22 at LC_X24_Y7_N5
--operation mode is normal
 
QB1_dout_iv_22 = GD1_dout_iv_1_22 # GD1_dout7_0_a2 & FD1_wb_o_22;
 
--QB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_22 at LC_X24_Y7_N5
--operation mode is normal
 
QB1_r32_o_22 = DFFEAS(QB1_dout_iv_22, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_22 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_22 at LC_X23_Y16_N5
--operation mode is normal
 
FB1_res_7_0_0_22 = CD1_res_7_0_0_a3_0 # ED1_r32_o_6 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_19;
 
--FB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_22 at LC_X23_Y16_N5
--operation mode is normal
 
FB1_r32_o_22 = DFFEAS(FB1_res_7_0_0_22, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_25 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_25 at LC_X25_Y6_N8
--operation mode is normal
 
QB1_dout_iv_25 = GD1_dout_iv_1_25 # FD1_wb_o_25 & GD1_dout7_0_a2;
 
--QB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_25 at LC_X25_Y6_N8
--operation mode is normal
 
QB1_r32_o_25 = DFFEAS(QB1_dout_iv_25, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_25 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_25 at LC_X24_Y13_N6
--operation mode is normal
 
FB1_res_7_0_0_25 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_9 # !CD1_res_7_0_0_a_22;
 
--FB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_25 at LC_X24_Y13_N6
--operation mode is normal
 
FB1_r32_o_25 = DFFEAS(FB1_res_7_0_0_25, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_25 at LC_X25_Y6_N0
--operation mode is normal
 
FD1_wb_o_25 = TC1_wb_mux_ctl_o_0 & F1_dout_25 # DB1_r32_o_25 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_25;
 
--FD1_r_data_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_25 at LC_X25_Y6_N0
--operation mode is normal
 
FD1_r_data_25 = DFFEAS(FD1_wb_o_25, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_26 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_26 at LC_X20_Y8_N4
--operation mode is normal
 
QB1_dout_iv_26 = GD1_dout_iv_1_26 # FD1_wb_o_26 & GD1_dout7_0_a2;
 
--QB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_26 at LC_X20_Y8_N4
--operation mode is normal
 
QB1_r32_o_26 = DFFEAS(QB1_dout_iv_26, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_26 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_26 at LC_X23_Y14_N5
--operation mode is normal
 
FB1_res_7_0_0_26 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_10 # !CD1_res_7_0_0_a_23;
 
--FB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_26 at LC_X23_Y14_N5
--operation mode is normal
 
FB1_r32_o_26 = DFFEAS(FB1_res_7_0_0_26, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_26 at LC_X29_Y7_N6
--operation mode is normal
 
FD1_wb_o_26 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_26 # F1_dout_26 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_26;
 
--FD1_r_data_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_26 at LC_X29_Y7_N6
--operation mode is normal
 
FD1_r_data_26 = DFFEAS(FD1_wb_o_26, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_29 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_29 at LC_X26_Y5_N9
--operation mode is normal
 
QB1_dout_iv_29 = GD1_dout_iv_1_29 # FD1_wb_o_29 & GD1_dout7_0_a2;
 
--QB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_29 at LC_X26_Y5_N9
--operation mode is normal
 
QB1_r32_o_29 = DFFEAS(QB1_dout_iv_29, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_29 at LC_X23_Y16_N7
--operation mode is normal
 
FB1_r32_o_29_lut_out = CD1_res_7_0_0_a3_0 # ED1_r32_o_13 & CD1_res_7_0_0_a2_16;
FB1_r32_o_29 = DFFEAS(FB1_r32_o_29_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_17 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_17 at LC_X26_Y6_N9
--operation mode is normal
 
QB1_dout_iv_17 = GD1_dout_iv_1_17 # FD1_wb_o_17 & GD1_dout7_0_a2;
 
--QB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_17 at LC_X26_Y6_N9
--operation mode is normal
 
QB1_r32_o_17 = DFFEAS(QB1_dout_iv_17, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_17 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_17 at LC_X23_Y15_N8
--operation mode is normal
 
FB1_res_7_0_0_17 = ED1_r32_o_1 & CD1_res_7_0_0_a2_16 # CD1_res_7_0_0_a_14 & ED1_r32_o_15 # !ED1_r32_o_1 & CD1_res_7_0_0_a_14 & ED1_r32_o_15;
 
--FB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_17 at LC_X23_Y15_N8
--operation mode is normal
 
FB1_r32_o_17 = DFFEAS(FB1_res_7_0_0_17, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_18 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_18 at LC_X21_Y8_N0
--operation mode is normal
 
QB1_dout_iv_18 = GD1_dout_iv_1_18 # FD1_wb_o_18 & GD1_dout7_0_a2;
 
--QB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_18 at LC_X21_Y8_N0
--operation mode is normal
 
QB1_r32_o_18 = DFFEAS(QB1_dout_iv_18, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_18 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_18 at LC_X22_Y12_N2
--operation mode is normal
 
FB1_res_7_0_0_18 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_2 # !CD1_res_7_0_0_a_15;
 
--FB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_18 at LC_X22_Y12_N2
--operation mode is normal
 
FB1_r32_o_18 = DFFEAS(FB1_res_7_0_0_18, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_37_iv_0_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[8] at LC_X6_Y16_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_a[8] = VD1_add1 & !VD1_un134_hilo_combout[8] # !VD1_add1 & !VD1_hilo_8;
 
 
--VD1_finish_0_sqmuxa_i is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish_0_sqmuxa_i at LC_X2_Y15_N7
--operation mode is normal
 
VD1_finish_0_sqmuxa_i = VD1_rdy_0_sqmuxa # VD1_addnop2110 & VD1_hilo_4_sqmuxa_0 # !sys_rst;
 
 
--VD1_un50_hilo_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add9 at LC_X10_Y4_N3
--operation mode is arithmetic
 
VD1_un50_hilo_add9_carry_eqn = (!VD1_un50_hilo_carry_5 & VD1_un50_hilo_carry_8) # (VD1_un50_hilo_carry_5 & VD1L8171);
VD1_un50_hilo_add9 = VD1_hilo_41 $ VD1_nop2_reged[9] $ VD1_un50_hilo_add9_carry_eqn;
 
--VD1_un50_hilo_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_9 at LC_X10_Y4_N3
--operation mode is arithmetic
 
VD1_un50_hilo_carry_9_cout_0 = VD1_hilo_41 & !VD1_nop2_reged[9] & !VD1_un50_hilo_carry_8 # !VD1_hilo_41 & !VD1_un50_hilo_carry_8 # !VD1_nop2_reged[9];
VD1_un50_hilo_carry_9 = CARRY(VD1_un50_hilo_carry_9_cout_0);
 
--VD1L0271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_9~COUT1_1 at LC_X10_Y4_N3
--operation mode is arithmetic
 
VD1L0271_cout_1 = VD1_hilo_41 & !VD1_nop2_reged[9] & !VD1L8171 # !VD1_hilo_41 & !VD1L8171 # !VD1_nop2_reged[9];
VD1L0271 = CARRY(VD1L0271_cout_1);
 
 
--VD1_un59_hilo_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add9 at LC_X9_Y5_N3
--operation mode is arithmetic
 
VD1_un59_hilo_add9_carry_eqn = (!VD1_un59_hilo_carry_5 & VD1_un59_hilo_carry_8) # (VD1_un59_hilo_carry_5 & VD1L1481);
VD1_un59_hilo_add9 = VD1_hilo_41 $ VD1_op2_reged[9] $ VD1_un59_hilo_add9_carry_eqn;
 
--VD1_un59_hilo_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_9 at LC_X9_Y5_N3
--operation mode is arithmetic
 
VD1_un59_hilo_carry_9_cout_0 = VD1_hilo_41 & !VD1_op2_reged[9] & !VD1_un59_hilo_carry_8 # !VD1_hilo_41 & !VD1_un59_hilo_carry_8 # !VD1_op2_reged[9];
VD1_un59_hilo_carry_9 = CARRY(VD1_un59_hilo_carry_9_cout_0);
 
--VD1L3481 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_9~COUT1_1 at LC_X9_Y5_N3
--operation mode is arithmetic
 
VD1L3481_cout_1 = VD1_hilo_41 & !VD1_op2_reged[9] & !VD1L1481 # !VD1_hilo_41 & !VD1L1481 # !VD1_op2_reged[9];
VD1L3481 = CARRY(VD1L3481_cout_1);
 
 
--VD1_hilo_37_iv_0_1[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[40] at LC_X5_Y6_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_1[40] = VD1_hilo_37_iv_0_1_a[40] # !VD1_un59_hilo_add8 & VD1_hilo_37_iv_0_a2_7[34] & VD1_addop2;
 
 
--VD1_hilo_37_iv_0_5_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[40] at LC_X7_Y3_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_5_a[40] = VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add8 # !VD1_hilo_24_add8 # !VD1_hilo_2_sqmuxa & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add8;
 
 
--VD1_nop2_reged[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[7] at LC_X12_Y4_N5
--operation mode is arithmetic
 
VD1_nop2_reged[7]_carry_eqn = VD1_nop2_reged_cout[5];
VD1_nop2_reged[7] = VD1_op2_reged[7] $ (VD1_op2_reged[6] # !VD1_nop2_reged[7]_carry_eqn);
 
--VD1_nop2_reged_cout[7] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[7] at LC_X12_Y4_N5
--operation mode is arithmetic
 
VD1_nop2_reged_cout[7]_cout_0 = VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[5];
VD1_nop2_reged_cout[7] = CARRY(VD1_nop2_reged_cout[7]_cout_0);
 
--VD1L3231 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[7]~COUT1_3 at LC_X12_Y4_N5
--operation mode is arithmetic
 
VD1L3231_cout_1 = VD1_op2_reged[7] # VD1_op2_reged[6] # !VD1_nop2_reged_cout[5];
VD1L3231 = CARRY(VD1L3231_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[6] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[6] at LC_X14_Y4_N0
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[6] = VD1_eqop2_2_32 & VD1_op2_reged[6] # !VD1_eqop2_2_32 & VD1_nop2_reged[6];
 
 
--YB1_rd_sel_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a[0] at LC_X25_Y19_N5
--operation mode is normal
 
YB1_rd_sel_2_0_0_a[0] = !YB1_rd_sel_2_0_0_a3_0[0] & !YB1_alu_func_2_i_m3_0_a2_0_x[2] & !YB1_alu_func_2_0_0_a2_2_x[0] # !YB1_alu_func_2_0_0_a2_x[0];
 
 
--YB1_rd_sel_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0_Z[1] at LC_X29_Y17_N6
--operation mode is normal
 
YB1_rd_sel_2_0_0_0_Z[1] = KE1_q_a[5] # YB1_rd_sel_2_0_0_0_a[1] & !KE1_q_a[6] # !KE1_q_a[7];
 
 
--YB1_rd_sel_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a[1] at LC_X28_Y17_N9
--operation mode is normal
 
YB1_rd_sel_2_0_0_a[1] = !KE1_q_a[4] & YB1_cmp_ctl_2_0_0_a2_1[0] # !KE1_q_a[3] & YB1_cmp_ctl_2_0_0_a2_0[0];
 
 
--YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl350_1_0_a2_0_a3_0_o2_x at LC_X24_Y18_N4
--operation mode is normal
 
YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x = KE1_q_a[2] # !KE1_q_a[3];
 
 
--YB1_alu_we_1_0_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1[0] at LC_X28_Y17_N7
--operation mode is normal
 
YB1_alu_we_1_0_0_a3_1[0] = !KE1_q_a[3] & !KE1_q_a[7] & !KE1_q_a[4] & YB1_alu_we_1_0_0_a3_1_0[0];
 
 
--YB1_alu_we_1_0_0_a3_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_a_x[0] at LC_X25_Y19_N6
--operation mode is normal
 
YB1_alu_we_1_0_0_a3_a_x[0] = !KE1_q_a[7] & !KE1_q_a[3] & !KE1_q_a[4];
 
 
--YB1_alu_func_2_i_m3_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a2_0_x[2] at LC_X25_Y19_N7
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_a2_0_x[2] = YB1_alu_func_2_0_0_a2_0_x[3] & !GE1_q_a[4] & GE1_q_a[1];
 
 
--YB1_alu_func_2_0_0_a2_2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2_x[0] at LC_X25_Y19_N9
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_2_x[0] = !GE1_q_a[0] & !GE1_q_a[5] & YB1_alu_func_2_0_0_a2_0_x[3];
 
 
--F1_dout_20 is mips_sys:isys|mips_dvc:imips_dvc|dout_20 at LC_X29_Y7_N2
--operation mode is normal
 
F1_dout_20_lut_out = F1_dout_0_0_a3_3[0] & F1_cmd[20] # K1_cntr_20 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a3_3[0] & K1_cntr_20 & F1_dout_0_0_a3_4[0];
F1_dout_20 = DFFEAS(F1_dout_20_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_20 at LC_X29_Y7_N5
--operation mode is normal
 
BB1_r32_o_20_lut_out = AB1_r32_o_18;
BB1_r32_o_20 = DFFEAS(BB1_r32_o_20_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_20 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_20 at LC_X21_Y7_N7
--operation mode is normal
 
QB1_dout_iv_20 = GD1_dout_iv_1_20 # GD1_dout7_0_a2 & FD1_wb_o_20;
 
--QB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_20 at LC_X21_Y7_N7
--operation mode is normal
 
QB1_r32_o_20 = DFFEAS(QB1_dout_iv_20, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--AD1_delay_counter_Sreg0[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[3] at LC_X31_Y17_N3
--operation mode is normal
 
AD1_delay_counter_Sreg0[3]_lut_out = WB07L1 # !sys_rst;
AD1_delay_counter_Sreg0[3] = DFFEAS(AD1_delay_counter_Sreg0[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--YB1_fsm_dly_2_0_0_a2_0_a_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|fsm_dly_2_0_0_a2_0_a_x[2] at LC_X26_Y9_N1
--operation mode is normal
 
YB1_fsm_dly_2_0_0_a2_0_a_x[2] = !KE1_q_a[0] & !JE1_q_a[5] & !JE1_q_a[6];
 
 
--YB1_alu_we_1s_1_o2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1s_1_o2_0_x[0] at LC_X26_Y13_N5
--operation mode is normal
 
YB1_alu_we_1s_1_o2_0_x[0] = JE1_q_a[3] # JE1_q_a[2] # JE1_q_a[1];
 
 
--YB1_alu_func_2_0_0_a2_0_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_0_x[3] at LC_X26_Y19_N3
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_0_x[3] = !KE1_q_a[6] & !KE1_q_a[2] & !GE1_q_a[2];
 
 
--YB1_alu_func_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_Z[1] at LC_X25_Y18_N6
--operation mode is normal
 
YB1_alu_func_2_0_0_1_Z[1] = !YB1_alu_func_2_0_0_1_a[1] & YB1_alu_func_2_0_0_a2_2_x[0] # GE1_q_a[1] # YB1_alu_func_2_0_0_a2_2[4];
 
 
--YB1_ext_ctl_2_0_0_o2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_o2[2] at LC_X26_Y13_N9
--operation mode is normal
 
YB1_ext_ctl_2_0_0_o2[2] = YB1_cmp_ctl_2_0_0_a2_0[0] # KE1_q_a[2] & JE1_q_a[0] # YB1_alu_we_1s_1_o2_0_x[0];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_o2_0_x[0] at LC_X29_Y16_N9
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] = KE1_q_a[3] # !KE1_q_a[7];
 
 
--YB1_ext_ctl_2_0_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a2_0_x[2] at LC_X25_Y16_N2
--operation mode is normal
 
YB1_ext_ctl_2_0_0_a2_0_x[2] = !KE1_q_a[5] & !KE1_q_a[7] & !KE1_q_a[3];
 
 
--YB1_cmp_ctl_2_0_0_a2_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_x[0] at LC_X25_Y16_N0
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a2_x[0] = !KE1_q_a[5] & KE1_q_a[4];
 
 
--YB1_cmp_ctl_2_0_0_a2_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a2_x[2] at LC_X26_Y13_N8
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a2_x[2] = KE1_q_a[2] & !YB1_alu_we_1s_1_o2_0_x[0] & !JE1_q_a[4];
 
 
--YB1_pc_gen_ctl_2_0_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a2_x[1] at LC_X26_Y17_N2
--operation mode is normal
 
YB1_pc_gen_ctl_2_0_0_a2_x[1] = !GE1_q_a[4] & !GE1_q_a[1];
 
 
--YB1_alu_func_2_0_0_a2_1_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_1_x[3] at LC_X26_Y19_N6
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_1_x[3] = !GE1_q_a[4] & GE1_q_a[5];
 
 
--YB1_alu_func_2_i_m3_0_a3_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_5[2] at LC_X25_Y18_N9
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_a3_5[2] = !GE1_q_a[3] & GE1_q_a[0] & YB1_alu_func_2_0_0_a2_0_x[3] & YB1_alu_func_2_i_m3_0_a3_5_a[2];
 
 
--YB1_alu_func_2_i_m3_0_2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_2[2] at LC_X29_Y16_N2
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_2[2] = YB1_alu_func_2_i_m3_0_a3_0_x[2] # !KE1_q_a[5] & YB1_alu_func_2_i_m3_0_2_a[2] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0];
 
 
--YB1_alu_func_2_i_m3_0_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_5_a[2] at LC_X28_Y16_N8
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_5_a[2] = !KE1_q_a[3] & YB1_alu_func_2_0_0_a2_0_x[4] # WB93L2 & YB1_cmp_ctl_2_0_0_a2_0[0];
 
 
--YB1_alu_func_2_0_0_a3_0_a_x[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_0_a_x[3] at LC_X27_Y18_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_0_a_x[3] = !KE1_q_a[3] & YB1_cmp_ctl_2_0_0_a2_1[0] # YB1_cmp_ctl_2_0_0_a2_0[0];
 
 
--YB1_alu_func_2_0_0_a3_1_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a3_1_a[3] at LC_X26_Y19_N1
--operation mode is normal
 
YB1_alu_func_2_0_0_a3_1_a[3] = !KE1_q_a[3] & !GE1_q_a[2] & !KE1_q_a[2] & !KE1_q_a[6];
 
 
--YB1_alu_func_2_0_0_1_a[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_a[4] at LC_X25_Y18_N7
--operation mode is normal
 
YB1_alu_func_2_0_0_1_a[4] = !YB1_alu_func_2_0_0_a2_2[4] & GE1_q_a[1] # !GE1_q_a[0] # !YB1_alu_func_2_0_0_a2_2_x[1];
 
 
--YB1_alu_func_2_0_0_o2_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_o2_0_a_x[0] at LC_X27_Y19_N4
--operation mode is normal
 
YB1_alu_func_2_0_0_o2_0_a_x[0] = !KE1_q_a[2] & !KE1_q_a[6] & GE1_q_a[5];
 
 
--YB1_alu_func_2_0_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_0_a[0] at LC_X26_Y18_N0
--operation mode is normal
 
YB1_alu_func_2_0_0_0_a[0] = GE1_q_a[1] & YB1_alu_func_2_0_0_a2_0_x[3] & !GE1_q_a[5] # !GE1_q_a[1] & YB1_alu_func_2_0_0_a2_2[4];
 
 
--VD1_hilo_37_iv_0_1_a[36] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[36] at LC_X6_Y6_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[36] = VD1_hilo_0_sqmuxa & !VD1_hilo_36 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_4 # !VD1_hilo_0_sqmuxa & !VD1_hilo_36 & VD1_hilo_37_iv_0_o3_2[34];
 
 
--YB1_muxb_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0 at LC_X25_Y17_N3
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_0 = YB1_muxa_ctl_2_0_0_a3_1[0] # !GE1_q_a[4] & YB1_muxb_ctl_2_0_0_a3_0_0_x[0] # !YB1_muxb_ctl_2_0_0_a[0];
 
 
--WB85L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:muxb_ctl_1_0_|lpm_latch:U1|q[0]~56 at LC_X25_Y17_N4
--operation mode is normal
 
WB85L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_muxb_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB85L1;
 
--AC1_muxb_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1|muxb_ctl_o_0 at LC_X25_Y17_N4
--operation mode is normal
 
AC1_muxb_ctl_o_0 = DFFEAS(WB85L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_muxb_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_1 at LC_X27_Y15_N4
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_1 = KE1_q_a[5] # YB1_muxb_ctl_2_0_0_0_Z[1] # !KE1_q_a[6] & YB1_muxb_ctl_2_0_0_a[1];
 
 
--WB95L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~68 at LC_X27_Y15_N3
--operation mode is normal
 
WB95L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_muxb_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB95L2;
 
 
--WB95L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1|q[0]~69 at LC_X27_Y15_N9
--operation mode is normal
 
WB95L2 = !YB1_un1_ins_i_23_2_0 & WB95L1;
 
--AC1_muxb_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1|muxb_ctl_o_1 at LC_X27_Y15_N9
--operation mode is normal
 
AC1_muxb_ctl_o_1 = DFFEAS(WB95L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_ext_ctl_2_i_m3_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_1 at LC_X29_Y16_N7
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_1 = KE1_q_a[4] & KE1_q_a[5] # !KE1_q_a[4] & KE1_q_a[5] & YB1_alu_func_2_0_0_a2_0_x[0] # !KE1_q_a[5] & YB1_ext_ctl_2_i_m3_0_a[1];
 
 
--WB15L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_1_|lpm_latch:U1|q[0]~56 at LC_X29_Y16_N8
--operation mode is normal
 
WB15L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_i_m3_0_1 # !YB1_un1_muxa_ctl370_x & WB15L1;
 
--DC1_ext_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_1 at LC_X29_Y16_N8
--operation mode is normal
 
DC1_ext_ctl_o_1 = DFFEAS(WB15L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_ext_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_0 at LC_X23_Y17_N6
--operation mode is normal
 
YB1_ext_ctl_2_0_0_0 = YB1_ext_ctl_2_0_0_o3[2] # YB1_ext_ctl_2_0_0_a3_1_0[2] & WB25L1 # !YB1_ext_ctl_2_0_0_a[2];
 
 
--WB25L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:ext_ctl_1_2_|lpm_latch:U1|q[0]~56 at LC_X23_Y17_N5
--operation mode is normal
 
WB25L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB25L1;
 
--DC1_ext_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_2 at LC_X23_Y17_N5
--operation mode is normal
 
DC1_ext_ctl_o_2 = DFFEAS(WB25L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_ext_ctl_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0 at LC_X24_Y17_N4
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_0 = YB1_ext_ctl_2_i_m3_0_2[0] # YB1_alu_func_2_0_0_o3[3] # YB1_fsm_dly_2_0_0_a2_x[2] & !YB1_ext_ctl_2_i_m3_0_a_x[0];
 
 
--WB05L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~68 at LC_X27_Y15_N6
--operation mode is normal
 
WB05L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_ext_ctl_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB05L2;
 
 
--WB05L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1|q[0]~69 at LC_X27_Y15_N5
--operation mode is normal
 
WB05L2 = !YB1_un1_ins_i_23_2_0 & WB05L1;
 
--DC1_ext_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4|ext_ctl_o_0 at LC_X27_Y15_N5
--operation mode is normal
 
DC1_ext_ctl_o_0 = DFFEAS(WB05L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_muxa_ctl_2_0_0_2[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_2[1] at LC_X29_Y17_N7
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_2[1] = YB1_muxa_ctl_2_0_0_0_Z[1] # !KE1_q_a[3] & !KE1_q_a[4] & !YB1_muxa_ctl_2_0_0_2_a[1];
 
 
--FD1_N_18_i_0_s3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3 at LC_X25_Y8_N1
--operation mode is normal
 
FD1_N_18_i_0_s3 = !YD1_mux_fw_1 & FD1_N_18_i_0_s3_a & FD1_un14_qa_NE # !FD1_r_wren;
 
 
--HD1_dout_iv_1_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[4] at LC_X16_Y11_N0
--operation mode is normal
 
HD1_dout_iv_1_a[4] = YD1_mux_fw_1 & !AB1_r32_o_2 & !FD1_N_14_i_0_s2 # !FD1_r_data_4 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_4;
 
 
--LD2_q_b[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[4] at M4K_X17_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[4] = LD2_q_b[4]_PORT_B_data_out[0];
 
--LD2_q_b[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[23] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[23] = LD2_q_b[4]_PORT_B_data_out[31];
 
--LD2_q_b[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[22] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[22] = LD2_q_b[4]_PORT_B_data_out[30];
 
--LD2_q_b[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[25] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[25] = LD2_q_b[4]_PORT_B_data_out[29];
 
--LD2_q_b[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[24] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[24] = LD2_q_b[4]_PORT_B_data_out[28];
 
--LD2_q_b[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[27] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[27] = LD2_q_b[4]_PORT_B_data_out[27];
 
--LD2_q_b[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[26] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[26] = LD2_q_b[4]_PORT_B_data_out[26];
 
--LD2_q_b[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[18] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[18] = LD2_q_b[4]_PORT_B_data_out[25];
 
--LD2_q_b[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[19] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[19] = LD2_q_b[4]_PORT_B_data_out[24];
 
--LD2_q_b[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[29] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[29] = LD2_q_b[4]_PORT_B_data_out[23];
 
--LD2_q_b[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[28] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[28] = LD2_q_b[4]_PORT_B_data_out[22];
 
--LD2_q_b[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[13] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[13] = LD2_q_b[4]_PORT_B_data_out[21];
 
--LD2_q_b[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[20] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[20] = LD2_q_b[4]_PORT_B_data_out[20];
 
--LD2_q_b[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[21] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[21] = LD2_q_b[4]_PORT_B_data_out[19];
 
--LD2_q_b[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[15] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[15] = LD2_q_b[4]_PORT_B_data_out[18];
 
--LD2_q_b[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[14] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[14] = LD2_q_b[4]_PORT_B_data_out[17];
 
--LD2_q_b[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[17] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[17] = LD2_q_b[4]_PORT_B_data_out[16];
 
--LD2_q_b[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[16] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[16] = LD2_q_b[4]_PORT_B_data_out[15];
 
--LD2_q_b[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[30] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[30] = LD2_q_b[4]_PORT_B_data_out[14];
 
--LD2_q_b[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[31] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[31] = LD2_q_b[4]_PORT_B_data_out[13];
 
--LD2_q_b[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[0] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[0] = LD2_q_b[4]_PORT_B_data_out[12];
 
--LD2_q_b[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[1] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[1] = LD2_q_b[4]_PORT_B_data_out[11];
 
--LD2_q_b[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[12] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[12] = LD2_q_b[4]_PORT_B_data_out[10];
 
--LD2_q_b[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[11] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[11] = LD2_q_b[4]_PORT_B_data_out[9];
 
--LD2_q_b[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[10] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[10] = LD2_q_b[4]_PORT_B_data_out[8];
 
--LD2_q_b[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[9] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[9] = LD2_q_b[4]_PORT_B_data_out[7];
 
--LD2_q_b[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[8] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[8] = LD2_q_b[4]_PORT_B_data_out[6];
 
--LD2_q_b[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[7] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[7] = LD2_q_b[4]_PORT_B_data_out[5];
 
--LD2_q_b[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[6] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[6] = LD2_q_b[4]_PORT_B_data_out[4];
 
--LD2_q_b[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[3] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[3] = LD2_q_b[4]_PORT_B_data_out[3];
 
--LD2_q_b[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[2] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[2] = LD2_q_b[4]_PORT_B_data_out[2];
 
--LD2_q_b[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|q_b[5] at M4K_X17_Y9
LD2_q_b[4]_PORT_A_data_in = BUS(FD1_wb_o_4, FD1_wb_o_5, FD1_wb_o_2, FD1_wb_o_3, FD1_wb_o_6, FD1_wb_o_7, FD1_wb_o_8, FD1_wb_o_9, FD1_wb_o_10, FD1_wb_o_11, FD1_wb_o_12, FD1_wb_o_1, FD1_wb_o_0, FD1_wb_o_31, FD1_wb_o_30, FD1_wb_o_16, FD1_wb_o_17, FD1_wb_o_14, FD1_wb_o_15, FD1_wb_o_21, FD1_wb_o_20, FD1_wb_o_13, FD1_wb_o_28, FD1_wb_o_29, FD1_wb_o_19, FD1_wb_o_18, FD1_wb_o_26, FD1_wb_o_27, FD1_wb_o_24, FD1_wb_o_25, FD1_wb_o_22, FD1_wb_o_23);
LD2_q_b[4]_PORT_A_data_in_reg = DFFE(LD2_q_b[4]_PORT_A_data_in, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_A_address = BUS(NB1_r5_o_0, NB1_r5_o_1, NB1_r5_o_2, NB1_r5_o_3, NB1_r5_o_4);
LD2_q_b[4]_PORT_A_address_reg = DFFE(LD2_q_b[4]_PORT_A_address, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_address = BUS(FD1_r_rdaddress_a_0_x[0], FD1_r_rdaddress_a_0_x[1], FD1_r_rdaddress_a_0_x[2], FD1_r_rdaddress_a_0_x[3], FD1_r_rdaddress_a_0_x[4]);
LD2_q_b[4]_PORT_B_address_reg = DFFE(LD2_q_b[4]_PORT_B_address, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_PORT_A_write_enable = MC1_wb_we_o_0;
LD2_q_b[4]_PORT_A_write_enable_reg = DFFE(LD2_q_b[4]_PORT_A_write_enable, LD2_q_b[4]_clock_0, , , );
LD2_q_b[4]_PORT_B_read_enable = VCC;
LD2_q_b[4]_PORT_B_read_enable_reg = DFFE(LD2_q_b[4]_PORT_B_read_enable, LD2_q_b[4]_clock_1, , , );
LD2_q_b[4]_clock_0 = GLOBAL(E1__clk0);
LD2_q_b[4]_clock_1 = GLOBAL(E1__clk0);
LD2_q_b[4]_PORT_B_data_out = MEMORY(LD2_q_b[4]_PORT_A_data_in_reg, , LD2_q_b[4]_PORT_A_address_reg, LD2_q_b[4]_PORT_B_address_reg, LD2_q_b[4]_PORT_A_write_enable_reg, LD2_q_b[4]_PORT_B_read_enable_reg, , , LD2_q_b[4]_clock_0, LD2_q_b[4]_clock_1, , , , );
LD2_q_b[5] = LD2_q_b[4]_PORT_B_data_out[1];
 
 
--YD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE at LC_X26_Y9_N6
--operation mode is normal
 
ED1_r32_o_25_qfbk = ED1_r32_o_25;
YD1_un17_mux_fw_NE = YD1_un17_mux_fw_NE_a # YD1_un17_mux_fw_NE_1 # NB1_r5_o_4 $ ED1_r32_o_25_qfbk;
 
--ED1_r32_o_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_25 at LC_X26_Y9_N6
--operation mode is normal
 
ED1_r32_o_25 = DFFEAS(YD1_un17_mux_fw_NE, GLOBAL(E1__clk0), VCC, , C1_G_504, KE1_q_a[1], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--YD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|mux_fw_1 at LC_X25_Y8_N8
--operation mode is normal
 
XC1_wb_we_o_0_qfbk = XC1_wb_we_o_0;
YD1_mux_fw_1 = !YD1_un1_mux_fw_NE & XC1_wb_we_o_0_qfbk & !WD1_un14_mux_fw;
 
--XC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22|wb_we_o_0 at LC_X25_Y8_N8
--operation mode is normal
 
XC1_wb_we_o_0 = DFFEAS(YD1_mux_fw_1, GLOBAL(E1__clk0), VCC, , , YC1_alu_we_o_0, , , VCC);
 
 
--WD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE_1 at LC_X27_Y9_N9
--operation mode is normal
 
AE1_q_0_qfbk = AE1_q_0;
WD1_un17_mux_fw_NE_1 = AE1_q_1 & AE1_q_0_qfbk $ NB1_r5_o_0 # !NB1_r5_o_1 # !AE1_q_1 & NB1_r5_o_1 # AE1_q_0_qfbk $ NB1_r5_o_0;
 
--AE1_q_0 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_0 at LC_X27_Y9_N9
--operation mode is normal
 
AE1_q_0 = DFFEAS(WD1_un17_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_21, , , VCC);
 
 
--WD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un17_mux_fw_NE_a at LC_X25_Y9_N1
--operation mode is normal
 
AE1_q_3_qfbk = AE1_q_3;
WD1_un17_mux_fw_NE_a = NB1_r5_o_3 & AE1_q_2 $ NB1_r5_o_2 # !AE1_q_3_qfbk # !NB1_r5_o_3 & AE1_q_3_qfbk # AE1_q_2 $ NB1_r5_o_2;
 
--AE1_q_3 is mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns|q_3 at LC_X25_Y9_N1
--operation mode is normal
 
AE1_q_3 = DFFEAS(WD1_un17_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , , ED1_r32_o_24, , , VCC);
 
 
--QB1_dout_iv_10 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_10 at LC_X20_Y8_N1
--operation mode is normal
 
QB1_dout_iv_10 = GD1_dout_iv_1_10 # FD1_wb_o_10 & GD1_dout7_0_a2;
 
--QB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_10 at LC_X20_Y8_N1
--operation mode is normal
 
QB1_r32_o_10 = DFFEAS(QB1_dout_iv_10, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_15 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_15 at LC_X24_Y4_N0
--operation mode is normal
 
QB1_dout_iv_15 = GD1_dout_iv_1_15 # FD1_wb_o_15 & GD1_dout7_0_a2;
 
--QB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_15 at LC_X24_Y4_N0
--operation mode is normal
 
QB1_r32_o_15 = DFFEAS(QB1_dout_iv_15, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_15 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_15 at LC_X25_Y10_N2
--operation mode is normal
 
FB1_res_7_0_0_15 = CD1_res_7_0_0_a2_0 & ED1_r32_o_15 # CD1_res_7_0_0_o3_0 & ED1_r32_o_13 # !CD1_res_7_0_0_a2_0 & CD1_res_7_0_0_o3_0 & ED1_r32_o_13;
 
--FB1_r32_o_0_15 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_0_15 at LC_X25_Y10_N2
--operation mode is normal
 
FB1_r32_o_0_15 = DFFEAS(FB1_res_7_0_0_15, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_15 at LC_X29_Y13_N5
--operation mode is normal
 
FD1_wb_o_15 = TC1_wb_mux_ctl_o_0 & DB1_r32_o_15 # F1_dout_15 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_15;
 
--FD1_r_data_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_15 at LC_X29_Y13_N5
--operation mode is normal
 
FD1_r_data_15 = DFFEAS(FD1_wb_o_15, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_27 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_27 at LC_X22_Y7_N4
--operation mode is normal
 
QB1_dout_iv_27 = GD1_dout_iv_1_27 # FD1_wb_o_27 & GD1_dout7_0_a2;
 
--QB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_27 at LC_X22_Y7_N4
--operation mode is normal
 
QB1_r32_o_27 = DFFEAS(QB1_dout_iv_27, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_27 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_27 at LC_X24_Y13_N4
--operation mode is normal
 
FB1_res_7_0_0_27 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_11 # !CD1_res_7_0_0_a_24;
 
--FB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_27 at LC_X24_Y13_N4
--operation mode is normal
 
FB1_r32_o_27 = DFFEAS(FB1_res_7_0_0_27, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_27 at LC_X25_Y15_N8
--operation mode is normal
 
FD1_wb_o_27 = TC1_wb_mux_ctl_o_0 & F1_dout_27 # DB1_r32_o_27 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_27;
 
--FD1_r_data_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_27 at LC_X25_Y15_N8
--operation mode is normal
 
FD1_r_data_27 = DFFEAS(FD1_wb_o_27, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_19 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_19 at LC_X26_Y7_N7
--operation mode is normal
 
QB1_dout_iv_19 = GD1_dout_iv_1_19 # FD1_wb_o_19 & GD1_dout7_0_a2;
 
--QB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_19 at LC_X26_Y7_N7
--operation mode is normal
 
QB1_r32_o_19 = DFFEAS(QB1_dout_iv_19, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_19 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_19 at LC_X22_Y15_N8
--operation mode is normal
 
FB1_res_7_0_0_19 = CD1_res_7_0_0_a3_0 # ED1_r32_o_3 & CD1_res_7_0_0_a2_16 # !CD1_res_7_0_0_a_16;
 
--FB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_19 at LC_X22_Y15_N8
--operation mode is normal
 
FB1_r32_o_19 = DFFEAS(FB1_res_7_0_0_19, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_20 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_20 at LC_X22_Y14_N7
--operation mode is normal
 
FB1_res_7_0_0_20 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_4 # !CD1_res_7_0_0_a_17;
 
--FB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_20 at LC_X22_Y14_N7
--operation mode is normal
 
FB1_r32_o_20 = DFFEAS(FB1_res_7_0_0_20, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_count[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[3] at LC_X32_Y9_N5
--operation mode is arithmetic
 
VD1_count[3]_carry_eqn = VD1_count_cout[2];
VD1_count[3]_lut_out = VD1_count[3] $ VD1_count[3]_carry_eqn;
VD1_count[3] = DFFEAS(VD1_count[3]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
--VD1_count_cout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[3] at LC_X32_Y9_N5
--operation mode is arithmetic
 
VD1_count_cout[3]_cout_0 = !VD1_count_cout[2] # !VD1_count[3];
VD1_count_cout[3] = CARRY(VD1_count_cout[3]_cout_0);
 
--VD1L011 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[3]~COUT1_3 at LC_X32_Y9_N5
--operation mode is arithmetic
 
VD1L011_cout_1 = !VD1_count_cout[2] # !VD1_count[3];
VD1L011 = CARRY(VD1L011_cout_1);
 
 
--VD1_un3_overflow_m_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un3_overflow_m_0 at LC_X8_Y13_N6
--operation mode is normal
 
VD1_un3_overflow_m_0 = RC1_alu_func_o_1 & RC1_alu_func_o_0 & RC1_alu_func_o_3 & !VD1_un29_sign_0_o2_0;
 
 
--VD1_over_add31_cout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_add31_cout at LC_X10_Y10_N5
--operation mode is arithmetic
 
VD1_over_add31_cout_cout_0 = VD1_b_o_iv_31 & !VD1_over_carry_30 # !PD1_a_o_31 # !VD1_b_o_iv_31 & !PD1_a_o_31 & !VD1_over_carry_30;
VD1_over_add31_cout = CARRY(VD1_over_add31_cout_cout_0);
 
--VD1L2741 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_add31_cout~COUT1_1 at LC_X10_Y10_N5
--operation mode is arithmetic
 
VD1L2741_cout_1 = VD1_b_o_iv_31 & !VD1_over_carry_30 # !PD1_a_o_31 # !VD1_b_o_iv_31 & !PD1_a_o_31 & !VD1_over_carry_30;
VD1L2741 = CARRY(VD1L2741_cout_1);
 
 
--VD1_un1_overflow_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_overflow_1 at LC_X2_Y15_N3
--operation mode is normal
 
VD1_un1_overflow_1 = VD1_overflow # VD1_finish & VD1_count[5];
 
 
--VD1_op1_sign_reged is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged at LC_X8_Y6_N3
--operation mode is normal
 
VD1_op1_sign_reged_lut_out = PD1_a_o_31 & RC1_alu_func_o_0;
VD1_op1_sign_reged = DFFEAS(VD1_op1_sign_reged_lut_out, GLOBAL(E1__clk0), VCC, , VD1_op1_sign_reged_0_sqmuxa_i, , , , );
 
 
--VD1_eqz_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2 at LC_X10_Y6_N2
--operation mode is normal
 
VD1_eqz_2 = VD1_eqz_2_30 & VD1_eqz_2_27 & VD1_eqz_2_17 & VD1_eqz_2_21;
 
 
--VD1_eqop2_2_NE is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE at LC_X12_Y5_N6
--operation mode is normal
 
VD1_eqop2_2_NE = VD1_eqop2_2_NE_12 # VD1_eqop2_2_NE_11 # VD1_eqop2_2_NE_10 # VD1_eqop2_2_NE_9;
 
 
--VD1_eqnop2_2_NE_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_7 at LC_X10_Y2_N9
--operation mode is normal
 
VD1_eqnop2_2_NE_7 = VD1_eqnop2_2_NE_7_a # VD1_eqnop2_2_NE_143 # VD1_nop2_reged[32] $ VD1_hilo[64];
 
 
--VD1_eqnop2_2_NE_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_9 at LC_X11_Y3_N9
--operation mode is normal
 
VD1_eqnop2_2_NE_9 = VD1_eqnop2_2_NE_130 # VD1_eqnop2_2_NE_132_0 # VD1_eqnop2_2_NE_131 # VD1_eqnop2_2_NE_129;
 
 
--VD1_eqnop2_2_NE_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_10 at LC_X14_Y4_N3
--operation mode is normal
 
VD1_eqnop2_2_NE_10 = VD1_eqnop2_2_NE_134 # VD1_eqnop2_2_NE_10_a # VD1_eqnop2_2_NE_133 # VD1_eqnop2_2_NE_135;
 
 
--VD1_eqnop2_2_NE_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_a at LC_X13_Y2_N4
--operation mode is normal
 
VD1_eqnop2_2_NE_a = !VD1_eqnop2_2_NE_5 & !VD1_eqnop2_2_NE_141 & !VD1_eqnop2_2_NE_8 & !VD1_eqnop2_2_NE_142;
 
 
--VD1_hilo_33_i_m[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[64] at LC_X7_Y9_N6
--operation mode is normal
 
VD1_hilo_33_i_m[64] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[64] # !VD1_hilo_33_1[64] & !VD1_hilo[64];
 
 
--VD1_hilo_37_iv_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[64] at LC_X7_Y9_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[64] = !VD1_hilo_15_3_i[63] & VD1_sign # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_1[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[64] at LC_X7_Y9_N9
--operation mode is normal
 
VD1_hilo_37_iv_1[64] = VD1_hilo_2_sqmuxa & !VD1_hilo_24_add32 # !VD1_hilo_37_iv_1_a[64];
 
 
--VD1_un1_addnop2104_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_addnop2104_1 at LC_X2_Y16_N9
--operation mode is normal
 
VD1_un1_addnop2104_1 = VD1_count[5] # VD1_overflow # VD1_mul & !VD1_sign;
 
 
--VD1_nop2_reged[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[2] at LC_X13_Y4_N3
--operation mode is arithmetic
 
VD1_nop2_reged[2] = VD1_op2_reged[2] $ !VD1_nop2_reged_cout[0];
 
--VD1_nop2_reged_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[2] at LC_X13_Y4_N3
--operation mode is arithmetic
 
VD1_nop2_reged_cout[2]_cout_0 = VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1_nop2_reged_cout[0];
VD1_nop2_reged_cout[2] = CARRY(VD1_nop2_reged_cout[2]_cout_0);
 
--VD1L5131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[2]~COUT1_14 at LC_X13_Y4_N3
--operation mode is arithmetic
 
VD1L5131_cout_1 = VD1_op2_reged[3] # VD1_op2_reged[2] # !VD1L1131;
VD1L5131 = CARRY(VD1L5131_cout_1);
 
 
--VD1_un1_mul_3_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_mul_3_a at LC_X8_Y6_N6
--operation mode is normal
 
VD1_un1_mul_3_a = VD1_op2_sign_reged & VD1_hilo[64] & !VD1_op1_sign_reged # !VD1_op2_sign_reged & !VD1_hilo[64] & !VD1_eqz_2 & VD1_op1_sign_reged;
 
 
--VD1_un1_op2_reged_1_combout[4] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[4] at LC_X8_Y5_N2
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[4] = VD1_eqop2_2_32 & VD1_op2_reged[4] # !VD1_eqop2_2_32 & VD1_nop2_reged[4];
 
 
--VD1_hilo_24_add3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add3 at LC_X8_Y5_N7
--operation mode is arithmetic
 
VD1_hilo_24_add3_carry_eqn = (!VD1_hilo_24_carry_0 & VD1_hilo_24_carry_2) # (VD1_hilo_24_carry_0 & VD1L184);
VD1_hilo_24_add3 = VD1_un1_op2_reged_1_combout[3] $ VD1_hilo_34 $ VD1_hilo_24_add3_carry_eqn;
 
--VD1_hilo_24_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_3 at LC_X8_Y5_N7
--operation mode is arithmetic
 
VD1_hilo_24_carry_3_cout_0 = VD1_un1_op2_reged_1_combout[3] & !VD1_hilo_34 & !VD1_hilo_24_carry_2 # !VD1_un1_op2_reged_1_combout[3] & !VD1_hilo_24_carry_2 # !VD1_hilo_34;
VD1_hilo_24_carry_3 = CARRY(VD1_hilo_24_carry_3_cout_0);
 
--VD1L384 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_3~COUT1_1 at LC_X8_Y5_N7
--operation mode is arithmetic
 
VD1L384_cout_1 = VD1_un1_op2_reged_1_combout[3] & !VD1_hilo_34 & !VD1L184 # !VD1_un1_op2_reged_1_combout[3] & !VD1L184 # !VD1_hilo_34;
VD1L384 = CARRY(VD1L384_cout_1);
 
 
--VD1_hilo_37_iv_0_3_a[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3_a[38] at LC_X5_Y7_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_3_a[38] = !VD1_hilo_37_iv_0_a3_2[38] & !VD1_hilo_37_iv_0_a3_6[38] & VD1_un50_hilo_add6 # !VD1_hilo_37_iv_0_a2_6_0[37];
 
 
--HD1_dout_iv_1_a[5] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[5] at LC_X20_Y11_N7
--operation mode is normal
 
HD1_dout_iv_1_a[5] = AB1_r32_o_3 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_5 # !AB1_r32_o_3 & !FD1_N_14_i_0_s2 # !FD1_r_data_5;
 
 
--QB1_dout_iv_16 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_16 at LC_X21_Y5_N2
--operation mode is normal
 
QB1_dout_iv_16 = GD1_dout_iv_1_16 # FD1_wb_o_16 & GD1_dout7_0_a2;
 
--QB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_16 at LC_X21_Y5_N2
--operation mode is normal
 
QB1_r32_o_16 = DFFEAS(QB1_dout_iv_16, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_16 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_16 at LC_X24_Y15_N4
--operation mode is normal
 
FB1_res_7_0_0_16 = CD1_res_7_0_0_0_14 # CD1_res_7_0_0_o3_0 & ED1_r32_o_14;
 
--FB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_16 at LC_X24_Y15_N4
--operation mode is normal
 
FB1_r32_o_16 = DFFEAS(FB1_res_7_0_0_16, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--CD1_res_7_0_0_a2_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a2_16 at LC_X23_Y16_N6
--operation mode is normal
 
CD1_res_7_0_0_a2_16 = !DC1_ext_ctl_o_0 & DC1_ext_ctl_o_1 & DC1_ext_ctl_o_2;
 
 
--CD1_res_7_0_0_a3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a3_0 at LC_X23_Y16_N3
--operation mode is normal
 
ED1_r32_o_15_qfbk = ED1_r32_o_15;
CD1_res_7_0_0_a3_0 = ED1_r32_o_15_qfbk & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_0 $ DC1_ext_ctl_o_2;
 
--ED1_r32_o_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_15 at LC_X23_Y16_N3
--operation mode is normal
 
ED1_r32_o_15 = DFFEAS(CD1_res_7_0_0_a3_0, GLOBAL(E1__clk0), VCC, , C1_G_504, HE1_q_a[7], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--QB1_dout_iv_28 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_28 at LC_X26_Y8_N7
--operation mode is normal
 
QB1_dout_iv_28 = GD1_dout_iv_1_28 # GD1_dout7_0_a2 & FD1_wb_o_28;
 
--QB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_28 at LC_X26_Y8_N7
--operation mode is normal
 
QB1_r32_o_28 = DFFEAS(QB1_dout_iv_28, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_23 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_23 at LC_X23_Y5_N7
--operation mode is normal
 
QB1_dout_iv_23 = GD1_dout_iv_1_23 # GD1_dout7_0_a2 & FD1_wb_o_23;
 
--QB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_23 at LC_X23_Y5_N7
--operation mode is normal
 
QB1_r32_o_23 = DFFEAS(QB1_dout_iv_23, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_23 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_23 at LC_X24_Y13_N0
--operation mode is normal
 
FB1_res_7_0_0_23 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_7 # !CD1_res_7_0_0_a_20;
 
--FB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_23 at LC_X24_Y13_N0
--operation mode is normal
 
FB1_r32_o_23 = DFFEAS(FB1_res_7_0_0_23, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--QB1_dout_iv_24 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_24 at LC_X23_Y6_N0
--operation mode is normal
 
QB1_dout_iv_24 = GD1_dout_iv_1_24 # FD1_wb_o_24 & GD1_dout7_0_a2;
 
--QB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_24 at LC_X23_Y6_N0
--operation mode is normal
 
QB1_r32_o_24 = DFFEAS(QB1_dout_iv_24, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FB1_res_7_0_0_24 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|res_7_0_0_24 at LC_X24_Y13_N3
--operation mode is normal
 
FB1_res_7_0_0_24 = CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_8 # !CD1_res_7_0_0_a_21;
 
--FB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg|r32_o_24 at LC_X24_Y13_N3
--operation mode is normal
 
FB1_r32_o_24 = DFFEAS(FB1_res_7_0_0_24, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--FD1_wb_o_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_24 at LC_X29_Y5_N3
--operation mode is normal
 
FD1_wb_o_24 = TC1_wb_mux_ctl_o_0 & F1_dout_24 # DB1_r32_o_24 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_24;
 
--FD1_r_data_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_24 at LC_X29_Y5_N3
--operation mode is normal
 
FD1_r_data_24 = DFFEAS(FD1_wb_o_24, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_nop2_reged[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[1] at LC_X12_Y4_N2
--operation mode is arithmetic
 
VD1_nop2_reged[1] = VD1_op2_reged[1] $ VD1_op2_reged[0];
 
--VD1_nop2_reged_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[1] at LC_X12_Y4_N2
--operation mode is arithmetic
 
VD1_nop2_reged_cout[1]_cout_0 = !VD1_op2_reged[1] & !VD1_op2_reged[0];
VD1_nop2_reged_cout[1] = CARRY(VD1_nop2_reged_cout[1]_cout_0);
 
--VD1L3131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[1]~COUT1_1 at LC_X12_Y4_N2
--operation mode is arithmetic
 
VD1L3131_cout_1 = !VD1_op2_reged[1] & !VD1_op2_reged[0];
VD1L3131 = CARRY(VD1L3131_cout_1);
 
 
--VD1_un50_hilo_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add1 at LC_X10_Y5_N5
--operation mode is arithmetic
 
VD1_un50_hilo_add1_carry_eqn = VD1_un50_hilo_carry_0;
VD1_un50_hilo_add1 = VD1_nop2_reged[1] $ VD1_hilo_33 $ VD1_un50_hilo_add1_carry_eqn;
 
--VD1_un50_hilo_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_1 at LC_X10_Y5_N5
--operation mode is arithmetic
 
VD1_un50_hilo_carry_1_cout_0 = VD1_nop2_reged[1] & !VD1_hilo_33 & !VD1_un50_hilo_carry_0 # !VD1_nop2_reged[1] & !VD1_un50_hilo_carry_0 # !VD1_hilo_33;
VD1_un50_hilo_carry_1 = CARRY(VD1_un50_hilo_carry_1_cout_0);
 
--VD1L5071 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_1~COUT1_1 at LC_X10_Y5_N5
--operation mode is arithmetic
 
VD1L5071_cout_1 = VD1_nop2_reged[1] & !VD1_hilo_33 & !VD1_un50_hilo_carry_0 # !VD1_nop2_reged[1] & !VD1_un50_hilo_carry_0 # !VD1_hilo_33;
VD1L5071 = CARRY(VD1L5071_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[1] at LC_X8_Y5_N3
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[1] = VD1_eqop2_2_32 & VD1_op2_reged[1] # !VD1_eqop2_2_32 & VD1_nop2_reged[1];
 
 
--VD1_un59_hilo_add2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add2 at LC_X9_Y6_N6
--operation mode is arithmetic
 
VD1_un59_hilo_add2_carry_eqn = (!VD1_un59_hilo_carry_0 & VD1_un59_hilo_carry_1) # (VD1_un59_hilo_carry_0 & VD1L8281);
VD1_un59_hilo_add2 = VD1_op2_reged[2] $ VD1_hilo_34 $ !VD1_un59_hilo_add2_carry_eqn;
 
--VD1_un59_hilo_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_2 at LC_X9_Y6_N6
--operation mode is arithmetic
 
VD1_un59_hilo_carry_2_cout_0 = VD1_op2_reged[2] & VD1_hilo_34 # !VD1_un59_hilo_carry_1 # !VD1_op2_reged[2] & VD1_hilo_34 & !VD1_un59_hilo_carry_1;
VD1_un59_hilo_carry_2 = CARRY(VD1_un59_hilo_carry_2_cout_0);
 
--VD1L0381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_2~COUT1_1 at LC_X9_Y6_N6
--operation mode is arithmetic
 
VD1L0381_cout_1 = VD1_op2_reged[2] & VD1_hilo_34 # !VD1L8281 # !VD1_op2_reged[2] & VD1_hilo_34 & !VD1L8281;
VD1L0381 = CARRY(VD1L0381_cout_1);
 
 
--VD1_hilo_33_i_m_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[35] at LC_X3_Y6_N5
--operation mode is normal
 
VD1_hilo_33_i_m_a[35] = VD1_addnop2 & !VD1_un50_hilo_add3 # !VD1_addnop2 & !VD1_un59_hilo_add3;
 
 
--VD1_hilo_22_a[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[35] at LC_X6_Y6_N5
--operation mode is normal
 
VD1_hilo_22_a[35] = VD1_hilo[0] & VD1_sign & !VD1_hilo_36 # !VD1_sign & !VD1_un59_hilo_add4 # !VD1_hilo[0] & !VD1_hilo_36;
 
 
--VD1_hilo_15_2[35] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[35] at LC_X6_Y6_N2
--operation mode is normal
 
VD1_hilo_15_2[35] = VD1_sub_or_yn & VD1_un59_hilo_add4 # !VD1_sub_or_yn & VD1_un50_hilo_add4;
 
 
--UD1_shift_out_80_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[16] at LC_X9_Y18_N6
--operation mode is normal
 
UD1_shift_out_80_a[16] = PD1_a_o_1 & !VD1_b_o_iv_19 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_17;
 
 
--UD1_shift_out_52_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[28] at LC_X11_Y17_N5
--operation mode is normal
 
UD1_shift_out_52_a[28] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--UD1_shift_out_77_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[16] at LC_X11_Y18_N2
--operation mode is normal
 
UD1_shift_out_77_a[16] = PD1_a_o_0 & !VD1_b_o_iv_7 # !PD1_a_o_0 & !VD1_b_o_iv_8;
 
 
--VD1_un134_hilo_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[16] at LC_X5_Y15_N0
--operation mode is arithmetic
 
VD1_un134_hilo_combout[16]_carry_eqn = VD1_un134_hilo_cout[14];
VD1_un134_hilo_combout[16] = VD1_hilo_16 $ !VD1_un134_hilo_combout[16]_carry_eqn;
 
--VD1_un134_hilo_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[16] at LC_X5_Y15_N0
--operation mode is arithmetic
 
VD1_un134_hilo_cout[16]_cout_0 = VD1_hilo_17 & VD1_hilo_16 & !VD1_un134_hilo_cout[14];
VD1_un134_hilo_cout[16] = CARRY(VD1_un134_hilo_cout[16]_cout_0);
 
--VD1L7791 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[16]~COUT1_19 at LC_X5_Y15_N0
--operation mode is arithmetic
 
VD1L7791_cout_1 = VD1_hilo_17 & VD1_hilo_16 & !VD1_un134_hilo_cout[14];
VD1L7791 = CARRY(VD1L7791_cout_1);
 
 
--VD1_hilo_33_i_m[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[48] at LC_X3_Y4_N6
--operation mode is normal
 
VD1_hilo_33_i_m[48] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[48] # !VD1_hilo_33_1[64] & !VD1_hilo_48;
 
 
--VD1_hilo_37_iv_2_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[48] at LC_X3_Y4_N9
--operation mode is normal
 
VD1_hilo_37_iv_2_a[48] = VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add16 # !VD1_hilo_16 # !VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add16;
 
 
--VD1_hilo_22_Z[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[48] at LC_X3_Y4_N8
--operation mode is normal
 
VD1_hilo_22_Z[48] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[48] # !VD1_sign & !VD1_hilo_22_a[48] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[48];
 
 
--RD1_r32_o_0_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_16 at LC_X21_Y3_N0
--operation mode is arithmetic
 
RD1_r32_o_0_16_carry_eqn = RD1_r32_o_cout[14];
RD1_r32_o_0_16_lut_out = KB1_r32_o_16 $ RD1_r32_o_0_16_carry_eqn;
RD1_r32_o_0_16 = DFFEAS(RD1_r32_o_0_16_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[16] at LC_X21_Y3_N0
--operation mode is arithmetic
 
RD1_r32_o_cout[16]_cout_0 = !RD1_r32_o_cout[14] # !KB1_r32_o_16 # !KB1_r32_o_17;
RD1_r32_o_cout[16] = CARRY(RD1_r32_o_cout[16]_cout_0);
 
--RD1L98 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[16]~COUT1_5 at LC_X21_Y3_N0
--operation mode is arithmetic
 
RD1L98_cout_1 = !RD1_r32_o_cout[14] # !KB1_r32_o_16 # !KB1_r32_o_17;
RD1L98 = CARRY(RD1L98_cout_1);
 
 
--PD1_a_o_3_d[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[16] at LC_X25_Y4_N8
--operation mode is normal
 
PD1_a_o_3_d[16] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_16 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[16] # !PD1_un6_a_o & !PD1_a_o_3_d_a[16];
 
 
--UD1_shift_out_80_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[17] at LC_X7_Y17_N5
--operation mode is normal
 
UD1_shift_out_80_a[17] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_20 # !PD1_a_o_1 & !VD1_b_o_iv_18;
 
 
--UD1_shift_out_52_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[29] at LC_X20_Y15_N8
--operation mode is normal
 
UD1_shift_out_52_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_10 # !PD1_a_o_0 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--VD1_un134_hilo_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[17] at LC_X4_Y15_N0
--operation mode is arithmetic
 
VD1_un134_hilo_combout[17]_carry_eqn = VD1_un134_hilo_cout[15];
VD1_un134_hilo_combout[17] = VD1_hilo_17 $ (VD1_hilo_16 & !VD1_un134_hilo_combout[17]_carry_eqn);
 
--VD1_un134_hilo_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[17] at LC_X4_Y15_N0
--operation mode is arithmetic
 
VD1_un134_hilo_cout[17]_cout_0 = VD1_hilo_16 & VD1_hilo_17 & !VD1_un134_hilo_cout[15];
VD1_un134_hilo_cout[17] = CARRY(VD1_un134_hilo_cout[17]_cout_0);
 
--VD1L9791 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[17]~COUT1_7 at LC_X4_Y15_N0
--operation mode is arithmetic
 
VD1L9791_cout_1 = VD1_hilo_16 & VD1_hilo_17 & !VD1_un134_hilo_cout[15];
VD1L9791 = CARRY(VD1L9791_cout_1);
 
 
--VD1_hilo_33_i_m[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[49] at LC_X3_Y4_N4
--operation mode is normal
 
VD1_hilo_33_i_m[49] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[49] # !VD1_hilo_33_1[64] & !VD1_hilo_49;
 
 
--VD1_hilo_37_iv_2_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[49] at LC_X3_Y8_N4
--operation mode is normal
 
VD1_hilo_37_iv_2_a[49] = VD1_hilo_24_add17 & VD1_hilo_0_sqmuxa & !VD1_hilo_17 # !VD1_hilo_24_add17 & VD1_hilo_2_sqmuxa # VD1_hilo_0_sqmuxa & !VD1_hilo_17;
 
 
--VD1_hilo_22_Z[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[49] at LC_X7_Y4_N8
--operation mode is normal
 
VD1_hilo_22_Z[49] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[49] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[49] # !VD1_sign & !VD1_hilo_22_a[49];
 
 
--RD1_r32_o_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_17 at LC_X23_Y3_N0
--operation mode is arithmetic
 
RD1_r32_o_17_carry_eqn = RD1_r32_o_cout[15];
RD1_r32_o_17_lut_out = KB1_r32_o_17 $ (KB1_r32_o_16 & RD1_r32_o_17_carry_eqn);
RD1_r32_o_17 = DFFEAS(RD1_r32_o_17_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[17] at LC_X23_Y3_N0
--operation mode is arithmetic
 
RD1_r32_o_cout[17]_cout_0 = !RD1_r32_o_cout[15] # !KB1_r32_o_17 # !KB1_r32_o_16;
RD1_r32_o_cout[17] = CARRY(RD1_r32_o_cout[17]_cout_0);
 
--RD1L19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[17]~COUT1_16 at LC_X23_Y3_N0
--operation mode is arithmetic
 
RD1L19_cout_1 = !RD1_r32_o_cout[15] # !KB1_r32_o_17 # !KB1_r32_o_16;
RD1L19 = CARRY(RD1L19_cout_1);
 
 
--PD1_a_o_3_d[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[17] at LC_X22_Y5_N7
--operation mode is normal
 
PD1_a_o_3_d[17] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_17 # !PD1_un6_a_o & !PD1_a_o_3_d_a[17] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[17];
 
 
--UD1_shift_out_80_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[14] at LC_X20_Y17_N0
--operation mode is normal
 
UD1_shift_out_80_a[14] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_17 # !PD1_a_o_1 & !VD1_b_o_iv_15;
 
 
--UD1_shift_out_48_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[30] at LC_X16_Y17_N8
--operation mode is normal
 
UD1_shift_out_48_a[30] = PD1_a_o_0 & PD1_a_o_1 & !VD1_b_o_iv_7 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_8;
 
 
--UD1_shift_out_45_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[30] at LC_X12_Y16_N7
--operation mode is normal
 
UD1_shift_out_45_a[30] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_3 # !PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--UD1_shift_out_79_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[14] at LC_X15_Y18_N1
--operation mode is normal
 
UD1_shift_out_79_a[14] = PD1_a_o_0 & !VD1_b_o_iv_23 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_22;
 
 
--VD1_un134_hilo_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[14] at LC_X5_Y16_N9
--operation mode is arithmetic
 
VD1_un134_hilo_combout[14]_carry_eqn = (!VD1_un134_hilo_cout[4] & VD1_un134_hilo_cout[12]) # (VD1_un134_hilo_cout[4] & VD1L1791);
VD1_un134_hilo_combout[14] = VD1_hilo_14 $ VD1_un134_hilo_combout[14]_carry_eqn;
 
--VD1_un134_hilo_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[14] at LC_X5_Y16_N9
--operation mode is arithmetic
 
VD1_un134_hilo_cout[14] = CARRY(!VD1L1791 # !VD1_hilo_14 # !VD1_hilo_15);
 
 
--VD1_hilo_33_i_m[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[46] at LC_X4_Y4_N4
--operation mode is normal
 
VD1_hilo_33_i_m[46] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[46] # !VD1_hilo_33_1[64] & !VD1_hilo_46;
 
 
--VD1_hilo_37_iv_2_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[46] at LC_X3_Y7_N2
--operation mode is normal
 
VD1_hilo_37_iv_2_a[46] = VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add14 # !VD1_hilo_14 # !VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add14;
 
 
--VD1_hilo_22_Z[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[46] at LC_X3_Y5_N6
--operation mode is normal
 
VD1_hilo_22_Z[46] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[46] # !VD1_sign & !VD1_hilo_22_a[46] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[46];
 
 
--RD1_r32_o_0_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_14 at LC_X21_Y4_N9
--operation mode is arithmetic
 
RD1_r32_o_0_14_carry_eqn = (!RD1_r32_o_cout[4] & RD1_r32_o_cout[12]) # (RD1_r32_o_cout[4] & RD1L38);
RD1_r32_o_0_14_lut_out = KB1_r32_o_14 $ !RD1_r32_o_0_14_carry_eqn;
RD1_r32_o_0_14 = DFFEAS(RD1_r32_o_0_14_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[14] at LC_X21_Y4_N9
--operation mode is arithmetic
 
RD1_r32_o_cout[14] = CARRY(KB1_r32_o_15 & KB1_r32_o_14 & !RD1L38);
 
 
--PD1_a_o_3_d[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[14] at LC_X25_Y11_N2
--operation mode is normal
 
PD1_a_o_3_d[14] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_14 # !PD1_un6_a_o & !PD1_a_o_3_d_a[14] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[14];
 
 
--UD1_shift_out_80_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[15] at LC_X13_Y16_N8
--operation mode is normal
 
UD1_shift_out_80_a[15] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_18 # !PD1_a_o_1 & !VD1_b_o_iv_16;
 
 
--UD1_shift_out_48_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[31] at LC_X11_Y16_N6
--operation mode is normal
 
UD1_shift_out_48_a[31] = PD1_a_o_0 & !VD1_b_o_iv_8 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_9;
 
 
--UD1_shift_out_45_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[31] at LC_X12_Y16_N5
--operation mode is normal
 
UD1_shift_out_45_a[31] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_4 # !PD1_a_o_0 & !VD1_b_o_iv_5 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--VD1_un134_hilo_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[15] at LC_X4_Y16_N9
--operation mode is arithmetic
 
VD1_un134_hilo_combout[15]_carry_eqn = (!VD1_un134_hilo_cout[5] & VD1_un134_hilo_cout[13]) # (VD1_un134_hilo_cout[5] & VD1L3791);
VD1_un134_hilo_combout[15] = VD1_hilo_15 $ (VD1_hilo_14 & VD1_un134_hilo_combout[15]_carry_eqn);
 
--VD1_un134_hilo_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[15] at LC_X4_Y16_N9
--operation mode is arithmetic
 
VD1_un134_hilo_cout[15] = CARRY(!VD1L3791 # !VD1_hilo_15 # !VD1_hilo_14);
 
 
--VD1_hilo_33_i_m[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[47] at LC_X2_Y7_N4
--operation mode is normal
 
VD1_hilo_33_i_m[47] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[47] # !VD1_hilo_33_1[64] & !VD1_hilo_47;
 
 
--VD1_hilo_37_iv_2_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[47] at LC_X2_Y7_N2
--operation mode is normal
 
VD1_hilo_37_iv_2_a[47] = VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add15 # !VD1_hilo_15 # !VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add15;
 
 
--VD1_hilo_22_Z[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[47] at LC_X3_Y5_N9
--operation mode is normal
 
VD1_hilo_22_Z[47] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[47] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[47] # !VD1_sign & !VD1_hilo_22_a[47];
 
 
--RD1_r32_o_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_15 at LC_X23_Y4_N9
--operation mode is arithmetic
 
RD1_r32_o_15_carry_eqn = (!RD1_r32_o_cout[5] & RD1_r32_o_cout[13]) # (RD1_r32_o_cout[5] & RD1L58);
RD1_r32_o_15_lut_out = KB1_r32_o_15 $ (KB1_r32_o_14 & !RD1_r32_o_15_carry_eqn);
RD1_r32_o_15 = DFFEAS(RD1_r32_o_15_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[15] at LC_X23_Y4_N9
--operation mode is arithmetic
 
RD1_r32_o_cout[15] = CARRY(KB1_r32_o_15 & KB1_r32_o_14 & !RD1L58);
 
 
--PD1_a_o_3_d[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[15] at LC_X19_Y6_N6
--operation mode is normal
 
PD1_a_o_3_d[15] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_15 # !PD1_un6_a_o & !PD1_a_o_3_d_a[15] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[15];
 
 
--UD1_shift_out_52[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[31] at LC_X16_Y18_N4
--operation mode is normal
 
UD1_shift_out_52[31] = PD1_a_o_1 & !UD1_shift_out_52_a[31] # !PD1_a_o_1 & UD1_shift_out_52_a[31] & VD1_b_o_iv_15 # !UD1_shift_out_52_a[31] & VD1_b_o_iv_14;
 
 
--UD1_shift_out_75_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[31] at LC_X12_Y14_N2
--operation mode is normal
 
UD1_shift_out_75_a[31] = PD1_a_o_2 & !UD1_shift_out_43[31] & PD1_a_o_3 # !PD1_a_o_2 & !UD1_shift_out_45[31] # !PD1_a_o_3;
 
 
--VD1_hilo_37_iv_0_2[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[31] at LC_X4_Y5_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_2[31] = VD1_un50_hilo_add0 & VD1_hilo_37_iv_0_a3_4[57] # VD1_hilo_37_iv_0_a6_1_0[40] & VD1_un59_hilo_add0 # !VD1_un50_hilo_add0 & VD1_hilo_37_iv_0_a6_1_0[40] & VD1_un59_hilo_add0;
 
 
--VD1_hilo_37_iv_0_1[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[31] at LC_X6_Y13_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_1[31] = VD1_hilo_31 & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo_37_iv_0_1_a[31];
 
 
--VD1_hilo_22_i_m[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_i_m[63] at LC_X7_Y9_N3
--operation mode is normal
 
VD1_hilo_22_i_m[63] = VD1_hilo_1_sqmuxa_1 & VD1_sign & VD1_hilo_15_3_i[63] # !VD1_sign & VD1_hilo_22_i_m_a[63];
 
 
--VD1_hilo_33_3[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_3[63] at LC_X8_Y8_N5
--operation mode is normal
 
VD1_hilo_33_3[63] = VD1_addnop2 & VD1_hilo_33_1[64] & VD1_un50_hilo_add31 # !VD1_hilo_33_1[64] & !VD1_hilo_33_3_a[63] # !VD1_addnop2 & !VD1_hilo_33_3_a[63];
 
 
--VD1_hilo_37_iv_2_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[63] at LC_X7_Y13_N4
--operation mode is normal
 
VD1_hilo_37_iv_2_a[63] = VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_31 # !VD1_hilo_24_add31 # !VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_31;
 
 
--UD1_shift_out_87_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[8] at LC_X11_Y17_N0
--operation mode is normal
 
UD1_shift_out_87_d_a[8] = PD1_a_o_1 & !VD1_b_o_iv_14 # !PD1_a_o_1 & !VD1_b_o_iv_12;
 
 
--UD1_shift_out_80[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[8] at LC_X11_Y17_N7
--operation mode is normal
 
UD1_shift_out_80[8] = UD1_shift_out_80_a[8] & VD1_b_o_iv_13 & PD1_a_o_2 # !UD1_shift_out_80_a[8] & VD1_b_o_iv_15 # !PD1_a_o_2;
 
 
--UD1_shift_out_85_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[8] at LC_X12_Y16_N8
--operation mode is normal
 
UD1_shift_out_85_d_a[8] = PD1_a_o_0 & !VD1_b_o_iv_5 # !PD1_a_o_0 & !VD1_b_o_iv_6;
 
 
--UD1_shift_out_45[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45[28] at LC_X14_Y18_N3
--operation mode is normal
 
UD1_shift_out_45[28] = PD1_a_o_1 & !UD1_shift_out_45_a[28] # !PD1_a_o_1 & UD1_shift_out_45_a[28] & VD1_b_o_iv_4 # !UD1_shift_out_45_a[28] & VD1_b_o_iv_3;
 
 
--UD1_shift_out_91_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[8] at LC_X16_Y15_N9
--operation mode is normal
 
UD1_shift_out_91_a[8] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_8 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[8];
 
 
--UD1_shift_out_76[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[8] at LC_X21_Y17_N6
--operation mode is normal
 
UD1_shift_out_76[8] = UD1_shift_out587 & UD1_shift_out_79[20] & !PD1_a_o_3 & PD1_a_o_2;
 
 
--PD1_a_o_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[8] at LC_X21_Y4_N0
--operation mode is normal
 
PD1_a_o_a[8] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_8 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_8;
 
 
--PD1_a_o_3_Z[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[8] at LC_X19_Y8_N7
--operation mode is normal
 
SD1_r32_o_8_qfbk = SD1_r32_o_8;
PD1_a_o_3_Z[8] = PD1_a_o_3_s[0] & SD1_r32_o_8_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[8];
 
--SD1_r32_o_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_8 at LC_X19_Y8_N7
--operation mode is normal
 
SD1_r32_o_8 = DFFEAS(PD1_a_o_3_Z[8], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_8, , , VCC);
 
 
--TD1_un1_b_1_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[8] at LC_X13_Y5_N4
--operation mode is normal
 
TD1_un1_b_1_combout[8] = VD1_b_o_iv_8 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[9] at LC_X12_Y18_N0
--operation mode is normal
 
UD1_shift_out_87_d_a[9] = PD1_a_o_1 & !VD1_b_o_iv_15 # !PD1_a_o_1 & !VD1_b_o_iv_13;
 
 
--UD1_shift_out_80[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[9] at LC_X12_Y18_N9
--operation mode is normal
 
UD1_shift_out_80[9] = PD1_a_o_2 & UD1_shift_out_80_a[9] & VD1_b_o_iv_14 # !UD1_shift_out_80_a[9] & VD1_b_o_iv_16 # !PD1_a_o_2 & !UD1_shift_out_80_a[9];
 
 
--UD1_shift_out_85_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[9] at LC_X14_Y19_N6
--operation mode is normal
 
UD1_shift_out_85_d_a[9] = PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_0 & !VD1_b_o_iv_7;
 
 
--UD1_shift_out_74_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[9] at LC_X12_Y12_N9
--operation mode is normal
 
UD1_shift_out_74_a[9] = PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & PD1_a_o_3 & !VD1_b_o_iv_31 # !PD1_a_o_3 & !UD1_shift_out_39[17];
 
 
--UD1_shift_out_91_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[9] at LC_X13_Y13_N7
--operation mode is normal
 
UD1_shift_out_91_a[9] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_9 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[9];
 
 
--UD1_shift_out_76[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[9] at LC_X15_Y14_N9
--operation mode is normal
 
UD1_shift_out_76[9] = PD1_a_o_2 & !PD1_a_o_3 & UD1_shift_out587 & UD1_shift_out_42[1];
 
 
--VD1_hilo_37_iv_0_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[9] at LC_X4_Y17_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[9] = VD1_hilo_2_sqmuxa & !VD1_hilo_8 & !VD1_hilo_10 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2_sqmuxa & !VD1_hilo_10 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[9] at LC_X4_Y17_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_0[9] = VD1_hilo_9 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[9] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_9 & VD1_un134_hilo_combout[9] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_2[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[41] at LC_X7_Y8_N7
--operation mode is normal
 
VD1_hilo_37_iv_2[41] = VD1_hilo_33_i_m[41] # VD1_hilo_37_iv_2_a[41] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[41];
 
 
--VD1_hilo_37_iv_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[41] at LC_X9_Y9_N6
--operation mode is normal
 
VD1_hilo_37_iv_a[41] = RC1_alu_func_o_0 & !PD1_a_o_9 # !RC1_alu_func_o_0 & !VD1_hilo_41;
 
 
--PD1_a_o_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[9] at LC_X19_Y4_N2
--operation mode is normal
 
PD1_a_o_a[9] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_9 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_9;
 
 
--PD1_a_o_3_Z[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[9] at LC_X19_Y10_N3
--operation mode is normal
 
SD1_r32_o_9_qfbk = SD1_r32_o_9;
PD1_a_o_3_Z[9] = PD1_a_o_3_s[0] & SD1_r32_o_9_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[9];
 
--SD1_r32_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_9 at LC_X19_Y10_N3
--operation mode is normal
 
SD1_r32_o_9 = DFFEAS(PD1_a_o_3_Z[9], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_9, , , VCC);
 
 
--VD1_hilo_37_iv_0_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[10] at LC_X4_Y17_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[10] = VD1_hilo_2_sqmuxa & !VD1_hilo_9 & !VD1_hilo_11 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2_sqmuxa & !VD1_hilo_11 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[10] at LC_X4_Y17_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[10] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_10 # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[10] # !VD1_hilo_37_iv_0_o5[0] & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[10];
 
 
--VD1_hilo_37_iv_2[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[42] at LC_X7_Y13_N1
--operation mode is normal
 
VD1_hilo_37_iv_2[42] = VD1_hilo_37_iv_2_a[42] # VD1_hilo_33_i_m[42] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[42];
 
 
--VD1_hilo_37_iv_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[42] at LC_X9_Y9_N8
--operation mode is normal
 
VD1_hilo_37_iv_a[42] = RC1_alu_func_o_0 & !PD1_a_o_10 # !RC1_alu_func_o_0 & !VD1_hilo_42;
 
 
--RD1_r32_o_0_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_10 at LC_X21_Y4_N7
--operation mode is arithmetic
 
RD1_r32_o_0_10_carry_eqn = (!RD1_r32_o_cout[4] & RD1_r32_o_cout[8]) # (RD1_r32_o_cout[4] & RD1L57);
RD1_r32_o_0_10_lut_out = KB1_r32_o_10 $ !RD1_r32_o_0_10_carry_eqn;
RD1_r32_o_0_10 = DFFEAS(RD1_r32_o_0_10_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[10] at LC_X21_Y4_N7
--operation mode is arithmetic
 
RD1_r32_o_cout[10]_cout_0 = KB1_r32_o_11 & KB1_r32_o_10 & !RD1_r32_o_cout[8];
RD1_r32_o_cout[10] = CARRY(RD1_r32_o_cout[10]_cout_0);
 
--RD1L97 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[10]~COUT1_3 at LC_X21_Y4_N7
--operation mode is arithmetic
 
RD1L97_cout_1 = KB1_r32_o_11 & KB1_r32_o_10 & !RD1L57;
RD1L97 = CARRY(RD1L97_cout_1);
 
 
--PD1_a_o_3_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[10] at LC_X19_Y12_N7
--operation mode is normal
 
PD1_a_o_3_d[10] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_10 # !PD1_un6_a_o & !PD1_a_o_3_d_a[10] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[10];
 
 
--UD1_shift_out_87_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d[10] at LC_X16_Y18_N8
--operation mode is normal
 
UD1_shift_out_87_d[10] = PD1_a_o_0 & UD1_shift_out_80[10] # !PD1_a_o_0 & !UD1_shift_out_87_d_a[10];
 
 
--UD1_shift_out_85_d[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d[10] at LC_X11_Y18_N3
--operation mode is normal
 
UD1_shift_out_85_d[10] = PD1_a_o_2 & UD1_shift_out_45[30] # !PD1_a_o_2 & !UD1_shift_out_77_a[16];
 
 
--UD1_shift_out_76[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76[10] at LC_X14_Y17_N5
--operation mode is normal
 
UD1_shift_out_76[10] = UD1_shift_out_76_a[10] & PD1_a_o_0 & VD1_b_o_iv_31 # !PD1_a_o_0 & VD1_b_o_iv_30;
 
 
--UD1_shift_out_91_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[10] at LC_X14_Y17_N0
--operation mode is normal
 
UD1_shift_out_91_a[10] = UD1_shift_out_sn_b10_0 & !VD1_b_o_iv_10 # !UD1_shift_out_sn_b10_0 & !UD1_shift_out_79[10];
 
 
--UD1_shift_out_77[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[10] at LC_X14_Y18_N1
--operation mode is normal
 
UD1_shift_out_77[10] = !PD1_a_o_2 & PD1_a_o_1 & VD1_b_o_iv_0 & UD1_shift_out_77_a[10] # !PD1_a_o_1 & !UD1_shift_out_77_a[10];
 
 
--UD1_shift_out_86[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[10] at LC_X19_Y16_N3
--operation mode is normal
 
UD1_shift_out_86[10] = UD1_shift_out_sn_b9_0 & !UD1_shift_out_86_a[10] # !UD1_shift_out_sn_b9_0 & UD1_shift_out_74[10];
 
 
--UD1_shift_out_87_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[11] at LC_X13_Y18_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[11] = PD1_a_o_1 & !VD1_b_o_iv_17 # !PD1_a_o_1 & !VD1_b_o_iv_15;
 
 
--UD1_shift_out_80[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[11] at LC_X13_Y18_N4
--operation mode is normal
 
UD1_shift_out_80[11] = PD1_a_o_2 & UD1_shift_out_80_a[11] & VD1_b_o_iv_16 # !UD1_shift_out_80_a[11] & VD1_b_o_iv_18 # !PD1_a_o_2 & !UD1_shift_out_80_a[11];
 
 
--UD1_shift_out_85_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_d_a[11] at LC_X11_Y16_N4
--operation mode is normal
 
UD1_shift_out_85_d_a[11] = PD1_a_o_0 & !VD1_b_o_iv_8 # !PD1_a_o_0 & !VD1_b_o_iv_9;
 
 
--UD1_shift_out_91_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_91_a[11] at LC_X15_Y15_N4
--operation mode is normal
 
UD1_shift_out_91_a[11] = PD1_a_o_2 & UD1_shift_out_39[19] & !PD1_a_o_1 & !PD1_a_o_3;
 
 
--UD1_shift_out_88[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88[11] at LC_X15_Y16_N1
--operation mode is normal
 
UD1_shift_out_88[11] = UD1_shift_out_sn_b10_0 & VD1_b_o_iv_11 # !UD1_shift_out_sn_b10_0 & UD1_shift_out_79[11];
 
 
--VD1_hilo_37_iv_0_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[11] at LC_X4_Y17_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_a[11] = VD1_hilo_2_sqmuxa & !VD1_hilo_10 & !VD1_hilo_12 # !VD1_hilo_1_sqmuxa_1 # !VD1_hilo_2_sqmuxa & !VD1_hilo_12 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_0_0[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[11] at LC_X4_Y17_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_0[11] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_11 # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[11] # !VD1_hilo_37_iv_0_o5[0] & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[11];
 
 
--VD1_hilo_37_iv_2[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[43] at LC_X7_Y6_N3
--operation mode is normal
 
VD1_hilo_37_iv_2[43] = VD1_hilo_37_iv_2_a[43] # VD1_hilo_33_i_m[43] # !VD1_hilo_22_Z[43] & VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[43] at LC_X4_Y8_N1
--operation mode is normal
 
VD1_hilo_37_iv_a[43] = RC1_alu_func_o_0 & !PD1_a_o_11 # !RC1_alu_func_o_0 & !VD1_hilo_43;
 
 
--PD1_a_o_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[11] at LC_X23_Y4_N0
--operation mode is normal
 
PD1_a_o_a[11] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_11 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_11;
 
 
--PD1_a_o_3_Z[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[11] at LC_X22_Y10_N8
--operation mode is normal
 
SD1_r32_o_11_qfbk = SD1_r32_o_11;
PD1_a_o_3_Z[11] = PD1_a_o_3_s[0] & SD1_r32_o_11_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[11];
 
--SD1_r32_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_11 at LC_X22_Y10_N8
--operation mode is normal
 
SD1_r32_o_11 = DFFEAS(PD1_a_o_3_Z[11], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_11, , , VCC);
 
 
--TD1_un1_b_1_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[11] at LC_X13_Y5_N5
--operation mode is normal
 
TD1_un1_b_1_combout[11] = VD1_b_o_iv_11 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_80_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[21] at LC_X7_Y18_N7
--operation mode is normal
 
UD1_shift_out_80_a[21] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_24 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_22;
 
 
--UD1_shift_out_54_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[29] at LC_X19_Y18_N8
--operation mode is normal
 
UD1_shift_out_54_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_14 # !PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--UD1_shift_out_79_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[21] at LC_X14_Y10_N3
--operation mode is normal
 
UD1_shift_out_79_a[21] = PD1_a_o_1 & !PD1_a_o_0 # !PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_30 # !PD1_a_o_0 & !VD1_b_o_iv_29;
 
 
--VD1_un134_hilo_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[21] at LC_X4_Y15_N2
--operation mode is arithmetic
 
VD1_un134_hilo_combout[21]_carry_eqn = (!VD1_un134_hilo_cout[15] & VD1_un134_hilo_cout[19]) # (VD1_un134_hilo_cout[15] & VD1L3891);
VD1_un134_hilo_combout[21] = VD1_hilo_21 $ (VD1_hilo_20 & !VD1_un134_hilo_combout[21]_carry_eqn);
 
--VD1_un134_hilo_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[21] at LC_X4_Y15_N2
--operation mode is arithmetic
 
VD1_un134_hilo_cout[21]_cout_0 = VD1_hilo_20 & VD1_hilo_21 & !VD1_un134_hilo_cout[19];
VD1_un134_hilo_cout[21] = CARRY(VD1_un134_hilo_cout[21]_cout_0);
 
--VD1L7891 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[21]~COUT1_9 at LC_X4_Y15_N2
--operation mode is arithmetic
 
VD1L7891_cout_1 = VD1_hilo_20 & VD1_hilo_21 & !VD1L3891;
VD1L7891 = CARRY(VD1L7891_cout_1);
 
 
--VD1_hilo_33_i_m[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[53] at LC_X6_Y4_N6
--operation mode is normal
 
VD1_hilo_33_i_m[53] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[53] # !VD1_hilo_33_1[64] & !VD1_hilo_53;
 
 
--VD1_hilo_37_iv_2_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[53] at LC_X6_Y4_N3
--operation mode is normal
 
VD1_hilo_37_iv_2_a[53] = VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_21 # !VD1_hilo_24_add21 # !VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_21;
 
 
--VD1_hilo_22_Z[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[53] at LC_X7_Y4_N7
--operation mode is normal
 
VD1_hilo_22_Z[53] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[53] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[53] # !VD1_sign & !VD1_hilo_22_a[53];
 
 
--RD1_r32_o_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_21 at LC_X23_Y3_N2
--operation mode is arithmetic
 
RD1_r32_o_21_carry_eqn = (!RD1_r32_o_cout[15] & RD1_r32_o_cout[19]) # (RD1_r32_o_cout[15] & RD1L59);
RD1_r32_o_21_lut_out = KB1_r32_o_21 $ (KB1_r32_o_20 & RD1_r32_o_21_carry_eqn);
RD1_r32_o_21 = DFFEAS(RD1_r32_o_21_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[21] at LC_X23_Y3_N2
--operation mode is arithmetic
 
RD1_r32_o_cout[21]_cout_0 = !RD1_r32_o_cout[19] # !KB1_r32_o_21 # !KB1_r32_o_20;
RD1_r32_o_cout[21] = CARRY(RD1_r32_o_cout[21]_cout_0);
 
--RD1L99 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[21]~COUT1_18 at LC_X23_Y3_N2
--operation mode is arithmetic
 
RD1L99_cout_1 = !RD1L59 # !KB1_r32_o_21 # !KB1_r32_o_20;
RD1L99 = CARRY(RD1L99_cout_1);
 
 
--PD1_a_o_3_d[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[21] at LC_X25_Y5_N9
--operation mode is normal
 
PD1_a_o_3_d[21] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_21 # !PD1_un6_a_o & !PD1_a_o_3_d_a[21] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[21];
 
 
--UD1_shift_out_80_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[20] at LC_X6_Y18_N6
--operation mode is normal
 
UD1_shift_out_80_a[20] = PD1_a_o_1 & !VD1_b_o_iv_23 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_21;
 
 
--UD1_shift_out_54_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[28] at LC_X10_Y18_N6
--operation mode is normal
 
UD1_shift_out_54_a[28] = PD1_a_o_0 & !VD1_b_o_iv_13 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_14;
 
 
--VD1_un134_hilo_combout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[20] at LC_X5_Y15_N2
--operation mode is arithmetic
 
VD1_un134_hilo_combout[20]_carry_eqn = (!VD1_un134_hilo_cout[14] & VD1_un134_hilo_cout[18]) # (VD1_un134_hilo_cout[14] & VD1L1891);
VD1_un134_hilo_combout[20] = VD1_hilo_20 $ !VD1_un134_hilo_combout[20]_carry_eqn;
 
--VD1_un134_hilo_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[20] at LC_X5_Y15_N2
--operation mode is arithmetic
 
VD1_un134_hilo_cout[20]_cout_0 = VD1_hilo_21 & VD1_hilo_20 & !VD1_un134_hilo_cout[18];
VD1_un134_hilo_cout[20] = CARRY(VD1_un134_hilo_cout[20]_cout_0);
 
--VD1L5891 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[20]~COUT1_21 at LC_X5_Y15_N2
--operation mode is arithmetic
 
VD1L5891_cout_1 = VD1_hilo_21 & VD1_hilo_20 & !VD1L1891;
VD1L5891 = CARRY(VD1L5891_cout_1);
 
 
--VD1_hilo_24_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add20 at LC_X8_Y3_N4
--operation mode is arithmetic
 
VD1_hilo_24_add20_carry_eqn = (!VD1_hilo_24_carry_15 & VD1_hilo_24_carry_19) # (VD1_hilo_24_carry_15 & VD1L215);
VD1_hilo_24_add20 = VD1_un1_op2_reged_1_i_m6[20] $ VD1_hilo_51 $ !VD1_hilo_24_add20_carry_eqn;
 
--VD1_hilo_24_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_20 at LC_X8_Y3_N4
--operation mode is arithmetic
 
VD1_hilo_24_carry_20 = CARRY(VD1_un1_op2_reged_1_i_m6[20] & VD1_hilo_51 # !VD1L215 # !VD1_un1_op2_reged_1_i_m6[20] & VD1_hilo_51 & !VD1L215);
 
 
--VD1_hilo_37_iv_0_3[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[52] at LC_X6_Y4_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_3[52] = VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add21 # !VD1_hilo_53 # !VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add21;
 
 
--VD1_hilo_37_iv_0_4[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[52] at LC_X6_Y4_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_4[52] = VD1_hilo_37_iv_0_4_a[52] # VD1_hilo_37_iv_0_1[52] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add20;
 
 
--RD1_r32_o_0_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_20 at LC_X21_Y3_N2
--operation mode is arithmetic
 
RD1_r32_o_0_20_carry_eqn = (!RD1_r32_o_cout[14] & RD1_r32_o_cout[18]) # (RD1_r32_o_cout[14] & RD1L39);
RD1_r32_o_0_20_lut_out = KB1_r32_o_20 $ (RD1_r32_o_0_20_carry_eqn);
RD1_r32_o_0_20 = DFFEAS(RD1_r32_o_0_20_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[20] at LC_X21_Y3_N2
--operation mode is arithmetic
 
RD1_r32_o_cout[20]_cout_0 = !RD1_r32_o_cout[18] # !KB1_r32_o_21 # !KB1_r32_o_20;
RD1_r32_o_cout[20] = CARRY(RD1_r32_o_cout[20]_cout_0);
 
--RD1L79 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[20]~COUT1_7 at LC_X21_Y3_N2
--operation mode is arithmetic
 
RD1L79_cout_1 = !RD1L39 # !KB1_r32_o_21 # !KB1_r32_o_20;
RD1L79 = CARRY(RD1L79_cout_1);
 
 
--PD1_a_o_3_d[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[20] at LC_X22_Y13_N2
--operation mode is normal
 
PD1_a_o_3_d[20] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_20 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[20] # !PD1_un6_a_o & !PD1_a_o_3_d_a[20];
 
 
--TD1_un1_b_1_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[19] at LC_X12_Y11_N5
--operation mode is normal
 
TD1_un1_b_1_combout[19] = VD1_b_o_iv_19 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_43[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_43[28] at LC_X9_Y17_N7
--operation mode is normal
 
UD1_shift_out_43[28] = !PD1_a_o_1 & !PD1_a_o_0 & VD1_b_o_iv_0;
 
 
--UD1_shift_out_48[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48[28] at LC_X15_Y11_N7
--operation mode is normal
 
UD1_shift_out_48[28] = PD1_a_o_1 & !UD1_shift_out_48_a[28] # !PD1_a_o_1 & UD1_shift_out_48_a[28] & VD1_b_o_iv_8 # !UD1_shift_out_48_a[28] & VD1_b_o_iv_7;
 
 
--UD1_shift_out_87_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[19] at LC_X10_Y9_N6
--operation mode is normal
 
UD1_shift_out_87_d_a[19] = PD1_a_o_1 & !VD1_b_o_iv_25 # !PD1_a_o_1 & !VD1_b_o_iv_23;
 
 
--UD1_shift_out_80[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[19] at LC_X10_Y9_N8
--operation mode is normal
 
UD1_shift_out_80[19] = PD1_a_o_2 & UD1_shift_out_80_a[19] & VD1_b_o_iv_24 # !UD1_shift_out_80_a[19] & VD1_b_o_iv_26 # !PD1_a_o_2 & !UD1_shift_out_80_a[19];
 
 
--UD1_shift_out_77_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[25] at LC_X14_Y12_N4
--operation mode is normal
 
UD1_shift_out_77_a[25] = PD1_a_o_0 & !VD1_b_o_iv_16 # !PD1_a_o_0 & !VD1_b_o_iv_17;
 
 
--VD1_hilo_37_iv_0_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[19] at LC_X4_Y14_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a[19] = VD1_hilo_20 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_18 # !VD1_hilo_2_sqmuxa # !VD1_hilo_20 & !VD1_hilo_18 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[19] at LC_X4_Y14_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[19] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_19 # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[19] # !VD1_hilo_37_iv_0_o5[0] & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[19];
 
 
--VD1_hilo_37_iv_0_8[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8[51] at LC_X5_Y5_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_8[51] = VD1_hilo_37_iv_0_8_a[51] # VD1_hilo_37_iv_0_6[51] # !PD1_a_o_19 & VD1_hilo_37_iv_0_a3_1[0];
 
 
--PD1_a_o_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[19] at LC_X22_Y15_N5
--operation mode is normal
 
PD1_a_o_a[19] = SC1_muxa_ctl_o_1 & !FB1_r32_o_19 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_19;
 
 
--PD1_a_o_3_Z[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[19] at LC_X22_Y6_N8
--operation mode is normal
 
SD1_r32_o_19_qfbk = SD1_r32_o_19;
PD1_a_o_3_Z[19] = PD1_a_o_3_s[0] & SD1_r32_o_19_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[19];
 
--SD1_r32_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_19 at LC_X22_Y6_N8
--operation mode is normal
 
SD1_r32_o_19 = DFFEAS(PD1_a_o_3_Z[19], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_19, , , VCC);
 
 
--UD1_shift_out_84_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[19] at LC_X11_Y16_N8
--operation mode is normal
 
UD1_shift_out_84_a[19] = PD1_a_o_2 & !UD1_shift_out_45[31] # !PD1_a_o_2 & !UD1_shift_out_48[31];
 
 
--UD1_shift_out_87_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[18] at LC_X7_Y18_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[18] = PD1_a_o_1 & !VD1_b_o_iv_24 # !PD1_a_o_1 & !VD1_b_o_iv_22;
 
 
--UD1_shift_out_80[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[18] at LC_X7_Y18_N5
--operation mode is normal
 
UD1_shift_out_80[18] = UD1_shift_out_80_a[18] & PD1_a_o_2 & VD1_b_o_iv_23 # !UD1_shift_out_80_a[18] & VD1_b_o_iv_25 # !PD1_a_o_2;
 
 
--UD1_shift_out_77_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[24] at LC_X9_Y17_N9
--operation mode is normal
 
UD1_shift_out_77_a[24] = PD1_a_o_0 & !VD1_b_o_iv_15 # !PD1_a_o_0 & !VD1_b_o_iv_16;
 
 
--UD1_shift_out_52[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52[30] at LC_X10_Y18_N2
--operation mode is normal
 
UD1_shift_out_52[30] = UD1_shift_out_52_a[30] & VD1_b_o_iv_14 & !PD1_a_o_1 # !UD1_shift_out_52_a[30] & VD1_b_o_iv_13 # PD1_a_o_1;
 
 
--UD1_shift_out_83_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_83_a[18] at LC_X13_Y17_N4
--operation mode is normal
 
UD1_shift_out_83_a[18] = PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !VD1_b_o_iv_30;
 
 
--UD1_shift_out_77[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[18] at LC_X11_Y18_N7
--operation mode is normal
 
UD1_shift_out_77[18] = PD1_a_o_2 & UD1_shift_out_85_d[10] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[10] # !PD1_a_o_1 & !UD1_shift_out_77_a[18];
 
 
--VD1_hilo_37_iv_1[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[18] at LC_X3_Y16_N4
--operation mode is normal
 
VD1_hilo_37_iv_1[18] = VD1_hilo_2_sqmuxa & VD1_hilo_17 # !VD1_hilo_37_iv_1_a[18];
 
 
--VD1_hilo_37_iv_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[18] at LC_X5_Y14_N7
--operation mode is normal
 
VD1_hilo_37_iv_a[18] = RC1_alu_func_o_0 & !VD1_hilo_18 # !RC1_alu_func_o_0 & !PD1_a_o_18 # !VD1_hilo25;
 
 
--VD1_hilo_37_iv_0_4[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4[50] at LC_X6_Y5_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_4[50] = VD1_hilo_37_iv_0_a6_1_0[40] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add18 # !VD1_un59_hilo_add19 # !VD1_hilo_37_iv_0_a6_1_0[40] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add18;
 
 
--VD1_hilo_37_iv_0_5[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[50] at LC_X6_Y3_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_5[50] = VD1_hilo_37_iv_0_5_a[50] # VD1_hilo_37_iv_0_1[50] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add19;
 
 
--VD1_hilo_37_iv_0_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[50] at LC_X6_Y5_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[50] = PD1_a_o_18 & !VD1_hilo_24_add18 & VD1_hilo_2_sqmuxa # !PD1_a_o_18 & VD1_hilo_37_iv_0_a3_1[0] # !VD1_hilo_24_add18 & VD1_hilo_2_sqmuxa;
 
 
--PD1_a_o_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[18] at LC_X22_Y12_N7
--operation mode is normal
 
PD1_a_o_a[18] = SC1_muxa_ctl_o_1 & !FB1_r32_o_18 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_18;
 
 
--PD1_a_o_3_Z[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[18] at LC_X19_Y5_N3
--operation mode is normal
 
SD1_r32_o_18_qfbk = SD1_r32_o_18;
PD1_a_o_3_Z[18] = PD1_a_o_3_s[0] & SD1_r32_o_18_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[18];
 
--SD1_r32_o_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_18 at LC_X19_Y5_N3
--operation mode is normal
 
SD1_r32_o_18 = DFFEAS(PD1_a_o_3_Z[18], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_18, , , VCC);
 
 
--TD1_un1_b_1_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[18] at LC_X14_Y5_N2
--operation mode is normal
 
TD1_un1_b_1_combout[18] = VD1_b_o_iv_18 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[26] at LC_X8_Y15_N9
--operation mode is normal
 
UD1_shift_out_87_d_a[26] = PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_30;
 
 
--UD1_shift_out_80[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[26] at LC_X8_Y15_N3
--operation mode is normal
 
UD1_shift_out_80[26] = PD1_a_o_2 & UD1_shift_out_80_a[26] & VD1_b_o_iv_31 # !UD1_shift_out_80_a[26] & UD1_shift_out_36_0 # !PD1_a_o_2 & !UD1_shift_out_80_a[26];
 
 
--UD1_shift_out_84_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[26] at LC_X11_Y15_N1
--operation mode is normal
 
UD1_shift_out_84_a[26] = PD1_a_o_4 & !UD1_shift_out_77[10] # !PD1_a_o_4 & !UD1_shift_out_77[26];
 
 
--VD1_hilo_37_iv_0_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[26] at LC_X3_Y15_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a[26] = VD1_hilo_27 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_25 # !VD1_hilo_2_sqmuxa # !VD1_hilo_27 & !VD1_hilo_25 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[26] at LC_X3_Y15_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[26] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_26 # VD1_un134_hilo_combout[26] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_37_iv_0_o5[0] & VD1_un134_hilo_combout[26] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_0_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[58] at LC_X6_Y9_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_1[58] = VD1_hilo_37_iv_0_1_a[58] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add26;
 
 
--VD1_hilo_37_iv_0_o3_1_0_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1[58] at LC_X5_Y3_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_1_0_1[58] = VD1_hilo_37_iv_0_a3[57] # VD1_hilo_37_iv_0_o3_1_0_1_1[58] # VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_26;
 
 
--VD1_hilo_37_iv_0_o3[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[58] at LC_X5_Y3_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_o3[58] = VD1_hilo_37_iv_0_o3_a[58] # !VD1_hilo_33_1[64] & VD1_hilo_37_iv_0_o3_1_0_1[58] # !VD1_hilo_58;
 
 
--PD1_a_o_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[26] at LC_X23_Y14_N2
--operation mode is normal
 
PD1_a_o_a[26] = SC1_muxa_ctl_o_1 & !FB1_r32_o_26 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_26;
 
 
--PD1_a_o_3_Z[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[26] at LC_X21_Y10_N3
--operation mode is normal
 
SD1_r32_o_26_qfbk = SD1_r32_o_26;
PD1_a_o_3_Z[26] = PD1_a_o_3_s[0] & SD1_r32_o_26_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[26];
 
--SD1_r32_o_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_26 at LC_X21_Y10_N3
--operation mode is normal
 
SD1_r32_o_26 = DFFEAS(PD1_a_o_3_Z[26], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_26, , , VCC);
 
 
--TD1_un1_b_1_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[26] at LC_X12_Y7_N9
--operation mode is normal
 
TD1_un1_b_1_combout[26] = VD1_b_o_iv_26 $ (!TD1_sum13_0_a2);
 
 
--UD1_shift_out_87_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[27] at LC_X11_Y7_N6
--operation mode is normal
 
UD1_shift_out_87_d_a[27] = PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_31;
 
 
--UD1_shift_out_80[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[27] at LC_X11_Y7_N3
--operation mode is normal
 
UD1_shift_out_80[27] = PD1_a_o_1 & !UD1_shift_out_80_a[27] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_80_a[27] # !PD1_a_o_2 & VD1_b_o_iv_28;
 
 
--UD1_shift_out_77[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[27] at LC_X14_Y12_N3
--operation mode is normal
 
UD1_shift_out_77[27] = PD1_a_o_2 & UD1_shift_out_85_d[19] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[19] # !PD1_a_o_1 & !UD1_shift_out_77_a[27];
 
 
--UD1_shift_out_75[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[27] at LC_X15_Y12_N0
--operation mode is normal
 
UD1_shift_out_75[27] = PD1_a_o_3 & UD1_shift_out_77[11] # !PD1_a_o_3 & !UD1_shift_out_84_a[19];
 
 
--VD1_hilo_37_iv_0[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[27] at LC_X3_Y15_N4
--operation mode is normal
 
VD1_hilo_37_iv_0[27] = VD1_hilo_28 & VD1_hilo_1_sqmuxa_1 # VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[27] # !VD1_hilo_28 & VD1_hilo_3_sqmuxa & !VD1_hilo_37_iv_0_a[27];
 
 
--VD1_hilo_8_Z[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[27] at LC_X3_Y15_N3
--operation mode is normal
 
VD1_hilo_8_Z[27] = RC1_alu_func_o_0 & VD1_hilo_27 # !RC1_alu_func_o_0 & PD1_a_o_27;
 
 
--VD1_hilo_37_iv_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[27] at LC_X3_Y15_N5
--operation mode is normal
 
VD1_hilo_37_iv_a[27] = VD1_hilo_26 & !VD1_hilo_2_sqmuxa & !PD1_a_o_27 # !VD1_addnop2109_0_a2 # !VD1_hilo_26 & !PD1_a_o_27 # !VD1_addnop2109_0_a2;
 
 
--VD1_hilo_37_iv_0_a[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[59] at LC_X5_Y2_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[59] = !VD1_hilo_37_iv_0_6[59] & VD1_hilo_24_add27 # !VD1_hilo_2_sqmuxa;
 
 
--PD1_a_o_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[27] at LC_X22_Y4_N4
--operation mode is normal
 
PD1_a_o_a[27] = SC1_muxa_ctl_o_1 & !FB1_r32_o_27 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_27;
 
 
--PD1_a_o_3_Z[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[27] at LC_X22_Y4_N3
--operation mode is normal
 
SD1_r32_o_27_qfbk = SD1_r32_o_27;
PD1_a_o_3_Z[27] = PD1_a_o_3_s[0] & SD1_r32_o_27_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[27];
 
--SD1_r32_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_27 at LC_X22_Y4_N3
--operation mode is normal
 
SD1_r32_o_27 = DFFEAS(PD1_a_o_3_Z[27], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_27, , , VCC);
 
 
--TD1_un1_b_1_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[27] at LC_X14_Y6_N5
--operation mode is normal
 
TD1_un1_b_1_combout[27] = TD1_sum13_0_a2 $ !VD1_b_o_iv_27;
 
 
--UD1_shift_out_87_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[28] at LC_X8_Y16_N5
--operation mode is normal
 
UD1_shift_out_87_d_a[28] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_29;
 
 
--UD1_shift_out_68[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[28] at LC_X8_Y17_N4
--operation mode is normal
 
UD1_shift_out_68[28] = PD1_a_o_0 & VD1_b_o_iv_25 # !PD1_a_o_0 & VD1_b_o_iv_26;
 
 
--PD1_a_o_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[28] at LC_X21_Y3_N8
--operation mode is normal
 
PD1_a_o_a[28] = SC1_muxa_ctl_o_1 & !FB1_r32_o_28 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_28;
 
 
--PD1_a_o_3_Z[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[28] at LC_X16_Y7_N8
--operation mode is normal
 
SD1_r32_o_28_qfbk = SD1_r32_o_28;
PD1_a_o_3_Z[28] = PD1_a_o_3_s[0] & SD1_r32_o_28_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[28];
 
--SD1_r32_o_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_28 at LC_X16_Y7_N8
--operation mode is normal
 
SD1_r32_o_28 = DFFEAS(PD1_a_o_3_Z[28], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_28, , , VCC);
 
 
--TD1_alu_out_9_a2_1_1_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_9_a2_1_1_0 at LC_X7_Y15_N5
--operation mode is normal
 
TD1_alu_out_9_a2_1_1_0 = TD1_m107 & !RC1_alu_func_o_3 & RC1_alu_func_o_2 $ !RC1_alu_func_o_0;
 
 
--MD1_c_0_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_0_a[28] at LC_X7_Y15_N2
--operation mode is normal
 
MD1_c_0_a[28] = VD1_un24_res & !VD1_hilo_60 # !VD1_un24_res & !VD1_hilo_28 # !VD1_un11_res;
 
 
--UD1_shift_out_75[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[28] at LC_X10_Y17_N2
--operation mode is normal
 
UD1_shift_out_75[28] = PD1_a_o_3 & UD1_shift_out_75_a[28] & UD1_shift_out_45[28] # !UD1_shift_out_75_a[28] & UD1_shift_out_43[28] # !PD1_a_o_3 & !UD1_shift_out_75_a[28];
 
 
--UD1_shift_out_77[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[28] at LC_X8_Y18_N3
--operation mode is normal
 
UD1_shift_out_77[28] = PD1_a_o_2 & !UD1_shift_out_77_a[28] # !PD1_a_o_2 & UD1_shift_out_77_a[28] & UD1_shift_out_68[22] # !UD1_shift_out_77_a[28] & UD1_shift_out_68[20];
 
 
--UD1_shift_out_84_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[29] at LC_X14_Y11_N1
--operation mode is normal
 
UD1_shift_out_84_a[29] = PD1_a_o_1 & !UD1_shift_out_85_d[21] # !PD1_a_o_1 & PD1_a_o_2 & !UD1_shift_out_85_d[21] # !PD1_a_o_2 & !UD1_shift_out_68[23];
 
 
--UD1_shift_out_75[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[29] at LC_X14_Y11_N8
--operation mode is normal
 
UD1_shift_out_75[29] = PD1_a_o_3 & UD1_shift_out_63[21] # !PD1_a_o_3 & UD1_shift_out_77[21];
 
 
--VD1_hilo_37_iv_0_a[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[61] at LC_X9_Y2_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[61] = !VD1_hilo_37_iv_0_6[61] & VD1_hilo_24_add29 # !VD1_hilo_2_sqmuxa;
 
 
--UD1_shift_out_80_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[13] at LC_X13_Y18_N0
--operation mode is normal
 
UD1_shift_out_80_a[13] = PD1_a_o_1 & !VD1_b_o_iv_16 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_14;
 
 
--UD1_shift_out_48_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[29] at LC_X15_Y11_N8
--operation mode is normal
 
UD1_shift_out_48_a[29] = PD1_a_o_1 & PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_0 & !VD1_b_o_iv_7 # !PD1_a_o_1 & !PD1_a_o_0;
 
 
--UD1_shift_out_45_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[29] at LC_X14_Y19_N2
--operation mode is normal
 
UD1_shift_out_45_a[29] = PD1_a_o_0 & !VD1_b_o_iv_2 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_3;
 
 
--VD1_un134_hilo_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[13] at LC_X4_Y16_N8
--operation mode is arithmetic
 
VD1_un134_hilo_combout[13]_carry_eqn = (!VD1_un134_hilo_cout[5] & VD1_un134_hilo_cout[11]) # (VD1_un134_hilo_cout[5] & VD1L9691);
VD1_un134_hilo_combout[13] = VD1_hilo_13 $ (VD1_hilo_12 & !VD1_un134_hilo_combout[13]_carry_eqn);
 
--VD1_un134_hilo_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[13] at LC_X4_Y16_N8
--operation mode is arithmetic
 
VD1_un134_hilo_cout[13]_cout_0 = VD1_hilo_13 & VD1_hilo_12 & !VD1_un134_hilo_cout[11];
VD1_un134_hilo_cout[13] = CARRY(VD1_un134_hilo_cout[13]_cout_0);
 
--VD1L3791 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[13]~COUT1_6 at LC_X4_Y16_N8
--operation mode is arithmetic
 
VD1L3791_cout_1 = VD1_hilo_13 & VD1_hilo_12 & !VD1L9691;
VD1L3791 = CARRY(VD1L3791_cout_1);
 
 
--VD1_hilo_33_i_m[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[45] at LC_X8_Y9_N8
--operation mode is normal
 
VD1_hilo_33_i_m[45] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[45] # !VD1_hilo_33_1[64] & !VD1_hilo_45;
 
 
--VD1_hilo_37_iv_2_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[45] at LC_X8_Y9_N5
--operation mode is normal
 
VD1_hilo_37_iv_2_a[45] = VD1_hilo_0_sqmuxa & !VD1_hilo_24_add13 & VD1_hilo_2_sqmuxa # !VD1_hilo_13 # !VD1_hilo_0_sqmuxa & !VD1_hilo_24_add13 & VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_22_Z[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[45] at LC_X4_Y4_N6
--operation mode is normal
 
VD1_hilo_22_Z[45] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[45] # !VD1_sign & !VD1_hilo_22_a[45] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[45];
 
 
--RD1_r32_o_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_13 at LC_X23_Y4_N8
--operation mode is arithmetic
 
RD1_r32_o_13_carry_eqn = (!RD1_r32_o_cout[5] & RD1_r32_o_cout[11]) # (RD1_r32_o_cout[5] & RD1L18);
RD1_r32_o_13_lut_out = KB1_r32_o_13 $ (KB1_r32_o_12 & RD1_r32_o_13_carry_eqn);
RD1_r32_o_13 = DFFEAS(RD1_r32_o_13_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[13] at LC_X23_Y4_N8
--operation mode is arithmetic
 
RD1_r32_o_cout[13]_cout_0 = !RD1_r32_o_cout[11] # !KB1_r32_o_13 # !KB1_r32_o_12;
RD1_r32_o_cout[13] = CARRY(RD1_r32_o_cout[13]_cout_0);
 
--RD1L58 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[13]~COUT1_15 at LC_X23_Y4_N8
--operation mode is arithmetic
 
RD1L58_cout_1 = !RD1L18 # !KB1_r32_o_13 # !KB1_r32_o_12;
RD1L58 = CARRY(RD1L58_cout_1);
 
 
--PD1_a_o_3_d[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[13] at LC_X24_Y9_N1
--operation mode is normal
 
PD1_a_o_3_d[13] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_13 # !PD1_un6_a_o & !PD1_a_o_3_d_a[13] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[13];
 
 
--TD1_un1_b_1_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[12] at LC_X13_Y7_N2
--operation mode is normal
 
TD1_un1_b_1_combout[12] = VD1_b_o_iv_12 $ !TD1_sum13_0_a2;
 
 
--VD1_hilo_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_28 at LC_X3_Y17_N5
--operation mode is normal
 
VD1_hilo_28_lut_out = VD1_hilo_37_iv_0_0[28] # PD1_a_o_28 & VD1_hilo_37_iv_0_o5_0[0] # !VD1_hilo_37_iv_0_a[28];
VD1_hilo_28 = DFFEAS(VD1_hilo_28_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--VD1_un134_hilo_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[29] at LC_X4_Y15_N6
--operation mode is arithmetic
 
VD1_un134_hilo_combout[29]_carry_eqn = (!VD1_un134_hilo_cout[25] & VD1_un134_hilo_cout[27]) # (VD1_un134_hilo_cout[25] & VD1L7991);
VD1_un134_hilo_combout[29] = VD1_hilo_29 $ (VD1_hilo_28 & !VD1_un134_hilo_combout[29]_carry_eqn);
 
--VD1_un134_hilo_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[29] at LC_X4_Y15_N6
--operation mode is arithmetic
 
VD1_un134_hilo_cout[29]_cout_0 = VD1_hilo_29 & VD1_hilo_28 & !VD1_un134_hilo_cout[27];
VD1_un134_hilo_cout[29] = CARRY(VD1_un134_hilo_cout[29]_cout_0);
 
--VD1L1002 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[29]~COUT1_12 at LC_X4_Y15_N6
--operation mode is arithmetic
 
VD1L1002_cout_1 = VD1_hilo_29 & VD1_hilo_28 & !VD1L7991;
VD1L1002 = CARRY(VD1L1002_cout_1);
 
 
--VD1_un134_hilo_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[26] at LC_X5_Y15_N5
--operation mode is arithmetic
 
VD1_un134_hilo_combout[26]_carry_eqn = VD1_un134_hilo_cout[24];
VD1_un134_hilo_combout[26] = VD1_hilo_26 $ VD1_un134_hilo_combout[26]_carry_eqn;
 
--VD1_un134_hilo_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[26] at LC_X5_Y15_N5
--operation mode is arithmetic
 
VD1_un134_hilo_cout[26]_cout_0 = !VD1_un134_hilo_cout[24] # !VD1_hilo_26 # !VD1_hilo_27;
VD1_un134_hilo_cout[26] = CARRY(VD1_un134_hilo_cout[26]_cout_0);
 
--VD1L5991 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[26]~COUT1_23 at LC_X5_Y15_N5
--operation mode is arithmetic
 
VD1L5991_cout_1 = !VD1_un134_hilo_cout[24] # !VD1_hilo_26 # !VD1_hilo_27;
VD1L5991 = CARRY(VD1L5991_cout_1);
 
 
--RD1_r32_o_0_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_28 at LC_X21_Y3_N6
--operation mode is arithmetic
 
RD1_r32_o_0_28_carry_eqn = (!RD1_r32_o_cout[24] & RD1_r32_o_cout[26]) # (RD1_r32_o_cout[24] & RD1L701);
RD1_r32_o_0_28_lut_out = KB1_r32_o_28 $ (RD1_r32_o_0_28_carry_eqn);
RD1_r32_o_0_28 = DFFEAS(RD1_r32_o_0_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[28] at LC_X21_Y3_N6
--operation mode is arithmetic
 
RD1_r32_o_cout[28]_cout_0 = !RD1_r32_o_cout[26] # !KB1_r32_o_29 # !KB1_r32_o_28;
RD1_r32_o_cout[28] = CARRY(RD1_r32_o_cout[28]_cout_0);
 
--RD1L111 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[28]~COUT1_10 at LC_X21_Y3_N6
--operation mode is arithmetic
 
RD1L111_cout_1 = !RD1L701 # !KB1_r32_o_29 # !KB1_r32_o_28;
RD1L111 = CARRY(RD1L111_cout_1);
 
 
--PD1_a_o_3_d_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[30] at LC_X24_Y3_N5
--operation mode is normal
 
PD1_a_o_3_d_a[30] = PD1_a_o_sn_m2 & !PB1_r32_o_30 # !PD1_a_o_sn_m2 & !AB1_r32_o_28;
 
 
--VD1_un1_op2_reged_1_combout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[30] at LC_X13_Y2_N8
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[30] = VD1_eqop2_2_32 & VD1_op2_reged[30] # !VD1_eqop2_2_32 & VD1_nop2_reged[30];
 
 
--VD1_hilo_24_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add29 at LC_X8_Y2_N3
--operation mode is arithmetic
 
VD1_hilo_24_add29_carry_eqn = (!VD1_hilo_24_carry_25 & VD1_hilo_24_carry_28) # (VD1_hilo_24_carry_25 & VD1L825);
VD1_hilo_24_add29 = VD1_un1_op2_reged_1_combout[29] $ VD1_hilo_60 $ VD1_hilo_24_add29_carry_eqn;
 
--VD1_hilo_24_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_29 at LC_X8_Y2_N3
--operation mode is arithmetic
 
VD1_hilo_24_carry_29_cout_0 = VD1_un1_op2_reged_1_combout[29] & !VD1_hilo_60 & !VD1_hilo_24_carry_28 # !VD1_un1_op2_reged_1_combout[29] & !VD1_hilo_24_carry_28 # !VD1_hilo_60;
VD1_hilo_24_carry_29 = CARRY(VD1_hilo_24_carry_29_cout_0);
 
--VD1L035 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_29~COUT1_1 at LC_X8_Y2_N3
--operation mode is arithmetic
 
VD1L035_cout_1 = VD1_un1_op2_reged_1_combout[29] & !VD1_hilo_60 & !VD1L825 # !VD1_un1_op2_reged_1_combout[29] & !VD1L825 # !VD1_hilo_60;
VD1L035 = CARRY(VD1L035_cout_1);
 
 
--VD1_hilo_37_iv_0_a5_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[62] at LC_X7_Y3_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a5_0[62] = VD1_hilo_37_iv_0_a3_1[62] & !VD1_hilo_62;
 
 
--VD1_hilo_37_iv_0_0[62] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[62] at LC_X7_Y3_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[62] = VD1_hilo_0_sqmuxa & !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_30 # !VD1_hilo_0_sqmuxa & !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--VD1_un50_hilo_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add30 at LC_X10_Y2_N4
--operation mode is arithmetic
 
VD1_un50_hilo_add30_carry_eqn = (!VD1_un50_hilo_carry_25 & VD1_un50_hilo_carry_29) # (VD1_un50_hilo_carry_25 & VD1L6571);
VD1_un50_hilo_add30 = VD1_nop2_reged[30] $ VD1_hilo_62 $ !VD1_un50_hilo_add30_carry_eqn;
 
--VD1_un50_hilo_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_30 at LC_X10_Y2_N4
--operation mode is arithmetic
 
VD1_un50_hilo_carry_30 = CARRY(VD1_nop2_reged[30] & VD1_hilo_62 # !VD1L6571 # !VD1_nop2_reged[30] & VD1_hilo_62 & !VD1L6571);
 
 
--VD1_un50_hilo_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add31 at LC_X10_Y2_N5
--operation mode is arithmetic
 
VD1_un50_hilo_add31_carry_eqn = VD1_un50_hilo_carry_30;
VD1_un50_hilo_add31 = VD1_hilo_63 $ VD1_nop2_reged[31] $ VD1_un50_hilo_add31_carry_eqn;
 
--VD1_un50_hilo_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_31 at LC_X10_Y2_N5
--operation mode is arithmetic
 
VD1_un50_hilo_carry_31_cout_0 = VD1_hilo_63 & !VD1_nop2_reged[31] & !VD1_un50_hilo_carry_30 # !VD1_hilo_63 & !VD1_un50_hilo_carry_30 # !VD1_nop2_reged[31];
VD1_un50_hilo_carry_31 = CARRY(VD1_un50_hilo_carry_31_cout_0);
 
--VD1L9571 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_31~COUT1_1 at LC_X10_Y2_N5
--operation mode is arithmetic
 
VD1L9571_cout_1 = VD1_hilo_63 & !VD1_nop2_reged[31] & !VD1_un50_hilo_carry_30 # !VD1_hilo_63 & !VD1_un50_hilo_carry_30 # !VD1_nop2_reged[31];
VD1L9571 = CARRY(VD1L9571_cout_1);
 
 
--VD1_un59_hilo_add30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add30 at LC_X9_Y3_N4
--operation mode is arithmetic
 
VD1_un59_hilo_add30_carry_eqn = (!VD1_un59_hilo_carry_25 & VD1_un59_hilo_carry_29) # (VD1_un59_hilo_carry_25 & VD1L9781);
VD1_un59_hilo_add30 = VD1_op2_reged[30] $ VD1_hilo_62 $ !VD1_un59_hilo_add30_carry_eqn;
 
--VD1_un59_hilo_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_30 at LC_X9_Y3_N4
--operation mode is arithmetic
 
VD1_un59_hilo_carry_30 = CARRY(VD1_op2_reged[30] & VD1_hilo_62 # !VD1L9781 # !VD1_op2_reged[30] & VD1_hilo_62 & !VD1L9781);
 
 
--UD1_shift_out_77[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[30] at LC_X8_Y17_N7
--operation mode is normal
 
UD1_shift_out_77[30] = PD1_a_o_1 & UD1_shift_out_85_d[22] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[22] # !PD1_a_o_2 & UD1_shift_out_68[24];
 
 
--UD1_shift_out_84_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[30] at LC_X12_Y17_N6
--operation mode is normal
 
UD1_shift_out_84_a[30] = PD1_a_o_3 & !UD1_shift_out_63[22] # !PD1_a_o_3 & !UD1_shift_out_63[30];
 
 
--UD1_shift_out_89_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_89_a[30] at LC_X11_Y13_N5
--operation mode is normal
 
UD1_shift_out_89_a[30] = PD1_a_o_0 & UD1_shift_out_63_a[17] & !VD1_b_o_iv_31 # !UD1_shift_out_63_a[17] & !UD1_shift_out_36_0 # !PD1_a_o_0 & !UD1_shift_out_36_0;
 
 
--UD1_shift_out_85[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85[30] at LC_X8_Y17_N0
--operation mode is normal
 
UD1_shift_out_85[30] = UD1_shift_out_85_c[30] & UD1_shift_out_68[26] # !PD1_a_o_2 # !UD1_shift_out_85_c[30] & PD1_a_o_2 & UD1_shift_out_68[28];
 
 
--UD1_shift_out_87_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[12] at LC_X19_Y18_N5
--operation mode is normal
 
UD1_shift_out_87_d_a[12] = PD1_a_o_1 & !VD1_b_o_iv_18 # !PD1_a_o_1 & !VD1_b_o_iv_16;
 
 
--UD1_shift_out_80[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[12] at LC_X19_Y18_N7
--operation mode is normal
 
UD1_shift_out_80[12] = PD1_a_o_2 & UD1_shift_out_80_a[12] & VD1_b_o_iv_17 # !UD1_shift_out_80_a[12] & VD1_b_o_iv_19 # !PD1_a_o_2 & !UD1_shift_out_80_a[12];
 
 
--UD1_shift_out_77_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[18] at LC_X11_Y18_N8
--operation mode is normal
 
UD1_shift_out_77_a[18] = PD1_a_o_0 & !VD1_b_o_iv_9 # !PD1_a_o_0 & !VD1_b_o_iv_10;
 
 
--UD1_shift_out_79[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[12] at LC_X15_Y18_N3
--operation mode is normal
 
UD1_shift_out_79[12] = PD1_a_o_1 & UD1_shift_out_79_a[12] & VD1_b_o_iv_22 # !UD1_shift_out_79_a[12] & VD1_b_o_iv_23 # !PD1_a_o_1 & !UD1_shift_out_79_a[12];
 
 
--VD1_hilo_37_iv_0_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[12] at LC_X4_Y18_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[12] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_13 & !VD1_hilo_2_sqmuxa # !VD1_hilo_11 # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_11;
 
 
--VD1_hilo_37_iv_0_0[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[12] at LC_X4_Y18_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[12] = VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[12] # VD1_hilo_37_iv_0_o5[0] & VD1_hilo_12 # !VD1_hilo_37_iv_0_a3_0[0] & VD1_hilo_37_iv_0_o5[0] & VD1_hilo_12;
 
 
--VD1_hilo_37_iv_0_o3[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3[44] at LC_X9_Y7_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_o3[44] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add12 # !VD1_un50_hilo_add13 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add12;
 
 
--VD1_hilo_37_iv_0_o2_3_0[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o2_3_0[44] at LC_X9_Y7_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_o2_3_0[44] = VD1_addnop2109_0_a2 # VD1_hilo_37_iv_0_o3_0[44];
 
 
--VD1_hilo_37_iv_0_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[44] at LC_X9_Y7_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a[44] = !VD1_hilo_37_iv_0_o3_0[44] & !VD1_hilo_37_iv_0_2[44] & PD1_a_o_12 # !VD1_hilo_37_iv_0_a3_1[0];
 
 
--PD1_a_o_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[12] at LC_X19_Y4_N8
--operation mode is normal
 
PD1_a_o_a[12] = SC1_muxa_ctl_o_1 & !FB1_r32_o_0_12 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_12;
 
 
--PD1_a_o_3_Z[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[12] at LC_X23_Y12_N7
--operation mode is normal
 
SD1_r32_o_12_qfbk = SD1_r32_o_12;
PD1_a_o_3_Z[12] = PD1_a_o_3_s[0] & SD1_r32_o_12_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[12];
 
--SD1_r32_o_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_12 at LC_X23_Y12_N7
--operation mode is normal
 
SD1_r32_o_12 = DFFEAS(PD1_a_o_3_Z[12], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_12, , , VCC);
 
 
--YB1_dmem_ctl_2_0_0_a[3] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|dmem_ctl_2_0_0_a[3] at LC_X29_Y16_N5
--operation mode is normal
 
YB1_dmem_ctl_2_0_0_a[3] = !KE1_q_a[6] & !KE1_q_a[5] & !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0] & KE1_q_a[2];
 
 
--UD1_shift_out_87_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[24] at LC_X8_Y18_N2
--operation mode is normal
 
UD1_shift_out_87_d_a[24] = PD1_a_o_1 & !VD1_b_o_iv_30 # !PD1_a_o_1 & !VD1_b_o_iv_28;
 
 
--UD1_shift_out_80[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[24] at LC_X8_Y18_N4
--operation mode is normal
 
UD1_shift_out_80[24] = PD1_a_o_2 & UD1_shift_out_80_a[24] & VD1_b_o_iv_29 # !UD1_shift_out_80_a[24] & VD1_b_o_iv_31 # !PD1_a_o_2 & !UD1_shift_out_80_a[24];
 
 
--UD1_shift_out_84_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_84_a[24] at LC_X9_Y17_N8
--operation mode is normal
 
UD1_shift_out_84_a[24] = PD1_a_o_4 & UD1_shift_out_43[28] & !PD1_a_o_2 # !PD1_a_o_4 & !UD1_shift_out_77[24];
 
 
--VD1_hilo_37_iv_1[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1[24] at LC_X4_Y9_N0
--operation mode is normal
 
VD1_hilo_37_iv_1[24] = VD1_hilo_37_iv_0[24] # VD1_hilo_2_sqmuxa & VD1_hilo_23;
 
 
--VD1_hilo_37_iv_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[24] at LC_X4_Y9_N6
--operation mode is normal
 
VD1_hilo_37_iv_a[24] = RC1_alu_func_o_0 & !VD1_hilo_24 # !RC1_alu_func_o_0 & !PD1_a_o_24 # !VD1_hilo25;
 
 
--VD1_hilo_37_iv_2[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[56] at LC_X4_Y7_N9
--operation mode is normal
 
VD1_hilo_37_iv_2[56] = VD1_hilo_33_i_m[56] # VD1_hilo_37_iv_2_a[56] # VD1_hilo_1_sqmuxa_1 & !VD1_hilo_22_Z[56];
 
 
--VD1_hilo_37_iv_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[56] at LC_X4_Y9_N9
--operation mode is normal
 
VD1_hilo_37_iv_a[56] = RC1_alu_func_o_0 & !PD1_a_o_24 # !RC1_alu_func_o_0 & !VD1_hilo_56;
 
 
--PD1_a_o_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[24] at LC_X20_Y3_N9
--operation mode is normal
 
PD1_a_o_a[24] = SC1_muxa_ctl_o_1 & !FB1_r32_o_24 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_24;
 
 
--PD1_a_o_3_Z[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[24] at LC_X20_Y3_N3
--operation mode is normal
 
SD1_r32_o_24_qfbk = SD1_r32_o_24;
PD1_a_o_3_Z[24] = PD1_a_o_3_s[0] & SD1_r32_o_24_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[24];
 
--SD1_r32_o_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_24 at LC_X20_Y3_N3
--operation mode is normal
 
SD1_r32_o_24 = DFFEAS(PD1_a_o_3_Z[24], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_24, , , VCC);
 
 
--TD1_un1_b_1_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[24] at LC_X13_Y5_N1
--operation mode is normal
 
TD1_un1_b_1_combout[24] = VD1_b_o_iv_24 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[25] at LC_X13_Y10_N1
--operation mode is normal
 
UD1_shift_out_87_d_a[25] = PD1_a_o_1 & !VD1_b_o_iv_31 # !PD1_a_o_1 & !VD1_b_o_iv_29;
 
 
--UD1_shift_out_80[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[25] at LC_X13_Y10_N5
--operation mode is normal
 
UD1_shift_out_80[25] = PD1_a_o_2 & UD1_shift_out_80_a[25] & VD1_b_o_iv_30 # !UD1_shift_out_80_a[25] & UD1_shift_out_36_0 # !PD1_a_o_2 & !UD1_shift_out_80_a[25];
 
 
--UD1_shift_out_75[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75[25] at LC_X14_Y15_N4
--operation mode is normal
 
UD1_shift_out_75[25] = PD1_a_o_2 & PD1_a_o_3 & !UD1_shift_out_75_a[25] # !PD1_a_o_3 & UD1_shift_out_45[29] # !PD1_a_o_2 & !UD1_shift_out_75_a[25];
 
 
--UD1_shift_out_77[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[25] at LC_X14_Y15_N1
--operation mode is normal
 
UD1_shift_out_77[25] = PD1_a_o_2 & UD1_shift_out_85_d[17] # !PD1_a_o_2 & PD1_a_o_1 & UD1_shift_out_85_d[17] # !PD1_a_o_1 & !UD1_shift_out_77_a[25];
 
 
--VD1_hilo_37_iv_0_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[25] at LC_X4_Y13_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[25] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_26 & !VD1_hilo_24 # !VD1_hilo_2_sqmuxa # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_24 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[25] at LC_X4_Y13_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[25] = VD1_hilo_25 & VD1_hilo_37_iv_0_o5[0] # VD1_un134_hilo_combout[25] & VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo_25 & VD1_un134_hilo_combout[25] & VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_37_iv_0_8[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8[57] at LC_X4_Y6_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_8[57] = VD1_hilo_37_iv_0_5[57] # VD1_hilo_37_iv_0_8_a[57] # !PD1_a_o_25 & VD1_hilo_37_iv_0_a3_1[0];
 
 
--PD1_a_o_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[25] at LC_X24_Y6_N9
--operation mode is normal
 
PD1_a_o_a[25] = SC1_muxa_ctl_o_1 & !FB1_r32_o_25 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_25;
 
 
--PD1_a_o_3_Z[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[25] at LC_X24_Y6_N3
--operation mode is normal
 
SD1_r32_o_25_qfbk = SD1_r32_o_25;
PD1_a_o_3_Z[25] = PD1_a_o_3_s[0] & SD1_r32_o_25_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[25];
 
--SD1_r32_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_25 at LC_X24_Y6_N3
--operation mode is normal
 
SD1_r32_o_25 = DFFEAS(PD1_a_o_3_Z[25], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_25, , , VCC);
 
 
--TD1_un1_b_1_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[25] at LC_X12_Y7_N8
--operation mode is normal
 
TD1_un1_b_1_combout[25] = VD1_b_o_iv_25 $ !TD1_sum13_0_a2;
 
 
--UD1_shift_out_87_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[22] at LC_X6_Y17_N3
--operation mode is normal
 
UD1_shift_out_87_d_a[22] = PD1_a_o_1 & !VD1_b_o_iv_28 # !PD1_a_o_1 & !VD1_b_o_iv_26;
 
 
--UD1_shift_out_80[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[22] at LC_X6_Y17_N4
--operation mode is normal
 
UD1_shift_out_80[22] = PD1_a_o_2 & UD1_shift_out_80_a[22] & VD1_b_o_iv_27 # !UD1_shift_out_80_a[22] & VD1_b_o_iv_29 # !PD1_a_o_2 & !UD1_shift_out_80_a[22];
 
 
--UD1_shift_out_54[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[30] at LC_X20_Y17_N2
--operation mode is normal
 
UD1_shift_out_54[30] = PD1_a_o_1 & !UD1_shift_out_54_a[30] # !PD1_a_o_1 & UD1_shift_out_54_a[30] & VD1_b_o_iv_18 # !UD1_shift_out_54_a[30] & VD1_b_o_iv_17;
 
 
--UD1_shift_out_79[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[22] at LC_X12_Y12_N4
--operation mode is normal
 
UD1_shift_out_79[22] = PD1_a_o_1 & UD1_shift_out_36_0 # !PD1_a_o_1 & !UD1_shift_out_79_a[22];
 
 
--UD1_shift_out_63[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_63[30] at LC_X12_Y17_N8
--operation mode is normal
 
UD1_shift_out_63[30] = PD1_a_o_2 & UD1_shift_out_48[30] # !PD1_a_o_2 & UD1_shift_out_52[30];
 
 
--VD1_hilo_37_iv_0_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[22] at LC_X5_Y9_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[22] = VD1_hilo_23 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_21 # !VD1_hilo_2_sqmuxa # !VD1_hilo_23 & !VD1_hilo_21 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_0[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[22] at LC_X5_Y13_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[22] = VD1_hilo_37_iv_0_o5[0] & VD1_hilo_22 # VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[22] # !VD1_hilo_37_iv_0_o5[0] & VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[22];
 
 
--VD1_hilo_37_iv_0_a[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[54] at LC_X5_Y4_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[54] = !VD1_hilo_37_iv_0_o5_0_0[54] & VD1_hilo_33_1[64] # VD1_hilo_54 # !VD1_hilo_3_sqmuxa;
 
 
--VD1_hilo_37_iv_0_3[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[54] at LC_X4_Y3_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_3[54] = VD1_hilo_37_iv_0_0[54] # VD1_hilo_37_iv_0_3_a[54] # !VD1_hilo_24_add22 & VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_o5[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5[54] at LC_X5_Y4_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_o5[54] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_22 # !VD1_un50_hilo_add23 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a3_1[0] & !PD1_a_o_22;
 
 
--PD1_a_o_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[22] at LC_X24_Y5_N6
--operation mode is normal
 
PD1_a_o_a[22] = SC1_muxa_ctl_o_1 & !FB1_r32_o_22 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_0_22;
 
 
--PD1_a_o_3_Z[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[22] at LC_X24_Y5_N7
--operation mode is normal
 
SD1_r32_o_22_qfbk = SD1_r32_o_22;
PD1_a_o_3_Z[22] = PD1_a_o_3_s[0] & SD1_r32_o_22_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[22];
 
--SD1_r32_o_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_22 at LC_X24_Y5_N7
--operation mode is normal
 
SD1_r32_o_22 = DFFEAS(PD1_a_o_3_Z[22], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_22, , , VCC);
 
 
--TD1_un1_b_1_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[22] at LC_X13_Y7_N5
--operation mode is normal
 
TD1_un1_b_1_combout[22] = TD1_sum13_0_a2 $ (!VD1_b_o_iv_22);
 
 
--UD1_shift_out_87_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[23] at LC_X14_Y6_N2
--operation mode is normal
 
UD1_shift_out_87_d_a[23] = PD1_a_o_1 & !VD1_b_o_iv_29 # !PD1_a_o_1 & !VD1_b_o_iv_27;
 
 
--UD1_shift_out_80[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[23] at LC_X14_Y7_N2
--operation mode is normal
 
UD1_shift_out_80[23] = PD1_a_o_2 & UD1_shift_out_80_a[23] & VD1_b_o_iv_28 # !UD1_shift_out_80_a[23] & VD1_b_o_iv_30 # !PD1_a_o_2 & !UD1_shift_out_80_a[23];
 
 
--UD1_shift_out_54[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54[31] at LC_X20_Y17_N6
--operation mode is normal
 
UD1_shift_out_54[31] = PD1_a_o_1 & !UD1_shift_out_54_a[31] # !PD1_a_o_1 & UD1_shift_out_54_a[31] & VD1_b_o_iv_19 # !UD1_shift_out_54_a[31] & VD1_b_o_iv_18;
 
 
--UD1_shift_out_88_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_88_a[23] at LC_X12_Y12_N3
--operation mode is normal
 
UD1_shift_out_88_a[23] = PD1_a_o_0 & !UD1_shift_out_36_0 # !PD1_a_o_0 & PD1_a_o_1 & !UD1_shift_out_36_0 # !PD1_a_o_1 & !VD1_b_o_iv_31;
 
 
--UD1_shift_out_77[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[23] at LC_X11_Y12_N7
--operation mode is normal
 
UD1_shift_out_77[23] = PD1_a_o_1 & UD1_shift_out_85_d[15] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[15] # !PD1_a_o_2 & !UD1_shift_out_77_a[23];
 
 
--VD1_hilo_37_iv_0[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[23] at LC_X4_Y9_N2
--operation mode is normal
 
VD1_hilo_37_iv_0[23] = VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_24 # !VD1_hilo_37_iv_0_a[23] # !VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_24;
 
 
--VD1_hilo_8_Z[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_8_Z[23] at LC_X5_Y9_N7
--operation mode is normal
 
VD1_hilo_8_Z[23] = RC1_alu_func_o_0 & VD1_hilo_23 # !RC1_alu_func_o_0 & PD1_a_o_23;
 
 
--VD1_hilo_37_iv_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[23] at LC_X5_Y9_N2
--operation mode is normal
 
VD1_hilo_37_iv_a[23] = VD1_hilo_2_sqmuxa & !VD1_hilo_22 & !PD1_a_o_23 # !VD1_addnop2109_0_a2 # !VD1_hilo_2_sqmuxa & !PD1_a_o_23 # !VD1_addnop2109_0_a2;
 
 
--VD1_hilo_37_iv_2[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2[55] at LC_X5_Y9_N4
--operation mode is normal
 
VD1_hilo_37_iv_2[55] = VD1_hilo_37_iv_2_a[55] # VD1_hilo_33_i_m[55] # !VD1_hilo_22_Z[55] & VD1_hilo_1_sqmuxa_1;
 
 
--VD1_hilo_37_iv_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_a[55] at LC_X9_Y9_N1
--operation mode is normal
 
VD1_hilo_37_iv_a[55] = RC1_alu_func_o_0 & !PD1_a_o_23 # !RC1_alu_func_o_0 & !VD1_hilo_55;
 
 
--PD1_a_o_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_a[23] at LC_X22_Y3_N4
--operation mode is normal
 
PD1_a_o_a[23] = SC1_muxa_ctl_o_1 & !FB1_r32_o_23 # !SC1_muxa_ctl_o_1 & !RD1_r32_o_23;
 
 
--PD1_a_o_3_Z[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_Z[23] at LC_X22_Y3_N7
--operation mode is normal
 
SD1_r32_o_23_qfbk = SD1_r32_o_23;
PD1_a_o_3_Z[23] = PD1_a_o_3_s[0] & SD1_r32_o_23_qfbk # !PD1_a_o_3_s[0] & PD1_a_o_3_d[23];
 
--SD1_r32_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc|r32_o_23 at LC_X22_Y3_N7
--operation mode is normal
 
SD1_r32_o_23 = DFFEAS(PD1_a_o_3_Z[23], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KB1_r32_o_23, , , VCC);
 
 
--TD1_un1_b_1_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_b_1_combout[23] at LC_X11_Y8_N7
--operation mode is normal
 
TD1_un1_b_1_combout[23] = TD1_sum13_0_a2 $ !VD1_b_o_iv_23;
 
 
--F1_dout_22 is mips_sys:isys|mips_dvc:imips_dvc|dout_22 at LC_X25_Y13_N2
--operation mode is normal
 
F1_dout_22_lut_out = F1_cmd[22] & F1_dout_0_0_a3_3[0] # F1_dout_0_0_a3_4[0] & K1_cntr_22 # !F1_cmd[22] & F1_dout_0_0_a3_4[0] & K1_cntr_22;
F1_dout_22 = DFFEAS(F1_dout_22_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_22 at LC_X25_Y13_N0
--operation mode is normal
 
BB1_r32_o_22_lut_out = AB1_r32_o_20;
BB1_r32_o_22 = DFFEAS(BB1_r32_o_22_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_14 at LC_X28_Y4_N2
--operation mode is normal
 
ND1_dout_2_a_14 = XD1_mux_fw_1 & !AB1_r32_o_12 # !XD1_mux_fw_1 & !QB1_r32_o_14;
 
 
--GD1_dout_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[8] at LC_X23_Y6_N6
--operation mode is normal
 
GD1_dout_iv_1_a[8] = FD1_r_data_8 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_6 # !FD1_r_data_8 & !ZD1_mux_fw_1 # !AB1_r32_o_6;
 
 
--F1_dout_21 is mips_sys:isys|mips_dvc:imips_dvc|dout_21 at LC_X30_Y5_N2
--operation mode is normal
 
F1_dout_21_lut_out = F1_dout_0_0_a3_3[0] & F1_cmd[21] # K1_cntr_21 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a3_3[0] & K1_cntr_21 & F1_dout_0_0_a3_4[0];
F1_dout_21 = DFFEAS(F1_dout_21_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_21 at LC_X30_Y5_N6
--operation mode is normal
 
BB1_r32_o_21_lut_out = AB1_r32_o_19;
BB1_r32_o_21 = DFFEAS(BB1_r32_o_21_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_13 at LC_X21_Y9_N2
--operation mode is normal
 
ND1_dout_2_a_13 = XD1_mux_fw_1 & !AB1_r32_o_11 # !XD1_mux_fw_1 & !QB1_r32_o_13;
 
 
--ND1_dout_2_a_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_12 at LC_X27_Y13_N2
--operation mode is normal
 
ND1_dout_2_a_12 = XD1_mux_fw_1 & !AB1_r32_o_10 # !XD1_mux_fw_1 & !QB1_r32_o_12;
 
 
--M1_bit_ctr23_i_i is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr23_i_i at LC_X33_Y15_N7
--operation mode is normal
 
M1_bit_ctr23_i_i = sys_rst & M1_ua_state[2];
 
 
--F1_dout_19 is mips_sys:isys|mips_dvc:imips_dvc|dout_19 at LC_X30_Y15_N0
--operation mode is normal
 
F1_dout_19_lut_out = K1_cntr_19 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[19] # !K1_cntr_19 & F1_dout_0_0_a3_3[0] & F1_cmd[19];
F1_dout_19 = DFFEAS(F1_dout_19_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_19 at LC_X30_Y15_N2
--operation mode is normal
 
BB1_r32_o_19_lut_out = AB1_r32_o_17;
BB1_r32_o_19 = DFFEAS(BB1_r32_o_19_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_11 at LC_X21_Y15_N4
--operation mode is normal
 
ND1_dout_2_a_11 = XD1_mux_fw_1 & !AB1_r32_o_9 # !XD1_mux_fw_1 & !QB1_r32_o_11;
 
 
--F1_dout_18 is mips_sys:isys|mips_dvc:imips_dvc|dout_18 at LC_X30_Y9_N0
--operation mode is normal
 
F1_dout_18_lut_out = K1_cntr_18 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[18] # !K1_cntr_18 & F1_dout_0_0_a3_3[0] & F1_cmd[18];
F1_dout_18 = DFFEAS(F1_dout_18_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_18 at LC_X30_Y9_N1
--operation mode is normal
 
BB1_r32_o_18_lut_out = AB1_r32_o_16;
BB1_r32_o_18 = DFFEAS(BB1_r32_o_18_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_10 at LC_X29_Y15_N8
--operation mode is normal
 
ND1_dout_2_a_10 = XD1_mux_fw_1 & !AB1_r32_o_8 # !XD1_mux_fw_1 & !QB1_r32_o_10;
 
 
--F1_dout_17 is mips_sys:isys|mips_dvc:imips_dvc|dout_17 at LC_X26_Y6_N7
--operation mode is normal
 
F1_dout_17_lut_out = K1_cntr_17 & F1_dout_0_0_a3_4[0] # F1_cmd[17] & F1_dout_0_0_a3_3[0] # !K1_cntr_17 & F1_cmd[17] & F1_dout_0_0_a3_3[0];
F1_dout_17 = DFFEAS(F1_dout_17_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_17 at LC_X26_Y6_N0
--operation mode is normal
 
BB1_r32_o_17_lut_out = AB1_r32_o_15;
BB1_r32_o_17 = DFFEAS(BB1_r32_o_17_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_9 at LC_X25_Y3_N1
--operation mode is normal
 
ND1_dout_2_a_9 = XD1_mux_fw_1 & !AB1_r32_o_7 # !XD1_mux_fw_1 & !QB1_r32_o_9;
 
 
--VD1_un59_hilo_add1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add1 at LC_X9_Y6_N5
--operation mode is arithmetic
 
VD1_un59_hilo_add1_carry_eqn = VD1_un59_hilo_carry_0;
VD1_un59_hilo_add1 = VD1_hilo_33 $ VD1_op2_reged[1] $ VD1_un59_hilo_add1_carry_eqn;
 
--VD1_un59_hilo_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_1 at LC_X9_Y6_N5
--operation mode is arithmetic
 
VD1_un59_hilo_carry_1_cout_0 = VD1_hilo_33 & !VD1_op2_reged[1] & !VD1_un59_hilo_carry_0 # !VD1_hilo_33 & !VD1_un59_hilo_carry_0 # !VD1_op2_reged[1];
VD1_un59_hilo_carry_1 = CARRY(VD1_un59_hilo_carry_1_cout_0);
 
--VD1L8281 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_1~COUT1_1 at LC_X9_Y6_N5
--operation mode is arithmetic
 
VD1L8281_cout_1 = VD1_hilo_33 & !VD1_op2_reged[1] & !VD1_un59_hilo_carry_0 # !VD1_hilo_33 & !VD1_un59_hilo_carry_0 # !VD1_op2_reged[1];
VD1L8281 = CARRY(VD1L8281_cout_1);
 
 
--F1_dout_16 is mips_sys:isys|mips_dvc:imips_dvc|dout_16 at LC_X30_Y3_N4
--operation mode is normal
 
F1_dout_16_lut_out = K1_cntr_16 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[16] # !K1_cntr_16 & F1_dout_0_0_a3_3[0] & F1_cmd[16];
F1_dout_16 = DFFEAS(F1_dout_16_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_16 at LC_X25_Y4_N6
--operation mode is normal
 
BB1_r32_o_16_lut_out = GND;
BB1_r32_o_16 = DFFEAS(BB1_r32_o_16_lut_out, GLOBAL(E1__clk0), VCC, , , AB1_r32_o_14, , , VCC);
 
 
--VD1_hilo_33_i_m_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[32] at LC_X4_Y5_N4
--operation mode is normal
 
VD1_hilo_33_i_m_a[32] = VD1_addnop2 & !VD1_un50_hilo_add0 # !VD1_addnop2 & !VD1_un59_hilo_add0;
 
 
--VD1_hilo_22_Z[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[32] at LC_X8_Y7_N4
--operation mode is normal
 
VD1_hilo_22_Z[32] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[32] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[32] # !VD1_sign & !VD1_hilo_22_a[32];
 
 
--VD1_hilo_37_iv_0_1_a[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[0] at LC_X6_Y13_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[0] = !VD1_hilo_1 # !VD1_hilo_1_sqmuxa_1;
 
 
--VD1_un1_op2_reged_1_combout[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[32] at LC_X10_Y2_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[32] = VD1_eqop2_2_32 & VD1_op2_sign_reged # !VD1_eqop2_2_32 & VD1_nop2_reged[32];
 
 
--VD1_hilo_24_add31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add31 at LC_X8_Y2_N5
--operation mode is arithmetic
 
VD1_hilo_24_add31_carry_eqn = VD1_hilo_24_carry_30;
VD1_hilo_24_add31 = VD1_un1_op2_reged_1_combout[31] $ VD1_hilo_62 $ VD1_hilo_24_add31_carry_eqn;
 
--VD1_hilo_24_carry_31 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_31 at LC_X8_Y2_N5
--operation mode is arithmetic
 
VD1_hilo_24_carry_31_cout_0 = VD1_un1_op2_reged_1_combout[31] & !VD1_hilo_62 & !VD1_hilo_24_carry_30 # !VD1_un1_op2_reged_1_combout[31] & !VD1_hilo_24_carry_30 # !VD1_hilo_62;
VD1_hilo_24_carry_31 = CARRY(VD1_hilo_24_carry_31_cout_0);
 
--VD1L335 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_31~COUT1_1 at LC_X8_Y2_N5
--operation mode is arithmetic
 
VD1L335_cout_1 = VD1_un1_op2_reged_1_combout[31] & !VD1_hilo_62 & !VD1_hilo_24_carry_30 # !VD1_un1_op2_reged_1_combout[31] & !VD1_hilo_24_carry_30 # !VD1_hilo_62;
VD1L335 = CARRY(VD1L335_cout_1);
 
 
--DD1_pc_next_0_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_30 at LC_X24_Y3_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_30 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_30 # !DD1_pc_next_0_iv_1_a[30];
 
 
--DD1_un1_pc_add30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add30 at LC_X23_Y8_N4
--operation mode is arithmetic
 
DD1_un1_pc_add30_carry_eqn = (!DD1_un1_pc_carry_25 & DD1_un1_pc_carry_29) # (DD1_un1_pc_carry_25 & DD1L352);
DD1_un1_pc_add30 = KB1_r32_o_30 $ DD1_un1_pc_prectl_1_0_a4[30] $ !DD1_un1_pc_add30_carry_eqn;
 
--DD1_un1_pc_carry_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_30 at LC_X23_Y8_N4
--operation mode is arithmetic
 
DD1_un1_pc_carry_30 = CARRY(KB1_r32_o_30 & DD1_un1_pc_prectl_1_0_a4[30] # !DD1L352 # !KB1_r32_o_30 & DD1_un1_pc_prectl_1_0_a4[30] & !DD1L352);
 
 
--DD1_pc_next_0_iv_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_a_0 at LC_X19_Y3_N0
--operation mode is normal
 
DD1_pc_next_0_iv_a_0 = KB1_r32_o_31 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_31 # !KB1_r32_o_31 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_31;
 
 
--G1_BUS24839_m[31] is mips_sys:isys|mips_core:mips_core|BUS24839_m[31] at LC_X24_Y11_N9
--operation mode is normal
 
G1_BUS24839_m[31] = PB1_dout_iv_31 & DD1_pc_next_2_sqmuxa_0_a4;
 
 
--DD1_un1_pc_add31 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add31 at LC_X23_Y8_N5
--operation mode is normal
 
DD1_un1_pc_add31_carry_eqn = DD1_un1_pc_carry_30;
DD1_un1_pc_add31 = KB1_r32_o_31 $ DD1_un1_pc_add31_carry_eqn $ DD1_un1_pc_prectl_1_0_a4[31];
 
 
--KB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_28 at LC_X21_Y10_N9
--operation mode is normal
 
KB1_r32_o_28_lut_out = DD1_pc_next_0_iv_1_28 # DD1_un1_pc_next46_0 & DD1_un1_pc_add28;
KB1_r32_o_28 = DFFEAS(KB1_r32_o_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_29 at LC_X23_Y8_N9
--operation mode is normal
 
KB1_r32_o_29_lut_out = DD1_pc_next_0_iv_1_29 # DD1_un1_pc_next46_0 & DD1_un1_pc_add29;
KB1_r32_o_29 = DFFEAS(KB1_r32_o_29_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RD1_r32_o_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_27 at LC_X23_Y3_N5
--operation mode is arithmetic
 
RD1_r32_o_27_carry_eqn = RD1_r32_o_cout[25];
RD1_r32_o_27_lut_out = KB1_r32_o_27 $ (KB1_r32_o_26 & !RD1_r32_o_27_carry_eqn);
RD1_r32_o_27 = DFFEAS(RD1_r32_o_27_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[27] at LC_X23_Y3_N5
--operation mode is arithmetic
 
RD1_r32_o_cout[27]_cout_0 = KB1_r32_o_26 & KB1_r32_o_27 & !RD1_r32_o_cout[25];
RD1_r32_o_cout[27] = CARRY(RD1_r32_o_cout[27]_cout_0);
 
--RD1L901 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[27]~COUT1_20 at LC_X23_Y3_N5
--operation mode is arithmetic
 
RD1L901_cout_1 = KB1_r32_o_26 & KB1_r32_o_27 & !RD1_r32_o_cout[25];
RD1L901 = CARRY(RD1L901_cout_1);
 
 
--PB1_dout_iv_31 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_31 at LC_X24_Y4_N2
--operation mode is normal
 
PB1_dout_iv_31 = FD1_reg_bank_m_0 # FD1_wb_o_31 & HD1_dout7_0_a2 # !HD1_dout_iv_a_0;
 
--PB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_31 at LC_X24_Y4_N2
--operation mode is normal
 
PB1_r32_o_31 = DFFEAS(PB1_dout_iv_31, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[31] at LC_X24_Y4_N7
--operation mode is normal
 
GD1_dout_iv_1_a[31] = AB1_r32_o_29 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_31 # !AB1_r32_o_29 & !FD1_N_16_i_0_s2 # !FD1_r_data_31;
 
 
--F1_cmd[31] is mips_sys:isys|mips_dvc:imips_dvc|cmd[31] at LC_X27_Y4_N3
--operation mode is normal
 
F1_cmd[31]_lut_out = CB1_r32_o_31;
F1_cmd[31] = DFFEAS(F1_cmd[31]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_30 at LC_X22_Y8_N1
--operation mode is normal
 
GD1_dout_iv_1_30 = FD1_N_20_i_0_s3 & LD1_q_b[30] # !GD1_dout_iv_1_a[30];
 
 
--F1_dout_30 is mips_sys:isys|mips_dvc:imips_dvc|dout_30 at LC_X32_Y13_N9
--operation mode is normal
 
F1_dout_30_lut_out = F1_dout_0_0_a3_4[0] & K1_cntr_30 # F1_dout_0_0_a3_3[0] & F1_cmd[30] # !F1_dout_0_0_a3_4[0] & F1_dout_0_0_a3_3[0] & F1_cmd[30];
F1_dout_30 = DFFEAS(F1_dout_30_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_30 at LC_X32_Y13_N3
--operation mode is normal
 
BB1_r32_o_30_lut_out = AB1_r32_o_28;
BB1_r32_o_30 = DFFEAS(BB1_r32_o_30_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[29] at LC_X21_Y9_N3
--operation mode is normal
 
PD1_a_o_3_d[29] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_29 # !PD1_un6_a_o & !PD1_a_o_3_d_a[29] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[29];
 
 
--TD1_lt_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_26 at LC_X16_Y7_N0
--operation mode is arithmetic
 
TD1_lt_26_cout_0 = VD1_b_o_iv_26 & !TD1_lt_25 # !PD1_a_o_26 # !VD1_b_o_iv_26 & !PD1_a_o_26 & !TD1_lt_25;
TD1_lt_26 = CARRY(TD1_lt_26_cout_0);
 
--TD1L091 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_26~COUT1_1 at LC_X16_Y7_N0
--operation mode is arithmetic
 
TD1L091_cout_1 = VD1_b_o_iv_26 & !TD1_lt_25 # !PD1_a_o_26 # !VD1_b_o_iv_26 & !PD1_a_o_26 & !TD1_lt_25;
TD1L091 = CARRY(TD1L091_cout_1);
 
 
--TD1_sum_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_27 at LC_X15_Y6_N1
--operation mode is arithmetic
 
TD1_sum_carry_27_cout_0 = VD1_b_o_iv_27 & !TD1_sum_carry_26 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !TD1_sum_carry_26;
TD1_sum_carry_27 = CARRY(TD1_sum_carry_27_cout_0);
 
--TD1L734 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_27~COUT1_1 at LC_X15_Y6_N1
--operation mode is arithmetic
 
TD1L734_cout_1 = VD1_b_o_iv_27 & !TD1L534 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !TD1L534;
TD1L734 = CARRY(TD1L734_cout_1);
 
 
--F1_dout_28 is mips_sys:isys|mips_dvc:imips_dvc|dout_28 at LC_X28_Y3_N9
--operation mode is normal
 
F1_dout_28_lut_out = K1_cntr_28 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[28] # !K1_cntr_28 & F1_dout_0_0_a3_3[0] & F1_cmd[28];
F1_dout_28 = DFFEAS(F1_dout_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_28 at LC_X26_Y8_N0
--operation mode is normal
 
BB1_r32_o_28_lut_out = AB1_r32_o_26;
BB1_r32_o_28 = DFFEAS(BB1_r32_o_28_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_27 at LC_X21_Y15_N7
--operation mode is normal
 
ND1_dout_2_a_27 = XD1_mux_fw_1 & !AB1_r32_o_25 # !XD1_mux_fw_1 & !QB1_r32_o_27;
 
 
--F1_dout_29 is mips_sys:isys|mips_dvc:imips_dvc|dout_29 at LC_X26_Y5_N0
--operation mode is normal
 
F1_dout_29_lut_out = K1_cntr_29 & F1_dout_0_0_a3_4[0] # F1_cmd[29] & F1_dout_0_0_a3_3[0] # !K1_cntr_29 & F1_cmd[29] & F1_dout_0_0_a3_3[0];
F1_dout_29 = DFFEAS(F1_dout_29_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_29 at LC_X26_Y5_N1
--operation mode is normal
 
BB1_r32_o_29_lut_out = AB1_r32_o_27;
BB1_r32_o_29 = DFFEAS(BB1_r32_o_29_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--ND1_dout_2_a_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_26 at LC_X29_Y6_N2
--operation mode is normal
 
ND1_dout_2_a_26 = XD1_mux_fw_1 & !AB1_r32_o_24 # !XD1_mux_fw_1 & !QB1_r32_o_26;
 
 
--ND1_dout_2_a_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_24 at LC_X29_Y5_N1
--operation mode is normal
 
ND1_dout_2_a_24 = XD1_mux_fw_1 & !AB1_r32_o_22 # !XD1_mux_fw_1 & !QB1_r32_o_24;
 
 
--ND1_dout_2_a_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_25 at LC_X25_Y3_N6
--operation mode is normal
 
ND1_dout_2_a_25 = XD1_mux_fw_1 & !AB1_r32_o_23 # !XD1_mux_fw_1 & !QB1_r32_o_25;
 
 
--ND1_dout_2_a_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_15 at LC_X27_Y3_N5
--operation mode is normal
 
ND1_dout_2_a_15 = XD1_mux_fw_1 & !AB1_r32_o_13 # !XD1_mux_fw_1 & !QB1_r32_o_15;
 
 
--UB1_dout_2_i_i[8] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[8] at LC_X31_Y13_N2
--operation mode is normal
 
UB1_dout_2_i_i[8] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[0] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[8];
 
 
--UB1_un1_ctl_5 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_5 at LC_X31_Y9_N4
--operation mode is normal
 
UB1_un1_ctl_5 = RB1_ctl_o_0 # RB1_ctl_o_3 & RB1_ctl_o_2 # !RB1_ctl_o_3 & !RB1_ctl_o_1;
 
 
--WB31L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_8__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y13_N3
--operation mode is normal
 
WB31L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[8] # !UB1_un1_byte_addr_2 & WB31L1;
 
--DB1_r32_o_8 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_8 at LC_X31_Y13_N3
--operation mode is normal
 
DB1_r32_o_8 = DFFEAS(WB31L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--M1_clk_ctr27_i_0_a5_4 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_4 at LC_X32_Y16_N0
--operation mode is normal
 
M1_clk_ctr27_i_0_a5_4 = !M1_clk_ctr[4] & M1_clk_ctr[9] & M1_clk_ctr[5] & M1_clk_ctr[1];
 
 
--M1_clk_ctr27_i_0_a5_5 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_5 at LC_X33_Y16_N4
--operation mode is normal
 
M1_clk_ctr27_i_0_a5_5 = !M1_clk_ctr[8] & M1_clk_ctr27_i_0_a5_5_a & M1_clk_ctr_3 & !M1_clk_ctr_2;
 
 
--HD1_dout_iv_1_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[2] at LC_X20_Y10_N2
--operation mode is normal
 
HD1_dout_iv_1_a[2] = YD1_mux_fw_1 & !AB1_r32_o_0 & !FD1_N_14_i_0_s2 # !FD1_r_data_2 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_2;
 
 
--BD1_res_3_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_3_0 at LC_X24_Y11_N4
--operation mode is normal
 
BD1_res_3_0 = BC1_cmp_ctl_o_2 & BC1_cmp_ctl_o_1 $ !PB1_dout_iv_31 # !BC1_cmp_ctl_o_2 & BC1_cmp_ctl_o_1 & BD1_res_2_NE;
 
 
--BD1_res_7_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_7_0_a at LC_X24_Y11_N6
--operation mode is normal
 
BD1_res_7_0_a = BC1_cmp_ctl_o_1 & !BC1_cmp_ctl_o_2 & !BD1_res_5 # !BC1_cmp_ctl_o_1 & BC1_cmp_ctl_o_2 & BD1_res_5 # !BC1_cmp_ctl_o_2 & !BD1_res_2_NE;
 
 
--HD1_dout_iv_1_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[3] at LC_X26_Y7_N2
--operation mode is normal
 
HD1_dout_iv_1_a[3] = YD1_mux_fw_1 & !AB1_r32_o_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_3 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_3;
 
 
--DD1_un1_pc_prectl_1_0_a3_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a3_a[0] at LC_X27_Y11_N1
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a3_a[0] = HC1_pc_gen_ctl_o_2 & !AD1_CurrState_Sreg0_5 & AD1_CurrState_Sreg0_3 # AD1_CurrState_Sreg0_ns_0_a3_0_o2_0;
 
 
--HD1_dout_iv_1_a[6] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[6] at LC_X25_Y8_N3
--operation mode is normal
 
HD1_dout_iv_1_a[6] = FD1_r_data_6 & !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_4 # !FD1_r_data_6 & !YD1_mux_fw_1 # !AB1_r32_o_4;
 
 
--HD1_dout_iv_1_a[7] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[7] at LC_X25_Y8_N7
--operation mode is normal
 
HD1_dout_iv_1_a[7] = FD1_r_data_7 & !FD1_N_14_i_0_s2 & !AB1_r32_o_5 # !YD1_mux_fw_1 # !FD1_r_data_7 & !AB1_r32_o_5 # !YD1_mux_fw_1;
 
 
--HD1_dout_iv_1_a[8] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[8] at LC_X19_Y8_N5
--operation mode is normal
 
HD1_dout_iv_1_a[8] = AB1_r32_o_6 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_8 # !AB1_r32_o_6 & !FD1_N_14_i_0_s2 # !FD1_r_data_8;
 
 
--HD1_dout_iv_1_a[9] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[9] at LC_X19_Y10_N7
--operation mode is normal
 
HD1_dout_iv_1_a[9] = AB1_r32_o_7 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_9 # !AB1_r32_o_7 & !FD1_N_14_i_0_s2 # !FD1_r_data_9;
 
 
--F1_dout_10 is mips_sys:isys|mips_dvc:imips_dvc|dout_10 at LC_X28_Y14_N7
--operation mode is normal
 
F1_dout_10_lut_out = F1_dout_0_0_a3_4[0] & K1_cntr_10 # F1_dout_0_0_a3_3[0] & F1_cmd[10] # !F1_dout_0_0_a3_4[0] & F1_dout_0_0_a3_3[0] & F1_cmd[10];
F1_dout_10 = DFFEAS(F1_dout_10_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_10 at LC_X28_Y14_N5
--operation mode is normal
 
BB1_r32_o_10_lut_out = AB1_r32_o_8;
BB1_r32_o_10 = DFFEAS(BB1_r32_o_10_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[10] at LC_X19_Y12_N2
--operation mode is normal
 
HD1_dout_iv_1_a[10] = FD1_r_data_10 & !FD1_N_14_i_0_s2 & !AB1_r32_o_8 # !YD1_mux_fw_1 # !FD1_r_data_10 & !AB1_r32_o_8 # !YD1_mux_fw_1;
 
 
--F1_dout_11 is mips_sys:isys|mips_dvc:imips_dvc|dout_11 at LC_X28_Y14_N6
--operation mode is normal
 
F1_dout_11_lut_out = F1_dout_0_0_a3_4[0] & K1_cntr_11 # F1_dout_0_0_a3_3[0] & F1_cmd[11] # !F1_dout_0_0_a3_4[0] & F1_dout_0_0_a3_3[0] & F1_cmd[11];
F1_dout_11 = DFFEAS(F1_dout_11_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_11 at LC_X28_Y14_N9
--operation mode is normal
 
BB1_r32_o_11_lut_out = AB1_r32_o_9;
BB1_r32_o_11 = DFFEAS(BB1_r32_o_11_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[11] at LC_X28_Y9_N0
--operation mode is normal
 
HD1_dout_iv_1_a[11] = YD1_mux_fw_1 & !AB1_r32_o_9 & !FD1_N_14_i_0_s2 # !FD1_r_data_11 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_11;
 
 
--F1_dout_12 is mips_sys:isys|mips_dvc:imips_dvc|dout_12 at LC_X27_Y8_N9
--operation mode is normal
 
F1_dout_12_lut_out = K1_cntr_12 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[12] # !K1_cntr_12 & F1_dout_0_0_a3_3[0] & F1_cmd[12];
F1_dout_12 = DFFEAS(F1_dout_12_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_12 at LC_X27_Y8_N0
--operation mode is normal
 
BB1_r32_o_12_lut_out = AB1_r32_o_10;
BB1_r32_o_12 = DFFEAS(BB1_r32_o_12_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[12] at LC_X27_Y8_N5
--operation mode is normal
 
HD1_dout_iv_1_a[12] = YD1_mux_fw_1 & !AB1_r32_o_10 & !FD1_r_data_12 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_12 # !FD1_N_14_i_0_s2;
 
 
--F1_dout_23 is mips_sys:isys|mips_dvc:imips_dvc|dout_23 at LC_X29_Y4_N9
--operation mode is normal
 
F1_dout_23_lut_out = K1_cntr_23 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[23] # !K1_cntr_23 & F1_dout_0_0_a3_3[0] & F1_cmd[23];
F1_dout_23 = DFFEAS(F1_dout_23_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_23 at LC_X29_Y4_N3
--operation mode is normal
 
BB1_r32_o_23_lut_out = AB1_r32_o_21;
BB1_r32_o_23 = DFFEAS(BB1_r32_o_23_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_0_0[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[9] at LC_X28_Y13_N6
--operation mode is normal
 
UB1_dout_2_0_0[9] = UB1_dout_2_0_0_a2_1[9] # UB1_dout_2_0_0_o2_0[9] & KE1_q_b[1] # !UB1_dout_2_0_0_a_x[9];
 
 
--WB41L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_9__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y13_N2
--operation mode is normal
 
WB41L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[9] # !UB1_un1_byte_addr_2 & WB41L1;
 
--DB1_r32_o_9 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_9 at LC_X28_Y13_N2
--operation mode is normal
 
DB1_r32_o_9 = DFFEAS(WB41L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_11 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_11 at LC_X22_Y7_N6
--operation mode is normal
 
GD1_dout_iv_1_11 = FD1_N_20_i_0_s3 & LD1_q_b[11] # !GD1_dout_iv_1_a[11];
 
 
--GD1_dout_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_13 at LC_X27_Y6_N8
--operation mode is normal
 
GD1_dout_iv_1_13 = FD1_N_20_i_0_s3 & LD1_q_b[13] # !GD1_dout_iv_1_a[13];
 
 
--F1_dout_13 is mips_sys:isys|mips_dvc:imips_dvc|dout_13 at LC_X27_Y6_N0
--operation mode is normal
 
F1_dout_13_lut_out = K1_cntr_13 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[13] # !K1_cntr_13 & F1_dout_0_0_a3_3[0] & F1_cmd[13];
F1_dout_13 = DFFEAS(F1_dout_13_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_13 at LC_X27_Y6_N7
--operation mode is normal
 
BB1_r32_o_13_lut_out = AB1_r32_o_11;
BB1_r32_o_13 = DFFEAS(BB1_r32_o_13_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_12 at LC_X27_Y8_N8
--operation mode is normal
 
GD1_dout_iv_1_12 = FD1_N_20_i_0_s3 & LD1_q_b[12] # !GD1_dout_iv_1_a[12];
 
 
--GD1_dout_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_14 at LC_X22_Y8_N5
--operation mode is normal
 
GD1_dout_iv_1_14 = FD1_N_20_i_0_s3 & LD1_q_b[14] # !GD1_dout_iv_1_a[14];
 
 
--F1_dout_14 is mips_sys:isys|mips_dvc:imips_dvc|dout_14 at LC_X28_Y3_N1
--operation mode is normal
 
F1_dout_14_lut_out = K1_cntr_14 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[14] # !K1_cntr_14 & F1_dout_0_0_a3_3[0] & F1_cmd[14];
F1_dout_14 = DFFEAS(F1_dout_14_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_14 at LC_X21_Y6_N2
--operation mode is normal
 
BB1_r32_o_14_lut_out = AB1_r32_o_12;
BB1_r32_o_14 = DFFEAS(BB1_r32_o_14_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[1] at LC_X25_Y7_N1
--operation mode is normal
 
HD1_dout_iv_1_a[1] = RB1_byte_addr_o_1 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_1 # !RB1_byte_addr_o_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_1;
 
 
--HD1_dout_iv_1_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[0] at LC_X26_Y4_N5
--operation mode is normal
 
HD1_dout_iv_1_a[0] = YD1_mux_fw_1 & !RB1_byte_addr_o_0 & !FD1_N_14_i_0_s2 # !FD1_r_data_0 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_0;
 
 
--GD1_dout_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_21 at LC_X20_Y7_N2
--operation mode is normal
 
GD1_dout_iv_1_21 = FD1_N_20_i_0_s3 & LD1_q_b[21] # !GD1_dout_iv_1_a[21];
 
 
--CD1_res_7_0_0_a_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_18 at LC_X22_Y9_N8
--operation mode is normal
 
CD1_res_7_0_0_a_18 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_19;
 
 
--GD1_dout_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_22 at LC_X24_Y7_N4
--operation mode is normal
 
GD1_dout_iv_1_22 = LD1_q_b[22] & FD1_N_20_i_0_s3 # !GD1_dout_iv_1_a[22];
 
 
--CD1_res_7_0_0_a_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_19 at LC_X23_Y16_N9
--operation mode is normal
 
CD1_res_7_0_0_a_19 = !ED1_r32_o_20 # !CD1_res_7_0_0_a2[18];
 
 
--GD1_dout_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_25 at LC_X25_Y6_N9
--operation mode is normal
 
GD1_dout_iv_1_25 = FD1_N_20_i_0_s3 & LD1_q_b[25] # !GD1_dout_iv_1_a[25];
 
 
--CD1_res_7_0_0_a_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_22 at LC_X24_Y13_N5
--operation mode is normal
 
CD1_res_7_0_0_a_22 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_23;
 
 
--F1_dout_25 is mips_sys:isys|mips_dvc:imips_dvc|dout_25 at LC_X28_Y3_N8
--operation mode is normal
 
F1_dout_25_lut_out = K1_cntr_25 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[25] # !K1_cntr_25 & F1_dout_0_0_a3_3[0] & F1_cmd[25];
F1_dout_25 = DFFEAS(F1_dout_25_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_25 at LC_X25_Y6_N1
--operation mode is normal
 
BB1_r32_o_25_lut_out = GND;
BB1_r32_o_25 = DFFEAS(BB1_r32_o_25_lut_out, GLOBAL(E1__clk0), VCC, , , AB1_r32_o_23, , , VCC);
 
 
--GD1_dout_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_26 at LC_X20_Y8_N3
--operation mode is normal
 
GD1_dout_iv_1_26 = FD1_N_20_i_0_s3 & LD1_q_b[26] # !GD1_dout_iv_1_a[26];
 
 
--CD1_res_7_0_0_a_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_23 at LC_X26_Y9_N3
--operation mode is normal
 
ED1_r32_o_24_qfbk = ED1_r32_o_24;
CD1_res_7_0_0_a_23 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_24_qfbk;
 
--ED1_r32_o_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_24 at LC_X26_Y9_N3
--operation mode is normal
 
ED1_r32_o_24 = DFFEAS(CD1_res_7_0_0_a_23, GLOBAL(E1__clk0), VCC, , C1_G_504, KE1_q_a[0], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--F1_dout_26 is mips_sys:isys|mips_dvc:imips_dvc|dout_26 at LC_X29_Y7_N8
--operation mode is normal
 
F1_dout_26_lut_out = F1_dout_0_0_a3_3[0] & F1_cmd[26] # K1_cntr_26 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a3_3[0] & K1_cntr_26 & F1_dout_0_0_a3_4[0];
F1_dout_26 = DFFEAS(F1_dout_26_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_26 at LC_X29_Y7_N4
--operation mode is normal
 
BB1_r32_o_26_lut_out = AB1_r32_o_24;
BB1_r32_o_26 = DFFEAS(BB1_r32_o_26_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_29 at LC_X26_Y5_N5
--operation mode is normal
 
GD1_dout_iv_1_29 = LD1_q_b[29] & FD1_N_20_i_0_s3 # !GD1_dout_iv_1_a[29];
 
 
--GD1_dout_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_17 at LC_X26_Y6_N8
--operation mode is normal
 
GD1_dout_iv_1_17 = FD1_N_20_i_0_s3 & LD1_q_b[17] # !GD1_dout_iv_1_a[17];
 
 
--CD1_res_7_0_0_a_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_14 at LC_X22_Y16_N3
--operation mode is normal
 
CD1_res_7_0_0_a_14 = DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_1 & !DC1_ext_ctl_o_0 # !DC1_ext_ctl_o_2 & DC1_ext_ctl_o_0;
 
 
--GD1_dout_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_18 at LC_X21_Y8_N5
--operation mode is normal
 
GD1_dout_iv_1_18 = FD1_N_20_i_0_s3 & LD1_q_b[18] # !GD1_dout_iv_1_a[18];
 
 
--CD1_res_7_0_0_a_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_15 at LC_X22_Y12_N5
--operation mode is normal
 
CD1_res_7_0_0_a_15 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_16;
 
 
--VD1_un134_hilo_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[8] at LC_X5_Y16_N6
--operation mode is arithmetic
 
VD1_un134_hilo_combout[8]_carry_eqn = (!VD1_un134_hilo_cout[4] & VD1_un134_hilo_cout[6]) # (VD1_un134_hilo_cout[4] & VD1L9591);
VD1_un134_hilo_combout[8] = VD1_hilo_8 $ !VD1_un134_hilo_combout[8]_carry_eqn;
 
--VD1_un134_hilo_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[8] at LC_X5_Y16_N6
--operation mode is arithmetic
 
VD1_un134_hilo_cout[8]_cout_0 = VD1_hilo_9 & VD1_hilo_8 & !VD1_un134_hilo_cout[6];
VD1_un134_hilo_cout[8] = CARRY(VD1_un134_hilo_cout[8]_cout_0);
 
--VD1L3691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[8]~COUT1_16 at LC_X5_Y16_N6
--operation mode is arithmetic
 
VD1L3691_cout_1 = VD1_hilo_9 & VD1_hilo_8 & !VD1L9591;
VD1L3691 = CARRY(VD1L3691_cout_1);
 
 
--VD1_nop2_reged[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[9] at LC_X12_Y4_N6
--operation mode is arithmetic
 
VD1_nop2_reged[9]_carry_eqn = (!VD1_nop2_reged_cout[5] & VD1_nop2_reged_cout[7]) # (VD1_nop2_reged_cout[5] & VD1L3231);
VD1_nop2_reged[9] = VD1_op2_reged[9] $ (VD1_op2_reged[8] # VD1_nop2_reged[9]_carry_eqn);
 
--VD1_nop2_reged_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[9] at LC_X12_Y4_N6
--operation mode is arithmetic
 
VD1_nop2_reged_cout[9]_cout_0 = !VD1_op2_reged[8] & !VD1_op2_reged[9] & !VD1_nop2_reged_cout[7];
VD1_nop2_reged_cout[9] = CARRY(VD1_nop2_reged_cout[9]_cout_0);
 
--VD1L7231 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[9]~COUT1_4 at LC_X12_Y4_N6
--operation mode is arithmetic
 
VD1L7231_cout_1 = !VD1_op2_reged[8] & !VD1_op2_reged[9] & !VD1L3231;
VD1L7231 = CARRY(VD1L7231_cout_1);
 
 
--VD1_hilo_37_iv_0_1_a[40] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[40] at LC_X5_Y6_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[40] = VD1_hilo_0_sqmuxa & !VD1_hilo_40 & VD1_hilo_37_iv_0_o3_2[34] # !VD1_hilo_8 # !VD1_hilo_0_sqmuxa & !VD1_hilo_40 & VD1_hilo_37_iv_0_o3_2[34];
 
 
--VD1_hilo_24_add8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add8 at LC_X8_Y4_N2
--operation mode is arithmetic
 
VD1_hilo_24_add8_carry_eqn = (!VD1_hilo_24_carry_5 & VD1_hilo_24_carry_7) # (VD1_hilo_24_carry_5 & VD1L094);
VD1_hilo_24_add8 = VD1_un1_op2_reged_1_combout[8] $ VD1_hilo_39 $ !VD1_hilo_24_add8_carry_eqn;
 
--VD1_hilo_24_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_8 at LC_X8_Y4_N2
--operation mode is arithmetic
 
VD1_hilo_24_carry_8_cout_0 = VD1_un1_op2_reged_1_combout[8] & VD1_hilo_39 # !VD1_hilo_24_carry_7 # !VD1_un1_op2_reged_1_combout[8] & VD1_hilo_39 & !VD1_hilo_24_carry_7;
VD1_hilo_24_carry_8 = CARRY(VD1_hilo_24_carry_8_cout_0);
 
--VD1L294 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_8~COUT1_1 at LC_X8_Y4_N2
--operation mode is arithmetic
 
VD1L294_cout_1 = VD1_un1_op2_reged_1_combout[8] & VD1_hilo_39 # !VD1L094 # !VD1_un1_op2_reged_1_combout[8] & VD1_hilo_39 & !VD1L094;
VD1L294 = CARRY(VD1L294_cout_1);
 
 
--YB1_rd_sel_2_0_0_a3_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a3_0[0] at LC_X26_Y19_N9
--operation mode is normal
 
YB1_rd_sel_2_0_0_a3_0[0] = YB1_alu_func_2_0_0_a2_1_x[3] & YB1_alu_func_2_0_0_a2_0[1] & !KE1_q_a[6] & YB1_rd_sel_2_0_0_a3_0_a[0];
 
 
--YB1_rd_sel_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_0_a[1] at LC_X29_Y17_N5
--operation mode is normal
 
YB1_rd_sel_2_0_0_0_a[1] = KE1_q_a[3] & !KE1_q_a[4] & KE1_q_a[2] # !KE1_q_a[3] & KE1_q_a[7];
 
 
--YB1_alu_we_1_0_0_a3_1_0[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1_0[0] at LC_X26_Y19_N4
--operation mode is normal
 
YB1_alu_we_1_0_0_a3_1_0[0] = YB1_alu_we_1_0_0_a3_1_0_a[0] & GE1_q_a[1] & !GE1_q_a[2] # !GE1_q_a[3];
 
 
--F1_cmd[20] is mips_sys:isys|mips_dvc:imips_dvc|cmd[20] at LC_X29_Y7_N3
--operation mode is normal
 
F1_cmd[20]_lut_out = CB1_r32_o_20;
F1_cmd[20] = DFFEAS(F1_cmd[20]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_20 at LC_X21_Y7_N6
--operation mode is normal
 
GD1_dout_iv_1_20 = FD1_N_20_i_0_s3 & LD1_q_b[20] # !GD1_dout_iv_1_a[20];
 
 
--AD1_un1_rst_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2 at LC_X30_Y17_N4
--operation mode is normal
 
AD1_un1_rst_2 = !AD1_CurrState_Sreg0_ns_0_a3_0_o2_0 & AD1_un1_rst_2_s & AD1_un1_rst_2_a;
 
 
--WB76L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_0_|lpm_latch:U1|q[0]~56 at LC_X30_Y17_N7
--operation mode is normal
 
AD1_delay_counter_Sreg0[0]_qfbk = AD1_delay_counter_Sreg0[0];
WB76L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & !AD1_delay_counter_Sreg0[0]_qfbk # !AD1_un1_rst_2 & WB76L1;
 
--AD1_delay_counter_Sreg0[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[0] at LC_X30_Y17_N7
--operation mode is normal
 
AD1_delay_counter_Sreg0[0] = DFFEAS(WB76L1, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--AD1_un4_next_delay_counter_Sreg0_sum5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum5 at LC_X31_Y17_N6
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_sum5 = AD1_delay_counter_Sreg0[5] $ (!AD1_un4_next_delay_counter_Sreg0_c3 & !AD1_delay_counter_Sreg0[4]);
 
 
--WB27L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1|q[0]~14 at LC_X31_Y17_N4
--operation mode is normal
 
WB27L1 = AD1_CurrState_Sreg0[2] # AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum5 # !AD1_un1_rst_2 & WB27L1;
 
 
--YB1_alu_func_2_0_0_a2_2[4] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_a2_2[4] at LC_X26_Y19_N7
--operation mode is normal
 
YB1_alu_func_2_0_0_a2_2[4] = !KE1_q_a[6] & GE1_q_a[2] & !KE1_q_a[2] & YB1_alu_func_2_0_0_a2_1_x[3];
 
 
--YB1_alu_func_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_0_0_1_a[1] at LC_X25_Y18_N5
--operation mode is normal
 
YB1_alu_func_2_0_0_1_a[1] = GE1_q_a[1] & !YB1_alu_func_2_0_0_a2_2_x[1] # !YB1_alu_func_2_0_0_a2_0[1] # !GE1_q_a[1] & !YB1_alu_func_2_0_0_a2_x[0];
 
 
--YB1_alu_func_2_i_m3_0_a3_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_5_a[2] at LC_X25_Y18_N8
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_a3_5_a[2] = !KE1_q_a[3] & !GE1_q_a[4] & GE1_q_a[1] & !KE1_q_a[4];
 
 
--YB1_alu_func_2_i_m3_0_a3_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_a3_0_x[2] at LC_X29_Y16_N0
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_a3_0_x[2] = KE1_q_a[5] & KE1_q_a[3] $ !KE1_q_a[4];
 
 
--YB1_alu_func_2_i_m3_0_2_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_func_2_i_m3_0_2_a[2] at LC_X29_Y16_N3
--operation mode is normal
 
YB1_alu_func_2_i_m3_0_2_a[2] = !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[0] # YB1_cmp_ctl_2_0_0_a2_1[0] & WB93L2;
 
 
--YB1_muxa_ctl_2_0_0_a3_1[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a3_1[0] at LC_X24_Y19_N3
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_a3_1[0] = !KE1_q_a[4] & !KE1_q_a[5] & !KE1_q_a[7] & YB1_alu_func_2_0_0_a2_0_x[0];
 
 
--YB1_muxb_ctl_2_0_0_a3_0_0_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a3_0_0_x[0] at LC_X27_Y17_N1
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_a3_0_0_x[0] = YB1_muxa_ctl_2_0_0_o2_0[1] & YB1_alu_func_2_0_0_a2_0[1];
 
 
--YB1_muxb_ctl_2_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a[0] at LC_X25_Y17_N2
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_a[0] = YB1_alu_func_2_0_0_a2_2_x[1] & !YB1_alu_func_2_0_0_a2_3_x[0] & !WB85L1 # !YB1_alu_func_2_0_0_a2_3[1] # !YB1_alu_func_2_0_0_a2_2_x[1] & !WB85L1 # !YB1_alu_func_2_0_0_a2_3[1];
 
 
--YB1_muxb_ctl_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0_Z[1] at LC_X27_Y15_N8
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_0_Z[1] = !KE1_q_a[4] & !KE1_q_a[7] & !KE1_q_a[3] & !YB1_muxb_ctl_2_0_0_0_a[1];
 
 
--YB1_muxb_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_a[1] at LC_X27_Y15_N0
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_a[1] = KE1_q_a[7] & !KE1_q_a[4] & KE1_q_a[2] # !KE1_q_a[3];
 
 
--YB1_ext_ctl_2_i_m3_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_a[1] at LC_X29_Y16_N6
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_a[1] = !KE1_q_a[7] & KE1_q_a[3] # YB1_fsm_dly_2_0_0_o2_x[2] & WB15L1;
 
 
--YB1_ext_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a[2] at LC_X24_Y17_N3
--operation mode is normal
 
YB1_ext_ctl_2_0_0_a[2] = !YB1_ext_ctl_2_0_0_a3_1_x[2] & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_ext_ctl_2_0_0_a2_0_x[2];
 
 
--YB1_ext_ctl_2_i_m3_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_a_x[0] at LC_X24_Y17_N6
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_a_x[0] = !KE1_q_a[3] & !YB1_cmp_ctl_2_0_0_a2_1[0] # !WB05L2;
 
 
--YB1_ext_ctl_2_i_m3_0_2[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_2[0] at LC_X24_Y17_N2
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_2[0] = YB1_ext_ctl_2_i_m3_0_0_Z[0] # !KE1_q_a[4] & !KE1_q_a[7] & !YB1_ext_ctl_2_i_m3_0_2_a[0];
 
 
--YB1_muxa_ctl_2_0_0_0_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0_Z[1] at LC_X29_Y17_N3
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_0_Z[1] = KE1_q_a[3] & YB1_muxa_ctl_2_0_0_a2_x[1] & KE1_q_a[7] # !KE1_q_a[3] & YB1_muxa_ctl_2_0_0_0_a[1] # KE1_q_a[7];
 
 
--YB1_muxa_ctl_2_0_0_2_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_2_a[1] at LC_X27_Y17_N7
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_2_a[1] = YB1_alu_func_2_0_0_o2_x[3] & !YB1_alu_func_2_0_0_a2_2_x[1] & GE1_q_a[4] # !YB1_muxa_ctl_2_0_0_o2_0[1] # !YB1_alu_func_2_0_0_o2_x[3] & GE1_q_a[4] # !YB1_muxa_ctl_2_0_0_o2_0[1];
 
 
--FD1_un14_qa_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE at LC_X26_Y14_N3
--operation mode is normal
 
FD1_r_wraddress[4]_qfbk = FD1_r_wraddress[4];
FD1_un14_qa_NE = FD1_un14_qa_NE_a # FD1_un14_qa_NE_1 # FD1_r_rdaddress_a[4] $ FD1_r_wraddress[4]_qfbk;
 
--FD1_r_wraddress[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[4] at LC_X26_Y14_N3
--operation mode is normal
 
FD1_r_wraddress[4] = DFFEAS(FD1_un14_qa_NE, GLOBAL(E1__clk0), VCC, , , NB1_r5_o_4, , , VCC);
 
 
--FD1_N_18_i_0_s3_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3_a at LC_X25_Y8_N0
--operation mode is normal
 
FD1_N_18_i_0_s3_a = !FD1_un23_qa_i_0_a2 & YD1_un17_mux_fw_NE # WD1_un30_mux_fw # !MC1_wb_we_o_0;
 
 
--FD1_N_14_i_0_s2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2 at LC_X25_Y8_N6
--operation mode is normal
 
FD1_N_14_i_0_s2 = !FD1_un23_qa_i_0_a2 & !FD1_un14_qa_NE & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2_a;
 
 
--FD1_r_rdaddress_a_0_x[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[0] at LC_X26_Y14_N4
--operation mode is normal
 
FD1_r_rdaddress_a[0]_qfbk = FD1_r_rdaddress_a[0];
FD1_r_rdaddress_a_0_x[0] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[0]_qfbk # !AD1_CurrState_Sreg0_2 & JE1_q_a[5];
 
--FD1_r_rdaddress_a[0] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[0] at LC_X26_Y14_N4
--operation mode is normal
 
FD1_r_rdaddress_a[0] = DFFEAS(FD1_r_rdaddress_a_0_x[0], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[5], , , VCC);
 
 
--FD1_r_rdaddress_a_0_x[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[1] at LC_X26_Y15_N2
--operation mode is normal
 
FD1_r_rdaddress_a_0_x[1] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[1] # !AD1_CurrState_Sreg0_2 & JE1_q_a[6];
 
 
--FD1_r_rdaddress_a_0_x[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[2] at LC_X27_Y14_N0
--operation mode is normal
 
FD1_r_rdaddress_a_0_x[2] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[2] # !AD1_CurrState_Sreg0_2 & JE1_q_a[7];
 
 
--FD1_r_rdaddress_a_0_x[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[3] at LC_X27_Y14_N5
--operation mode is normal
 
FD1_r_rdaddress_a[3]_qfbk = FD1_r_rdaddress_a[3];
FD1_r_rdaddress_a_0_x[3] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[3]_qfbk # !AD1_CurrState_Sreg0_2 & KE1_q_a[0];
 
--FD1_r_rdaddress_a[3] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[3] at LC_X27_Y14_N5
--operation mode is normal
 
FD1_r_rdaddress_a[3] = DFFEAS(FD1_r_rdaddress_a_0_x[3], GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KE1_q_a[0], , , VCC);
 
 
--FD1_r_rdaddress_a_0_x[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a_0_x[4] at LC_X27_Y14_N8
--operation mode is normal
 
FD1_r_rdaddress_a_0_x[4] = AD1_CurrState_Sreg0_2 & FD1_r_rdaddress_a[4] # !AD1_CurrState_Sreg0_2 & KE1_q_a[1];
 
 
--YD1_un17_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE_1 at LC_X26_Y9_N5
--operation mode is normal
 
ED1_r32_o_22_qfbk = ED1_r32_o_22;
YD1_un17_mux_fw_NE_1 = NB1_r5_o_1 & ED1_r32_o_21 $ NB1_r5_o_0 # !ED1_r32_o_22_qfbk # !NB1_r5_o_1 & ED1_r32_o_22_qfbk # ED1_r32_o_21 $ NB1_r5_o_0;
 
--ED1_r32_o_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_22 at LC_X26_Y9_N5
--operation mode is normal
 
ED1_r32_o_22 = DFFEAS(YD1_un17_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[6], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--YD1_un17_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un17_mux_fw_NE_a at LC_X26_Y9_N8
--operation mode is normal
 
ED1_r32_o_23_qfbk = ED1_r32_o_23;
YD1_un17_mux_fw_NE_a = NB1_r5_o_2 & ED1_r32_o_24 $ NB1_r5_o_3 # !ED1_r32_o_23_qfbk # !NB1_r5_o_2 & ED1_r32_o_23_qfbk # ED1_r32_o_24 $ NB1_r5_o_3;
 
--ED1_r32_o_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_23 at LC_X26_Y9_N8
--operation mode is normal
 
ED1_r32_o_23 = DFFEAS(YD1_un17_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[7], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--YD1_un1_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE at LC_X25_Y8_N2
--operation mode is normal
 
MB1_r5_o_4_qfbk = MB1_r5_o_4;
YD1_un1_mux_fw_NE = YD1_un1_mux_fw_NE_a # YD1_un1_mux_fw_NE_1 # ED1_r32_o_25 $ MB1_r5_o_4_qfbk;
 
--MB1_r5_o_4 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_4 at LC_X25_Y8_N2
--operation mode is normal
 
MB1_r5_o_4 = DFFEAS(YD1_un1_mux_fw_NE, GLOBAL(E1__clk0), VCC, , , LB1_r5_o_4, , , VCC);
 
 
--GD1_dout_iv_1_10 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_10 at LC_X20_Y8_N0
--operation mode is normal
 
GD1_dout_iv_1_10 = FD1_N_20_i_0_s3 & LD1_q_b[10] # !GD1_dout_iv_1_a[10];
 
 
--GD1_dout_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_15 at LC_X24_Y4_N5
--operation mode is normal
 
GD1_dout_iv_1_15 = FD1_N_20_i_0_s3 & LD1_q_b[15] # !GD1_dout_iv_1_a[15];
 
 
--F1_dout_15 is mips_sys:isys|mips_dvc:imips_dvc|dout_15 at LC_X30_Y3_N8
--operation mode is normal
 
F1_dout_15_lut_out = K1_cntr_15 & F1_dout_0_0_a3_4[0] # F1_dout_0_0_a3_3[0] & F1_cmd[15] # !K1_cntr_15 & F1_dout_0_0_a3_3[0] & F1_cmd[15];
F1_dout_15 = DFFEAS(F1_dout_15_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_15 at LC_X29_Y13_N7
--operation mode is normal
 
BB1_r32_o_15_lut_out = AB1_r32_o_13;
BB1_r32_o_15 = DFFEAS(BB1_r32_o_15_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_27 at LC_X22_Y7_N3
--operation mode is normal
 
GD1_dout_iv_1_27 = FD1_N_20_i_0_s3 & LD1_q_b[27] # !GD1_dout_iv_1_a[27];
 
 
--CD1_res_7_0_0_a_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_24 at LC_X24_Y13_N8
--operation mode is normal
 
CD1_res_7_0_0_a_24 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_25;
 
 
--F1_dout_27 is mips_sys:isys|mips_dvc:imips_dvc|dout_27 at LC_X25_Y15_N0
--operation mode is normal
 
F1_dout_27_lut_out = K1_cntr_27 & F1_dout_0_0_a3_4[0] # F1_cmd[27] & F1_dout_0_0_a3_3[0] # !K1_cntr_27 & F1_cmd[27] & F1_dout_0_0_a3_3[0];
F1_dout_27 = DFFEAS(F1_dout_27_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_27 at LC_X25_Y15_N9
--operation mode is normal
 
BB1_r32_o_27_lut_out = AB1_r32_o_25;
BB1_r32_o_27 = DFFEAS(BB1_r32_o_27_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_19 at LC_X27_Y7_N6
--operation mode is normal
 
GD1_dout_iv_1_19 = FD1_N_20_i_0_s3 & LD1_q_b[19] # !GD1_dout_iv_1_a[19];
 
 
--CD1_res_7_0_0_a_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_16 at LC_X22_Y15_N6
--operation mode is normal
 
CD1_res_7_0_0_a_16 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_17;
 
 
--CD1_res_7_0_0_a_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_17 at LC_X22_Y14_N6
--operation mode is normal
 
CD1_res_7_0_0_a_17 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_18;
 
 
--VD1_count[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[2] at LC_X32_Y9_N4
--operation mode is arithmetic
 
VD1_count[2]_lut_out = VD1_count[2] $ !VD1_count_cout[1];
VD1_count[2] = DFFEAS(VD1_count[2]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
--VD1_count_cout[2] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[2] at LC_X32_Y9_N4
--operation mode is arithmetic
 
VD1_count_cout[2] = CARRY(VD1_count[2] & !VD1L701);
 
 
--VD1_over_carry_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_30 at LC_X10_Y10_N4
--operation mode is arithmetic
 
VD1_over_carry_30 = CARRY(PD1_a_o_30 & !VD1L7251 # !VD1_b_o_iv_30 # !PD1_a_o_30 & !VD1_b_o_iv_30 & !VD1L7251);
 
 
--VD1_eqz_2_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_17 at LC_X10_Y6_N4
--operation mode is normal
 
VD1_eqz_2_17 = !VD1_hilo_40 & !VD1_hilo_39 & !VD1_hilo_38 & !VD1_hilo_52;
 
 
--VD1_eqz_2_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_21 at LC_X10_Y6_N5
--operation mode is normal
 
VD1_eqz_2_21 = !VD1_hilo_45 & !VD1_hilo_51 & !VD1_hilo_59 & !VD1_hilo_53;
 
 
--VD1_eqz_2_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_27 at LC_X10_Y5_N1
--operation mode is normal
 
VD1_eqz_2_27 = !VD1_hilo_35 & VD1_eqz_2_16 & !VD1_hilo_50 & VD1_eqz_2_27_a;
 
 
--VD1_eqz_2_30 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_30 at LC_X11_Y4_N9
--operation mode is normal
 
VD1_eqz_2_30 = VD1_eqz_2_19 & VD1_eqz_2_22 & VD1_eqz_2_20 & VD1_eqz_2_23;
 
 
--VD1_eqop2_2_NE_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_11 at LC_X12_Y5_N8
--operation mode is normal
 
VD1_eqop2_2_NE_11 = VD1_eqop2_2_NE_11_a # VD1_eqop2_2_NE_123 # VD1_eqop2_2_NE_122 # VD1_eqop2_2_NE_121;
 
 
--VD1_eqop2_2_NE_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_9 at LC_X11_Y5_N7
--operation mode is normal
 
VD1_eqop2_2_NE_9 = VD1_eqop2_2_NE_112 # VD1_eqop2_2_NE_114 # VD1_eqop2_2_NE_115_0 # VD1_eqop2_2_NE_113;
 
 
--VD1_eqop2_2_NE_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_10 at LC_X14_Y4_N2
--operation mode is normal
 
VD1_eqop2_2_NE_10 = VD1_eqop2_2_NE_118 # VD1_eqop2_2_NE_116 # VD1_eqop2_2_NE_117 # VD1_eqop2_2_NE_119;
 
 
--VD1_eqop2_2_NE_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_12 at LC_X11_Y2_N6
--operation mode is normal
 
VD1_eqop2_2_NE_12 = VD1_eqop2_2_32 # VD1_eqop2_2_NE_126 # VD1_eqop2_2_NE_124 # !VD1_eqop2_2_NE_12_a;
 
 
--VD1_nop2_reged[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[32] at LC_X13_Y3_N8
--operation mode is normal
 
VD1_nop2_reged[32]_carry_eqn = (!VD1_nop2_reged_cout[24] & VD1_nop2_reged_cout[30]) # (VD1_nop2_reged_cout[24] & VD1L5631);
VD1_nop2_reged[32] = VD1_op2_sign_reged $ (VD1_nop2_reged[32]_carry_eqn);
 
 
--VD1_eqnop2_2_NE_7_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_7_a at LC_X11_Y6_N2
--operation mode is normal
 
VD1_eqnop2_2_NE_7_a = VD1_hilo_48 & VD1_hilo[32] $ VD1_op2_reged[0] # !VD1_nop2_reged[16] # !VD1_hilo_48 & VD1_nop2_reged[16] # VD1_hilo[32] $ VD1_op2_reged[0];
 
 
--VD1_eqnop2_2_NE_143 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_143 at LC_X10_Y2_N8
--operation mode is normal
 
VD1_eqnop2_2_NE_143 = VD1_hilo_47 & VD1_nop2_reged[31] $ VD1_hilo_63 # !VD1_nop2_reged[15] # !VD1_hilo_47 & VD1_nop2_reged[15] # VD1_nop2_reged[31] $ VD1_hilo_63;
 
 
--VD1_eqnop2_2_NE_129 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_129 at LC_X11_Y3_N6
--operation mode is normal
 
VD1_eqnop2_2_NE_129 = VD1_nop2_reged[1] & VD1_nop2_reged[17] $ VD1_hilo_49 # !VD1_hilo_33 # !VD1_nop2_reged[1] & VD1_hilo_33 # VD1_nop2_reged[17] $ VD1_hilo_49;
 
 
--VD1_eqnop2_2_NE_131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_131 at LC_X11_Y3_N8
--operation mode is normal
 
VD1_eqnop2_2_NE_131 = VD1_hilo_35 & VD1_nop2_reged[19] $ VD1_hilo_51 # !VD1_nop2_reged[3] # !VD1_hilo_35 & VD1_nop2_reged[3] # VD1_nop2_reged[19] $ VD1_hilo_51;
 
 
--VD1_eqnop2_2_NE_130 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_130 at LC_X11_Y5_N4
--operation mode is normal
 
VD1_eqnop2_2_NE_130 = VD1_hilo_50 & VD1_hilo_34 $ VD1_nop2_reged[2] # !VD1_nop2_reged[18] # !VD1_hilo_50 & VD1_nop2_reged[18] # VD1_hilo_34 $ VD1_nop2_reged[2];
 
 
--VD1_eqnop2_2_NE_132_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_132_0 at LC_X11_Y3_N5
--operation mode is normal
 
VD1_eqnop2_2_NE_132_0 = VD1_nop2_reged[20] & VD1_hilo_36 $ VD1_nop2_reged[4] # !VD1_hilo_52 # !VD1_nop2_reged[20] & VD1_hilo_52 # VD1_hilo_36 $ VD1_nop2_reged[4];
 
 
--VD1_eqnop2_2_NE_133 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_133 at LC_X10_Y5_N2
--operation mode is normal
 
VD1_eqnop2_2_NE_133 = VD1_hilo_37 & VD1_hilo_53 $ VD1_nop2_reged[21] # !VD1_nop2_reged[5] # !VD1_hilo_37 & VD1_nop2_reged[5] # VD1_hilo_53 $ VD1_nop2_reged[21];
 
 
--VD1_eqnop2_2_NE_134 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_134 at LC_X14_Y4_N6
--operation mode is normal
 
VD1_eqnop2_2_NE_134 = VD1_hilo_54 & VD1_nop2_reged[6] $ VD1_hilo_38 # !VD1_nop2_reged[22] # !VD1_hilo_54 & VD1_nop2_reged[22] # VD1_nop2_reged[6] $ VD1_hilo_38;
 
 
--VD1_eqnop2_2_NE_135 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_135 at LC_X15_Y4_N4
--operation mode is normal
 
VD1_eqnop2_2_NE_135 = VD1_nop2_reged[7] & VD1_nop2_reged[23] $ VD1_hilo_55 # !VD1_hilo_39 # !VD1_nop2_reged[7] & VD1_hilo_39 # VD1_nop2_reged[23] $ VD1_hilo_55;
 
 
--VD1_eqnop2_2_NE_10_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_10_a at LC_X14_Y4_N5
--operation mode is normal
 
VD1_eqnop2_2_NE_10_a = VD1_nop2_reged[24] & VD1_hilo_40 $ VD1_nop2_reged[8] # !VD1_hilo_56 # !VD1_nop2_reged[24] & VD1_hilo_56 # VD1_hilo_40 $ VD1_nop2_reged[8];
 
 
--VD1_eqnop2_2_NE_141 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_141 at LC_X11_Y2_N2
--operation mode is normal
 
VD1_eqnop2_2_NE_141 = VD1_nop2_reged[29] & VD1_hilo_45 $ VD1_nop2_reged[13] # !VD1_hilo_61 # !VD1_nop2_reged[29] & VD1_hilo_61 # VD1_hilo_45 $ VD1_nop2_reged[13];
 
 
--VD1_eqnop2_2_NE_142 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_142 at LC_X13_Y2_N5
--operation mode is normal
 
VD1_eqnop2_2_NE_142 = VD1_nop2_reged[14] & VD1_nop2_reged[30] $ VD1_hilo_62 # !VD1_hilo_46 # !VD1_nop2_reged[14] & VD1_hilo_46 # VD1_nop2_reged[30] $ VD1_hilo_62;
 
 
--VD1_eqnop2_2_NE_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_5 at LC_X12_Y2_N6
--operation mode is normal
 
VD1_eqnop2_2_NE_5 = VD1_eqnop2_2_NE_5_a # VD1_eqnop2_2_9 # VD1_hilo_58 $ VD1_nop2_reged[26];
 
 
--VD1_eqnop2_2_NE_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_8 at LC_X12_Y5_N4
--operation mode is normal
 
VD1_eqnop2_2_NE_8 = VD1_eqnop2_2_NE_8_a # VD1_hilo_59 $ VD1_nop2_reged[27] # !VD1_eqnop2_2_NE_140_i_a2;
 
 
--VD1_hilo_33_i_m_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[64] at LC_X7_Y9_N0
--operation mode is normal
 
VD1_hilo_33_i_m_a[64] = VD1_addnop2 & !VD1_un50_hilo_add32 # !VD1_addnop2 & !VD1_un59_hilo_add32;
 
 
--VD1_hilo_15_3_i[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_3_i[63] at LC_X7_Y9_N2
--operation mode is normal
 
VD1_hilo_15_3_i[63] = VD1_hilo_15_3_i_a[63] # !VD1_hilo[64] & !VD1_hilo_15_1[56];
 
 
--VD1_hilo_37_iv_1_a[64] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1_a[64] at LC_X7_Y9_N8
--operation mode is normal
 
VD1_hilo_37_iv_1_a[64] = VD1_hilo25 & VD1_hilo[64] & !RC1_alu_func_o_0 # !VD1_hilo25 & VD1_hilo[64] # !VD1_hilo_0_sqmuxa;
 
 
--VD1_nop2_reged_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[0] at LC_X13_Y4_N2
--operation mode is arithmetic
 
VD1_nop2_reged_cout[0]_cout_0 = !VD1_op2_reged[0] & !VD1_op2_reged[1];
VD1_nop2_reged_cout[0] = CARRY(VD1_nop2_reged_cout[0]_cout_0);
 
--VD1L1131 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[0]~COUT1_13 at LC_X13_Y4_N2
--operation mode is arithmetic
 
VD1L1131_cout_1 = !VD1_op2_reged[0] & !VD1_op2_reged[1];
VD1L1131 = CARRY(VD1L1131_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[3] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[3] at LC_X12_Y4_N0
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[3] = VD1_eqop2_2_32 & VD1_op2_reged[3] # !VD1_eqop2_2_32 & VD1_nop2_reged[3];
 
 
--VD1_hilo_37_iv_0_a3_2[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_2[38] at LC_X5_Y7_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_2[38] = VD1_hilo_0_sqmuxa & !VD1_hilo_6;
 
 
--VD1_hilo_37_iv_0_a3_6[38] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a3_6[38] at LC_X5_Y6_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_a3_6[38] = VD1_hilo_3_sqmuxa & VD1_addop2 & !VD1_un59_hilo_add6 & !VD1_addnop2;
 
 
--GD1_dout_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_16 at LC_X21_Y5_N4
--operation mode is normal
 
GD1_dout_iv_1_16 = FD1_N_20_i_0_s3 & LD1_q_b[16] # !GD1_dout_iv_1_a[16];
 
 
--CD1_res_7_0_0_0_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_14 at LC_X24_Y15_N5
--operation mode is normal
 
ED1_r32_o_0_qfbk = ED1_r32_o_0;
CD1_res_7_0_0_0_14 = CD1_res_7_0_0_0_a[16] & ED1_r32_o_15 # CD1_res_7_0_0_a2_16 & ED1_r32_o_0_qfbk # !CD1_res_7_0_0_0_a[16] & CD1_res_7_0_0_a2_16 & ED1_r32_o_0_qfbk;
 
--ED1_r32_o_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_0 at LC_X24_Y15_N5
--operation mode is normal
 
ED1_r32_o_0 = DFFEAS(CD1_res_7_0_0_0_14, GLOBAL(E1__clk0), VCC, , C1_G_504, GE1_q_a[0], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--GD1_dout_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_28 at LC_X26_Y8_N1
--operation mode is normal
 
GD1_dout_iv_1_28 = FD1_N_20_i_0_s3 & LD1_q_b[28] # !GD1_dout_iv_1_a[28];
 
 
--GD1_dout_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_23 at LC_X23_Y5_N6
--operation mode is normal
 
GD1_dout_iv_1_23 = FD1_N_20_i_0_s3 & LD1_q_b[23] # !GD1_dout_iv_1_a[23];
 
 
--CD1_res_7_0_0_a_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_20 at LC_X24_Y13_N9
--operation mode is normal
 
CD1_res_7_0_0_a_20 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_21;
 
 
--GD1_dout_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_24 at LC_X23_Y6_N3
--operation mode is normal
 
GD1_dout_iv_1_24 = FD1_N_20_i_0_s3 & LD1_q_b[24] # !GD1_dout_iv_1_a[24];
 
 
--CD1_res_7_0_0_a_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_a_21 at LC_X24_Y13_N2
--operation mode is normal
 
CD1_res_7_0_0_a_21 = !CD1_res_7_0_0_a2[18] # !ED1_r32_o_22;
 
 
--F1_dout_24 is mips_sys:isys|mips_dvc:imips_dvc|dout_24 at LC_X29_Y5_N6
--operation mode is normal
 
F1_dout_24_lut_out = F1_cmd[24] & F1_dout_0_0_a3_3[0] # F1_dout_0_0_a3_4[0] & K1_cntr_24 # !F1_cmd[24] & F1_dout_0_0_a3_4[0] & K1_cntr_24;
F1_dout_24 = DFFEAS(F1_dout_24_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--BB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_24 at LC_X29_Y5_N5
--operation mode is normal
 
BB1_r32_o_24_lut_out = AB1_r32_o_22;
BB1_r32_o_24 = DFFEAS(BB1_r32_o_24_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un50_hilo_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add0 at LC_X10_Y5_N4
--operation mode is arithmetic
 
VD1_un50_hilo_add0 = VD1_hilo[32] $ VD1_op2_reged[0];
 
--VD1_un50_hilo_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_0 at LC_X10_Y5_N4
--operation mode is arithmetic
 
VD1_un50_hilo_carry_0 = CARRY(VD1_hilo[32] & VD1_op2_reged[0]);
 
 
--VD1_hilo_33_i_m_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[48] at LC_X3_Y5_N7
--operation mode is normal
 
VD1_hilo_33_i_m_a[48] = VD1_addnop2 & !VD1_un50_hilo_add16 # !VD1_addnop2 & !VD1_un59_hilo_add16;
 
 
--VD1_hilo_24_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add16 at LC_X8_Y3_N0
--operation mode is arithmetic
 
VD1_hilo_24_add16_carry_eqn = VD1_hilo_24_carry_15;
VD1_hilo_24_add16 = VD1_hilo_47 $ VD1_un1_op2_reged_1_combout[16] $ !VD1_hilo_24_add16_carry_eqn;
 
--VD1_hilo_24_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_16 at LC_X8_Y3_N0
--operation mode is arithmetic
 
VD1_hilo_24_carry_16_cout_0 = VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] # !VD1_hilo_24_carry_15 # !VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] & !VD1_hilo_24_carry_15;
VD1_hilo_24_carry_16 = CARRY(VD1_hilo_24_carry_16_cout_0);
 
--VD1L605 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_16~COUT1_1 at LC_X8_Y3_N0
--operation mode is arithmetic
 
VD1L605_cout_1 = VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] # !VD1_hilo_24_carry_15 # !VD1_hilo_47 & VD1_un1_op2_reged_1_combout[16] & !VD1_hilo_24_carry_15;
VD1L605 = CARRY(VD1L605_cout_1);
 
 
--VD1_hilo_22_a[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[48] at LC_X3_Y4_N3
--operation mode is normal
 
VD1_hilo_22_a[48] = VD1_sign & !VD1_hilo_49 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add17 # !VD1_hilo[0] & !VD1_hilo_49;
 
 
--VD1_hilo_15_2[48] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[48] at LC_X3_Y4_N7
--operation mode is normal
 
VD1_hilo_15_2[48] = VD1_sub_or_yn & VD1_un59_hilo_add17 # !VD1_sub_or_yn & VD1_un50_hilo_add17;
 
 
--KB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_16 at LC_X28_Y5_N7
--operation mode is normal
 
KB1_r32_o_16_lut_out = DD1_pc_next_0_iv_1_16 # DD1_un1_pc_next46_0 & DD1_un1_pc_add16;
KB1_r32_o_16 = DFFEAS(KB1_r32_o_16_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_17 at LC_X22_Y5_N3
--operation mode is normal
 
KB1_r32_o_17_lut_out = DD1_pc_next_0_iv_1_17 # DD1_un1_pc_next46_0 & DD1_un1_pc_add17;
KB1_r32_o_17 = DFFEAS(KB1_r32_o_17_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d_a[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[16] at LC_X25_Y4_N7
--operation mode is normal
 
PD1_a_o_3_d_a[16] = PD1_a_o_sn_m2 & !PB1_r32_o_16 # !PD1_a_o_sn_m2 & !AB1_r32_o_14;
 
 
--VD1_hilo_33_i_m_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[49] at LC_X3_Y4_N2
--operation mode is normal
 
VD1_hilo_33_i_m_a[49] = VD1_addnop2 & !VD1_un50_hilo_add17 # !VD1_addnop2 & !VD1_un59_hilo_add17;
 
 
--VD1_hilo_24_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add17 at LC_X8_Y3_N1
--operation mode is arithmetic
 
VD1_hilo_24_add17_carry_eqn = (!VD1_hilo_24_carry_15 & VD1_hilo_24_carry_16) # (VD1_hilo_24_carry_15 & VD1L605);
VD1_hilo_24_add17 = VD1_un1_op2_reged_1_combout[17] $ VD1_hilo_48 $ VD1_hilo_24_add17_carry_eqn;
 
--VD1_hilo_24_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_17 at LC_X8_Y3_N1
--operation mode is arithmetic
 
VD1_hilo_24_carry_17_cout_0 = VD1_un1_op2_reged_1_combout[17] & !VD1_hilo_48 & !VD1_hilo_24_carry_16 # !VD1_un1_op2_reged_1_combout[17] & !VD1_hilo_24_carry_16 # !VD1_hilo_48;
VD1_hilo_24_carry_17 = CARRY(VD1_hilo_24_carry_17_cout_0);
 
--VD1L805 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_17~COUT1_1 at LC_X8_Y3_N1
--operation mode is arithmetic
 
VD1L805_cout_1 = VD1_un1_op2_reged_1_combout[17] & !VD1_hilo_48 & !VD1L605 # !VD1_un1_op2_reged_1_combout[17] & !VD1L605 # !VD1_hilo_48;
VD1L805 = CARRY(VD1L805_cout_1);
 
 
--VD1_hilo_22_a[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[49] at LC_X7_Y4_N5
--operation mode is normal
 
VD1_hilo_22_a[49] = VD1_sign & !VD1_hilo_50 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add18 # !VD1_hilo[0] & !VD1_hilo_50;
 
 
--VD1_hilo_15_2[49] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[49] at LC_X7_Y4_N9
--operation mode is normal
 
VD1_hilo_15_2[49] = VD1_sub_or_yn & VD1_un59_hilo_add18 # !VD1_sub_or_yn & VD1_un50_hilo_add18;
 
 
--PD1_a_o_3_d_a[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[17] at LC_X22_Y5_N0
--operation mode is normal
 
PD1_a_o_3_d_a[17] = PD1_a_o_sn_m2 & !PB1_r32_o_17 # !PD1_a_o_sn_m2 & !AB1_r32_o_15;
 
 
--VD1_un134_hilo_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[12] at LC_X5_Y16_N8
--operation mode is arithmetic
 
VD1_un134_hilo_combout[12]_carry_eqn = (!VD1_un134_hilo_cout[4] & VD1_un134_hilo_cout[10]) # (VD1_un134_hilo_cout[4] & VD1L7691);
VD1_un134_hilo_combout[12] = VD1_hilo_12 $ !VD1_un134_hilo_combout[12]_carry_eqn;
 
--VD1_un134_hilo_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[12] at LC_X5_Y16_N8
--operation mode is arithmetic
 
VD1_un134_hilo_cout[12]_cout_0 = VD1_hilo_13 & VD1_hilo_12 & !VD1_un134_hilo_cout[10];
VD1_un134_hilo_cout[12] = CARRY(VD1_un134_hilo_cout[12]_cout_0);
 
--VD1L1791 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[12]~COUT1_18 at LC_X5_Y16_N8
--operation mode is arithmetic
 
VD1L1791_cout_1 = VD1_hilo_13 & VD1_hilo_12 & !VD1L7691;
VD1L1791 = CARRY(VD1L1791_cout_1);
 
 
--VD1_hilo_33_i_m_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[46] at LC_X4_Y4_N3
--operation mode is normal
 
VD1_hilo_33_i_m_a[46] = VD1_addnop2 & !VD1_un50_hilo_add14 # !VD1_addnop2 & !VD1_un59_hilo_add14;
 
 
--VD1_hilo_24_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add14 at LC_X8_Y4_N8
--operation mode is arithmetic
 
VD1_hilo_24_add14_carry_eqn = (!VD1_hilo_24_carry_10 & VD1_hilo_24_carry_13) # (VD1_hilo_24_carry_10 & VD1L105);
VD1_hilo_24_add14 = VD1_hilo_45 $ VD1_un1_op2_reged_1_combout[14] $ !VD1_hilo_24_add14_carry_eqn;
 
--VD1_hilo_24_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_14 at LC_X8_Y4_N8
--operation mode is arithmetic
 
VD1_hilo_24_carry_14_cout_0 = VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] # !VD1_hilo_24_carry_13 # !VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] & !VD1_hilo_24_carry_13;
VD1_hilo_24_carry_14 = CARRY(VD1_hilo_24_carry_14_cout_0);
 
--VD1L305 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_14~COUT1_1 at LC_X8_Y4_N8
--operation mode is arithmetic
 
VD1L305_cout_1 = VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] # !VD1L105 # !VD1_hilo_45 & VD1_un1_op2_reged_1_combout[14] & !VD1L105;
VD1L305 = CARRY(VD1L305_cout_1);
 
 
--VD1_hilo_22_a[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[46] at LC_X3_Y5_N5
--operation mode is normal
 
VD1_hilo_22_a[46] = VD1_sign & !VD1_hilo_47 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add15 # !VD1_hilo[0] & !VD1_hilo_47;
 
 
--VD1_hilo_15_2[46] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[46] at LC_X3_Y5_N4
--operation mode is normal
 
VD1_hilo_15_2[46] = VD1_sub_or_yn & VD1_un59_hilo_add15 # !VD1_sub_or_yn & VD1_un50_hilo_add15;
 
 
--KB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_14 at LC_X25_Y11_N7
--operation mode is normal
 
KB1_r32_o_14_lut_out = DD1_pc_next_0_iv_1_14 # DD1_un1_pc_next46_0 & DD1_un1_pc_add14;
KB1_r32_o_14 = DFFEAS(KB1_r32_o_14_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_15 at LC_X19_Y6_N9
--operation mode is normal
 
KB1_r32_o_15_lut_out = DD1_pc_next_0_iv_1_15 # DD1_un1_pc_next46_0 & DD1_un1_pc_add15;
KB1_r32_o_15 = DFFEAS(KB1_r32_o_15_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RD1_r32_o_0_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_12 at LC_X21_Y4_N8
--operation mode is arithmetic
 
RD1_r32_o_0_12_carry_eqn = (!RD1_r32_o_cout[4] & RD1_r32_o_cout[10]) # (RD1_r32_o_cout[4] & RD1L97);
RD1_r32_o_0_12_lut_out = KB1_r32_o_12 $ RD1_r32_o_0_12_carry_eqn;
RD1_r32_o_0_12 = DFFEAS(RD1_r32_o_0_12_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[12] at LC_X21_Y4_N8
--operation mode is arithmetic
 
RD1_r32_o_cout[12]_cout_0 = !RD1_r32_o_cout[10] # !KB1_r32_o_12 # !KB1_r32_o_13;
RD1_r32_o_cout[12] = CARRY(RD1_r32_o_cout[12]_cout_0);
 
--RD1L38 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[12]~COUT1_4 at LC_X21_Y4_N8
--operation mode is arithmetic
 
RD1L38_cout_1 = !RD1L97 # !KB1_r32_o_12 # !KB1_r32_o_13;
RD1L38 = CARRY(RD1L38_cout_1);
 
 
--PD1_a_o_3_d_a[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[14] at LC_X25_Y11_N1
--operation mode is normal
 
PD1_a_o_3_d_a[14] = PD1_a_o_sn_m2 & !PB1_r32_o_14 # !PD1_a_o_sn_m2 & !AB1_r32_o_12;
 
 
--VD1_hilo_33_i_m_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[47] at LC_X3_Y5_N2
--operation mode is normal
 
VD1_hilo_33_i_m_a[47] = VD1_addnop2 & !VD1_un50_hilo_add15 # !VD1_addnop2 & !VD1_un59_hilo_add15;
 
 
--VD1_hilo_24_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add15 at LC_X8_Y4_N9
--operation mode is arithmetic
 
VD1_hilo_24_add15_carry_eqn = (!VD1_hilo_24_carry_10 & VD1_hilo_24_carry_14) # (VD1_hilo_24_carry_10 & VD1L305);
VD1_hilo_24_add15 = VD1_hilo_46 $ VD1_un1_op2_reged_1_combout[15] $ VD1_hilo_24_add15_carry_eqn;
 
--VD1_hilo_24_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_15 at LC_X8_Y4_N9
--operation mode is arithmetic
 
VD1_hilo_24_carry_15 = CARRY(VD1_hilo_46 & !VD1_un1_op2_reged_1_combout[15] & !VD1L305 # !VD1_hilo_46 & !VD1L305 # !VD1_un1_op2_reged_1_combout[15]);
 
 
--VD1_hilo_22_a[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[47] at LC_X3_Y5_N3
--operation mode is normal
 
VD1_hilo_22_a[47] = VD1_hilo[0] & VD1_sign & !VD1_hilo_48 # !VD1_sign & !VD1_un59_hilo_add16 # !VD1_hilo[0] & !VD1_hilo_48;
 
 
--VD1_hilo_15_2[47] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[47] at LC_X3_Y5_N8
--operation mode is normal
 
VD1_hilo_15_2[47] = VD1_sub_or_yn & VD1_un59_hilo_add16 # !VD1_sub_or_yn & VD1_un50_hilo_add16;
 
 
--PD1_a_o_3_d_a[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[15] at LC_X19_Y6_N1
--operation mode is normal
 
PD1_a_o_3_d_a[15] = PD1_a_o_sn_m2 & !PB1_r32_o_15 # !PD1_a_o_sn_m2 & !AB1_r32_o_13;
 
 
--UD1_shift_out_52_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[31] at LC_X16_Y18_N3
--operation mode is normal
 
UD1_shift_out_52_a[31] = PD1_a_o_0 & PD1_a_o_1 & !VD1_b_o_iv_12 # !PD1_a_o_0 & !VD1_b_o_iv_13 # !PD1_a_o_1;
 
 
--VD1_un59_hilo_add0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add0 at LC_X9_Y6_N4
--operation mode is arithmetic
 
VD1_un59_hilo_add0 = VD1_op2_reged[0] $ VD1_hilo[32];
 
--VD1_un59_hilo_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_0 at LC_X9_Y6_N4
--operation mode is arithmetic
 
VD1_un59_hilo_carry_0 = CARRY(VD1_op2_reged[0] & VD1_hilo[32]);
 
 
--VD1_hilo_37_iv_0_1_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[31] at LC_X6_Y13_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[31] = VD1_hilo[32] & !VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_un134_hilo_combout[31] # !VD1_hilo_37_iv_0_a3_0[0] # !VD1_hilo[32] & !VD1_un134_hilo_combout[31] # !VD1_hilo_37_iv_0_a3_0[0];
 
 
--VD1_hilo_22_i_m_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_i_m_a[63] at LC_X7_Y9_N7
--operation mode is normal
 
VD1_hilo_22_i_m_a[63] = VD1_hilo[0] & !VD1_un59_hilo_add32 # !VD1_hilo[0] & !VD1_hilo[64];
 
 
--VD1_hilo_33_3_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_3_a[63] at LC_X8_Y8_N1
--operation mode is normal
 
VD1_hilo_33_3_a[63] = VD1_hilo_33_1[64] & !VD1_un59_hilo_add31 # !VD1_hilo_33_1[64] & !VD1_hilo_63;
 
 
--UD1_shift_out_80_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[8] at LC_X11_Y17_N8
--operation mode is normal
 
UD1_shift_out_80_a[8] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_11 # !PD1_a_o_1 & !VD1_b_o_iv_9;
 
 
--UD1_shift_out_45_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_45_a[28] at LC_X14_Y18_N7
--operation mode is normal
 
UD1_shift_out_45_a[28] = PD1_a_o_0 & PD1_a_o_1 & !VD1_b_o_iv_1 # !PD1_a_o_0 & !VD1_b_o_iv_2 # !PD1_a_o_1;
 
 
--RD1_r32_o_0_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_8 at LC_X21_Y4_N6
--operation mode is arithmetic
 
RD1_r32_o_0_8_carry_eqn = (!RD1_r32_o_cout[4] & RD1_r32_o_cout[6]) # (RD1_r32_o_cout[4] & RD1L17);
RD1_r32_o_0_8_lut_out = KB1_r32_o_8 $ RD1_r32_o_0_8_carry_eqn;
RD1_r32_o_0_8 = DFFEAS(RD1_r32_o_0_8_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[8] at LC_X21_Y4_N6
--operation mode is arithmetic
 
RD1_r32_o_cout[8]_cout_0 = !RD1_r32_o_cout[6] # !KB1_r32_o_8 # !KB1_r32_o_9;
RD1_r32_o_cout[8] = CARRY(RD1_r32_o_cout[8]_cout_0);
 
--RD1L57 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[8]~COUT1_2 at LC_X21_Y4_N6
--operation mode is arithmetic
 
RD1L57_cout_1 = !RD1L17 # !KB1_r32_o_8 # !KB1_r32_o_9;
RD1L57 = CARRY(RD1L57_cout_1);
 
 
--PD1_a_o_3_d[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[8] at LC_X19_Y8_N0
--operation mode is normal
 
PD1_a_o_3_d[8] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_8 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[8] # !PD1_un6_a_o & !PD1_a_o_3_d_a[8];
 
 
--UD1_shift_out_80_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[9] at LC_X12_Y18_N8
--operation mode is normal
 
UD1_shift_out_80_a[9] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_12 # !PD1_a_o_1 & !VD1_b_o_iv_10;
 
 
--VD1_un134_hilo_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[9] at LC_X4_Y16_N6
--operation mode is arithmetic
 
VD1_un134_hilo_combout[9]_carry_eqn = (!VD1_un134_hilo_cout[5] & VD1_un134_hilo_cout[7]) # (VD1_un134_hilo_cout[5] & VD1L1691);
VD1_un134_hilo_combout[9] = VD1_hilo_9 $ (VD1_hilo_8 & !VD1_un134_hilo_combout[9]_carry_eqn);
 
--VD1_un134_hilo_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[9] at LC_X4_Y16_N6
--operation mode is arithmetic
 
VD1_un134_hilo_cout[9]_cout_0 = VD1_hilo_9 & VD1_hilo_8 & !VD1_un134_hilo_cout[7];
VD1_un134_hilo_cout[9] = CARRY(VD1_un134_hilo_cout[9]_cout_0);
 
--VD1L5691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[9]~COUT1_4 at LC_X4_Y16_N6
--operation mode is arithmetic
 
VD1L5691_cout_1 = VD1_hilo_9 & VD1_hilo_8 & !VD1L1691;
VD1L5691 = CARRY(VD1L5691_cout_1);
 
 
--VD1_hilo_33_i_m[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[41] at LC_X7_Y8_N2
--operation mode is normal
 
VD1_hilo_33_i_m[41] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[41] # !VD1_hilo_33_1[64] & !VD1_hilo_41;
 
 
--VD1_hilo_37_iv_2_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[41] at LC_X7_Y8_N8
--operation mode is normal
 
VD1_hilo_37_iv_2_a[41] = VD1_hilo_9 & !VD1_hilo_24_add9 & VD1_hilo_2_sqmuxa # !VD1_hilo_9 & VD1_hilo_0_sqmuxa # !VD1_hilo_24_add9 & VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_22_Z[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[41] at LC_X7_Y8_N6
--operation mode is normal
 
VD1_hilo_22_Z[41] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[41] # !VD1_sign & !VD1_hilo_22_a[41] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[41];
 
 
--RD1_r32_o_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_9 at LC_X23_Y4_N6
--operation mode is arithmetic
 
RD1_r32_o_9_carry_eqn = (!RD1_r32_o_cout[5] & RD1_r32_o_cout[7]) # (RD1_r32_o_cout[5] & RD1L37);
RD1_r32_o_9_lut_out = KB1_r32_o_9 $ (KB1_r32_o_8 & RD1_r32_o_9_carry_eqn);
RD1_r32_o_9 = DFFEAS(RD1_r32_o_9_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[9] at LC_X23_Y4_N6
--operation mode is arithmetic
 
RD1_r32_o_cout[9]_cout_0 = !RD1_r32_o_cout[7] # !KB1_r32_o_8 # !KB1_r32_o_9;
RD1_r32_o_cout[9] = CARRY(RD1_r32_o_cout[9]_cout_0);
 
--RD1L77 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[9]~COUT1_13 at LC_X23_Y4_N6
--operation mode is arithmetic
 
RD1L77_cout_1 = !RD1L37 # !KB1_r32_o_8 # !KB1_r32_o_9;
RD1L77 = CARRY(RD1L77_cout_1);
 
 
--PD1_a_o_3_d[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[9] at LC_X19_Y10_N2
--operation mode is normal
 
PD1_a_o_3_d[9] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_9 # !PD1_un6_a_o & !PD1_a_o_3_d_a[9] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[9];
 
 
--VD1_un134_hilo_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[10] at LC_X5_Y16_N7
--operation mode is arithmetic
 
VD1_un134_hilo_combout[10]_carry_eqn = (!VD1_un134_hilo_cout[4] & VD1_un134_hilo_cout[8]) # (VD1_un134_hilo_cout[4] & VD1L3691);
VD1_un134_hilo_combout[10] = VD1_hilo_10 $ (VD1_un134_hilo_combout[10]_carry_eqn);
 
--VD1_un134_hilo_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[10] at LC_X5_Y16_N7
--operation mode is arithmetic
 
VD1_un134_hilo_cout[10]_cout_0 = !VD1_un134_hilo_cout[8] # !VD1_hilo_11 # !VD1_hilo_10;
VD1_un134_hilo_cout[10] = CARRY(VD1_un134_hilo_cout[10]_cout_0);
 
--VD1L7691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[10]~COUT1_17 at LC_X5_Y16_N7
--operation mode is arithmetic
 
VD1L7691_cout_1 = !VD1L3691 # !VD1_hilo_11 # !VD1_hilo_10;
VD1L7691 = CARRY(VD1L7691_cout_1);
 
 
--VD1_hilo_33_i_m[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[42] at LC_X7_Y8_N0
--operation mode is normal
 
VD1_hilo_33_i_m[42] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[42] # !VD1_hilo_33_1[64] & !VD1_hilo_42;
 
 
--VD1_hilo_37_iv_2_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[42] at LC_X7_Y13_N5
--operation mode is normal
 
VD1_hilo_37_iv_2_a[42] = VD1_hilo_10 & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add10 # !VD1_hilo_10 & VD1_hilo_0_sqmuxa # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add10;
 
 
--VD1_hilo_22_Z[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[42] at LC_X7_Y6_N9
--operation mode is normal
 
VD1_hilo_22_Z[42] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[42] # !VD1_sign & !VD1_hilo_22_a[42] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[42];
 
 
--PD1_a_o_3_d_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[10] at LC_X19_Y12_N6
--operation mode is normal
 
PD1_a_o_3_d_a[10] = PD1_a_o_sn_m2 & !PB1_r32_o_10 # !PD1_a_o_sn_m2 & !AB1_r32_o_8;
 
 
--UD1_shift_out_87_d_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_87_d_a[10] at LC_X16_Y18_N2
--operation mode is normal
 
UD1_shift_out_87_d_a[10] = PD1_a_o_1 & !VD1_b_o_iv_16 # !PD1_a_o_1 & !VD1_b_o_iv_14;
 
 
--UD1_shift_out_80[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80[10] at LC_X16_Y18_N7
--operation mode is normal
 
UD1_shift_out_80[10] = PD1_a_o_2 & UD1_shift_out_80_a[10] & VD1_b_o_iv_15 # !UD1_shift_out_80_a[10] & VD1_b_o_iv_17 # !PD1_a_o_2 & !UD1_shift_out_80_a[10];
 
 
--UD1_shift_out_76_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_76_a[10] at LC_X14_Y17_N4
--operation mode is normal
 
UD1_shift_out_76_a[10] = !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out587 & !PD1_a_o_3;
 
 
--UD1_shift_out_77_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[10] at LC_X14_Y18_N0
--operation mode is normal
 
UD1_shift_out_77_a[10] = PD1_a_o_0 & !VD1_b_o_iv_1 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_2;
 
 
--UD1_shift_out_74[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[10] at LC_X19_Y16_N9
--operation mode is normal
 
UD1_shift_out_74[10] = PD1_a_o_3 & !UD1_shift_out_74_a[7] # !PD1_a_o_3 & UD1_shift_out_74_a[7] & UD1_shift_out_79[18] # !UD1_shift_out_74_a[7] & UD1_shift_out_41[2];
 
 
--UD1_shift_out_86_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86_a[10] at LC_X19_Y16_N0
--operation mode is normal
 
UD1_shift_out_86_a[10] = UD1_shift_out587 & PD1_a_o_2 & !UD1_shift_out_47[2] # !PD1_a_o_2 & !UD1_shift_out_79[18] # !UD1_shift_out587 & !UD1_shift_out_47[2];
 
 
--UD1_shift_out_80_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[11] at LC_X13_Y18_N3
--operation mode is normal
 
UD1_shift_out_80_a[11] = PD1_a_o_1 & !VD1_b_o_iv_14 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_12;
 
 
--VD1_un134_hilo_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[11] at LC_X4_Y16_N7
--operation mode is arithmetic
 
VD1_un134_hilo_combout[11]_carry_eqn = (!VD1_un134_hilo_cout[5] & VD1_un134_hilo_cout[9]) # (VD1_un134_hilo_cout[5] & VD1L5691);
VD1_un134_hilo_combout[11] = VD1_hilo_11 $ (VD1_hilo_10 & VD1_un134_hilo_combout[11]_carry_eqn);
 
--VD1_un134_hilo_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[11] at LC_X4_Y16_N7
--operation mode is arithmetic
 
VD1_un134_hilo_cout[11]_cout_0 = !VD1_un134_hilo_cout[9] # !VD1_hilo_10 # !VD1_hilo_11;
VD1_un134_hilo_cout[11] = CARRY(VD1_un134_hilo_cout[11]_cout_0);
 
--VD1L9691 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[11]~COUT1_5 at LC_X4_Y16_N7
--operation mode is arithmetic
 
VD1L9691_cout_1 = !VD1L5691 # !VD1_hilo_10 # !VD1_hilo_11;
VD1L9691 = CARRY(VD1L9691_cout_1);
 
 
--VD1_hilo_33_i_m[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[43] at LC_X7_Y6_N2
--operation mode is normal
 
VD1_hilo_33_i_m[43] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[43] # !VD1_hilo_33_1[64] & !VD1_hilo_43;
 
 
--VD1_hilo_37_iv_2_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[43] at LC_X7_Y6_N5
--operation mode is normal
 
VD1_hilo_37_iv_2_a[43] = VD1_hilo_11 & !VD1_hilo_24_add11 & VD1_hilo_2_sqmuxa # !VD1_hilo_11 & VD1_hilo_0_sqmuxa # !VD1_hilo_24_add11 & VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_22_Z[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[43] at LC_X7_Y6_N6
--operation mode is normal
 
VD1_hilo_22_Z[43] = VD1_hilo_15_1[56] & VD1_sign & VD1_hilo_15_2[43] # !VD1_sign & !VD1_hilo_22_a[43] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[43];
 
 
--RD1_r32_o_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_11 at LC_X23_Y4_N7
--operation mode is arithmetic
 
RD1_r32_o_11_carry_eqn = (!RD1_r32_o_cout[5] & RD1_r32_o_cout[9]) # (RD1_r32_o_cout[5] & RD1L77);
RD1_r32_o_11_lut_out = KB1_r32_o_11 $ (KB1_r32_o_10 & !RD1_r32_o_11_carry_eqn);
RD1_r32_o_11 = DFFEAS(RD1_r32_o_11_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[11] at LC_X23_Y4_N7
--operation mode is arithmetic
 
RD1_r32_o_cout[11]_cout_0 = KB1_r32_o_11 & KB1_r32_o_10 & !RD1_r32_o_cout[9];
RD1_r32_o_cout[11] = CARRY(RD1_r32_o_cout[11]_cout_0);
 
--RD1L18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[11]~COUT1_14 at LC_X23_Y4_N7
--operation mode is arithmetic
 
RD1L18_cout_1 = KB1_r32_o_11 & KB1_r32_o_10 & !RD1L77;
RD1L18 = CARRY(RD1L18_cout_1);
 
 
--PD1_a_o_3_d[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[11] at LC_X22_Y10_N2
--operation mode is normal
 
PD1_a_o_3_d[11] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_11 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[11] # !PD1_un6_a_o & !PD1_a_o_3_d_a[11];
 
 
--VD1_un134_hilo_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[19] at LC_X4_Y15_N1
--operation mode is arithmetic
 
VD1_un134_hilo_combout[19]_carry_eqn = (!VD1_un134_hilo_cout[15] & VD1_un134_hilo_cout[17]) # (VD1_un134_hilo_cout[15] & VD1L9791);
VD1_un134_hilo_combout[19] = VD1_hilo_19 $ (VD1_hilo_18 & VD1_un134_hilo_combout[19]_carry_eqn);
 
--VD1_un134_hilo_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[19] at LC_X4_Y15_N1
--operation mode is arithmetic
 
VD1_un134_hilo_cout[19]_cout_0 = !VD1_un134_hilo_cout[17] # !VD1_hilo_19 # !VD1_hilo_18;
VD1_un134_hilo_cout[19] = CARRY(VD1_un134_hilo_cout[19]_cout_0);
 
--VD1L3891 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[19]~COUT1_8 at LC_X4_Y15_N1
--operation mode is arithmetic
 
VD1L3891_cout_1 = !VD1L9791 # !VD1_hilo_19 # !VD1_hilo_18;
VD1L3891 = CARRY(VD1L3891_cout_1);
 
 
--VD1_hilo_33_i_m_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[53] at LC_X6_Y4_N4
--operation mode is normal
 
VD1_hilo_33_i_m_a[53] = VD1_addnop2 & !VD1_un50_hilo_add21 # !VD1_addnop2 & !VD1_un59_hilo_add21;
 
 
--VD1_hilo_24_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add21 at LC_X8_Y3_N5
--operation mode is arithmetic
 
VD1_hilo_24_add21_carry_eqn = VD1_hilo_24_carry_20;
VD1_hilo_24_add21 = VD1_hilo_52 $ VD1_un1_op2_reged_1_combout[21] $ VD1_hilo_24_add21_carry_eqn;
 
--VD1_hilo_24_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_21 at LC_X8_Y3_N5
--operation mode is arithmetic
 
VD1_hilo_24_carry_21_cout_0 = VD1_hilo_52 & !VD1_un1_op2_reged_1_combout[21] & !VD1_hilo_24_carry_20 # !VD1_hilo_52 & !VD1_hilo_24_carry_20 # !VD1_un1_op2_reged_1_combout[21];
VD1_hilo_24_carry_21 = CARRY(VD1_hilo_24_carry_21_cout_0);
 
--VD1L515 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_21~COUT1_1 at LC_X8_Y3_N5
--operation mode is arithmetic
 
VD1L515_cout_1 = VD1_hilo_52 & !VD1_un1_op2_reged_1_combout[21] & !VD1_hilo_24_carry_20 # !VD1_hilo_52 & !VD1_hilo_24_carry_20 # !VD1_un1_op2_reged_1_combout[21];
VD1L515 = CARRY(VD1L515_cout_1);
 
 
--VD1_hilo_22_a[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[53] at LC_X7_Y4_N3
--operation mode is normal
 
VD1_hilo_22_a[53] = VD1_sign & !VD1_hilo_54 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add22 # !VD1_hilo[0] & !VD1_hilo_54;
 
 
--VD1_hilo_15_2[53] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[53] at LC_X7_Y4_N1
--operation mode is normal
 
VD1_hilo_15_2[53] = VD1_sub_or_yn & VD1_un59_hilo_add22 # !VD1_sub_or_yn & VD1_un50_hilo_add22;
 
 
--KB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_20 at LC_X22_Y13_N7
--operation mode is normal
 
KB1_r32_o_20_lut_out = DD1_pc_next_0_iv_1_20 # DD1_un1_pc_next46_0 & DD1_un1_pc_add20;
KB1_r32_o_20 = DFFEAS(KB1_r32_o_20_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_21 at LC_X22_Y9_N4
--operation mode is normal
 
KB1_r32_o_21_lut_out = DD1_pc_next_0_iv_1_21 # DD1_un1_pc_next46_0 & DD1_un1_pc_add21;
KB1_r32_o_21 = DFFEAS(KB1_r32_o_21_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--RD1_r32_o_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_19 at LC_X23_Y3_N1
--operation mode is arithmetic
 
RD1_r32_o_19_carry_eqn = (!RD1_r32_o_cout[15] & RD1_r32_o_cout[17]) # (RD1_r32_o_cout[15] & RD1L19);
RD1_r32_o_19_lut_out = KB1_r32_o_19 $ (KB1_r32_o_18 & !RD1_r32_o_19_carry_eqn);
RD1_r32_o_19 = DFFEAS(RD1_r32_o_19_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[19] at LC_X23_Y3_N1
--operation mode is arithmetic
 
RD1_r32_o_cout[19]_cout_0 = KB1_r32_o_18 & KB1_r32_o_19 & !RD1_r32_o_cout[17];
RD1_r32_o_cout[19] = CARRY(RD1_r32_o_cout[19]_cout_0);
 
--RD1L59 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[19]~COUT1_17 at LC_X23_Y3_N1
--operation mode is arithmetic
 
RD1L59_cout_1 = KB1_r32_o_18 & KB1_r32_o_19 & !RD1L19;
RD1L59 = CARRY(RD1L59_cout_1);
 
 
--PD1_a_o_3_d_a[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[21] at LC_X25_Y5_N8
--operation mode is normal
 
PD1_a_o_3_d_a[21] = PD1_a_o_sn_m2 & !PB1_r32_o_21 # !PD1_a_o_sn_m2 & !AB1_r32_o_19;
 
 
--VD1_un134_hilo_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[18] at LC_X5_Y15_N1
--operation mode is arithmetic
 
VD1_un134_hilo_combout[18]_carry_eqn = (!VD1_un134_hilo_cout[14] & VD1_un134_hilo_cout[16]) # (VD1_un134_hilo_cout[14] & VD1L7791);
VD1_un134_hilo_combout[18] = VD1_hilo_18 $ VD1_un134_hilo_combout[18]_carry_eqn;
 
--VD1_un134_hilo_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[18] at LC_X5_Y15_N1
--operation mode is arithmetic
 
VD1_un134_hilo_cout[18]_cout_0 = !VD1_un134_hilo_cout[16] # !VD1_hilo_18 # !VD1_hilo_19;
VD1_un134_hilo_cout[18] = CARRY(VD1_un134_hilo_cout[18]_cout_0);
 
--VD1L1891 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[18]~COUT1_20 at LC_X5_Y15_N1
--operation mode is arithmetic
 
VD1L1891_cout_1 = !VD1L7791 # !VD1_hilo_18 # !VD1_hilo_19;
VD1L1891 = CARRY(VD1L1891_cout_1);
 
 
--VD1_un1_op2_reged_1_i_m6[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_i_m6[20] at LC_X11_Y3_N4
--operation mode is normal
 
VD1_un1_op2_reged_1_i_m6[20] = VD1_eqop2_2_32 & VD1_op2_reged[20] # !VD1_eqop2_2_32 & VD1_nop2_reged[20];
 
 
--VD1_hilo_24_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add19 at LC_X8_Y3_N3
--operation mode is arithmetic
 
VD1_hilo_24_add19_carry_eqn = (!VD1_hilo_24_carry_15 & VD1_hilo_24_carry_18) # (VD1_hilo_24_carry_15 & VD1L015);
VD1_hilo_24_add19 = VD1_hilo_50 $ VD1_un1_op2_reged_1_combout[19] $ VD1_hilo_24_add19_carry_eqn;
 
--VD1_hilo_24_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_19 at LC_X8_Y3_N3
--operation mode is arithmetic
 
VD1_hilo_24_carry_19_cout_0 = VD1_hilo_50 & !VD1_un1_op2_reged_1_combout[19] & !VD1_hilo_24_carry_18 # !VD1_hilo_50 & !VD1_hilo_24_carry_18 # !VD1_un1_op2_reged_1_combout[19];
VD1_hilo_24_carry_19 = CARRY(VD1_hilo_24_carry_19_cout_0);
 
--VD1L215 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_19~COUT1_1 at LC_X8_Y3_N3
--operation mode is arithmetic
 
VD1L215_cout_1 = VD1_hilo_50 & !VD1_un1_op2_reged_1_combout[19] & !VD1L015 # !VD1_hilo_50 & !VD1L015 # !VD1_un1_op2_reged_1_combout[19];
VD1L215 = CARRY(VD1L215_cout_1);
 
 
--VD1_un59_hilo_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add21 at LC_X9_Y4_N5
--operation mode is arithmetic
 
VD1_un59_hilo_add21_carry_eqn = VD1_un59_hilo_carry_20;
VD1_un59_hilo_add21 = VD1_hilo_53 $ VD1_op2_reged[21] $ VD1_un59_hilo_add21_carry_eqn;
 
--VD1_un59_hilo_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_21 at LC_X9_Y4_N5
--operation mode is arithmetic
 
VD1_un59_hilo_carry_21_cout_0 = VD1_hilo_53 & !VD1_op2_reged[21] & !VD1_un59_hilo_carry_20 # !VD1_hilo_53 & !VD1_un59_hilo_carry_20 # !VD1_op2_reged[21];
VD1_un59_hilo_carry_21 = CARRY(VD1_un59_hilo_carry_21_cout_0);
 
--VD1L4681 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_21~COUT1_1 at LC_X9_Y4_N5
--operation mode is arithmetic
 
VD1L4681_cout_1 = VD1_hilo_53 & !VD1_op2_reged[21] & !VD1_un59_hilo_carry_20 # !VD1_hilo_53 & !VD1_un59_hilo_carry_20 # !VD1_op2_reged[21];
VD1L4681 = CARRY(VD1L4681_cout_1);
 
 
--VD1_hilo_37_iv_0_1[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[52] at LC_X5_Y6_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_1[52] = VD1_hilo_37_iv_0_1_a[52] # !VD1_un59_hilo_add20 & VD1_addop2 & VD1_hilo_37_iv_0_a2_7[34];
 
 
--VD1_un50_hilo_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add20 at LC_X10_Y3_N4
--operation mode is arithmetic
 
VD1_un50_hilo_add20_carry_eqn = (!VD1_un50_hilo_carry_15 & VD1_un50_hilo_carry_19) # (VD1_un50_hilo_carry_15 & VD1L8371);
VD1_un50_hilo_add20 = VD1_hilo_52 $ VD1_nop2_reged[20] $ !VD1_un50_hilo_add20_carry_eqn;
 
--VD1_un50_hilo_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_20 at LC_X10_Y3_N4
--operation mode is arithmetic
 
VD1_un50_hilo_carry_20 = CARRY(VD1_hilo_52 & VD1_nop2_reged[20] # !VD1L8371 # !VD1_hilo_52 & VD1_nop2_reged[20] & !VD1L8371);
 
 
--VD1_hilo_37_iv_0_4_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_4_a[52] at LC_X6_Y8_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_4_a[52] = VD1_hilo_1_sqmuxa_1 & !VD1_un50_hilo_add21 & VD1_hilo_37_iv_0_a2_7_2_1[37] & !VD1_sub_or_yn;
 
 
--RD1_r32_o_0_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_18 at LC_X21_Y3_N1
--operation mode is arithmetic
 
RD1_r32_o_0_18_carry_eqn = (!RD1_r32_o_cout[14] & RD1_r32_o_cout[16]) # (RD1_r32_o_cout[14] & RD1L98);
RD1_r32_o_0_18_lut_out = KB1_r32_o_18 $ (!RD1_r32_o_0_18_carry_eqn);
RD1_r32_o_0_18 = DFFEAS(RD1_r32_o_0_18_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[18] at LC_X21_Y3_N1
--operation mode is arithmetic
 
RD1_r32_o_cout[18]_cout_0 = KB1_r32_o_18 & KB1_r32_o_19 & !RD1_r32_o_cout[16];
RD1_r32_o_cout[18] = CARRY(RD1_r32_o_cout[18]_cout_0);
 
--RD1L39 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[18]~COUT1_6 at LC_X21_Y3_N1
--operation mode is arithmetic
 
RD1L39_cout_1 = KB1_r32_o_18 & KB1_r32_o_19 & !RD1L98;
RD1L39 = CARRY(RD1L39_cout_1);
 
 
--PD1_a_o_3_d_a[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[20] at LC_X22_Y13_N1
--operation mode is normal
 
PD1_a_o_3_d_a[20] = PD1_a_o_sn_m2 & !PB1_r32_o_20 # !PD1_a_o_sn_m2 & !AB1_r32_o_18;
 
 
--UD1_shift_out_48_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_48_a[28] at LC_X15_Y11_N6
--operation mode is normal
 
UD1_shift_out_48_a[28] = PD1_a_o_0 & PD1_a_o_1 & !VD1_b_o_iv_5 # !PD1_a_o_0 & !VD1_b_o_iv_6 # !PD1_a_o_1;
 
 
--UD1_shift_out_80_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[19] at LC_X10_Y9_N7
--operation mode is normal
 
UD1_shift_out_80_a[19] = PD1_a_o_1 & !VD1_b_o_iv_22 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_20;
 
 
--VD1_hilo_37_iv_0_8_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8_a[51] at LC_X6_Y3_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_8_a[51] = VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add19 # !VD1_un50_hilo_add20 # !VD1_hilo_37_iv_0_a3_4[57] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add19;
 
 
--VD1_hilo_37_iv_0_6[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[51] at LC_X5_Y5_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_6[51] = VD1_hilo_37_iv_0_2[51] # VD1_hilo_37_iv_0_6_a[51] # VD1_hilo_2_sqmuxa & !VD1_hilo_24_add19;
 
 
--PD1_a_o_3_d[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[19] at LC_X22_Y6_N4
--operation mode is normal
 
PD1_a_o_3_d[19] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_19 # !PD1_un6_a_o & !PD1_a_o_3_d_a[19] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[19];
 
 
--UD1_shift_out_80_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[18] at LC_X7_Y18_N9
--operation mode is normal
 
UD1_shift_out_80_a[18] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_21 # !PD1_a_o_1 & !VD1_b_o_iv_19;
 
 
--UD1_shift_out_52_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_52_a[30] at LC_X10_Y18_N3
--operation mode is normal
 
UD1_shift_out_52_a[30] = PD1_a_o_0 & !VD1_b_o_iv_11 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_12;
 
 
--VD1_hilo_37_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_1_a[18] at LC_X3_Y16_N9
--operation mode is normal
 
VD1_hilo_37_iv_1_a[18] = VD1_hilo_19 & !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_3_sqmuxa # !VD1_hilo_29_Z[18] # !VD1_hilo_19 & !VD1_hilo_3_sqmuxa # !VD1_hilo_29_Z[18];
 
 
--VD1_un59_hilo_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add19 at LC_X9_Y4_N3
--operation mode is arithmetic
 
VD1_un59_hilo_add19_carry_eqn = (!VD1_un59_hilo_carry_15 & VD1_un59_hilo_carry_18) # (VD1_un59_hilo_carry_15 & VD1L9581);
VD1_un59_hilo_add19 = VD1_hilo_51 $ VD1_op2_reged[19] $ VD1_un59_hilo_add19_carry_eqn;
 
--VD1_un59_hilo_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_19 at LC_X9_Y4_N3
--operation mode is arithmetic
 
VD1_un59_hilo_carry_19_cout_0 = VD1_hilo_51 & !VD1_op2_reged[19] & !VD1_un59_hilo_carry_18 # !VD1_hilo_51 & !VD1_un59_hilo_carry_18 # !VD1_op2_reged[19];
VD1_un59_hilo_carry_19 = CARRY(VD1_un59_hilo_carry_19_cout_0);
 
--VD1L1681 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_19~COUT1_1 at LC_X9_Y4_N3
--operation mode is arithmetic
 
VD1L1681_cout_1 = VD1_hilo_51 & !VD1_op2_reged[19] & !VD1L9581 # !VD1_hilo_51 & !VD1L9581 # !VD1_op2_reged[19];
VD1L1681 = CARRY(VD1L1681_cout_1);
 
 
--VD1_un50_hilo_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add18 at LC_X10_Y3_N2
--operation mode is arithmetic
 
VD1_un50_hilo_add18_carry_eqn = (!VD1_un50_hilo_carry_15 & VD1_un50_hilo_carry_17) # (VD1_un50_hilo_carry_15 & VD1L4371);
VD1_un50_hilo_add18 = VD1_nop2_reged[18] $ VD1_hilo_50 $ !VD1_un50_hilo_add18_carry_eqn;
 
--VD1_un50_hilo_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_18 at LC_X10_Y3_N2
--operation mode is arithmetic
 
VD1_un50_hilo_carry_18_cout_0 = VD1_nop2_reged[18] & VD1_hilo_50 # !VD1_un50_hilo_carry_17 # !VD1_nop2_reged[18] & VD1_hilo_50 & !VD1_un50_hilo_carry_17;
VD1_un50_hilo_carry_18 = CARRY(VD1_un50_hilo_carry_18_cout_0);
 
--VD1L6371 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_18~COUT1_1 at LC_X10_Y3_N2
--operation mode is arithmetic
 
VD1L6371_cout_1 = VD1_nop2_reged[18] & VD1_hilo_50 # !VD1L4371 # !VD1_nop2_reged[18] & VD1_hilo_50 & !VD1L4371;
VD1L6371 = CARRY(VD1L6371_cout_1);
 
 
--VD1_hilo_37_iv_0_1[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[50] at LC_X6_Y3_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_1[50] = VD1_hilo_37_iv_0_1_a[50] # !VD1_hilo_33_1[64] & !VD1_hilo_50 & VD1_hilo_3_sqmuxa;
 
 
--VD1_un50_hilo_add19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add19 at LC_X10_Y3_N3
--operation mode is arithmetic
 
VD1_un50_hilo_add19_carry_eqn = (!VD1_un50_hilo_carry_15 & VD1_un50_hilo_carry_18) # (VD1_un50_hilo_carry_15 & VD1L6371);
VD1_un50_hilo_add19 = VD1_nop2_reged[19] $ VD1_hilo_51 $ VD1_un50_hilo_add19_carry_eqn;
 
--VD1_un50_hilo_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_19 at LC_X10_Y3_N3
--operation mode is arithmetic
 
VD1_un50_hilo_carry_19_cout_0 = VD1_nop2_reged[19] & !VD1_hilo_51 & !VD1_un50_hilo_carry_18 # !VD1_nop2_reged[19] & !VD1_un50_hilo_carry_18 # !VD1_hilo_51;
VD1_un50_hilo_carry_19 = CARRY(VD1_un50_hilo_carry_19_cout_0);
 
--VD1L8371 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_19~COUT1_1 at LC_X10_Y3_N3
--operation mode is arithmetic
 
VD1L8371_cout_1 = VD1_nop2_reged[19] & !VD1_hilo_51 & !VD1L6371 # !VD1_nop2_reged[19] & !VD1L6371 # !VD1_hilo_51;
VD1L8371 = CARRY(VD1L8371_cout_1);
 
 
--VD1_hilo_37_iv_0_5_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[50] at LC_X6_Y3_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_5_a[50] = VD1_hilo_50 & VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_hilo_51 # !VD1_hilo_50 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_hilo_51;
 
 
--VD1_hilo_24_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add18 at LC_X8_Y3_N2
--operation mode is arithmetic
 
VD1_hilo_24_add18_carry_eqn = (!VD1_hilo_24_carry_15 & VD1_hilo_24_carry_17) # (VD1_hilo_24_carry_15 & VD1L805);
VD1_hilo_24_add18 = VD1_hilo_49 $ VD1_un1_op2_reged_1_combout[18] $ !VD1_hilo_24_add18_carry_eqn;
 
--VD1_hilo_24_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_18 at LC_X8_Y3_N2
--operation mode is arithmetic
 
VD1_hilo_24_carry_18_cout_0 = VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] # !VD1_hilo_24_carry_17 # !VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] & !VD1_hilo_24_carry_17;
VD1_hilo_24_carry_18 = CARRY(VD1_hilo_24_carry_18_cout_0);
 
--VD1L015 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_18~COUT1_1 at LC_X8_Y3_N2
--operation mode is arithmetic
 
VD1L015_cout_1 = VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] # !VD1L805 # !VD1_hilo_49 & VD1_un1_op2_reged_1_combout[18] & !VD1L805;
VD1L015 = CARRY(VD1L015_cout_1);
 
 
--PD1_a_o_3_d[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[18] at LC_X19_Y5_N2
--operation mode is normal
 
PD1_a_o_3_d[18] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_18 # !PD1_un6_a_o & !PD1_a_o_3_d_a[18] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[18];
 
 
--UD1_shift_out_80_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[26] at LC_X8_Y15_N2
--operation mode is normal
 
UD1_shift_out_80_a[26] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_29 # !PD1_a_o_1 & !VD1_b_o_iv_27;
 
 
--UD1_shift_out_77[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[26] at LC_X10_Y18_N5
--operation mode is normal
 
UD1_shift_out_77[26] = PD1_a_o_1 & UD1_shift_out_85_d[18] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[18] # !PD1_a_o_2 & !UD1_shift_out_77_a[26];
 
 
--VD1_hilo_37_iv_0_1_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[58] at LC_X6_Y9_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[58] = VD1_hilo_37_iv_0_a3_1[62] & VD1_hilo_0_sqmuxa & !VD1_hilo_26 # !VD1_hilo_58 # !VD1_hilo_37_iv_0_a3_1[62] & VD1_hilo_0_sqmuxa & !VD1_hilo_26;
 
 
--VD1_hilo_24_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add26 at LC_X8_Y2_N0
--operation mode is arithmetic
 
VD1_hilo_24_add26_carry_eqn = VD1_hilo_24_carry_25;
VD1_hilo_24_add26 = VD1_hilo_57 $ VD1_un1_op2_reged_1_combout[26] $ !VD1_hilo_24_add26_carry_eqn;
 
--VD1_hilo_24_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_26 at LC_X8_Y2_N0
--operation mode is arithmetic
 
VD1_hilo_24_carry_26_cout_0 = VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] # !VD1_hilo_24_carry_25 # !VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] & !VD1_hilo_24_carry_25;
VD1_hilo_24_carry_26 = CARRY(VD1_hilo_24_carry_26_cout_0);
 
--VD1L425 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_26~COUT1_1 at LC_X8_Y2_N0
--operation mode is arithmetic
 
VD1L425_cout_1 = VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] # !VD1_hilo_24_carry_25 # !VD1_hilo_57 & VD1_un1_op2_reged_1_combout[26] & !VD1_hilo_24_carry_25;
VD1L425 = CARRY(VD1L425_cout_1);
 
 
--VD1_hilo_37_iv_0_o3_1_0_1_1[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1_1[58] at LC_X5_Y3_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_1_0_1_1[58] = VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add27;
 
 
--VD1_hilo_37_iv_0_o3_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_a[58] at LC_X5_Y6_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_a[58] = VD1_addnop2 & !VD1_un50_hilo_add26 & !VD1_addop2 # !VD1_addnop2 & VD1_addop2 & !VD1_un59_hilo_add26;
 
 
--RD1_r32_o_0_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_26 at LC_X21_Y3_N5
--operation mode is arithmetic
 
RD1_r32_o_0_26_carry_eqn = RD1_r32_o_cout[24];
RD1_r32_o_0_26_lut_out = KB1_r32_o_26 $ !RD1_r32_o_0_26_carry_eqn;
RD1_r32_o_0_26 = DFFEAS(RD1_r32_o_0_26_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[26] at LC_X21_Y3_N5
--operation mode is arithmetic
 
RD1_r32_o_cout[26]_cout_0 = KB1_r32_o_27 & KB1_r32_o_26 & !RD1_r32_o_cout[24];
RD1_r32_o_cout[26] = CARRY(RD1_r32_o_cout[26]_cout_0);
 
--RD1L701 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[26]~COUT1_9 at LC_X21_Y3_N5
--operation mode is arithmetic
 
RD1L701_cout_1 = KB1_r32_o_27 & KB1_r32_o_26 & !RD1_r32_o_cout[24];
RD1L701 = CARRY(RD1L701_cout_1);
 
 
--PD1_a_o_3_d[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[26] at LC_X21_Y10_N2
--operation mode is normal
 
PD1_a_o_3_d[26] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_26 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[26] # !PD1_un6_a_o & !PD1_a_o_3_d_a[26];
 
 
--UD1_shift_out_80_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[27] at LC_X11_Y7_N2
--operation mode is normal
 
UD1_shift_out_80_a[27] = PD1_a_o_2 & !UD1_shift_out_36_0 # !PD1_a_o_2 & !VD1_b_o_iv_30;
 
 
--VD1_hilo_37_iv_0_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[27] at LC_X3_Y15_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[27] = VD1_add1 & !VD1_un134_hilo_combout[27] # !VD1_add1 & !VD1_hilo_27;
 
 
--VD1_hilo_24_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add27 at LC_X8_Y2_N1
--operation mode is arithmetic
 
VD1_hilo_24_add27_carry_eqn = (!VD1_hilo_24_carry_25 & VD1_hilo_24_carry_26) # (VD1_hilo_24_carry_25 & VD1L425);
VD1_hilo_24_add27 = VD1_un1_op2_reged_1_combout[27] $ VD1_hilo_58 $ VD1_hilo_24_add27_carry_eqn;
 
--VD1_hilo_24_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_27 at LC_X8_Y2_N1
--operation mode is arithmetic
 
VD1_hilo_24_carry_27_cout_0 = VD1_un1_op2_reged_1_combout[27] & !VD1_hilo_58 & !VD1_hilo_24_carry_26 # !VD1_un1_op2_reged_1_combout[27] & !VD1_hilo_24_carry_26 # !VD1_hilo_58;
VD1_hilo_24_carry_27 = CARRY(VD1_hilo_24_carry_27_cout_0);
 
--VD1L625 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_27~COUT1_1 at LC_X8_Y2_N1
--operation mode is arithmetic
 
VD1L625_cout_1 = VD1_un1_op2_reged_1_combout[27] & !VD1_hilo_58 & !VD1L425 # !VD1_un1_op2_reged_1_combout[27] & !VD1L425 # !VD1_hilo_58;
VD1L625 = CARRY(VD1L625_cout_1);
 
 
--VD1_hilo_37_iv_0_6[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[59] at LC_X5_Y2_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_6[59] = VD1_hilo_37_iv_0_3[59] # VD1_hilo_37_iv_0_6_a[59] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add28;
 
 
--PD1_a_o_3_d[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[27] at LC_X22_Y4_N2
--operation mode is normal
 
PD1_a_o_3_d[27] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_27 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[27] # !PD1_un6_a_o & !PD1_a_o_3_d_a[27];
 
 
--PD1_a_o_3_d[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[28] at LC_X16_Y7_N7
--operation mode is normal
 
PD1_a_o_3_d[28] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_28 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[28] # !PD1_un6_a_o & !PD1_a_o_3_d_a[28];
 
 
--VD1_hilo_60 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_60 at LC_X5_Y3_N4
--operation mode is normal
 
VD1_hilo_60_lut_out = !VD1_hilo_37_iv_0_a3[57] & VD1_hilo_37_iv_0_a[60] & PD1_a_o_28 # !VD1_hilo_37_iv_0_a3_1[0];
VD1_hilo_60 = DFFEAS(VD1_hilo_60_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_505, , , !sys_rst, );
 
 
--UD1_shift_out_75_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[28] at LC_X10_Y17_N1
--operation mode is normal
 
UD1_shift_out_75_a[28] = PD1_a_o_2 & !PD1_a_o_3 & !UD1_shift_out_48[28] # !PD1_a_o_2 & PD1_a_o_3 # !UD1_shift_out_52[28];
 
 
--UD1_shift_out_77_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77_a[28] at LC_X10_Y18_N8
--operation mode is normal
 
UD1_shift_out_77_a[28] = PD1_a_o_2 & !UD1_shift_out_54[28] # !PD1_a_o_2 & !PD1_a_o_1;
 
 
--VD1_hilo_37_iv_0_6[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[61] at LC_X7_Y3_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_6[61] = VD1_hilo_37_iv_0_3[61] # VD1_hilo_37_iv_0_6_a[61] # !VD1_un50_hilo_add30 & VD1_hilo_37_iv_0_a3_4[57];
 
 
--VD1_hilo_33_i_m_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[45] at LC_X8_Y9_N4
--operation mode is normal
 
VD1_hilo_33_i_m_a[45] = VD1_addnop2 & !VD1_un50_hilo_add13 # !VD1_addnop2 & !VD1_un59_hilo_add13;
 
 
--VD1_hilo_24_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add13 at LC_X8_Y4_N7
--operation mode is arithmetic
 
VD1_hilo_24_add13_carry_eqn = (!VD1_hilo_24_carry_10 & VD1_hilo_24_carry_12) # (VD1_hilo_24_carry_10 & VD1L994);
VD1_hilo_24_add13 = VD1_un1_op2_reged_1_combout[13] $ VD1_hilo_44 $ VD1_hilo_24_add13_carry_eqn;
 
--VD1_hilo_24_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_13 at LC_X8_Y4_N7
--operation mode is arithmetic
 
VD1_hilo_24_carry_13_cout_0 = VD1_un1_op2_reged_1_combout[13] & !VD1_hilo_44 & !VD1_hilo_24_carry_12 # !VD1_un1_op2_reged_1_combout[13] & !VD1_hilo_24_carry_12 # !VD1_hilo_44;
VD1_hilo_24_carry_13 = CARRY(VD1_hilo_24_carry_13_cout_0);
 
--VD1L105 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_13~COUT1_1 at LC_X8_Y4_N7
--operation mode is arithmetic
 
VD1L105_cout_1 = VD1_un1_op2_reged_1_combout[13] & !VD1_hilo_44 & !VD1L994 # !VD1_un1_op2_reged_1_combout[13] & !VD1L994 # !VD1_hilo_44;
VD1L105 = CARRY(VD1L105_cout_1);
 
 
--VD1_hilo_22_a[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[45] at LC_X4_Y4_N5
--operation mode is normal
 
VD1_hilo_22_a[45] = VD1_hilo[0] & VD1_sign & !VD1_hilo_46 # !VD1_sign & !VD1_un59_hilo_add14 # !VD1_hilo[0] & !VD1_hilo_46;
 
 
--VD1_hilo_15_2[45] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[45] at LC_X4_Y4_N2
--operation mode is normal
 
VD1_hilo_15_2[45] = VD1_sub_or_yn & VD1_un59_hilo_add14 # !VD1_sub_or_yn & VD1_un50_hilo_add14;
 
 
--KB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_13 at LC_X24_Y9_N9
--operation mode is normal
 
KB1_r32_o_13_lut_out = DD1_pc_next_0_iv_1_13 # DD1_un1_pc_next46_0 & DD1_un1_pc_add13;
KB1_r32_o_13 = DFFEAS(KB1_r32_o_13_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d_a[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[13] at LC_X24_Y9_N0
--operation mode is normal
 
PD1_a_o_3_d_a[13] = PD1_a_o_sn_m2 & !PB1_r32_o_13 # !PD1_a_o_sn_m2 & !AB1_r32_o_11;
 
 
--VD1_hilo_37_iv_0_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[28] at LC_X3_Y17_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a[28] = VD1_hilo_1_sqmuxa_1 & !VD1_hilo_29 & !VD1_hilo_2_sqmuxa # !VD1_hilo_27 # !VD1_hilo_1_sqmuxa_1 & !VD1_hilo_2_sqmuxa # !VD1_hilo_27;
 
 
--VD1_hilo_37_iv_0_0[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[28] at LC_X3_Y17_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[28] = VD1_hilo_37_iv_0_a3_0[0] & VD1_un134_hilo_combout[28] # VD1_hilo_28 & VD1_hilo_37_iv_0_o5[0] # !VD1_hilo_37_iv_0_a3_0[0] & VD1_hilo_28 & VD1_hilo_37_iv_0_o5[0];
 
 
--VD1_un134_hilo_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[27] at LC_X4_Y15_N5
--operation mode is arithmetic
 
VD1_un134_hilo_combout[27]_carry_eqn = VD1_un134_hilo_cout[25];
VD1_un134_hilo_combout[27] = VD1_hilo_27 $ (VD1_hilo_26 & VD1_un134_hilo_combout[27]_carry_eqn);
 
--VD1_un134_hilo_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[27] at LC_X4_Y15_N5
--operation mode is arithmetic
 
VD1_un134_hilo_cout[27]_cout_0 = !VD1_un134_hilo_cout[25] # !VD1_hilo_26 # !VD1_hilo_27;
VD1_un134_hilo_cout[27] = CARRY(VD1_un134_hilo_cout[27]_cout_0);
 
--VD1L7991 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[27]~COUT1_11 at LC_X4_Y15_N5
--operation mode is arithmetic
 
VD1L7991_cout_1 = !VD1_un134_hilo_cout[25] # !VD1_hilo_26 # !VD1_hilo_27;
VD1L7991 = CARRY(VD1L7991_cout_1);
 
 
--VD1_un134_hilo_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[24] at LC_X5_Y15_N4
--operation mode is arithmetic
 
VD1_un134_hilo_combout[24]_carry_eqn = (!VD1_un134_hilo_cout[14] & VD1_un134_hilo_cout[22]) # (VD1_un134_hilo_cout[14] & VD1L9891);
VD1_un134_hilo_combout[24] = VD1_hilo_24 $ (!VD1_un134_hilo_combout[24]_carry_eqn);
 
--VD1_un134_hilo_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[24] at LC_X5_Y15_N4
--operation mode is arithmetic
 
VD1_un134_hilo_cout[24] = CARRY(VD1_hilo_24 & VD1_hilo_25 & !VD1L9891);
 
 
--PB1_dout_iv_30 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_30 at LC_X22_Y8_N9
--operation mode is normal
 
PB1_dout_iv_30 = HD1_dout_iv_1_30 # HD1_dout7_0_a2 & FD1_wb_o_30;
 
--PB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_30 at LC_X22_Y8_N9
--operation mode is normal
 
PB1_r32_o_30 = DFFEAS(PB1_dout_iv_30, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_nop2_reged[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[30] at LC_X13_Y3_N7
--operation mode is arithmetic
 
VD1_nop2_reged[30]_carry_eqn = (!VD1_nop2_reged_cout[24] & VD1_nop2_reged_cout[28]) # (VD1_nop2_reged_cout[24] & VD1L1631);
VD1_nop2_reged[30] = VD1_op2_reged[30] $ !VD1_nop2_reged[30]_carry_eqn;
 
--VD1_nop2_reged_cout[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[30] at LC_X13_Y3_N7
--operation mode is arithmetic
 
VD1_nop2_reged_cout[30]_cout_0 = VD1_op2_reged[31] # VD1_op2_reged[30] # !VD1_nop2_reged_cout[28];
VD1_nop2_reged_cout[30] = CARRY(VD1_nop2_reged_cout[30]_cout_0);
 
--VD1L5631 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[30]~COUT1_25 at LC_X13_Y3_N7
--operation mode is arithmetic
 
VD1L5631_cout_1 = VD1_op2_reged[31] # VD1_op2_reged[30] # !VD1L1631;
VD1L5631 = CARRY(VD1L5631_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[29] at LC_X11_Y2_N8
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[29] = VD1_eqop2_2_32 & VD1_op2_reged[29] # !VD1_eqop2_2_32 & VD1_nop2_reged[29];
 
 
--VD1_hilo_24_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add28 at LC_X8_Y2_N2
--operation mode is arithmetic
 
VD1_hilo_24_add28_carry_eqn = (!VD1_hilo_24_carry_25 & VD1_hilo_24_carry_27) # (VD1_hilo_24_carry_25 & VD1L625);
VD1_hilo_24_add28 = VD1_hilo_59 $ VD1_un1_op2_reged_1_combout[28] $ !VD1_hilo_24_add28_carry_eqn;
 
--VD1_hilo_24_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_28 at LC_X8_Y2_N2
--operation mode is arithmetic
 
VD1_hilo_24_carry_28_cout_0 = VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] # !VD1_hilo_24_carry_27 # !VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] & !VD1_hilo_24_carry_27;
VD1_hilo_24_carry_28 = CARRY(VD1_hilo_24_carry_28_cout_0);
 
--VD1L825 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_28~COUT1_1 at LC_X8_Y2_N2
--operation mode is arithmetic
 
VD1L825_cout_1 = VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] # !VD1L625 # !VD1_hilo_59 & VD1_un1_op2_reged_1_combout[28] & !VD1L625;
VD1L825 = CARRY(VD1L825_cout_1);
 
 
--VD1_un50_hilo_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add29 at LC_X10_Y2_N3
--operation mode is arithmetic
 
VD1_un50_hilo_add29_carry_eqn = (!VD1_un50_hilo_carry_25 & VD1_un50_hilo_carry_28) # (VD1_un50_hilo_carry_25 & VD1L4571);
VD1_un50_hilo_add29 = VD1_nop2_reged[29] $ VD1_hilo_61 $ VD1_un50_hilo_add29_carry_eqn;
 
--VD1_un50_hilo_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_29 at LC_X10_Y2_N3
--operation mode is arithmetic
 
VD1_un50_hilo_carry_29_cout_0 = VD1_nop2_reged[29] & !VD1_hilo_61 & !VD1_un50_hilo_carry_28 # !VD1_nop2_reged[29] & !VD1_un50_hilo_carry_28 # !VD1_hilo_61;
VD1_un50_hilo_carry_29 = CARRY(VD1_un50_hilo_carry_29_cout_0);
 
--VD1L6571 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_29~COUT1_1 at LC_X10_Y2_N3
--operation mode is arithmetic
 
VD1L6571_cout_1 = VD1_nop2_reged[29] & !VD1_hilo_61 & !VD1L4571 # !VD1_nop2_reged[29] & !VD1L4571 # !VD1_hilo_61;
VD1L6571 = CARRY(VD1L6571_cout_1);
 
 
--VD1_nop2_reged[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[31] at LC_X12_Y3_N7
--operation mode is normal
 
VD1_nop2_reged[31]_carry_eqn = (!VD1_nop2_reged_cout[25] & VD1_nop2_reged_cout[29]) # (VD1_nop2_reged_cout[25] & VD1L3631);
VD1_nop2_reged[31] = VD1_op2_reged[31] $ (VD1_op2_reged[30] # !VD1_nop2_reged[31]_carry_eqn);
 
 
--VD1_un59_hilo_add29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add29 at LC_X9_Y3_N3
--operation mode is arithmetic
 
VD1_un59_hilo_add29_carry_eqn = (!VD1_un59_hilo_carry_25 & VD1_un59_hilo_carry_28) # (VD1_un59_hilo_carry_25 & VD1L7781);
VD1_un59_hilo_add29 = VD1_hilo_61 $ VD1_op2_reged[29] $ VD1_un59_hilo_add29_carry_eqn;
 
--VD1_un59_hilo_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_29 at LC_X9_Y3_N3
--operation mode is arithmetic
 
VD1_un59_hilo_carry_29_cout_0 = VD1_hilo_61 & !VD1_op2_reged[29] & !VD1_un59_hilo_carry_28 # !VD1_hilo_61 & !VD1_un59_hilo_carry_28 # !VD1_op2_reged[29];
VD1_un59_hilo_carry_29 = CARRY(VD1_un59_hilo_carry_29_cout_0);
 
--VD1L9781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_29~COUT1_1 at LC_X9_Y3_N3
--operation mode is arithmetic
 
VD1L9781_cout_1 = VD1_hilo_61 & !VD1_op2_reged[29] & !VD1L7781 # !VD1_hilo_61 & !VD1L7781 # !VD1_op2_reged[29];
VD1L9781 = CARRY(VD1L9781_cout_1);
 
 
--UD1_shift_out_85_c[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_85_c[30] at LC_X6_Y17_N2
--operation mode is normal
 
UD1_shift_out_85_c[30] = PD1_a_o_1 & PD1_a_o_2 # UD1_shift_out_68[30] # !PD1_a_o_1 & VD1_b_o_iv_29 & !PD1_a_o_2;
 
 
--UD1_shift_out_80_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[12] at LC_X19_Y18_N6
--operation mode is normal
 
UD1_shift_out_80_a[12] = PD1_a_o_1 & !VD1_b_o_iv_15 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_13;
 
 
--UD1_shift_out_79_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[12] at LC_X15_Y18_N2
--operation mode is normal
 
UD1_shift_out_79_a[12] = PD1_a_o_0 & !VD1_b_o_iv_21 & !PD1_a_o_1 # !PD1_a_o_0 & PD1_a_o_1 # !VD1_b_o_iv_20;
 
 
--VD1_un50_hilo_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add13 at LC_X10_Y4_N7
--operation mode is arithmetic
 
VD1_un50_hilo_add13_carry_eqn = (!VD1_un50_hilo_carry_10 & VD1_un50_hilo_carry_12) # (VD1_un50_hilo_carry_10 & VD1L5271);
VD1_un50_hilo_add13 = VD1_nop2_reged[13] $ VD1_hilo_45 $ VD1_un50_hilo_add13_carry_eqn;
 
--VD1_un50_hilo_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_13 at LC_X10_Y4_N7
--operation mode is arithmetic
 
VD1_un50_hilo_carry_13_cout_0 = VD1_nop2_reged[13] & !VD1_hilo_45 & !VD1_un50_hilo_carry_12 # !VD1_nop2_reged[13] & !VD1_un50_hilo_carry_12 # !VD1_hilo_45;
VD1_un50_hilo_carry_13 = CARRY(VD1_un50_hilo_carry_13_cout_0);
 
--VD1L7271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_13~COUT1_1 at LC_X10_Y4_N7
--operation mode is arithmetic
 
VD1L7271_cout_1 = VD1_nop2_reged[13] & !VD1_hilo_45 & !VD1L5271 # !VD1_nop2_reged[13] & !VD1L5271 # !VD1_hilo_45;
VD1L7271 = CARRY(VD1L7271_cout_1);
 
 
--VD1_hilo_24_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add12 at LC_X8_Y4_N6
--operation mode is arithmetic
 
VD1_hilo_24_add12_carry_eqn = (!VD1_hilo_24_carry_10 & VD1_hilo_24_carry_11) # (VD1_hilo_24_carry_10 & VD1L794);
VD1_hilo_24_add12 = VD1_hilo_43 $ VD1_un1_op2_reged_1_combout[12] $ !VD1_hilo_24_add12_carry_eqn;
 
--VD1_hilo_24_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_12 at LC_X8_Y4_N6
--operation mode is arithmetic
 
VD1_hilo_24_carry_12_cout_0 = VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] # !VD1_hilo_24_carry_11 # !VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] & !VD1_hilo_24_carry_11;
VD1_hilo_24_carry_12 = CARRY(VD1_hilo_24_carry_12_cout_0);
 
--VD1L994 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_12~COUT1_1 at LC_X8_Y4_N6
--operation mode is arithmetic
 
VD1L994_cout_1 = VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] # !VD1L794 # !VD1_hilo_43 & VD1_un1_op2_reged_1_combout[12] & !VD1L794;
VD1L994 = CARRY(VD1L994_cout_1);
 
 
--VD1_hilo_37_iv_0_o3_0[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0[44] at LC_X8_Y11_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_0[44] = VD1_hilo_37_iv_0_o3_0_a[44] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add13;
 
 
--VD1_hilo_37_iv_0_2[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[44] at LC_X7_Y5_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_2[44] = VD1_hilo_37_iv_0_2_a[44] # VD1_hilo_37_iv_0_a2_0[38] # !VD1_un50_hilo_add12 & VD1_hilo_37_iv_0_a2_6_0[37];
 
 
--PD1_a_o_3_d[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[12] at LC_X23_Y12_N2
--operation mode is normal
 
PD1_a_o_3_d[12] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_12 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[12] # !PD1_un6_a_o & !PD1_a_o_3_d_a[12];
 
 
--UD1_shift_out_80_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[24] at LC_X8_Y18_N1
--operation mode is normal
 
UD1_shift_out_80_a[24] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_27 # !PD1_a_o_1 & !VD1_b_o_iv_25;
 
 
--UD1_shift_out_77[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_77[24] at LC_X9_Y17_N5
--operation mode is normal
 
UD1_shift_out_77[24] = PD1_a_o_1 & UD1_shift_out_85_d[16] # !PD1_a_o_1 & PD1_a_o_2 & UD1_shift_out_85_d[16] # !PD1_a_o_2 & !UD1_shift_out_77_a[24];
 
 
--VD1_hilo_37_iv_0[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0[24] at LC_X4_Y9_N8
--operation mode is normal
 
VD1_hilo_37_iv_0[24] = VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_25 # !VD1_hilo_37_iv_0_a[24] # !VD1_hilo_3_sqmuxa & VD1_hilo_1_sqmuxa_1 & VD1_hilo_25;
 
 
--VD1_hilo_33_i_m[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[56] at LC_X4_Y7_N4
--operation mode is normal
 
VD1_hilo_33_i_m[56] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[56] # !VD1_hilo_33_1[64] & !VD1_hilo_56;
 
 
--VD1_hilo_37_iv_2_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[56] at LC_X4_Y7_N7
--operation mode is normal
 
VD1_hilo_37_iv_2_a[56] = VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add24 # !VD1_hilo_24 # !VD1_hilo_0_sqmuxa & VD1_hilo_2_sqmuxa & !VD1_hilo_24_add24;
 
 
--VD1_hilo_22_Z[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[56] at LC_X4_Y7_N8
--operation mode is normal
 
VD1_hilo_22_Z[56] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[56] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[56] # !VD1_sign & !VD1_hilo_22_a[56];
 
 
--RD1_r32_o_0_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_24 at LC_X21_Y3_N4
--operation mode is arithmetic
 
RD1_r32_o_0_24_carry_eqn = (!RD1_r32_o_cout[14] & RD1_r32_o_cout[22]) # (RD1_r32_o_cout[14] & RD1L101);
RD1_r32_o_0_24_lut_out = KB1_r32_o_24 $ (RD1_r32_o_0_24_carry_eqn);
RD1_r32_o_0_24 = DFFEAS(RD1_r32_o_0_24_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[24] at LC_X21_Y3_N4
--operation mode is arithmetic
 
RD1_r32_o_cout[24] = CARRY(!RD1L101 # !KB1_r32_o_25 # !KB1_r32_o_24);
 
 
--PD1_a_o_3_d[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[24] at LC_X20_Y3_N2
--operation mode is normal
 
PD1_a_o_3_d[24] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_24 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[24] # !PD1_un6_a_o & !PD1_a_o_3_d_a[24];
 
 
--UD1_shift_out_80_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[25] at LC_X13_Y10_N4
--operation mode is normal
 
UD1_shift_out_80_a[25] = PD1_a_o_1 & !VD1_b_o_iv_28 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_26;
 
 
--UD1_shift_out_75_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_75_a[25] at LC_X14_Y15_N3
--operation mode is normal
 
UD1_shift_out_75_a[25] = PD1_a_o_3 & !UD1_shift_out_63[17] # !PD1_a_o_3 & !UD1_shift_out_48[29];
 
 
--VD1_un134_hilo_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[25] at LC_X4_Y15_N4
--operation mode is arithmetic
 
VD1_un134_hilo_combout[25]_carry_eqn = (!VD1_un134_hilo_cout[15] & VD1_un134_hilo_cout[23]) # (VD1_un134_hilo_cout[15] & VD1L1991);
VD1_un134_hilo_combout[25] = VD1_hilo_25 $ (VD1_hilo_24 & !VD1_un134_hilo_combout[25]_carry_eqn);
 
--VD1_un134_hilo_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[25] at LC_X4_Y15_N4
--operation mode is arithmetic
 
VD1_un134_hilo_cout[25] = CARRY(VD1_hilo_24 & VD1_hilo_25 & !VD1L1991);
 
 
--VD1_hilo_37_iv_0_5[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5[57] at LC_X4_Y6_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_5[57] = VD1_hilo_37_iv_0_2[57] # VD1_hilo_37_iv_0_5_a[57] # VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add25;
 
 
--VD1_hilo_37_iv_0_8_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_8_a[57] at LC_X4_Y6_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_8_a[57] = VD1_hilo_24_add25 & VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add26 # !VD1_hilo_24_add25 & VD1_hilo_2_sqmuxa # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add26;
 
 
--RD1_r32_o_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_25 at LC_X23_Y3_N4
--operation mode is arithmetic
 
RD1_r32_o_25_carry_eqn = (!RD1_r32_o_cout[15] & RD1_r32_o_cout[23]) # (RD1_r32_o_cout[15] & RD1L301);
RD1_r32_o_25_lut_out = KB1_r32_o_25 $ (KB1_r32_o_24 & RD1_r32_o_25_carry_eqn);
RD1_r32_o_25 = DFFEAS(RD1_r32_o_25_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[25] at LC_X23_Y3_N4
--operation mode is arithmetic
 
RD1_r32_o_cout[25] = CARRY(!RD1L301 # !KB1_r32_o_25 # !KB1_r32_o_24);
 
 
--PD1_a_o_3_d[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[25] at LC_X24_Y6_N2
--operation mode is normal
 
PD1_a_o_3_d[25] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_25 # !PD1_un6_a_o & !PD1_a_o_3_d_a[25] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[25];
 
 
--UD1_shift_out_80_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[22] at LC_X6_Y17_N5
--operation mode is normal
 
UD1_shift_out_80_a[22] = PD1_a_o_2 & !PD1_a_o_1 # !PD1_a_o_2 & PD1_a_o_1 & !VD1_b_o_iv_25 # !PD1_a_o_1 & !VD1_b_o_iv_23;
 
 
--UD1_shift_out_54_a[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[30] at LC_X20_Y17_N1
--operation mode is normal
 
UD1_shift_out_54_a[30] = PD1_a_o_0 & !VD1_b_o_iv_15 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_16;
 
 
--UD1_shift_out_79_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[22] at LC_X12_Y12_N1
--operation mode is normal
 
UD1_shift_out_79_a[22] = PD1_a_o_0 & !VD1_b_o_iv_31 # !PD1_a_o_0 & !VD1_b_o_iv_30;
 
 
--VD1_un134_hilo_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[22] at LC_X5_Y15_N3
--operation mode is arithmetic
 
VD1_un134_hilo_combout[22]_carry_eqn = (!VD1_un134_hilo_cout[14] & VD1_un134_hilo_cout[20]) # (VD1_un134_hilo_cout[14] & VD1L5891);
VD1_un134_hilo_combout[22] = VD1_hilo_22 $ VD1_un134_hilo_combout[22]_carry_eqn;
 
--VD1_un134_hilo_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[22] at LC_X5_Y15_N3
--operation mode is arithmetic
 
VD1_un134_hilo_cout[22]_cout_0 = !VD1_un134_hilo_cout[20] # !VD1_hilo_22 # !VD1_hilo_23;
VD1_un134_hilo_cout[22] = CARRY(VD1_un134_hilo_cout[22]_cout_0);
 
--VD1L9891 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[22]~COUT1_22 at LC_X5_Y15_N3
--operation mode is arithmetic
 
VD1L9891_cout_1 = !VD1L5891 # !VD1_hilo_22 # !VD1_hilo_23;
VD1L9891 = CARRY(VD1L9891_cout_1);
 
 
--VD1_hilo_37_iv_0_o5_0_0[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o5_0_0[54] at LC_X5_Y4_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_o5_0_0[54] = VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add23 # !VD1_hilo_55 # !VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add23;
 
 
--VD1_hilo_37_iv_0_0[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[54] at LC_X4_Y3_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_0[54] = VD1_hilo_22 & VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add22 # !VD1_hilo_22 & VD1_hilo_0_sqmuxa # VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add22;
 
 
--VD1_hilo_24_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add22 at LC_X8_Y3_N6
--operation mode is arithmetic
 
VD1_hilo_24_add22_carry_eqn = (!VD1_hilo_24_carry_20 & VD1_hilo_24_carry_21) # (VD1_hilo_24_carry_20 & VD1L515);
VD1_hilo_24_add22 = VD1_hilo_53 $ VD1_un1_op2_reged_1_combout[22] $ !VD1_hilo_24_add22_carry_eqn;
 
--VD1_hilo_24_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_22 at LC_X8_Y3_N6
--operation mode is arithmetic
 
VD1_hilo_24_carry_22_cout_0 = VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] # !VD1_hilo_24_carry_21 # !VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] & !VD1_hilo_24_carry_21;
VD1_hilo_24_carry_22 = CARRY(VD1_hilo_24_carry_22_cout_0);
 
--VD1L715 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_22~COUT1_1 at LC_X8_Y3_N6
--operation mode is arithmetic
 
VD1L715_cout_1 = VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] # !VD1L515 # !VD1_hilo_53 & VD1_un1_op2_reged_1_combout[22] & !VD1L515;
VD1L715 = CARRY(VD1L715_cout_1);
 
 
--VD1_hilo_37_iv_0_3_a[54] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3_a[54] at LC_X4_Y3_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_3_a[54] = VD1_hilo_37_iv_0_a3_1[62] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add22 # !VD1_hilo_54 # !VD1_hilo_37_iv_0_a3_1[62] & VD1_hilo_37_iv_0_a2_6_0[37] & !VD1_un50_hilo_add22;
 
 
--VD1_un50_hilo_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add23 at LC_X10_Y3_N7
--operation mode is arithmetic
 
VD1_un50_hilo_add23_carry_eqn = (!VD1_un50_hilo_carry_20 & VD1_un50_hilo_carry_22) # (VD1_un50_hilo_carry_20 & VD1L3471);
VD1_un50_hilo_add23 = VD1_nop2_reged[23] $ VD1_hilo_55 $ VD1_un50_hilo_add23_carry_eqn;
 
--VD1_un50_hilo_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_23 at LC_X10_Y3_N7
--operation mode is arithmetic
 
VD1_un50_hilo_carry_23_cout_0 = VD1_nop2_reged[23] & !VD1_hilo_55 & !VD1_un50_hilo_carry_22 # !VD1_nop2_reged[23] & !VD1_un50_hilo_carry_22 # !VD1_hilo_55;
VD1_un50_hilo_carry_23 = CARRY(VD1_un50_hilo_carry_23_cout_0);
 
--VD1L5471 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_23~COUT1_1 at LC_X10_Y3_N7
--operation mode is arithmetic
 
VD1L5471_cout_1 = VD1_nop2_reged[23] & !VD1_hilo_55 & !VD1L3471 # !VD1_nop2_reged[23] & !VD1L3471 # !VD1_hilo_55;
VD1L5471 = CARRY(VD1L5471_cout_1);
 
 
--RD1_r32_o_0_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_0_22 at LC_X21_Y3_N3
--operation mode is arithmetic
 
RD1_r32_o_0_22_carry_eqn = (!RD1_r32_o_cout[14] & RD1_r32_o_cout[20]) # (RD1_r32_o_cout[14] & RD1L79);
RD1_r32_o_0_22_lut_out = KB1_r32_o_22 $ (!RD1_r32_o_0_22_carry_eqn);
RD1_r32_o_0_22 = DFFEAS(RD1_r32_o_0_22_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[22] at LC_X21_Y3_N3
--operation mode is arithmetic
 
RD1_r32_o_cout[22]_cout_0 = KB1_r32_o_22 & KB1_r32_o_23 & !RD1_r32_o_cout[20];
RD1_r32_o_cout[22] = CARRY(RD1_r32_o_cout[22]_cout_0);
 
--RD1L101 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[22]~COUT1_8 at LC_X21_Y3_N3
--operation mode is arithmetic
 
RD1L101_cout_1 = KB1_r32_o_22 & KB1_r32_o_23 & !RD1L79;
RD1L101 = CARRY(RD1L101_cout_1);
 
 
--PD1_a_o_3_d[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[22] at LC_X24_Y5_N2
--operation mode is normal
 
PD1_a_o_3_d[22] = PD1_un6_a_o & PD1_a_o_sn_m2 & FD1_wb_o_22 # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[22] # !PD1_un6_a_o & !PD1_a_o_3_d_a[22];
 
 
--UD1_shift_out_80_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[23] at LC_X14_Y7_N1
--operation mode is normal
 
UD1_shift_out_80_a[23] = PD1_a_o_1 & !PD1_a_o_2 & !VD1_b_o_iv_26 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_24;
 
 
--UD1_shift_out_54_a[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_54_a[31] at LC_X20_Y17_N5
--operation mode is normal
 
UD1_shift_out_54_a[31] = PD1_a_o_0 & !VD1_b_o_iv_16 & PD1_a_o_1 # !PD1_a_o_0 & !PD1_a_o_1 # !VD1_b_o_iv_17;
 
 
--VD1_hilo_37_iv_0_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[23] at LC_X4_Y9_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_a[23] = VD1_add1 & !VD1_un134_hilo_combout[23] # !VD1_add1 & !VD1_hilo_23;
 
 
--VD1_hilo_33_i_m[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m[55] at LC_X5_Y4_N7
--operation mode is normal
 
VD1_hilo_33_i_m[55] = VD1_hilo_3_sqmuxa & VD1_hilo_33_1[64] & VD1_hilo_33_i_m_a[55] # !VD1_hilo_33_1[64] & !VD1_hilo_55;
 
 
--VD1_hilo_37_iv_2_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_2_a[55] at LC_X5_Y9_N6
--operation mode is normal
 
VD1_hilo_37_iv_2_a[55] = VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_23 # !VD1_hilo_24_add23 # !VD1_hilo_2_sqmuxa & VD1_hilo_0_sqmuxa & !VD1_hilo_23;
 
 
--VD1_hilo_22_Z[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_Z[55] at LC_X4_Y7_N5
--operation mode is normal
 
VD1_hilo_22_Z[55] = VD1_sign & VD1_hilo_15_1[56] & VD1_hilo_15_2[55] # !VD1_hilo_15_1[56] & !VD1_hilo_22_a[55] # !VD1_sign & !VD1_hilo_22_a[55];
 
 
--RD1_r32_o_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_23 at LC_X23_Y3_N3
--operation mode is arithmetic
 
RD1_r32_o_23_carry_eqn = (!RD1_r32_o_cout[15] & RD1_r32_o_cout[21]) # (RD1_r32_o_cout[15] & RD1L99);
RD1_r32_o_23_lut_out = KB1_r32_o_23 $ (KB1_r32_o_22 & !RD1_r32_o_23_carry_eqn);
RD1_r32_o_23 = DFFEAS(RD1_r32_o_23_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
--RD1_r32_o_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[23] at LC_X23_Y3_N3
--operation mode is arithmetic
 
RD1_r32_o_cout[23]_cout_0 = KB1_r32_o_22 & KB1_r32_o_23 & !RD1_r32_o_cout[21];
RD1_r32_o_cout[23] = CARRY(RD1_r32_o_cout[23]_cout_0);
 
--RD1L301 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt|r32_o_cout[23]~COUT1_19 at LC_X23_Y3_N3
--operation mode is arithmetic
 
RD1L301_cout_1 = KB1_r32_o_22 & KB1_r32_o_23 & !RD1L99;
RD1L301 = CARRY(RD1L301_cout_1);
 
 
--PD1_a_o_3_d[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d[23] at LC_X22_Y3_N6
--operation mode is normal
 
PD1_a_o_3_d[23] = PD1_a_o_sn_m2 & PD1_un6_a_o & FD1_wb_o_23 # !PD1_un6_a_o & !PD1_a_o_3_d_a[23] # !PD1_a_o_sn_m2 & !PD1_a_o_3_d_a[23];
 
 
--F1_cmd[22] is mips_sys:isys|mips_dvc:imips_dvc|cmd[22] at LC_X31_Y8_N5
--operation mode is normal
 
F1_cmd[22]_lut_out = CB1_r32_o_22;
F1_cmd[22] = DFFEAS(F1_cmd[22]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[21] is mips_sys:isys|mips_dvc:imips_dvc|cmd[21] at LC_X30_Y5_N4
--operation mode is normal
 
F1_cmd[21]_lut_out = CB1_r32_o_21;
F1_cmd[21] = DFFEAS(F1_cmd[21]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[19] is mips_sys:isys|mips_dvc:imips_dvc|cmd[19] at LC_X30_Y15_N5
--operation mode is normal
 
F1_cmd[19]_lut_out = CB1_r32_o_19;
F1_cmd[19] = DFFEAS(F1_cmd[19]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[18] is mips_sys:isys|mips_dvc:imips_dvc|cmd[18] at LC_X31_Y8_N2
--operation mode is normal
 
F1_cmd[18]_lut_out = CB1_r32_o_18;
F1_cmd[18] = DFFEAS(F1_cmd[18]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[17] is mips_sys:isys|mips_dvc:imips_dvc|cmd[17] at LC_X26_Y6_N5
--operation mode is normal
 
F1_cmd[17]_lut_out = CB1_r32_o_17;
F1_cmd[17] = DFFEAS(F1_cmd[17]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[16] is mips_sys:isys|mips_dvc:imips_dvc|cmd[16] at LC_X30_Y3_N0
--operation mode is normal
 
F1_cmd[16]_lut_out = CB1_r32_o_16;
F1_cmd[16] = DFFEAS(F1_cmd[16]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--VD1_hilo_22_a[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[32] at LC_X8_Y7_N8
--operation mode is normal
 
VD1_hilo_22_a[32] = VD1_hilo[0] & VD1_sign & !VD1_hilo_33 # !VD1_sign & !VD1_un59_hilo_add1 # !VD1_hilo[0] & !VD1_hilo_33;
 
 
--VD1_hilo_15_2[32] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[32] at LC_X8_Y7_N9
--operation mode is normal
 
VD1_hilo_15_2[32] = VD1_sub_or_yn & VD1_un59_hilo_add1 # !VD1_sub_or_yn & VD1_un50_hilo_add1;
 
 
--VD1_un1_op2_reged_1_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[31] at LC_X8_Y2_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[31] = VD1_eqop2_2_32 & VD1_op2_reged[31] # !VD1_eqop2_2_32 & VD1_nop2_reged[31];
 
 
--DD1_pc_next_0_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[30] at LC_X24_Y3_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[30] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_30 & !DD1_pc_next_1_sqmuxa_0_a4 # !KB1_r32_o_30 # !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !KB1_r32_o_30;
 
 
--DD1_un1_pc_prectl_1_0_a4[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[30] at LC_X23_Y16_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[30] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # ED1_r32_o_14 & CD1_res_7_0_0_a2_16;
 
 
--DD1_un1_pc_add29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add29 at LC_X23_Y8_N3
--operation mode is arithmetic
 
DD1_un1_pc_add29_carry_eqn = (!DD1_un1_pc_carry_25 & DD1_un1_pc_carry_28) # (DD1_un1_pc_carry_25 & DD1L152);
DD1_un1_pc_add29 = KB1_r32_o_29 $ DD1_un1_pc_prectl_1_0_a4[29] $ DD1_un1_pc_add29_carry_eqn;
 
--DD1_un1_pc_carry_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_29 at LC_X23_Y8_N3
--operation mode is arithmetic
 
DD1_un1_pc_carry_29_cout_0 = KB1_r32_o_29 & !DD1_un1_pc_prectl_1_0_a4[29] & !DD1_un1_pc_carry_28 # !KB1_r32_o_29 & !DD1_un1_pc_carry_28 # !DD1_un1_pc_prectl_1_0_a4[29];
DD1_un1_pc_carry_29 = CARRY(DD1_un1_pc_carry_29_cout_0);
 
--DD1L352 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_29~COUT1_1 at LC_X23_Y8_N3
--operation mode is arithmetic
 
DD1L352_cout_1 = KB1_r32_o_29 & !DD1_un1_pc_prectl_1_0_a4[29] & !DD1L152 # !KB1_r32_o_29 & !DD1L152 # !DD1_un1_pc_prectl_1_0_a4[29];
DD1L352 = CARRY(DD1L352_cout_1);
 
 
--DD1_un1_pc_prectl_1_0_a4[31] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[31] at LC_X28_Y8_N2
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[31] = FB1_res_7_0_0_31 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_28 at LC_X21_Y10_N8
--operation mode is normal
 
DD1_pc_next_0_iv_1_28 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_28 # !DD1_pc_next_0_iv_1_a[28];
 
 
--DD1_un1_pc_add28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add28 at LC_X23_Y8_N2
--operation mode is arithmetic
 
DD1_un1_pc_add28_carry_eqn = (!DD1_un1_pc_carry_25 & DD1_un1_pc_carry_27) # (DD1_un1_pc_carry_25 & DD1L942);
DD1_un1_pc_add28 = DD1_un1_pc_prectl_1_0_a4[28] $ KB1_r32_o_28 $ !DD1_un1_pc_add28_carry_eqn;
 
--DD1_un1_pc_carry_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_28 at LC_X23_Y8_N2
--operation mode is arithmetic
 
DD1_un1_pc_carry_28_cout_0 = DD1_un1_pc_prectl_1_0_a4[28] & KB1_r32_o_28 # !DD1_un1_pc_carry_27 # !DD1_un1_pc_prectl_1_0_a4[28] & KB1_r32_o_28 & !DD1_un1_pc_carry_27;
DD1_un1_pc_carry_28 = CARRY(DD1_un1_pc_carry_28_cout_0);
 
--DD1L152 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_28~COUT1_1 at LC_X23_Y8_N2
--operation mode is arithmetic
 
DD1L152_cout_1 = DD1_un1_pc_prectl_1_0_a4[28] & KB1_r32_o_28 # !DD1L942 # !DD1_un1_pc_prectl_1_0_a4[28] & KB1_r32_o_28 & !DD1L942;
DD1L152 = CARRY(DD1L152_cout_1);
 
 
--DD1_pc_next_0_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_29 at LC_X22_Y6_N3
--operation mode is normal
 
DD1_pc_next_0_iv_1_29 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_29 # !DD1_pc_next_0_iv_1_a[29];
 
 
--KB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_26 at LC_X23_Y8_N6
--operation mode is normal
 
KB1_r32_o_26_lut_out = DD1_pc_next_0_iv_1_26 # DD1_un1_pc_next46_0 & DD1_un1_pc_add26;
KB1_r32_o_26 = DFFEAS(KB1_r32_o_26_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_27 at LC_X22_Y4_N9
--operation mode is normal
 
KB1_r32_o_27_lut_out = DD1_pc_next_0_iv_1_27 # DD1_un1_pc_next46_0 & DD1_un1_pc_add27;
KB1_r32_o_27 = DFFEAS(KB1_r32_o_27_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_a_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_a_0 at LC_X27_Y4_N7
--operation mode is normal
 
HD1_dout_iv_a_0 = YD1_mux_fw_1 & !AB1_r32_o_29 & !FD1_N_14_i_0_s2 # !FD1_r_data_31 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_31;
 
 
--FD1_reg_bank_m_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|reg_bank_m_0 at LC_X24_Y2_N2
--operation mode is normal
 
FD1_reg_bank_m_0 = LD2_q_b[31] & FD1_N_18_i_0_s3;
 
 
--UB1_dout_2_i_i_x[31] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[31] at LC_X27_Y4_N2
--operation mode is normal
 
UB1_dout_2_i_i_x[31] = UB1_dout_2_i_i_a2[16] # KE1_q_b[7] & UB1_dout_2_i_i_a3_0[16];
 
 
--UB1_un1_ctl_6_2_0 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_6_2_0 at LC_X31_Y9_N1
--operation mode is normal
 
UB1_un1_ctl_6_2_0 = RB1_byte_addr_o_0 & UB1_un1_ctl_5 # !RB1_byte_addr_o_0 & RB1_ctl_o_0 # !UB1_un1_ctl_6_2_0_a;
 
 
--WB63L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_31__Z|lpm_latch:U1|q[0]~56 at LC_X27_Y4_N0
--operation mode is normal
 
WB63L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[31] # !UB1_un1_byte_addr_2 & WB63L1;
 
--DB1_r32_o_31 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_31 at LC_X27_Y4_N0
--operation mode is normal
 
DB1_r32_o_31 = DFFEAS(WB63L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[30] at LC_X22_Y8_N0
--operation mode is normal
 
GD1_dout_iv_1_a[30] = AB1_r32_o_28 & !ZD1_mux_fw_1 & !FD1_r_data_30 # !FD1_N_16_i_0_s2 # !AB1_r32_o_28 & !FD1_r_data_30 # !FD1_N_16_i_0_s2;
 
 
--F1_cmd[30] is mips_sys:isys|mips_dvc:imips_dvc|cmd[30] at LC_X32_Y13_N5
--operation mode is normal
 
F1_cmd[30]_lut_out = CB1_r32_o_30;
F1_cmd[30] = DFFEAS(F1_cmd[30]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--PD1_a_o_3_d_a[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[29] at LC_X21_Y9_N1
--operation mode is normal
 
PD1_a_o_3_d_a[29] = PD1_a_o_sn_m2 & !PB1_r32_o_29 # !PD1_a_o_sn_m2 & !AB1_r32_o_27;
 
 
--TD1_lt_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_25 at LC_X16_Y8_N9
--operation mode is arithmetic
 
TD1_lt_25 = CARRY(VD1_b_o_iv_25 & PD1_a_o_25 & !TD1L781 # !VD1_b_o_iv_25 & PD1_a_o_25 # !TD1L781);
 
 
--TD1_sum_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_26 at LC_X15_Y6_N0
--operation mode is arithmetic
 
TD1_sum_carry_26_cout_0 = VD1_b_o_iv_26 & PD1_a_o_26 & !TD1_sum_carry_25 # !VD1_b_o_iv_26 & PD1_a_o_26 # !TD1_sum_carry_25;
TD1_sum_carry_26 = CARRY(TD1_sum_carry_26_cout_0);
 
--TD1L534 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_26~COUT1_1 at LC_X15_Y6_N0
--operation mode is arithmetic
 
TD1L534_cout_1 = VD1_b_o_iv_26 & PD1_a_o_26 & !TD1_sum_carry_25 # !VD1_b_o_iv_26 & PD1_a_o_26 # !TD1_sum_carry_25;
TD1L534 = CARRY(TD1L534_cout_1);
 
 
--F1_cmd[28] is mips_sys:isys|mips_dvc:imips_dvc|cmd[28] at LC_X28_Y3_N3
--operation mode is normal
 
F1_cmd[28]_lut_out = CB1_r32_o_28;
F1_cmd[28] = DFFEAS(F1_cmd[28]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[29] is mips_sys:isys|mips_dvc:imips_dvc|cmd[29] at LC_X26_Y5_N3
--operation mode is normal
 
F1_cmd[29]_lut_out = CB1_r32_o_29;
F1_cmd[29] = DFFEAS(F1_cmd[29]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--UB1_dout_2_0_0_o2_0[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_0[9] at LC_X29_Y9_N8
--operation mode is normal
 
UB1_dout_2_0_0_o2_0[9] = !UB1_dout_2_0_0_o2_0_a[9] & !RB1_byte_addr_o_0 & !RB1_byte_addr_o_1;
 
 
--UB1_dout_2_i_i_a_x[8] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[8] at LC_X31_Y13_N4
--operation mode is normal
 
UB1_dout_2_i_i_a_x[8] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[0];
 
 
--UB1_dout_2_0_0_a2_1[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a2_1[9] at LC_X29_Y13_N9
--operation mode is normal
 
UB1_dout_2_0_0_a2_1[9] = !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # UB1_dout_2_0_0_a2_1_a[9] & UB1_dout_2_i_i_a3_1[15];
 
 
--M1_clk_ctr27_i_0_a5_5_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_0_a5_5_a at LC_X33_Y16_N8
--operation mode is normal
 
M1_clk_ctr27_i_0_a5_5_a = !M1_clk_ctr[10] & M1_clk_ctr[11];
 
 
--YB1_pc_gen_ctl_2_i_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_0 at LC_X27_Y17_N0
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_0 = !YB1_pc_gen_ctl_2_i_0_5[2] & !YB1_pc_gen_ctl_2_i_0_a[2] & !KE1_q_a[3] # !YB1_fsm_dly_2_0_0_a2_x[2];
 
 
--WB26L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~68 at LC_X27_Y15_N1
--operation mode is normal
 
WB26L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_i_0_0 # !YB1_un1_muxa_ctl370_x & WB26L2;
 
 
--WB26L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1|q[0]~69 at LC_X27_Y15_N2
--operation mode is normal
 
WB26L2 = !YB1_un1_ins_i_23_2_0 & WB26L1;
 
--HC1_pc_gen_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_2 at LC_X27_Y15_N2
--operation mode is normal
 
HC1_pc_gen_ctl_o_2 = DFFEAS(WB26L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_pc_gen_ctl_2_i_m3_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_0 at LC_X27_Y17_N4
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_0 = YB1_pc_gen_ctl_2_i_m3_0_5[0] # !GE1_q_a[4] & YB1_muxa_ctl_2_0_0_o2_0[1] & YB1_pc_gen_ctl_2_i_m3_0_a_x[0];
 
 
--WB06L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~68 at LC_X27_Y18_N6
--operation mode is normal
 
WB06L1 = YB1_un1_ins_i_20 # YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_i_m3_0_0 # !YB1_un1_muxa_ctl370_x & WB06L2;
 
 
--WB06L2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1|q[0]~69 at LC_X27_Y18_N7
--operation mode is normal
 
WB06L2 = !YB1_un1_ins_i_23_2_0 & WB06L1;
 
--HC1_pc_gen_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_0 at LC_X27_Y18_N7
--operation mode is normal
 
HC1_pc_gen_ctl_o_0 = DFFEAS(WB06L2, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_pc_gen_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_0 at LC_X26_Y17_N4
--operation mode is normal
 
YB1_pc_gen_ctl_2_0_0_0 = YB1_alu_func_2_0_0_a2_3_x[0] & YB1_pc_gen_ctl_2_0_0_a2_x[1] & YB1_alu_func_2_0_0_a2_2_x[0] # !YB1_pc_gen_ctl_2_0_0_a[1];
 
 
--WB16L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:pc_gen_ctl_1_1_|lpm_latch:U1|q[0]~56 at LC_X26_Y16_N2
--operation mode is normal
 
WB16L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_pc_gen_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB16L1;
 
--HC1_pc_gen_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8|pc_gen_ctl_o_1 at LC_X26_Y16_N2
--operation mode is normal
 
HC1_pc_gen_ctl_o_1 = DFFEAS(WB16L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--BD1_res_2_NE is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE at LC_X24_Y11_N5
--operation mode is normal
 
BD1_res_2_NE = BD1_res_2_NE_9_0 # BD1_res_2_NE_10_0 # BD1_res_2_NE_11_0 # BD1_res_2_NE_12_0;
 
 
--BD1_res_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_5 at LC_X24_Y11_N2
--operation mode is normal
 
BD1_res_5 = !PB1_dout_iv_31 & BD1_un10_res_28 # BD1_un10_res_27;
 
 
--F1_cmd[10] is mips_sys:isys|mips_dvc:imips_dvc|cmd[10] at LC_X28_Y14_N3
--operation mode is normal
 
F1_cmd[10]_lut_out = CB1_r32_o_10;
F1_cmd[10] = DFFEAS(F1_cmd[10]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[11] is mips_sys:isys|mips_dvc:imips_dvc|cmd[11] at LC_X28_Y14_N0
--operation mode is normal
 
F1_cmd[11]_lut_out = CB1_r32_o_11;
F1_cmd[11] = DFFEAS(F1_cmd[11]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[12] is mips_sys:isys|mips_dvc:imips_dvc|cmd[12] at LC_X34_Y6_N4
--operation mode is normal
 
F1_cmd[12]_lut_out = CB1_r32_o_12;
F1_cmd[12] = DFFEAS(F1_cmd[12]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--F1_cmd[23] is mips_sys:isys|mips_dvc:imips_dvc|cmd[23] at LC_X29_Y4_N4
--operation mode is normal
 
F1_cmd[23]_lut_out = CB1_r32_o_23;
F1_cmd[23] = DFFEAS(F1_cmd[23]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--UB1_dout_2_0_0_a_x[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[9] at LC_X28_Y13_N7
--operation mode is normal
 
UB1_dout_2_0_0_a_x[9] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[1];
 
 
--GD1_dout_iv_1_a[11] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[11] at LC_X22_Y7_N5
--operation mode is normal
 
GD1_dout_iv_1_a[11] = FD1_r_data_11 & !FD1_N_16_i_0_s2 & !AB1_r32_o_9 # !ZD1_mux_fw_1 # !FD1_r_data_11 & !AB1_r32_o_9 # !ZD1_mux_fw_1;
 
 
--GD1_dout_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[13] at LC_X27_Y6_N5
--operation mode is normal
 
GD1_dout_iv_1_a[13] = AB1_r32_o_11 & !ZD1_mux_fw_1 & !FD1_r_data_13 # !FD1_N_16_i_0_s2 # !AB1_r32_o_11 & !FD1_r_data_13 # !FD1_N_16_i_0_s2;
 
 
--F1_cmd[13] is mips_sys:isys|mips_dvc:imips_dvc|cmd[13] at LC_X31_Y8_N8
--operation mode is normal
 
F1_cmd[13]_lut_out = CB1_r32_o_13;
F1_cmd[13] = DFFEAS(F1_cmd[13]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[12] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[12] at LC_X27_Y8_N7
--operation mode is normal
 
GD1_dout_iv_1_a[12] = ZD1_mux_fw_1 & !AB1_r32_o_10 & !FD1_r_data_12 # !FD1_N_16_i_0_s2 # !ZD1_mux_fw_1 & !FD1_r_data_12 # !FD1_N_16_i_0_s2;
 
 
--GD1_dout_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[14] at LC_X21_Y6_N6
--operation mode is normal
 
GD1_dout_iv_1_a[14] = FD1_r_data_14 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_12 # !FD1_r_data_14 & !ZD1_mux_fw_1 # !AB1_r32_o_12;
 
 
--F1_cmd[14] is mips_sys:isys|mips_dvc:imips_dvc|cmd[14] at LC_X28_Y3_N5
--operation mode is normal
 
F1_cmd[14]_lut_out = CB1_r32_o_14;
F1_cmd[14] = DFFEAS(F1_cmd[14]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[21] at LC_X20_Y7_N9
--operation mode is normal
 
GD1_dout_iv_1_a[21] = FD1_N_16_i_0_s2 & !FD1_r_data_21 & !ZD1_mux_fw_1 # !AB1_r32_o_19 # !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_19;
 
 
--GD1_dout_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[22] at LC_X24_Y7_N0
--operation mode is normal
 
GD1_dout_iv_1_a[22] = FD1_r_data_22 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_20 # !FD1_r_data_22 & !ZD1_mux_fw_1 # !AB1_r32_o_20;
 
 
--GD1_dout_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[25] at LC_X25_Y6_N6
--operation mode is normal
 
GD1_dout_iv_1_a[25] = FD1_r_data_25 & !FD1_N_16_i_0_s2 & !AB1_r32_o_23 # !ZD1_mux_fw_1 # !FD1_r_data_25 & !AB1_r32_o_23 # !ZD1_mux_fw_1;
 
 
--F1_cmd[25] is mips_sys:isys|mips_dvc:imips_dvc|cmd[25] at LC_X28_Y3_N6
--operation mode is normal
 
F1_cmd[25]_lut_out = CB1_r32_o_25;
F1_cmd[25] = DFFEAS(F1_cmd[25]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[26] at LC_X20_Y8_N9
--operation mode is normal
 
GD1_dout_iv_1_a[26] = FD1_N_16_i_0_s2 & !FD1_r_data_26 & !ZD1_mux_fw_1 # !AB1_r32_o_24 # !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_24;
 
 
--F1_cmd[26] is mips_sys:isys|mips_dvc:imips_dvc|cmd[26] at LC_X29_Y7_N0
--operation mode is normal
 
F1_cmd[26]_lut_out = CB1_r32_o_26;
F1_cmd[26] = DFFEAS(F1_cmd[26]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[29] at LC_X26_Y5_N4
--operation mode is normal
 
GD1_dout_iv_1_a[29] = ZD1_mux_fw_1 & !AB1_r32_o_27 & !FD1_N_16_i_0_s2 # !FD1_r_data_29 # !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_29;
 
 
--GD1_dout_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[17] at LC_X26_Y6_N2
--operation mode is normal
 
GD1_dout_iv_1_a[17] = AB1_r32_o_15 & !ZD1_mux_fw_1 & !FD1_r_data_17 # !FD1_N_16_i_0_s2 # !AB1_r32_o_15 & !FD1_r_data_17 # !FD1_N_16_i_0_s2;
 
 
--GD1_dout_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[18] at LC_X21_Y8_N9
--operation mode is normal
 
GD1_dout_iv_1_a[18] = FD1_N_16_i_0_s2 & !FD1_r_data_18 & !ZD1_mux_fw_1 # !AB1_r32_o_16 # !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_16;
 
 
--VD1_un1_op2_reged_1_combout[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[8] at LC_X13_Y4_N0
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[8] = VD1_eqop2_2_32 & VD1_op2_reged[8] # !VD1_eqop2_2_32 & VD1_nop2_reged[8];
 
 
--YB1_rd_sel_2_0_0_a3_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|rd_sel_2_0_0_a3_0_a[0] at LC_X26_Y19_N8
--operation mode is normal
 
YB1_rd_sel_2_0_0_a3_0_a[0] = !KE1_q_a[2] & !GE1_q_a[2] & GE1_q_a[1] # !GE1_q_a[3];
 
 
--YB1_alu_we_1_0_0_a3_1_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|alu_we_1_0_0_a3_1_0_a[0] at LC_X26_Y19_N0
--operation mode is normal
 
YB1_alu_we_1_0_0_a3_1_0_a[0] = !KE1_q_a[2] & !KE1_q_a[6] & !GE1_q_a[4] & GE1_q_a[5];
 
 
--UB1_dout_2_i_i_x[20] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[20] at LC_X30_Y7_N5
--operation mode is normal
 
UB1_dout_2_i_i_x[20] = UB1_dout_2_i_i_a2[16] # JE1_q_b[4] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB52L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_20__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y7_N9
--operation mode is normal
 
WB52L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[20] # !UB1_un1_byte_addr_2 & WB52L1;
 
--DB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_20 at LC_X30_Y7_N9
--operation mode is normal
 
DB1_r32_o_20 = DFFEAS(WB52L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--GD1_dout_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[20] at LC_X21_Y7_N5
--operation mode is normal
 
GD1_dout_iv_1_a[20] = FD1_r_data_20 & !FD1_N_16_i_0_s2 & !AB1_r32_o_18 # !ZD1_mux_fw_1 # !FD1_r_data_20 & !AB1_r32_o_18 # !ZD1_mux_fw_1;
 
 
--AD1_un1_rst_2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2_a at LC_X30_Y17_N5
--operation mode is normal
 
AD1_un1_rst_2_a = !AD1_CurrState_Sreg0_3 & AD1_delay_counter_Sreg0[0] # AD1_delay_counter_Sreg0[5] # !AD1_un1_delay_counter_Sreg0_1_0_a2_0_a2_1_0;
 
 
--AD1_un1_rst_2_s is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un1_rst_2_s at LC_X27_Y14_N7
--operation mode is normal
 
AD1_un1_rst_2_s = !AD1_CurrState_Sreg0[7] & !AD1_CurrState_Sreg0_5 & sys_rst & !AD1_CurrState_Sreg0_2;
 
 
--AD1_un4_next_delay_counter_Sreg0_c3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_c3 at LC_X31_Y17_N1
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_c3 = AD1_delay_counter_Sreg0[2] # AD1_delay_counter_Sreg0[3] # AD1_delay_counter_Sreg0[1] # AD1_delay_counter_Sreg0[0];
 
 
--AD1_un4_next_delay_counter_Sreg0_sum1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum1 at LC_X30_Y17_N1
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_sum1 = AD1_delay_counter_Sreg0[1] $ !AD1_delay_counter_Sreg0[0];
 
 
--WB86L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_1_|lpm_latch:U1|q[0]~14 at LC_X30_Y17_N3
--operation mode is normal
 
WB86L1 = AD1_CurrState_Sreg0[2] # AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum1 # !AD1_un1_rst_2 & WB86L1;
 
--AD1_delay_counter_Sreg0[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[1] at LC_X30_Y17_N3
--operation mode is normal
 
AD1_delay_counter_Sreg0[1] = DFFEAS(WB86L1, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--AD1_un4_next_delay_counter_Sreg0_sum2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum2 at LC_X30_Y17_N6
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_sum2 = AD1_delay_counter_Sreg0[2] $ (!AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[0]);
 
 
--WB96L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_2__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y17_N8
--operation mode is normal
 
WB96L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum2 # !AD1_un1_rst_2 & WB96L1;
 
--AD1_delay_counter_Sreg0[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[2] at LC_X30_Y17_N8
--operation mode is normal
 
AD1_delay_counter_Sreg0[2] = DFFEAS(WB96L1, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--AD1_un4_next_delay_counter_Sreg0_sum3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum3 at LC_X31_Y17_N7
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_sum3 = AD1_delay_counter_Sreg0[3] $ (!AD1_delay_counter_Sreg0[2] & !AD1_delay_counter_Sreg0[1] & !AD1_delay_counter_Sreg0[0]);
 
 
--WB07L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y17_N0
--operation mode is normal
 
WB07L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum3 # !AD1_un1_rst_2 & WB07L1;
 
 
--AD1_un4_next_delay_counter_Sreg0_sum4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|un4_next_delay_counter_Sreg0_sum4 at LC_X31_Y17_N2
--operation mode is normal
 
AD1_un4_next_delay_counter_Sreg0_sum4 = AD1_delay_counter_Sreg0[4] $ (!AD1_un4_next_delay_counter_Sreg0_c3);
 
 
--WB17L1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_4__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y17_N8
--operation mode is normal
 
WB17L1 = !AD1_CurrState_Sreg0[2] & AD1_un1_rst_2 & AD1_un4_next_delay_counter_Sreg0_sum4 # !AD1_un1_rst_2 & WB17L1;
 
--AD1_delay_counter_Sreg0[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|delay_counter_Sreg0[4] at LC_X31_Y17_N8
--operation mode is normal
 
AD1_delay_counter_Sreg0[4] = DFFEAS(WB17L1, GLOBAL(E1__clk0), VCC, , , , , !sys_rst, );
 
 
--YB1_muxa_ctl_2_0_0_o2_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_o2_0[1] at LC_X27_Y17_N8
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_o2_0[1] = YB1_alu_func_2_0_0_o2_x[3] & GE1_q_a[5] & YB1_muxa_ctl_2_0_0_a2_0_0[1] # !YB1_alu_func_2_0_0_o2_x[3] & YB1_alu_func_2_0_0_a2_0_x[3] # GE1_q_a[5] & YB1_muxa_ctl_2_0_0_a2_0_0[1];
 
 
--YB1_muxb_ctl_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxb_ctl_2_0_0_0_a[1] at LC_X27_Y15_N7
--operation mode is normal
 
YB1_muxb_ctl_2_0_0_0_a[1] = WB95L2 & !YB1_fsm_dly_2_0_0_o2_x[2] & JE1_q_a[7] # !YB1_fsm_dly_2_0_0_a2_0[2] # !WB95L2 & JE1_q_a[7] # !YB1_fsm_dly_2_0_0_a2_0[2];
 
 
--YB1_ext_ctl_2_0_0_a3_1_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_0_0_a3_1_x[2] at LC_X24_Y17_N0
--operation mode is normal
 
YB1_ext_ctl_2_0_0_a3_1_x[2] = KE1_q_a[2] & KE1_q_a[3] & KE1_q_a[4];
 
 
--YB1_ext_ctl_2_i_m3_0_0_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0_Z[0] at LC_X24_Y17_N8
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_0_Z[0] = !KE1_q_a[4] & YB1_ext_ctl_2_i_m3_0_0_a[0] # KE1_q_a[5] & !KE1_q_a[2];
 
 
--YB1_ext_ctl_2_i_m3_0_2_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_2_a[0] at LC_X24_Y17_N1
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_2_a[0] = YB1_cmp_ctl_2_0_0_a2_0[0] & !WB05L2 & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2] # !YB1_cmp_ctl_2_0_0_a2_0[0] & YB1_alu_func_2_0_0_o2_x[3] # !YB1_ext_ctl_2_0_0_a2_2_x[2];
 
 
--YB1_muxa_ctl_2_0_0_a2_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_x[1] at LC_X29_Y17_N9
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_a2_x[1] = !KE1_q_a[4] & KE1_q_a[2];
 
 
--YB1_muxa_ctl_2_0_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_0_a[1] at LC_X28_Y15_N7
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_0_a[1] = WB75L2 & !KE1_q_a[4] & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
 
 
--FD1_un14_qa_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE_1 at LC_X26_Y14_N2
--operation mode is normal
 
FD1_r_rdaddress_a[1]_qfbk = FD1_r_rdaddress_a[1];
FD1_un14_qa_NE_1 = FD1_r_wraddress[1] & FD1_r_rdaddress_a[0] $ FD1_r_wraddress[0] # !FD1_r_rdaddress_a[1]_qfbk # !FD1_r_wraddress[1] & FD1_r_rdaddress_a[1]_qfbk # FD1_r_rdaddress_a[0] $ FD1_r_wraddress[0];
 
--FD1_r_rdaddress_a[1] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[1] at LC_X26_Y14_N2
--operation mode is normal
 
FD1_r_rdaddress_a[1] = DFFEAS(FD1_un14_qa_NE_1, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[6], , , VCC);
 
 
--FD1_un14_qa_NE_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un14_qa_NE_a at LC_X26_Y14_N1
--operation mode is normal
 
FD1_r_wraddress[2]_qfbk = FD1_r_wraddress[2];
FD1_un14_qa_NE_a = FD1_r_rdaddress_a[2] & FD1_r_rdaddress_a[3] $ FD1_r_wraddress[3] # !FD1_r_wraddress[2]_qfbk # !FD1_r_rdaddress_a[2] & FD1_r_wraddress[2]_qfbk # FD1_r_rdaddress_a[3] $ FD1_r_wraddress[3];
 
--FD1_r_wraddress[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wraddress[2] at LC_X26_Y14_N1
--operation mode is normal
 
FD1_r_wraddress[2] = DFFEAS(FD1_un14_qa_NE_a, GLOBAL(E1__clk0), VCC, , , NB1_r5_o_2, , , VCC);
 
 
--FD1_un23_qa_i_0_a2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qa_i_0_a2 at LC_X27_Y14_N3
--operation mode is normal
 
FD1_r_rdaddress_a[4]_qfbk = FD1_r_rdaddress_a[4];
FD1_un23_qa_i_0_a2 = !FD1_r_rdaddress_a[0] & !FD1_r_rdaddress_a[1] & !FD1_r_rdaddress_a[4]_qfbk & FD1_un23_qa_i_0_a2_a;
 
--FD1_r_rdaddress_a[4] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[4] at LC_X27_Y14_N3
--operation mode is normal
 
FD1_r_rdaddress_a[4] = DFFEAS(FD1_un23_qa_i_0_a2, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, KE1_q_a[1], , , VCC);
 
 
--FD1_N_14_i_0_s2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2_a at LC_X25_Y8_N5
--operation mode is normal
 
FD1_r_wren_qfbk = FD1_r_wren;
FD1_N_14_i_0_s2_a = MC1_wb_we_o_0 & !YD1_un17_mux_fw_NE & !WD1_un30_mux_fw # !FD1_r_wren_qfbk;
 
--FD1_r_wren is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_wren at LC_X25_Y8_N5
--operation mode is normal
 
FD1_r_wren = DFFEAS(FD1_N_14_i_0_s2_a, GLOBAL(E1__clk0), VCC, , , MC1_wb_we_o_0, , , VCC);
 
 
--YD1_un1_mux_fw_NE_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE_1 at LC_X26_Y9_N4
--operation mode is normal
 
ED1_r32_o_21_qfbk = ED1_r32_o_21;
YD1_un1_mux_fw_NE_1 = MB1_r5_o_1 & MB1_r5_o_0 $ ED1_r32_o_21_qfbk # !ED1_r32_o_22 # !MB1_r5_o_1 & ED1_r32_o_22 # MB1_r5_o_0 $ ED1_r32_o_21_qfbk;
 
--ED1_r32_o_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_21 at LC_X26_Y9_N4
--operation mode is normal
 
ED1_r32_o_21 = DFFEAS(YD1_un1_mux_fw_NE_1, GLOBAL(E1__clk0), VCC, , C1_G_504, JE1_q_a[5], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--YD1_un1_mux_fw_NE_a is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|un1_mux_fw_NE_a at LC_X25_Y10_N4
--operation mode is normal
 
MB1_r5_o_2_qfbk = MB1_r5_o_2;
YD1_un1_mux_fw_NE_a = ED1_r32_o_24 & ED1_r32_o_23 $ MB1_r5_o_2_qfbk # !MB1_r5_o_3 # !ED1_r32_o_24 & MB1_r5_o_3 # ED1_r32_o_23 $ MB1_r5_o_2_qfbk;
 
--MB1_r5_o_2 is mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_2 at LC_X25_Y10_N4
--operation mode is normal
 
MB1_r5_o_2 = DFFEAS(YD1_un1_mux_fw_NE_a, GLOBAL(E1__clk0), VCC, , , LB1_r5_o_2, , , VCC);
 
 
--GD1_dout_iv_1_a[10] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[10] at LC_X20_Y8_N2
--operation mode is normal
 
GD1_dout_iv_1_a[10] = AB1_r32_o_8 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_10 # !AB1_r32_o_8 & !FD1_N_16_i_0_s2 # !FD1_r_data_10;
 
 
--GD1_dout_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[15] at LC_X24_Y4_N4
--operation mode is normal
 
GD1_dout_iv_1_a[15] = AB1_r32_o_13 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_15 # !AB1_r32_o_13 & !FD1_N_16_i_0_s2 # !FD1_r_data_15;
 
 
--F1_cmd[15] is mips_sys:isys|mips_dvc:imips_dvc|cmd[15] at LC_X30_Y3_N5
--operation mode is normal
 
F1_cmd[15]_lut_out = CB1_r32_o_15;
F1_cmd[15] = DFFEAS(F1_cmd[15]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[27] at LC_X22_Y7_N8
--operation mode is normal
 
GD1_dout_iv_1_a[27] = FD1_r_data_27 & !FD1_N_16_i_0_s2 & !AB1_r32_o_25 # !ZD1_mux_fw_1 # !FD1_r_data_27 & !AB1_r32_o_25 # !ZD1_mux_fw_1;
 
 
--F1_cmd[27] is mips_sys:isys|mips_dvc:imips_dvc|cmd[27] at LC_X25_Y15_N3
--operation mode is normal
 
F1_cmd[27]_lut_out = CB1_r32_o_27;
F1_cmd[27] = DFFEAS(F1_cmd[27]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--GD1_dout_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[19] at LC_X27_Y7_N5
--operation mode is normal
 
GD1_dout_iv_1_a[19] = FD1_r_data_19 & !FD1_N_16_i_0_s2 & !ZD1_mux_fw_1 # !AB1_r32_o_17 # !FD1_r_data_19 & !ZD1_mux_fw_1 # !AB1_r32_o_17;
 
 
--VD1_count[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[1] at LC_X32_Y9_N3
--operation mode is arithmetic
 
VD1_count[1]_lut_out = VD1_count[1] $ VD1_count_cout[0];
VD1_count[1] = DFFEAS(VD1_count[1]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
--VD1_count_cout[1] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[1] at LC_X32_Y9_N3
--operation mode is arithmetic
 
VD1_count_cout[1]_cout_0 = !VD1_count_cout[0] # !VD1_count[1];
VD1_count_cout[1] = CARRY(VD1_count_cout[1]_cout_0);
 
--VD1L701 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[1]~COUT1_2 at LC_X32_Y9_N3
--operation mode is arithmetic
 
VD1L701_cout_1 = !VD1L501 # !VD1_count[1];
VD1L701 = CARRY(VD1L701_cout_1);
 
 
--VD1_over_carry_29 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_29 at LC_X10_Y10_N3
--operation mode is arithmetic
 
VD1_over_carry_29_cout_0 = VD1_b_o_iv_29 & !VD1_over_carry_28 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !VD1_over_carry_28;
VD1_over_carry_29 = CARRY(VD1_over_carry_29_cout_0);
 
--VD1L7251 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_29~COUT1_1 at LC_X10_Y10_N3
--operation mode is arithmetic
 
VD1L7251_cout_1 = VD1_b_o_iv_29 & !VD1L5251 # !PD1_a_o_29 # !VD1_b_o_iv_29 & !PD1_a_o_29 & !VD1L5251;
VD1L7251 = CARRY(VD1L7251_cout_1);
 
 
--VD1_eqz_2_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_16 at LC_X10_Y5_N3
--operation mode is normal
 
VD1_eqz_2_16 = !VD1_hilo[32] & !VD1_hilo_33 & !VD1_hilo_37;
 
 
--VD1_eqz_2_27_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_27_a at LC_X10_Y5_N0
--operation mode is normal
 
VD1_eqz_2_27_a = !VD1_hilo_46 & !VD1_hilo_49 & !VD1_hilo_36 & !VD1_hilo_34;
 
 
--VD1_eqz_2_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_19 at LC_X11_Y4_N2
--operation mode is normal
 
VD1_eqz_2_19 = !VD1_hilo_41 & !VD1_hilo_62 & !VD1_hilo_44 & !VD1_hilo_63;
 
 
--VD1_eqz_2_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_20 at LC_X7_Y2_N1
--operation mode is normal
 
VD1_eqz_2_20 = !VD1_hilo_55 & !VD1_hilo_58 & !VD1_hilo_60 & !VD1_hilo_61;
 
 
--VD1_eqz_2_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_22 at LC_X11_Y4_N5
--operation mode is normal
 
VD1_eqz_2_22 = !VD1_hilo_43 & !VD1_hilo_56 & !VD1_hilo_42 & !VD1_hilo[64];
 
 
--VD1_eqz_2_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqz_2_23 at LC_X11_Y4_N6
--operation mode is normal
 
VD1_eqz_2_23 = !VD1_hilo_47 & !VD1_hilo_48 & !VD1_hilo_54 & !VD1_hilo_57;
 
 
--VD1_eqop2_2_NE_121 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_121 at LC_X12_Y5_N7
--operation mode is normal
 
VD1_eqop2_2_NE_121 = VD1_hilo_42 & VD1_op2_reged[26] $ VD1_hilo_58 # !VD1_op2_reged[10] # !VD1_hilo_42 & VD1_op2_reged[10] # VD1_op2_reged[26] $ VD1_hilo_58;
 
 
--VD1_eqop2_2_NE_123 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_123 at LC_X12_Y5_N5
--operation mode is normal
 
VD1_eqop2_2_NE_123 = VD1_op2_reged[28] & VD1_hilo_44 $ VD1_op2_reged[12] # !VD1_hilo_60 # !VD1_op2_reged[28] & VD1_hilo_60 # VD1_hilo_44 $ VD1_op2_reged[12];
 
 
--VD1_eqop2_2_NE_122 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_122 at LC_X12_Y5_N9
--operation mode is normal
 
VD1_eqop2_2_NE_122 = VD1_op2_reged[27] & VD1_hilo_43 $ VD1_op2_reged[11] # !VD1_hilo_59 # !VD1_op2_reged[27] & VD1_hilo_59 # VD1_hilo_43 $ VD1_op2_reged[11];
 
 
--VD1_eqop2_2_NE_11_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_11_a at LC_X12_Y2_N4
--operation mode is normal
 
VD1_eqop2_2_NE_11_a = VD1_hilo_41 & VD1_op2_reged[25] $ VD1_hilo_57 # !VD1_op2_reged[9] # !VD1_hilo_41 & VD1_op2_reged[9] # VD1_op2_reged[25] $ VD1_hilo_57;
 
 
--VD1_eqop2_2_NE_114 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_114 at LC_X11_Y5_N5
--operation mode is normal
 
VD1_eqop2_2_NE_114 = VD1_op2_reged[19] & VD1_op2_reged[3] $ VD1_hilo_35 # !VD1_hilo_51 # !VD1_op2_reged[19] & VD1_hilo_51 # VD1_op2_reged[3] $ VD1_hilo_35;
 
 
--VD1_eqop2_2_NE_115_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_115_0 at LC_X11_Y5_N8
--operation mode is normal
 
VD1_eqop2_2_NE_115_0 = VD1_hilo_52 & VD1_hilo_36 $ VD1_op2_reged[4] # !VD1_op2_reged[20] # !VD1_hilo_52 & VD1_op2_reged[20] # VD1_hilo_36 $ VD1_op2_reged[4];
 
 
--VD1_eqop2_2_NE_112 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_112 at LC_X11_Y5_N9
--operation mode is normal
 
VD1_eqop2_2_NE_112 = VD1_op2_reged[1] & VD1_hilo_49 $ VD1_op2_reged[17] # !VD1_hilo_33 # !VD1_op2_reged[1] & VD1_hilo_33 # VD1_hilo_49 $ VD1_op2_reged[17];
 
 
--VD1_eqop2_2_NE_113 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_113 at LC_X11_Y5_N6
--operation mode is normal
 
VD1_eqop2_2_NE_113 = VD1_hilo_50 & VD1_hilo_34 $ VD1_op2_reged[2] # !VD1_op2_reged[18] # !VD1_hilo_50 & VD1_op2_reged[18] # VD1_hilo_34 $ VD1_op2_reged[2];
 
 
--VD1_eqop2_2_NE_118 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_118 at LC_X15_Y4_N1
--operation mode is normal
 
VD1_eqop2_2_NE_118 = VD1_op2_reged[7] & VD1_op2_reged[23] $ VD1_hilo_55 # !VD1_hilo_39 # !VD1_op2_reged[7] & VD1_hilo_39 # VD1_op2_reged[23] $ VD1_hilo_55;
 
 
--VD1_eqop2_2_NE_119 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_119 at LC_X14_Y4_N1
--operation mode is normal
 
VD1_eqop2_2_NE_119 = VD1_hilo_56 & VD1_hilo_40 $ VD1_op2_reged[8] # !VD1_op2_reged[24] # !VD1_hilo_56 & VD1_op2_reged[24] # VD1_hilo_40 $ VD1_op2_reged[8];
 
 
--VD1_eqop2_2_NE_116 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_116 at LC_X14_Y4_N8
--operation mode is normal
 
VD1_eqop2_2_NE_116 = VD1_hilo_37 & VD1_op2_reged[21] $ VD1_hilo_53 # !VD1_op2_reged[5] # !VD1_hilo_37 & VD1_op2_reged[5] # VD1_op2_reged[21] $ VD1_hilo_53;
 
 
--VD1_eqop2_2_NE_117 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_117 at LC_X14_Y4_N9
--operation mode is normal
 
VD1_eqop2_2_NE_117 = VD1_hilo_54 & VD1_op2_reged[6] $ VD1_hilo_38 # !VD1_op2_reged[22] # !VD1_hilo_54 & VD1_op2_reged[22] # VD1_op2_reged[6] $ VD1_hilo_38;
 
 
--VD1_eqop2_2_NE_126 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_126 at LC_X11_Y2_N4
--operation mode is normal
 
VD1_eqop2_2_NE_126 = VD1_op2_reged[15] & VD1_op2_reged[31] $ VD1_hilo_63 # !VD1_hilo_47 # !VD1_op2_reged[15] & VD1_hilo_47 # VD1_op2_reged[31] $ VD1_hilo_63;
 
 
--VD1_eqop2_2_NE_124 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_124 at LC_X11_Y2_N5
--operation mode is normal
 
VD1_eqop2_2_NE_124 = VD1_op2_reged[13] & VD1_hilo_61 $ VD1_op2_reged[29] # !VD1_hilo_45 # !VD1_op2_reged[13] & VD1_hilo_45 # VD1_hilo_61 $ VD1_op2_reged[29];
 
 
--VD1_eqop2_2_NE_12_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_12_a at LC_X11_Y2_N3
--operation mode is normal
 
VD1_eqop2_2_NE_12_a = !VD1_eqop2_2_0 & VD1_eqop2_2_NE_125_i_a2 & VD1_hilo_48 $ !VD1_op2_reged[16];
 
 
--VD1_nop2_reged[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[16] at LC_X13_Y3_N0
--operation mode is arithmetic
 
VD1_nop2_reged[16]_carry_eqn = VD1_nop2_reged_cout[14];
VD1_nop2_reged[16] = VD1_op2_reged[16] $ VD1_nop2_reged[16]_carry_eqn;
 
--VD1_nop2_reged_cout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[16] at LC_X13_Y3_N0
--operation mode is arithmetic
 
VD1_nop2_reged_cout[16]_cout_0 = !VD1_op2_reged[17] & !VD1_op2_reged[16] & !VD1_nop2_reged_cout[14];
VD1_nop2_reged_cout[16] = CARRY(VD1_nop2_reged_cout[16]_cout_0);
 
--VD1L9331 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[16]~COUT1_19 at LC_X13_Y3_N0
--operation mode is arithmetic
 
VD1L9331_cout_1 = !VD1_op2_reged[17] & !VD1_op2_reged[16] & !VD1_nop2_reged_cout[14];
VD1L9331 = CARRY(VD1L9331_cout_1);
 
 
--VD1_nop2_reged[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[15] at LC_X12_Y4_N9
--operation mode is arithmetic
 
VD1_nop2_reged[15]_carry_eqn = (!VD1_nop2_reged_cout[5] & VD1_nop2_reged_cout[13]) # (VD1_nop2_reged_cout[5] & VD1L5331);
VD1_nop2_reged[15] = VD1_op2_reged[15] $ (VD1_op2_reged[14] # !VD1_nop2_reged[15]_carry_eqn);
 
--VD1_nop2_reged_cout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[15] at LC_X12_Y4_N9
--operation mode is arithmetic
 
VD1_nop2_reged_cout[15] = CARRY(VD1_op2_reged[14] # VD1_op2_reged[15] # !VD1L5331);
 
 
--VD1_nop2_reged[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[17] at LC_X12_Y3_N0
--operation mode is arithmetic
 
VD1_nop2_reged[17]_carry_eqn = VD1_nop2_reged_cout[15];
VD1_nop2_reged[17] = VD1_op2_reged[17] $ (VD1_op2_reged[16] # VD1_nop2_reged[17]_carry_eqn);
 
--VD1_nop2_reged_cout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[17] at LC_X12_Y3_N0
--operation mode is arithmetic
 
VD1_nop2_reged_cout[17]_cout_0 = !VD1_op2_reged[16] & !VD1_op2_reged[17] & !VD1_nop2_reged_cout[15];
VD1_nop2_reged_cout[17] = CARRY(VD1_nop2_reged_cout[17]_cout_0);
 
--VD1L1431 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[17]~COUT1_7 at LC_X12_Y3_N0
--operation mode is arithmetic
 
VD1L1431_cout_1 = !VD1_op2_reged[16] & !VD1_op2_reged[17] & !VD1_nop2_reged_cout[15];
VD1L1431 = CARRY(VD1L1431_cout_1);
 
 
--VD1_nop2_reged[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[19] at LC_X12_Y3_N1
--operation mode is arithmetic
 
VD1_nop2_reged[19]_carry_eqn = (!VD1_nop2_reged_cout[15] & VD1_nop2_reged_cout[17]) # (VD1_nop2_reged_cout[15] & VD1L1431);
VD1_nop2_reged[19] = VD1_op2_reged[19] $ (VD1_op2_reged[18] # !VD1_nop2_reged[19]_carry_eqn);
 
--VD1_nop2_reged_cout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[19] at LC_X12_Y3_N1
--operation mode is arithmetic
 
VD1_nop2_reged_cout[19]_cout_0 = VD1_op2_reged[19] # VD1_op2_reged[18] # !VD1_nop2_reged_cout[17];
VD1_nop2_reged_cout[19] = CARRY(VD1_nop2_reged_cout[19]_cout_0);
 
--VD1L5431 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[19]~COUT1_8 at LC_X12_Y3_N1
--operation mode is arithmetic
 
VD1L5431_cout_1 = VD1_op2_reged[19] # VD1_op2_reged[18] # !VD1L1431;
VD1L5431 = CARRY(VD1L5431_cout_1);
 
 
--VD1_nop2_reged[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[18] at LC_X13_Y3_N1
--operation mode is arithmetic
 
VD1_nop2_reged[18]_carry_eqn = (!VD1_nop2_reged_cout[14] & VD1_nop2_reged_cout[16]) # (VD1_nop2_reged_cout[14] & VD1L9331);
VD1_nop2_reged[18] = VD1_op2_reged[18] $ (!VD1_nop2_reged[18]_carry_eqn);
 
--VD1_nop2_reged_cout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[18] at LC_X13_Y3_N1
--operation mode is arithmetic
 
VD1_nop2_reged_cout[18]_cout_0 = VD1_op2_reged[18] # VD1_op2_reged[19] # !VD1_nop2_reged_cout[16];
VD1_nop2_reged_cout[18] = CARRY(VD1_nop2_reged_cout[18]_cout_0);
 
--VD1L3431 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[18]~COUT1_20 at LC_X13_Y3_N1
--operation mode is arithmetic
 
VD1L3431_cout_1 = VD1_op2_reged[18] # VD1_op2_reged[19] # !VD1L9331;
VD1L3431 = CARRY(VD1L3431_cout_1);
 
 
--VD1_nop2_reged[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[20] at LC_X13_Y3_N2
--operation mode is arithmetic
 
VD1_nop2_reged[20]_carry_eqn = (!VD1_nop2_reged_cout[14] & VD1_nop2_reged_cout[18]) # (VD1_nop2_reged_cout[14] & VD1L3431);
VD1_nop2_reged[20] = VD1_op2_reged[20] $ VD1_nop2_reged[20]_carry_eqn;
 
--VD1_nop2_reged_cout[20] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[20] at LC_X13_Y3_N2
--operation mode is arithmetic
 
VD1_nop2_reged_cout[20]_cout_0 = !VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1_nop2_reged_cout[18];
VD1_nop2_reged_cout[20] = CARRY(VD1_nop2_reged_cout[20]_cout_0);
 
--VD1L7431 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[20]~COUT1_21 at LC_X13_Y3_N2
--operation mode is arithmetic
 
VD1L7431_cout_1 = !VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1L3431;
VD1L7431 = CARRY(VD1L7431_cout_1);
 
 
--VD1_nop2_reged[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[21] at LC_X12_Y3_N2
--operation mode is arithmetic
 
VD1_nop2_reged[21]_carry_eqn = (!VD1_nop2_reged_cout[15] & VD1_nop2_reged_cout[19]) # (VD1_nop2_reged_cout[15] & VD1L5431);
VD1_nop2_reged[21] = VD1_op2_reged[21] $ (VD1_op2_reged[20] # VD1_nop2_reged[21]_carry_eqn);
 
--VD1_nop2_reged_cout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[21] at LC_X12_Y3_N2
--operation mode is arithmetic
 
VD1_nop2_reged_cout[21]_cout_0 = !VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1_nop2_reged_cout[19];
VD1_nop2_reged_cout[21] = CARRY(VD1_nop2_reged_cout[21]_cout_0);
 
--VD1L9431 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[21]~COUT1_9 at LC_X12_Y3_N2
--operation mode is arithmetic
 
VD1L9431_cout_1 = !VD1_op2_reged[21] & !VD1_op2_reged[20] & !VD1L5431;
VD1L9431 = CARRY(VD1L9431_cout_1);
 
 
--VD1_nop2_reged[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[22] at LC_X13_Y3_N3
--operation mode is arithmetic
 
VD1_nop2_reged[22]_carry_eqn = (!VD1_nop2_reged_cout[14] & VD1_nop2_reged_cout[20]) # (VD1_nop2_reged_cout[14] & VD1L7431);
VD1_nop2_reged[22] = VD1_op2_reged[22] $ (!VD1_nop2_reged[22]_carry_eqn);
 
--VD1_nop2_reged_cout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[22] at LC_X13_Y3_N3
--operation mode is arithmetic
 
VD1_nop2_reged_cout[22]_cout_0 = VD1_op2_reged[22] # VD1_op2_reged[23] # !VD1_nop2_reged_cout[20];
VD1_nop2_reged_cout[22] = CARRY(VD1_nop2_reged_cout[22]_cout_0);
 
--VD1L1531 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[22]~COUT1_22 at LC_X13_Y3_N3
--operation mode is arithmetic
 
VD1L1531_cout_1 = VD1_op2_reged[22] # VD1_op2_reged[23] # !VD1L7431;
VD1L1531 = CARRY(VD1L1531_cout_1);
 
 
--VD1_nop2_reged[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[23] at LC_X12_Y3_N3
--operation mode is arithmetic
 
VD1_nop2_reged[23]_carry_eqn = (!VD1_nop2_reged_cout[15] & VD1_nop2_reged_cout[21]) # (VD1_nop2_reged_cout[15] & VD1L9431);
VD1_nop2_reged[23] = VD1_op2_reged[23] $ (VD1_op2_reged[22] # !VD1_nop2_reged[23]_carry_eqn);
 
--VD1_nop2_reged_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[23] at LC_X12_Y3_N3
--operation mode is arithmetic
 
VD1_nop2_reged_cout[23]_cout_0 = VD1_op2_reged[22] # VD1_op2_reged[23] # !VD1_nop2_reged_cout[21];
VD1_nop2_reged_cout[23] = CARRY(VD1_nop2_reged_cout[23]_cout_0);
 
--VD1L3531 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[23]~COUT1_10 at LC_X12_Y3_N3
--operation mode is arithmetic
 
VD1L3531_cout_1 = VD1_op2_reged[22] # VD1_op2_reged[23] # !VD1L9431;
VD1L3531 = CARRY(VD1L3531_cout_1);
 
 
--VD1_nop2_reged[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[24] at LC_X13_Y3_N4
--operation mode is arithmetic
 
VD1_nop2_reged[24]_carry_eqn = (!VD1_nop2_reged_cout[14] & VD1_nop2_reged_cout[22]) # (VD1_nop2_reged_cout[14] & VD1L1531);
VD1_nop2_reged[24] = VD1_op2_reged[24] $ (VD1_nop2_reged[24]_carry_eqn);
 
--VD1_nop2_reged_cout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[24] at LC_X13_Y3_N4
--operation mode is arithmetic
 
VD1_nop2_reged_cout[24] = CARRY(!VD1_op2_reged[24] & !VD1_op2_reged[25] & !VD1L1531);
 
 
--VD1_nop2_reged[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[13] at LC_X12_Y4_N8
--operation mode is arithmetic
 
VD1_nop2_reged[13]_carry_eqn = (!VD1_nop2_reged_cout[5] & VD1_nop2_reged_cout[11]) # (VD1_nop2_reged_cout[5] & VD1L1331);
VD1_nop2_reged[13] = VD1_op2_reged[13] $ (VD1_op2_reged[12] # VD1_nop2_reged[13]_carry_eqn);
 
--VD1_nop2_reged_cout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[13] at LC_X12_Y4_N8
--operation mode is arithmetic
 
VD1_nop2_reged_cout[13]_cout_0 = !VD1_op2_reged[12] & !VD1_op2_reged[13] & !VD1_nop2_reged_cout[11];
VD1_nop2_reged_cout[13] = CARRY(VD1_nop2_reged_cout[13]_cout_0);
 
--VD1L5331 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[13]~COUT1_6 at LC_X12_Y4_N8
--operation mode is arithmetic
 
VD1L5331_cout_1 = !VD1_op2_reged[12] & !VD1_op2_reged[13] & !VD1L1331;
VD1L5331 = CARRY(VD1L5331_cout_1);
 
 
--VD1_nop2_reged[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[29] at LC_X12_Y3_N6
--operation mode is arithmetic
 
VD1_nop2_reged[29]_carry_eqn = (!VD1_nop2_reged_cout[25] & VD1_nop2_reged_cout[27]) # (VD1_nop2_reged_cout[25] & VD1L9531);
VD1_nop2_reged[29] = VD1_op2_reged[29] $ (VD1_op2_reged[28] # VD1_nop2_reged[29]_carry_eqn);
 
--VD1_nop2_reged_cout[29] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[29] at LC_X12_Y3_N6
--operation mode is arithmetic
 
VD1_nop2_reged_cout[29]_cout_0 = !VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1_nop2_reged_cout[27];
VD1_nop2_reged_cout[29] = CARRY(VD1_nop2_reged_cout[29]_cout_0);
 
--VD1L3631 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[29]~COUT1_12 at LC_X12_Y3_N6
--operation mode is arithmetic
 
VD1L3631_cout_1 = !VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1L9531;
VD1L3631 = CARRY(VD1L3631_cout_1);
 
 
--VD1_nop2_reged[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[14] at LC_X13_Y4_N9
--operation mode is arithmetic
 
VD1_nop2_reged[14]_carry_eqn = (!VD1_nop2_reged_cout[4] & VD1_nop2_reged_cout[12]) # (VD1_nop2_reged_cout[4] & VD1L3331);
VD1_nop2_reged[14] = VD1_op2_reged[14] $ !VD1_nop2_reged[14]_carry_eqn;
 
--VD1_nop2_reged_cout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[14] at LC_X13_Y4_N9
--operation mode is arithmetic
 
VD1_nop2_reged_cout[14] = CARRY(VD1_op2_reged[15] # VD1_op2_reged[14] # !VD1L3331);
 
 
--VD1_nop2_reged[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[26] at LC_X13_Y3_N5
--operation mode is arithmetic
 
VD1_nop2_reged[26]_carry_eqn = VD1_nop2_reged_cout[24];
VD1_nop2_reged[26] = VD1_op2_reged[26] $ (!VD1_nop2_reged[26]_carry_eqn);
 
--VD1_nop2_reged_cout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[26] at LC_X13_Y3_N5
--operation mode is arithmetic
 
VD1_nop2_reged_cout[26]_cout_0 = VD1_op2_reged[26] # VD1_op2_reged[27] # !VD1_nop2_reged_cout[24];
VD1_nop2_reged_cout[26] = CARRY(VD1_nop2_reged_cout[26]_cout_0);
 
--VD1L7531 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[26]~COUT1_23 at LC_X13_Y3_N5
--operation mode is arithmetic
 
VD1L7531_cout_1 = VD1_op2_reged[26] # VD1_op2_reged[27] # !VD1_nop2_reged_cout[24];
VD1L7531 = CARRY(VD1L7531_cout_1);
 
 
--VD1_eqnop2_2_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_9 at LC_X12_Y2_N5
--operation mode is normal
 
VD1_eqnop2_2_9 = VD1_hilo_41 $ (VD1_nop2_reged[9]);
 
 
--VD1_eqnop2_2_NE_5_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_5_a at LC_X11_Y4_N7
--operation mode is normal
 
VD1_eqnop2_2_NE_5_a = VD1_nop2_reged[25] & VD1_hilo_42 $ VD1_nop2_reged[10] # !VD1_hilo_57 # !VD1_nop2_reged[25] & VD1_hilo_57 # VD1_hilo_42 $ VD1_nop2_reged[10];
 
 
--VD1_nop2_reged[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[27] at LC_X12_Y3_N5
--operation mode is arithmetic
 
VD1_nop2_reged[27]_carry_eqn = VD1_nop2_reged_cout[25];
VD1_nop2_reged[27] = VD1_op2_reged[27] $ (VD1_op2_reged[26] # !VD1_nop2_reged[27]_carry_eqn);
 
--VD1_nop2_reged_cout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[27] at LC_X12_Y3_N5
--operation mode is arithmetic
 
VD1_nop2_reged_cout[27]_cout_0 = VD1_op2_reged[27] # VD1_op2_reged[26] # !VD1_nop2_reged_cout[25];
VD1_nop2_reged_cout[27] = CARRY(VD1_nop2_reged_cout[27]_cout_0);
 
--VD1L9531 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[27]~COUT1_11 at LC_X12_Y3_N5
--operation mode is arithmetic
 
VD1L9531_cout_1 = VD1_op2_reged[27] # VD1_op2_reged[26] # !VD1_nop2_reged_cout[25];
VD1L9531 = CARRY(VD1L9531_cout_1);
 
 
--VD1_eqnop2_2_NE_8_a is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_8_a at LC_X12_Y5_N2
--operation mode is normal
 
VD1_eqnop2_2_NE_8_a = VD1_nop2_reged[11] $ (VD1_hilo_43);
 
 
--VD1_eqnop2_2_NE_140_i_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqnop2_2_NE_140_i_a2 at LC_X12_Y5_N3
--operation mode is normal
 
VD1_eqnop2_2_NE_140_i_a2 = VD1_nop2_reged[12] & VD1_hilo_44 & VD1_nop2_reged[28] $ !VD1_hilo_60 # !VD1_nop2_reged[12] & !VD1_hilo_44 & VD1_nop2_reged[28] $ !VD1_hilo_60;
 
 
--VD1_un59_hilo_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add32 at LC_X9_Y3_N6
--operation mode is normal
 
VD1_un59_hilo_add32_carry_eqn = (!VD1_un59_hilo_carry_30 & VD1_un59_hilo_carry_31) # (VD1_un59_hilo_carry_30 & VD1L2881);
VD1_un59_hilo_add32 = VD1_op2_sign_reged $ (VD1_un59_hilo_add32_carry_eqn $ !VD1_hilo[64]);
 
 
--VD1_un50_hilo_add32 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add32 at LC_X10_Y2_N6
--operation mode is normal
 
VD1_un50_hilo_add32_carry_eqn = (!VD1_un50_hilo_carry_30 & VD1_un50_hilo_carry_31) # (VD1_un50_hilo_carry_30 & VD1L9571);
VD1_un50_hilo_add32 = VD1_hilo[64] $ VD1_un50_hilo_add32_carry_eqn $ !VD1_nop2_reged[32];
 
 
--VD1_hilo_15_3_i_a[63] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_3_i_a[63] at LC_X7_Y9_N1
--operation mode is normal
 
VD1_hilo_15_3_i_a[63] = VD1_sub_or_yn & !VD1_un59_hilo_add32 & !VD1_hilo[0] # !VD1_sub_or_yn & !VD1_un50_hilo_add32 & VD1_hilo[0];
 
 
--GD1_dout_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[16] at LC_X21_Y5_N3
--operation mode is normal
 
GD1_dout_iv_1_a[16] = AB1_r32_o_14 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_16 # !AB1_r32_o_14 & !FD1_N_16_i_0_s2 # !FD1_r_data_16;
 
 
--CD1_res_7_0_0_0_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext|res_7_0_0_0_a[16] at LC_X22_Y16_N8
--operation mode is normal
 
CD1_res_7_0_0_0_a[16] = !DC1_ext_ctl_o_2 & !DC1_ext_ctl_o_1 & DC1_ext_ctl_o_0;
 
 
--GD1_dout_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[28] at LC_X26_Y8_N6
--operation mode is normal
 
GD1_dout_iv_1_a[28] = FD1_r_data_28 & !FD1_N_16_i_0_s2 & !AB1_r32_o_26 # !ZD1_mux_fw_1 # !FD1_r_data_28 & !AB1_r32_o_26 # !ZD1_mux_fw_1;
 
 
--GD1_dout_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[23] at LC_X23_Y5_N5
--operation mode is normal
 
GD1_dout_iv_1_a[23] = ZD1_mux_fw_1 & !AB1_r32_o_21 & !FD1_N_16_i_0_s2 # !FD1_r_data_23 # !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_23;
 
 
--GD1_dout_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt|dout_iv_1_a[24] at LC_X23_Y6_N2
--operation mode is normal
 
GD1_dout_iv_1_a[24] = AB1_r32_o_22 & !ZD1_mux_fw_1 & !FD1_N_16_i_0_s2 # !FD1_r_data_24 # !AB1_r32_o_22 & !FD1_N_16_i_0_s2 # !FD1_r_data_24;
 
 
--F1_cmd[24] is mips_sys:isys|mips_dvc:imips_dvc|cmd[24] at LC_X29_Y5_N2
--operation mode is normal
 
F1_cmd[24]_lut_out = CB1_r32_o_24;
F1_cmd[24] = DFFEAS(F1_cmd[24]_lut_out, GLOBAL(E1__clk0), VCC, , C1_G_602, , , !sys_rst, );
 
 
--VD1_un59_hilo_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add16 at LC_X9_Y4_N0
--operation mode is arithmetic
 
VD1_un59_hilo_add16_carry_eqn = VD1_un59_hilo_carry_15;
VD1_un59_hilo_add16 = VD1_hilo_48 $ VD1_op2_reged[16] $ !VD1_un59_hilo_add16_carry_eqn;
 
--VD1_un59_hilo_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_16 at LC_X9_Y4_N0
--operation mode is arithmetic
 
VD1_un59_hilo_carry_16_cout_0 = VD1_hilo_48 & VD1_op2_reged[16] # !VD1_un59_hilo_carry_15 # !VD1_hilo_48 & VD1_op2_reged[16] & !VD1_un59_hilo_carry_15;
VD1_un59_hilo_carry_16 = CARRY(VD1_un59_hilo_carry_16_cout_0);
 
--VD1L5581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_16~COUT1_1 at LC_X9_Y4_N0
--operation mode is arithmetic
 
VD1L5581_cout_1 = VD1_hilo_48 & VD1_op2_reged[16] # !VD1_un59_hilo_carry_15 # !VD1_hilo_48 & VD1_op2_reged[16] & !VD1_un59_hilo_carry_15;
VD1L5581 = CARRY(VD1L5581_cout_1);
 
 
--VD1_un50_hilo_add16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add16 at LC_X10_Y3_N0
--operation mode is arithmetic
 
VD1_un50_hilo_add16_carry_eqn = VD1_un50_hilo_carry_15;
VD1_un50_hilo_add16 = VD1_nop2_reged[16] $ VD1_hilo_48 $ !VD1_un50_hilo_add16_carry_eqn;
 
--VD1_un50_hilo_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_16 at LC_X10_Y3_N0
--operation mode is arithmetic
 
VD1_un50_hilo_carry_16_cout_0 = VD1_nop2_reged[16] & VD1_hilo_48 # !VD1_un50_hilo_carry_15 # !VD1_nop2_reged[16] & VD1_hilo_48 & !VD1_un50_hilo_carry_15;
VD1_un50_hilo_carry_16 = CARRY(VD1_un50_hilo_carry_16_cout_0);
 
--VD1L2371 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_16~COUT1_1 at LC_X10_Y3_N0
--operation mode is arithmetic
 
VD1L2371_cout_1 = VD1_nop2_reged[16] & VD1_hilo_48 # !VD1_un50_hilo_carry_15 # !VD1_nop2_reged[16] & VD1_hilo_48 & !VD1_un50_hilo_carry_15;
VD1L2371 = CARRY(VD1L2371_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[16] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[16] at LC_X11_Y6_N4
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[16] = VD1_eqop2_2_32 & VD1_op2_reged[16] # !VD1_eqop2_2_32 & VD1_nop2_reged[16];
 
 
--VD1_un59_hilo_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add17 at LC_X9_Y4_N1
--operation mode is arithmetic
 
VD1_un59_hilo_add17_carry_eqn = (!VD1_un59_hilo_carry_15 & VD1_un59_hilo_carry_16) # (VD1_un59_hilo_carry_15 & VD1L5581);
VD1_un59_hilo_add17 = VD1_op2_reged[17] $ VD1_hilo_49 $ VD1_un59_hilo_add17_carry_eqn;
 
--VD1_un59_hilo_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_17 at LC_X9_Y4_N1
--operation mode is arithmetic
 
VD1_un59_hilo_carry_17_cout_0 = VD1_op2_reged[17] & !VD1_hilo_49 & !VD1_un59_hilo_carry_16 # !VD1_op2_reged[17] & !VD1_un59_hilo_carry_16 # !VD1_hilo_49;
VD1_un59_hilo_carry_17 = CARRY(VD1_un59_hilo_carry_17_cout_0);
 
--VD1L7581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_17~COUT1_1 at LC_X9_Y4_N1
--operation mode is arithmetic
 
VD1L7581_cout_1 = VD1_op2_reged[17] & !VD1_hilo_49 & !VD1L5581 # !VD1_op2_reged[17] & !VD1L5581 # !VD1_hilo_49;
VD1L7581 = CARRY(VD1L7581_cout_1);
 
 
--VD1_un50_hilo_add17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add17 at LC_X10_Y3_N1
--operation mode is arithmetic
 
VD1_un50_hilo_add17_carry_eqn = (!VD1_un50_hilo_carry_15 & VD1_un50_hilo_carry_16) # (VD1_un50_hilo_carry_15 & VD1L2371);
VD1_un50_hilo_add17 = VD1_nop2_reged[17] $ VD1_hilo_49 $ VD1_un50_hilo_add17_carry_eqn;
 
--VD1_un50_hilo_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_17 at LC_X10_Y3_N1
--operation mode is arithmetic
 
VD1_un50_hilo_carry_17_cout_0 = VD1_nop2_reged[17] & !VD1_hilo_49 & !VD1_un50_hilo_carry_16 # !VD1_nop2_reged[17] & !VD1_un50_hilo_carry_16 # !VD1_hilo_49;
VD1_un50_hilo_carry_17 = CARRY(VD1_un50_hilo_carry_17_cout_0);
 
--VD1L4371 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_17~COUT1_1 at LC_X10_Y3_N1
--operation mode is arithmetic
 
VD1L4371_cout_1 = VD1_nop2_reged[17] & !VD1_hilo_49 & !VD1L2371 # !VD1_nop2_reged[17] & !VD1L2371 # !VD1_hilo_49;
VD1L4371 = CARRY(VD1L4371_cout_1);
 
 
--DD1_pc_next_0_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_16 at LC_X28_Y5_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_16 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_16 # !DD1_pc_next_0_iv_1_a[16];
 
 
--DD1_un1_pc_add16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add16 at LC_X23_Y9_N0
--operation mode is arithmetic
 
DD1_un1_pc_add16_carry_eqn = DD1_un1_pc_carry_15;
DD1_un1_pc_add16 = KB1_r32_o_16 $ DD1_un1_pc_prectl_1_0_a4[16] $ !DD1_un1_pc_add16_carry_eqn;
 
--DD1_un1_pc_carry_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_16 at LC_X23_Y9_N0
--operation mode is arithmetic
 
DD1_un1_pc_carry_16_cout_0 = KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] # !DD1_un1_pc_carry_15 # !KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] & !DD1_un1_pc_carry_15;
DD1_un1_pc_carry_16 = CARRY(DD1_un1_pc_carry_16_cout_0);
 
--DD1L922 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_16~COUT1_1 at LC_X23_Y9_N0
--operation mode is arithmetic
 
DD1L922_cout_1 = KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] # !DD1_un1_pc_carry_15 # !KB1_r32_o_16 & DD1_un1_pc_prectl_1_0_a4[16] & !DD1_un1_pc_carry_15;
DD1L922 = CARRY(DD1L922_cout_1);
 
 
--DD1_pc_next_0_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_17 at LC_X22_Y5_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_17 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_17 # !DD1_pc_next_0_iv_1_a[17];
 
 
--DD1_un1_pc_add17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add17 at LC_X23_Y9_N1
--operation mode is arithmetic
 
DD1_un1_pc_add17_carry_eqn = (!DD1_un1_pc_carry_15 & DD1_un1_pc_carry_16) # (DD1_un1_pc_carry_15 & DD1L922);
DD1_un1_pc_add17 = DD1_un1_pc_prectl_1_0_a4[17] $ KB1_r32_o_17 $ DD1_un1_pc_add17_carry_eqn;
 
--DD1_un1_pc_carry_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_17 at LC_X23_Y9_N1
--operation mode is arithmetic
 
DD1_un1_pc_carry_17_cout_0 = DD1_un1_pc_prectl_1_0_a4[17] & !KB1_r32_o_17 & !DD1_un1_pc_carry_16 # !DD1_un1_pc_prectl_1_0_a4[17] & !DD1_un1_pc_carry_16 # !KB1_r32_o_17;
DD1_un1_pc_carry_17 = CARRY(DD1_un1_pc_carry_17_cout_0);
 
--DD1L132 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_17~COUT1_1 at LC_X23_Y9_N1
--operation mode is arithmetic
 
DD1L132_cout_1 = DD1_un1_pc_prectl_1_0_a4[17] & !KB1_r32_o_17 & !DD1L922 # !DD1_un1_pc_prectl_1_0_a4[17] & !DD1L922 # !KB1_r32_o_17;
DD1L132 = CARRY(DD1L132_cout_1);
 
 
--PB1_dout_iv_16 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_16 at LC_X25_Y4_N3
--operation mode is normal
 
PB1_dout_iv_16 = HD1_dout_iv_1_16 # HD1_dout7_0_a2 & FD1_wb_o_16;
 
--PB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_16 at LC_X25_Y4_N3
--operation mode is normal
 
PB1_r32_o_16 = DFFEAS(PB1_dout_iv_16, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un1_op2_reged_1_combout[17] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[17] at LC_X12_Y3_N9
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[17] = VD1_eqop2_2_32 & VD1_op2_reged[17] # !VD1_eqop2_2_32 & VD1_nop2_reged[17];
 
 
--VD1_un59_hilo_add18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add18 at LC_X9_Y4_N2
--operation mode is arithmetic
 
VD1_un59_hilo_add18_carry_eqn = (!VD1_un59_hilo_carry_15 & VD1_un59_hilo_carry_17) # (VD1_un59_hilo_carry_15 & VD1L7581);
VD1_un59_hilo_add18 = VD1_op2_reged[18] $ VD1_hilo_50 $ !VD1_un59_hilo_add18_carry_eqn;
 
--VD1_un59_hilo_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_18 at LC_X9_Y4_N2
--operation mode is arithmetic
 
VD1_un59_hilo_carry_18_cout_0 = VD1_op2_reged[18] & VD1_hilo_50 # !VD1_un59_hilo_carry_17 # !VD1_op2_reged[18] & VD1_hilo_50 & !VD1_un59_hilo_carry_17;
VD1_un59_hilo_carry_18 = CARRY(VD1_un59_hilo_carry_18_cout_0);
 
--VD1L9581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_18~COUT1_1 at LC_X9_Y4_N2
--operation mode is arithmetic
 
VD1L9581_cout_1 = VD1_op2_reged[18] & VD1_hilo_50 # !VD1L7581 # !VD1_op2_reged[18] & VD1_hilo_50 & !VD1L7581;
VD1L9581 = CARRY(VD1L9581_cout_1);
 
 
--PB1_dout_iv_17 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_17 at LC_X25_Y7_N0
--operation mode is normal
 
PB1_dout_iv_17 = HD1_dout_iv_1_17 # FD1_wb_o_17 & HD1_dout7_0_a2;
 
--PB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_17 at LC_X25_Y7_N0
--operation mode is normal
 
PB1_r32_o_17 = DFFEAS(PB1_dout_iv_17, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un59_hilo_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add14 at LC_X9_Y5_N8
--operation mode is arithmetic
 
VD1_un59_hilo_add14_carry_eqn = (!VD1_un59_hilo_carry_10 & VD1_un59_hilo_carry_13) # (VD1_un59_hilo_carry_10 & VD1L0581);
VD1_un59_hilo_add14 = VD1_op2_reged[14] $ VD1_hilo_46 $ !VD1_un59_hilo_add14_carry_eqn;
 
--VD1_un59_hilo_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_14 at LC_X9_Y5_N8
--operation mode is arithmetic
 
VD1_un59_hilo_carry_14_cout_0 = VD1_op2_reged[14] & VD1_hilo_46 # !VD1_un59_hilo_carry_13 # !VD1_op2_reged[14] & VD1_hilo_46 & !VD1_un59_hilo_carry_13;
VD1_un59_hilo_carry_14 = CARRY(VD1_un59_hilo_carry_14_cout_0);
 
--VD1L2581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_14~COUT1_1 at LC_X9_Y5_N8
--operation mode is arithmetic
 
VD1L2581_cout_1 = VD1_op2_reged[14] & VD1_hilo_46 # !VD1L0581 # !VD1_op2_reged[14] & VD1_hilo_46 & !VD1L0581;
VD1L2581 = CARRY(VD1L2581_cout_1);
 
 
--VD1_un50_hilo_add14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add14 at LC_X10_Y4_N8
--operation mode is arithmetic
 
VD1_un50_hilo_add14_carry_eqn = (!VD1_un50_hilo_carry_10 & VD1_un50_hilo_carry_13) # (VD1_un50_hilo_carry_10 & VD1L7271);
VD1_un50_hilo_add14 = VD1_nop2_reged[14] $ VD1_hilo_46 $ !VD1_un50_hilo_add14_carry_eqn;
 
--VD1_un50_hilo_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_14 at LC_X10_Y4_N8
--operation mode is arithmetic
 
VD1_un50_hilo_carry_14_cout_0 = VD1_nop2_reged[14] & VD1_hilo_46 # !VD1_un50_hilo_carry_13 # !VD1_nop2_reged[14] & VD1_hilo_46 & !VD1_un50_hilo_carry_13;
VD1_un50_hilo_carry_14 = CARRY(VD1_un50_hilo_carry_14_cout_0);
 
--VD1L9271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_14~COUT1_1 at LC_X10_Y4_N8
--operation mode is arithmetic
 
VD1L9271_cout_1 = VD1_nop2_reged[14] & VD1_hilo_46 # !VD1L7271 # !VD1_nop2_reged[14] & VD1_hilo_46 & !VD1L7271;
VD1L9271 = CARRY(VD1L9271_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[14] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[14] at LC_X13_Y2_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[14] = VD1_eqop2_2_32 & VD1_op2_reged[14] # !VD1_eqop2_2_32 & VD1_nop2_reged[14];
 
 
--VD1_un59_hilo_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add15 at LC_X9_Y5_N9
--operation mode is arithmetic
 
VD1_un59_hilo_add15_carry_eqn = (!VD1_un59_hilo_carry_10 & VD1_un59_hilo_carry_14) # (VD1_un59_hilo_carry_10 & VD1L2581);
VD1_un59_hilo_add15 = VD1_hilo_47 $ VD1_op2_reged[15] $ VD1_un59_hilo_add15_carry_eqn;
 
--VD1_un59_hilo_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_15 at LC_X9_Y5_N9
--operation mode is arithmetic
 
VD1_un59_hilo_carry_15 = CARRY(VD1_hilo_47 & !VD1_op2_reged[15] & !VD1L2581 # !VD1_hilo_47 & !VD1L2581 # !VD1_op2_reged[15]);
 
 
--VD1_un50_hilo_add15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add15 at LC_X10_Y4_N9
--operation mode is arithmetic
 
VD1_un50_hilo_add15_carry_eqn = (!VD1_un50_hilo_carry_10 & VD1_un50_hilo_carry_14) # (VD1_un50_hilo_carry_10 & VD1L9271);
VD1_un50_hilo_add15 = VD1_hilo_47 $ VD1_nop2_reged[15] $ VD1_un50_hilo_add15_carry_eqn;
 
--VD1_un50_hilo_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_15 at LC_X10_Y4_N9
--operation mode is arithmetic
 
VD1_un50_hilo_carry_15 = CARRY(VD1_hilo_47 & !VD1_nop2_reged[15] & !VD1L9271 # !VD1_hilo_47 & !VD1L9271 # !VD1_nop2_reged[15]);
 
 
--DD1_pc_next_0_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_14 at LC_X25_Y11_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_14 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_14 # !DD1_pc_next_0_iv_1_a[14];
 
 
--DD1_un1_pc_add14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add14 at LC_X23_Y10_N8
--operation mode is arithmetic
 
DD1_un1_pc_add14_carry_eqn = (!DD1_un1_pc_carry_10 & DD1_un1_pc_carry_13) # (DD1_un1_pc_carry_10 & DD1L422);
DD1_un1_pc_add14 = DD1_un1_pc_prectl_1_0_a4[14] $ KB1_r32_o_14 $ !DD1_un1_pc_add14_carry_eqn;
 
--DD1_un1_pc_carry_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_14 at LC_X23_Y10_N8
--operation mode is arithmetic
 
DD1_un1_pc_carry_14_cout_0 = DD1_un1_pc_prectl_1_0_a4[14] & KB1_r32_o_14 # !DD1_un1_pc_carry_13 # !DD1_un1_pc_prectl_1_0_a4[14] & KB1_r32_o_14 & !DD1_un1_pc_carry_13;
DD1_un1_pc_carry_14 = CARRY(DD1_un1_pc_carry_14_cout_0);
 
--DD1L622 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_14~COUT1_1 at LC_X23_Y10_N8
--operation mode is arithmetic
 
DD1L622_cout_1 = DD1_un1_pc_prectl_1_0_a4[14] & KB1_r32_o_14 # !DD1L422 # !DD1_un1_pc_prectl_1_0_a4[14] & KB1_r32_o_14 & !DD1L422;
DD1L622 = CARRY(DD1L622_cout_1);
 
 
--DD1_pc_next_0_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_15 at LC_X19_Y6_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_15 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_15 # !DD1_pc_next_0_iv_1_a[15];
 
 
--DD1_un1_pc_add15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add15 at LC_X23_Y10_N9
--operation mode is arithmetic
 
DD1_un1_pc_add15_carry_eqn = (!DD1_un1_pc_carry_10 & DD1_un1_pc_carry_14) # (DD1_un1_pc_carry_10 & DD1L622);
DD1_un1_pc_add15 = DD1_un1_pc_prectl_1_0_a4[15] $ KB1_r32_o_15 $ DD1_un1_pc_add15_carry_eqn;
 
--DD1_un1_pc_carry_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_15 at LC_X23_Y10_N9
--operation mode is arithmetic
 
DD1_un1_pc_carry_15 = CARRY(DD1_un1_pc_prectl_1_0_a4[15] & !KB1_r32_o_15 & !DD1L622 # !DD1_un1_pc_prectl_1_0_a4[15] & !DD1L622 # !KB1_r32_o_15);
 
 
--PB1_dout_iv_14 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_14 at LC_X23_Y7_N6
--operation mode is normal
 
PB1_dout_iv_14 = HD1_dout_iv_1_14 # HD1_dout7_0_a2 & FD1_wb_o_14;
 
--PB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_14 at LC_X23_Y7_N6
--operation mode is normal
 
PB1_r32_o_14 = DFFEAS(PB1_dout_iv_14, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un1_op2_reged_1_combout[15] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[15] at LC_X11_Y2_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[15] = VD1_eqop2_2_32 & VD1_op2_reged[15] # !VD1_eqop2_2_32 & VD1_nop2_reged[15];
 
 
--PB1_dout_iv_15 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_15 at LC_X23_Y7_N7
--operation mode is normal
 
PB1_dout_iv_15 = HD1_dout_iv_1_15 # HD1_dout7_0_a2 & FD1_wb_o_15;
 
--PB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_15 at LC_X23_Y7_N7
--operation mode is normal
 
PB1_r32_o_15 = DFFEAS(PB1_dout_iv_15, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un134_hilo_combout[31] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[31] at LC_X4_Y15_N7
--operation mode is normal
 
VD1_un134_hilo_combout[31]_carry_eqn = (!VD1_un134_hilo_cout[25] & VD1_un134_hilo_cout[29]) # (VD1_un134_hilo_cout[25] & VD1L1002);
VD1_un134_hilo_combout[31] = VD1_hilo_31 $ (VD1_un134_hilo_combout[31]_carry_eqn & VD1_hilo_30);
 
 
--PD1_a_o_3_d_a[8] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[8] at LC_X19_Y8_N2
--operation mode is normal
 
PD1_a_o_3_d_a[8] = PD1_a_o_sn_m2 & !PB1_r32_o_8 # !PD1_a_o_sn_m2 & !AB1_r32_o_6;
 
 
--VD1_hilo_33_i_m_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[41] at LC_X7_Y8_N3
--operation mode is normal
 
VD1_hilo_33_i_m_a[41] = VD1_addnop2 & !VD1_un50_hilo_add9 # !VD1_addnop2 & !VD1_un59_hilo_add9;
 
 
--VD1_hilo_24_add9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add9 at LC_X8_Y4_N3
--operation mode is arithmetic
 
VD1_hilo_24_add9_carry_eqn = (!VD1_hilo_24_carry_5 & VD1_hilo_24_carry_8) # (VD1_hilo_24_carry_5 & VD1L294);
VD1_hilo_24_add9 = VD1_un1_op2_reged_1_combout[9] $ VD1_hilo_40 $ VD1_hilo_24_add9_carry_eqn;
 
--VD1_hilo_24_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_9 at LC_X8_Y4_N3
--operation mode is arithmetic
 
VD1_hilo_24_carry_9_cout_0 = VD1_un1_op2_reged_1_combout[9] & !VD1_hilo_40 & !VD1_hilo_24_carry_8 # !VD1_un1_op2_reged_1_combout[9] & !VD1_hilo_24_carry_8 # !VD1_hilo_40;
VD1_hilo_24_carry_9 = CARRY(VD1_hilo_24_carry_9_cout_0);
 
--VD1L494 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_9~COUT1_1 at LC_X8_Y4_N3
--operation mode is arithmetic
 
VD1L494_cout_1 = VD1_un1_op2_reged_1_combout[9] & !VD1_hilo_40 & !VD1L294 # !VD1_un1_op2_reged_1_combout[9] & !VD1L294 # !VD1_hilo_40;
VD1L494 = CARRY(VD1L494_cout_1);
 
 
--VD1_hilo_22_a[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[41] at LC_X7_Y8_N1
--operation mode is normal
 
VD1_hilo_22_a[41] = VD1_hilo[0] & VD1_sign & !VD1_hilo_42 # !VD1_sign & !VD1_un59_hilo_add10 # !VD1_hilo[0] & !VD1_hilo_42;
 
 
--VD1_hilo_15_2[41] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[41] at LC_X7_Y8_N5
--operation mode is normal
 
VD1_hilo_15_2[41] = VD1_sub_or_yn & VD1_un59_hilo_add10 # !VD1_sub_or_yn & VD1_un50_hilo_add10;
 
 
--PD1_a_o_3_d_a[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[9] at LC_X19_Y10_N1
--operation mode is normal
 
PD1_a_o_3_d_a[9] = PD1_a_o_sn_m2 & !PB1_r32_o_9 # !PD1_a_o_sn_m2 & !AB1_r32_o_7;
 
 
--VD1_hilo_33_i_m_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[42] at LC_X7_Y8_N9
--operation mode is normal
 
VD1_hilo_33_i_m_a[42] = VD1_addnop2 & !VD1_un50_hilo_add10 # !VD1_addnop2 & !VD1_un59_hilo_add10;
 
 
--VD1_hilo_24_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add10 at LC_X8_Y4_N4
--operation mode is arithmetic
 
VD1_hilo_24_add10_carry_eqn = (!VD1_hilo_24_carry_5 & VD1_hilo_24_carry_9) # (VD1_hilo_24_carry_5 & VD1L494);
VD1_hilo_24_add10 = VD1_hilo_41 $ VD1_un1_op2_reged_1_combout[10] $ !VD1_hilo_24_add10_carry_eqn;
 
--VD1_hilo_24_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_10 at LC_X8_Y4_N4
--operation mode is arithmetic
 
VD1_hilo_24_carry_10 = CARRY(VD1_hilo_41 & VD1_un1_op2_reged_1_combout[10] # !VD1L494 # !VD1_hilo_41 & VD1_un1_op2_reged_1_combout[10] & !VD1L494);
 
 
--VD1_hilo_22_a[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[42] at LC_X7_Y6_N4
--operation mode is normal
 
VD1_hilo_22_a[42] = VD1_sign & !VD1_hilo_43 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add11 # !VD1_hilo[0] & !VD1_hilo_43;
 
 
--VD1_hilo_15_2[42] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[42] at LC_X7_Y6_N7
--operation mode is normal
 
VD1_hilo_15_2[42] = VD1_sub_or_yn & VD1_un59_hilo_add11 # !VD1_sub_or_yn & VD1_un50_hilo_add11;
 
 
--UD1_shift_out_80_a[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_80_a[10] at LC_X16_Y18_N6
--operation mode is normal
 
UD1_shift_out_80_a[10] = PD1_a_o_1 & !VD1_b_o_iv_13 & !PD1_a_o_2 # !PD1_a_o_1 & PD1_a_o_2 # !VD1_b_o_iv_11;
 
 
--VD1_hilo_33_i_m_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[43] at LC_X7_Y6_N0
--operation mode is normal
 
VD1_hilo_33_i_m_a[43] = VD1_addnop2 & !VD1_un50_hilo_add11 # !VD1_addnop2 & !VD1_un59_hilo_add11;
 
 
--VD1_hilo_24_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add11 at LC_X8_Y4_N5
--operation mode is arithmetic
 
VD1_hilo_24_add11_carry_eqn = VD1_hilo_24_carry_10;
VD1_hilo_24_add11 = VD1_hilo_42 $ VD1_un1_op2_reged_1_combout[11] $ VD1_hilo_24_add11_carry_eqn;
 
--VD1_hilo_24_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_11 at LC_X8_Y4_N5
--operation mode is arithmetic
 
VD1_hilo_24_carry_11_cout_0 = VD1_hilo_42 & !VD1_un1_op2_reged_1_combout[11] & !VD1_hilo_24_carry_10 # !VD1_hilo_42 & !VD1_hilo_24_carry_10 # !VD1_un1_op2_reged_1_combout[11];
VD1_hilo_24_carry_11 = CARRY(VD1_hilo_24_carry_11_cout_0);
 
--VD1L794 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_11~COUT1_1 at LC_X8_Y4_N5
--operation mode is arithmetic
 
VD1L794_cout_1 = VD1_hilo_42 & !VD1_un1_op2_reged_1_combout[11] & !VD1_hilo_24_carry_10 # !VD1_hilo_42 & !VD1_hilo_24_carry_10 # !VD1_un1_op2_reged_1_combout[11];
VD1L794 = CARRY(VD1L794_cout_1);
 
 
--VD1_hilo_22_a[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[43] at LC_X7_Y6_N1
--operation mode is normal
 
VD1_hilo_22_a[43] = VD1_sign & !VD1_hilo_44 # !VD1_sign & VD1_hilo[0] & !VD1_un59_hilo_add12 # !VD1_hilo[0] & !VD1_hilo_44;
 
 
--VD1_hilo_15_2[43] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[43] at LC_X7_Y6_N8
--operation mode is normal
 
VD1_hilo_15_2[43] = VD1_sub_or_yn & VD1_un59_hilo_add12 # !VD1_sub_or_yn & VD1_un50_hilo_add12;
 
 
--PD1_a_o_3_d_a[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[11] at LC_X22_Y10_N1
--operation mode is normal
 
PD1_a_o_3_d_a[11] = PD1_a_o_sn_m2 & !PB1_r32_o_11 # !PD1_a_o_sn_m2 & !AB1_r32_o_9;
 
 
--VD1_un50_hilo_add21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add21 at LC_X10_Y3_N5
--operation mode is arithmetic
 
VD1_un50_hilo_add21_carry_eqn = VD1_un50_hilo_carry_20;
VD1_un50_hilo_add21 = VD1_nop2_reged[21] $ VD1_hilo_53 $ VD1_un50_hilo_add21_carry_eqn;
 
--VD1_un50_hilo_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_21 at LC_X10_Y3_N5
--operation mode is arithmetic
 
VD1_un50_hilo_carry_21_cout_0 = VD1_nop2_reged[21] & !VD1_hilo_53 & !VD1_un50_hilo_carry_20 # !VD1_nop2_reged[21] & !VD1_un50_hilo_carry_20 # !VD1_hilo_53;
VD1_un50_hilo_carry_21 = CARRY(VD1_un50_hilo_carry_21_cout_0);
 
--VD1L1471 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_21~COUT1_1 at LC_X10_Y3_N5
--operation mode is arithmetic
 
VD1L1471_cout_1 = VD1_nop2_reged[21] & !VD1_hilo_53 & !VD1_un50_hilo_carry_20 # !VD1_nop2_reged[21] & !VD1_un50_hilo_carry_20 # !VD1_hilo_53;
VD1L1471 = CARRY(VD1L1471_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[21] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[21] at LC_X12_Y3_N8
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[21] = VD1_eqop2_2_32 & VD1_op2_reged[21] # !VD1_eqop2_2_32 & VD1_nop2_reged[21];
 
 
--VD1_un59_hilo_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add22 at LC_X9_Y4_N6
--operation mode is arithmetic
 
VD1_un59_hilo_add22_carry_eqn = (!VD1_un59_hilo_carry_20 & VD1_un59_hilo_carry_21) # (VD1_un59_hilo_carry_20 & VD1L4681);
VD1_un59_hilo_add22 = VD1_op2_reged[22] $ VD1_hilo_54 $ !VD1_un59_hilo_add22_carry_eqn;
 
--VD1_un59_hilo_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_22 at LC_X9_Y4_N6
--operation mode is arithmetic
 
VD1_un59_hilo_carry_22_cout_0 = VD1_op2_reged[22] & VD1_hilo_54 # !VD1_un59_hilo_carry_21 # !VD1_op2_reged[22] & VD1_hilo_54 & !VD1_un59_hilo_carry_21;
VD1_un59_hilo_carry_22 = CARRY(VD1_un59_hilo_carry_22_cout_0);
 
--VD1L6681 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_22~COUT1_1 at LC_X9_Y4_N6
--operation mode is arithmetic
 
VD1L6681_cout_1 = VD1_op2_reged[22] & VD1_hilo_54 # !VD1L4681 # !VD1_op2_reged[22] & VD1_hilo_54 & !VD1L4681;
VD1L6681 = CARRY(VD1L6681_cout_1);
 
 
--VD1_un50_hilo_add22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add22 at LC_X10_Y3_N6
--operation mode is arithmetic
 
VD1_un50_hilo_add22_carry_eqn = (!VD1_un50_hilo_carry_20 & VD1_un50_hilo_carry_21) # (VD1_un50_hilo_carry_20 & VD1L1471);
VD1_un50_hilo_add22 = VD1_hilo_54 $ VD1_nop2_reged[22] $ !VD1_un50_hilo_add22_carry_eqn;
 
--VD1_un50_hilo_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_22 at LC_X10_Y3_N6
--operation mode is arithmetic
 
VD1_un50_hilo_carry_22_cout_0 = VD1_hilo_54 & VD1_nop2_reged[22] # !VD1_un50_hilo_carry_21 # !VD1_hilo_54 & VD1_nop2_reged[22] & !VD1_un50_hilo_carry_21;
VD1_un50_hilo_carry_22 = CARRY(VD1_un50_hilo_carry_22_cout_0);
 
--VD1L3471 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_22~COUT1_1 at LC_X10_Y3_N6
--operation mode is arithmetic
 
VD1L3471_cout_1 = VD1_hilo_54 & VD1_nop2_reged[22] # !VD1L1471 # !VD1_hilo_54 & VD1_nop2_reged[22] & !VD1L1471;
VD1L3471 = CARRY(VD1L3471_cout_1);
 
 
--DD1_pc_next_0_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_20 at LC_X22_Y13_N9
--operation mode is normal
 
DD1_pc_next_0_iv_1_20 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_20 # !DD1_pc_next_0_iv_1_a[20];
 
 
--DD1_un1_pc_add20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add20 at LC_X23_Y9_N4
--operation mode is arithmetic
 
DD1_un1_pc_add20_carry_eqn = (!DD1_un1_pc_carry_15 & DD1_un1_pc_carry_19) # (DD1_un1_pc_carry_15 & DD1L532);
DD1_un1_pc_add20 = DD1_un1_pc_prectl_1_0_a4[20] $ KB1_r32_o_20 $ !DD1_un1_pc_add20_carry_eqn;
 
--DD1_un1_pc_carry_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_20 at LC_X23_Y9_N4
--operation mode is arithmetic
 
DD1_un1_pc_carry_20 = CARRY(DD1_un1_pc_prectl_1_0_a4[20] & KB1_r32_o_20 # !DD1L532 # !DD1_un1_pc_prectl_1_0_a4[20] & KB1_r32_o_20 & !DD1L532);
 
 
--DD1_pc_next_0_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_21 at LC_X22_Y9_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_21 = PB1_dout_iv_21 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[21];
 
 
--DD1_un1_pc_add21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add21 at LC_X23_Y9_N5
--operation mode is arithmetic
 
DD1_un1_pc_add21_carry_eqn = DD1_un1_pc_carry_20;
DD1_un1_pc_add21 = KB1_r32_o_21 $ DD1_un1_pc_prectl_1_0_a4[21] $ DD1_un1_pc_add21_carry_eqn;
 
--DD1_un1_pc_carry_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_21 at LC_X23_Y9_N5
--operation mode is arithmetic
 
DD1_un1_pc_carry_21_cout_0 = KB1_r32_o_21 & !DD1_un1_pc_prectl_1_0_a4[21] & !DD1_un1_pc_carry_20 # !KB1_r32_o_21 & !DD1_un1_pc_carry_20 # !DD1_un1_pc_prectl_1_0_a4[21];
DD1_un1_pc_carry_21 = CARRY(DD1_un1_pc_carry_21_cout_0);
 
--DD1L832 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_21~COUT1_1 at LC_X23_Y9_N5
--operation mode is arithmetic
 
DD1L832_cout_1 = KB1_r32_o_21 & !DD1_un1_pc_prectl_1_0_a4[21] & !DD1_un1_pc_carry_20 # !KB1_r32_o_21 & !DD1_un1_pc_carry_20 # !DD1_un1_pc_prectl_1_0_a4[21];
DD1L832 = CARRY(DD1L832_cout_1);
 
 
--KB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_18 at LC_X19_Y5_N9
--operation mode is normal
 
KB1_r32_o_18_lut_out = DD1_pc_next_0_iv_1_18 # DD1_un1_pc_next46_0 & DD1_un1_pc_add18;
KB1_r32_o_18 = DFFEAS(KB1_r32_o_18_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_19 at LC_X22_Y6_N7
--operation mode is normal
 
KB1_r32_o_19_lut_out = DD1_pc_next_0_iv_1_19 # DD1_un1_pc_next46_0 & DD1_un1_pc_add19;
KB1_r32_o_19 = DFFEAS(KB1_r32_o_19_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PB1_dout_iv_21 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_21 at LC_X20_Y7_N8
--operation mode is normal
 
PB1_dout_iv_21 = HD1_dout_iv_1_21 # HD1_dout7_0_a2 & FD1_wb_o_21;
 
--PB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_21 at LC_X20_Y7_N8
--operation mode is normal
 
PB1_r32_o_21 = DFFEAS(PB1_dout_iv_21, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un1_op2_reged_1_combout[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[19] at LC_X11_Y3_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[19] = VD1_eqop2_2_32 & VD1_op2_reged[19] # !VD1_eqop2_2_32 & VD1_nop2_reged[19];
 
 
--VD1_un59_hilo_add20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add20 at LC_X9_Y4_N4
--operation mode is arithmetic
 
VD1_un59_hilo_add20_carry_eqn = (!VD1_un59_hilo_carry_15 & VD1_un59_hilo_carry_19) # (VD1_un59_hilo_carry_15 & VD1L1681);
VD1_un59_hilo_add20 = VD1_op2_reged[20] $ VD1_hilo_52 $ !VD1_un59_hilo_add20_carry_eqn;
 
--VD1_un59_hilo_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_20 at LC_X9_Y4_N4
--operation mode is arithmetic
 
VD1_un59_hilo_carry_20 = CARRY(VD1_op2_reged[20] & VD1_hilo_52 # !VD1L1681 # !VD1_op2_reged[20] & VD1_hilo_52 & !VD1L1681);
 
 
--VD1_hilo_37_iv_0_1_a[52] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[52] at LC_X9_Y8_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[52] = VD1_hilo_20 & VD1_hilo_37_iv_0_o3_2[34] & !VD1_hilo_52 # !VD1_hilo_20 & VD1_hilo_0_sqmuxa # VD1_hilo_37_iv_0_o3_2[34] & !VD1_hilo_52;
 
 
--PB1_dout_iv_20 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_20 at LC_X21_Y7_N9
--operation mode is normal
 
PB1_dout_iv_20 = HD1_dout_iv_1_20 # FD1_wb_o_20 & HD1_dout7_0_a2;
 
--PB1_r32_o_20 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_20 at LC_X21_Y7_N9
--operation mode is normal
 
PB1_r32_o_20 = DFFEAS(PB1_dout_iv_20, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_37_iv_0_2[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[51] at LC_X5_Y5_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_2[51] = VD1_hilo_37_iv_0_2_a[51] # !VD1_hilo_51 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a3_4[62];
 
 
--VD1_hilo_37_iv_0_6_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[51] at LC_X5_Y5_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_6_a[51] = VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add20 # !VD1_hilo_52 # !VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add20;
 
 
--PD1_a_o_3_d_a[19] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[19] at LC_X22_Y6_N2
--operation mode is normal
 
PD1_a_o_3_d_a[19] = PD1_a_o_sn_m2 & !PB1_r32_o_19 # !PD1_a_o_sn_m2 & !AB1_r32_o_17;
 
 
--VD1_hilo_29_Z[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_29_Z[18] at LC_X3_Y16_N7
--operation mode is normal
 
VD1_hilo_29_Z[18] = VD1_add1 & VD1_un134_hilo_combout[18] # !VD1_add1 & VD1_hilo_18;
 
 
--VD1_hilo_37_iv_0_1_a[50] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1_a[50] at LC_X6_Y3_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_1_a[50] = VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add18 # !VD1_hilo_18 # !VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add18;
 
 
--VD1_un1_op2_reged_1_combout[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[18] at LC_X11_Y5_N2
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[18] = VD1_eqop2_2_32 & VD1_op2_reged[18] # !VD1_eqop2_2_32 & VD1_nop2_reged[18];
 
 
--PD1_a_o_3_d_a[18] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[18] at LC_X19_Y5_N1
--operation mode is normal
 
PD1_a_o_3_d_a[18] = PD1_a_o_sn_m2 & !PB1_r32_o_18 # !PD1_a_o_sn_m2 & !AB1_r32_o_16;
 
 
--VD1_un1_op2_reged_1_combout[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[26] at LC_X13_Y3_N9
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[26] = VD1_eqop2_2_32 & VD1_op2_reged[26] # !VD1_eqop2_2_32 & VD1_nop2_reged[26];
 
 
--VD1_hilo_24_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add25 at LC_X8_Y3_N9
--operation mode is arithmetic
 
VD1_hilo_24_add25_carry_eqn = (!VD1_hilo_24_carry_20 & VD1_hilo_24_carry_24) # (VD1_hilo_24_carry_20 & VD1L125);
VD1_hilo_24_add25 = VD1_un1_op2_reged_1_combout[25] $ VD1_hilo_56 $ VD1_hilo_24_add25_carry_eqn;
 
--VD1_hilo_24_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_25 at LC_X8_Y3_N9
--operation mode is arithmetic
 
VD1_hilo_24_carry_25 = CARRY(VD1_un1_op2_reged_1_combout[25] & !VD1_hilo_56 & !VD1L125 # !VD1_un1_op2_reged_1_combout[25] & !VD1L125 # !VD1_hilo_56);
 
 
--VD1_un50_hilo_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add27 at LC_X10_Y2_N1
--operation mode is arithmetic
 
VD1_un50_hilo_add27_carry_eqn = (!VD1_un50_hilo_carry_25 & VD1_un50_hilo_carry_26) # (VD1_un50_hilo_carry_25 & VD1L0571);
VD1_un50_hilo_add27 = VD1_nop2_reged[27] $ VD1_hilo_59 $ VD1_un50_hilo_add27_carry_eqn;
 
--VD1_un50_hilo_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_27 at LC_X10_Y2_N1
--operation mode is arithmetic
 
VD1_un50_hilo_carry_27_cout_0 = VD1_nop2_reged[27] & !VD1_hilo_59 & !VD1_un50_hilo_carry_26 # !VD1_nop2_reged[27] & !VD1_un50_hilo_carry_26 # !VD1_hilo_59;
VD1_un50_hilo_carry_27 = CARRY(VD1_un50_hilo_carry_27_cout_0);
 
--VD1L2571 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_27~COUT1_1 at LC_X10_Y2_N1
--operation mode is arithmetic
 
VD1L2571_cout_1 = VD1_nop2_reged[27] & !VD1_hilo_59 & !VD1L0571 # !VD1_nop2_reged[27] & !VD1L0571 # !VD1_hilo_59;
VD1L2571 = CARRY(VD1L2571_cout_1);
 
 
--VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_1_0_1_1_a[58] at LC_X5_Y3_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_1_0_1_1_a[58] = VD1_hilo_59 & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add27 # !VD1_hilo_59 & VD1_hilo_37_iv_0_a6_0_1[40] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add27;
 
 
--VD1_un59_hilo_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add26 at LC_X9_Y3_N0
--operation mode is arithmetic
 
VD1_un59_hilo_add26_carry_eqn = VD1_un59_hilo_carry_25;
VD1_un59_hilo_add26 = VD1_op2_reged[26] $ VD1_hilo_58 $ !VD1_un59_hilo_add26_carry_eqn;
 
--VD1_un59_hilo_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_26 at LC_X9_Y3_N0
--operation mode is arithmetic
 
VD1_un59_hilo_carry_26_cout_0 = VD1_op2_reged[26] & VD1_hilo_58 # !VD1_un59_hilo_carry_25 # !VD1_op2_reged[26] & VD1_hilo_58 & !VD1_un59_hilo_carry_25;
VD1_un59_hilo_carry_26 = CARRY(VD1_un59_hilo_carry_26_cout_0);
 
--VD1L3781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_26~COUT1_1 at LC_X9_Y3_N0
--operation mode is arithmetic
 
VD1L3781_cout_1 = VD1_op2_reged[26] & VD1_hilo_58 # !VD1_un59_hilo_carry_25 # !VD1_op2_reged[26] & VD1_hilo_58 & !VD1_un59_hilo_carry_25;
VD1L3781 = CARRY(VD1L3781_cout_1);
 
 
--VD1_un50_hilo_add26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add26 at LC_X10_Y2_N0
--operation mode is arithmetic
 
VD1_un50_hilo_add26_carry_eqn = VD1_un50_hilo_carry_25;
VD1_un50_hilo_add26 = VD1_hilo_58 $ VD1_nop2_reged[26] $ !VD1_un50_hilo_add26_carry_eqn;
 
--VD1_un50_hilo_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_26 at LC_X10_Y2_N0
--operation mode is arithmetic
 
VD1_un50_hilo_carry_26_cout_0 = VD1_hilo_58 & VD1_nop2_reged[26] # !VD1_un50_hilo_carry_25 # !VD1_hilo_58 & VD1_nop2_reged[26] & !VD1_un50_hilo_carry_25;
VD1_un50_hilo_carry_26 = CARRY(VD1_un50_hilo_carry_26_cout_0);
 
--VD1L0571 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_26~COUT1_1 at LC_X10_Y2_N0
--operation mode is arithmetic
 
VD1L0571_cout_1 = VD1_hilo_58 & VD1_nop2_reged[26] # !VD1_un50_hilo_carry_25 # !VD1_hilo_58 & VD1_nop2_reged[26] & !VD1_un50_hilo_carry_25;
VD1L0571 = CARRY(VD1L0571_cout_1);
 
 
--PD1_a_o_3_d_a[26] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[26] at LC_X21_Y10_N1
--operation mode is normal
 
PD1_a_o_3_d_a[26] = PD1_a_o_sn_m2 & !PB1_r32_o_26 # !PD1_a_o_sn_m2 & !AB1_r32_o_24;
 
 
--VD1_un1_op2_reged_1_combout[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[27] at LC_X8_Y2_N9
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[27] = VD1_eqop2_2_32 & VD1_op2_reged[27] # !VD1_eqop2_2_32 & VD1_nop2_reged[27];
 
 
--VD1_un50_hilo_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add28 at LC_X10_Y2_N2
--operation mode is arithmetic
 
VD1_un50_hilo_add28_carry_eqn = (!VD1_un50_hilo_carry_25 & VD1_un50_hilo_carry_27) # (VD1_un50_hilo_carry_25 & VD1L2571);
VD1_un50_hilo_add28 = VD1_nop2_reged[28] $ VD1_hilo_60 $ !VD1_un50_hilo_add28_carry_eqn;
 
--VD1_un50_hilo_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_28 at LC_X10_Y2_N2
--operation mode is arithmetic
 
VD1_un50_hilo_carry_28_cout_0 = VD1_nop2_reged[28] & VD1_hilo_60 # !VD1_un50_hilo_carry_27 # !VD1_nop2_reged[28] & VD1_hilo_60 & !VD1_un50_hilo_carry_27;
VD1_un50_hilo_carry_28 = CARRY(VD1_un50_hilo_carry_28_cout_0);
 
--VD1L4571 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_28~COUT1_1 at LC_X10_Y2_N2
--operation mode is arithmetic
 
VD1L4571_cout_1 = VD1_nop2_reged[28] & VD1_hilo_60 # !VD1L2571 # !VD1_nop2_reged[28] & VD1_hilo_60 & !VD1L2571;
VD1L4571 = CARRY(VD1L4571_cout_1);
 
 
--VD1_hilo_37_iv_0_3[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[59] at LC_X5_Y2_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_3[59] = VD1_hilo_37_iv_0_1[59] # VD1_hilo_37_iv_0_a5_0[59] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add28;
 
 
--VD1_hilo_37_iv_0_6_a[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[59] at LC_X5_Y2_N1
--operation mode is normal
 
VD1_hilo_37_iv_0_6_a[59] = VD1_un50_hilo_add27 & VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_hilo_60 # !VD1_un50_hilo_add27 & VD1_hilo_37_iv_0_a2_6_0[37] # VD1_hilo_37_iv_0_a6_0_1[40] & !VD1_hilo_60;
 
 
--PD1_a_o_3_d_a[27] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[27] at LC_X22_Y4_N5
--operation mode is normal
 
PD1_a_o_3_d_a[27] = PD1_a_o_sn_m2 & !PB1_r32_o_27 # !PD1_a_o_sn_m2 & !AB1_r32_o_25;
 
 
--PD1_a_o_3_d_a[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[28] at LC_X26_Y8_N5
--operation mode is normal
 
PD1_a_o_3_d_a[28] = PD1_a_o_sn_m2 & !PB1_r32_o_28 # !PD1_a_o_sn_m2 & !AB1_r32_o_26;
 
 
--VD1_hilo_37_iv_0_a[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[60] at LC_X5_Y3_N0
--operation mode is normal
 
VD1_hilo_37_iv_0_a[60] = !VD1_hilo_37_iv_0_6[60] & VD1_hilo_24_add28 # !VD1_hilo_2_sqmuxa;
 
 
--VD1_hilo_37_iv_0_3[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[61] at LC_X7_Y3_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_3[61] = VD1_hilo_37_iv_0_1[61] # VD1_hilo_37_iv_0_a5_0[61] # !VD1_un59_hilo_add30 & VD1_hilo_37_iv_0_a6_1_0[40];
 
 
--VD1_hilo_37_iv_0_6_a[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[61] at LC_X7_Y3_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_6_a[61] = VD1_hilo_62 & !VD1_un50_hilo_add29 & VD1_hilo_37_iv_0_a2_6_0[37] # !VD1_hilo_62 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_un50_hilo_add29 & VD1_hilo_37_iv_0_a2_6_0[37];
 
 
--VD1_un59_hilo_add13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add13 at LC_X9_Y5_N7
--operation mode is arithmetic
 
VD1_un59_hilo_add13_carry_eqn = (!VD1_un59_hilo_carry_10 & VD1_un59_hilo_carry_12) # (VD1_un59_hilo_carry_10 & VD1L8481);
VD1_un59_hilo_add13 = VD1_hilo_45 $ VD1_op2_reged[13] $ VD1_un59_hilo_add13_carry_eqn;
 
--VD1_un59_hilo_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_13 at LC_X9_Y5_N7
--operation mode is arithmetic
 
VD1_un59_hilo_carry_13_cout_0 = VD1_hilo_45 & !VD1_op2_reged[13] & !VD1_un59_hilo_carry_12 # !VD1_hilo_45 & !VD1_un59_hilo_carry_12 # !VD1_op2_reged[13];
VD1_un59_hilo_carry_13 = CARRY(VD1_un59_hilo_carry_13_cout_0);
 
--VD1L0581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_13~COUT1_1 at LC_X9_Y5_N7
--operation mode is arithmetic
 
VD1L0581_cout_1 = VD1_hilo_45 & !VD1_op2_reged[13] & !VD1L8481 # !VD1_hilo_45 & !VD1L8481 # !VD1_op2_reged[13];
VD1L0581 = CARRY(VD1L0581_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[13] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[13] at LC_X11_Y2_N9
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[13] = VD1_eqop2_2_32 & VD1_op2_reged[13] # !VD1_eqop2_2_32 & VD1_nop2_reged[13];
 
 
--DD1_pc_next_0_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_13 at LC_X24_Y9_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_13 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_13 # !DD1_pc_next_0_iv_1_a[13];
 
 
--DD1_un1_pc_add13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add13 at LC_X23_Y10_N7
--operation mode is arithmetic
 
DD1_un1_pc_add13_carry_eqn = (!DD1_un1_pc_carry_10 & DD1_un1_pc_carry_12) # (DD1_un1_pc_carry_10 & DD1L222);
DD1_un1_pc_add13 = DD1_un1_pc_prectl_1_0_a4[13] $ KB1_r32_o_13 $ DD1_un1_pc_add13_carry_eqn;
 
--DD1_un1_pc_carry_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_13 at LC_X23_Y10_N7
--operation mode is arithmetic
 
DD1_un1_pc_carry_13_cout_0 = DD1_un1_pc_prectl_1_0_a4[13] & !KB1_r32_o_13 & !DD1_un1_pc_carry_12 # !DD1_un1_pc_prectl_1_0_a4[13] & !DD1_un1_pc_carry_12 # !KB1_r32_o_13;
DD1_un1_pc_carry_13 = CARRY(DD1_un1_pc_carry_13_cout_0);
 
--DD1L422 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_13~COUT1_1 at LC_X23_Y10_N7
--operation mode is arithmetic
 
DD1L422_cout_1 = DD1_un1_pc_prectl_1_0_a4[13] & !KB1_r32_o_13 & !DD1L222 # !DD1_un1_pc_prectl_1_0_a4[13] & !DD1L222 # !KB1_r32_o_13;
DD1L422 = CARRY(DD1L422_cout_1);
 
 
--PB1_dout_iv_13 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_13 at LC_X26_Y11_N6
--operation mode is normal
 
PB1_dout_iv_13 = HD1_dout_iv_1_13 # HD1_dout7_0_a2 & FD1_wb_o_13;
 
--PB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_13 at LC_X26_Y11_N6
--operation mode is normal
 
PB1_r32_o_13 = DFFEAS(PB1_dout_iv_13, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_30 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_30 at LC_X22_Y8_N8
--operation mode is normal
 
HD1_dout_iv_1_30 = FD1_N_18_i_0_s3 & LD2_q_b[30] # !HD1_dout_iv_1_a[30];
 
 
--VD1_nop2_reged[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[28] at LC_X13_Y3_N6
--operation mode is arithmetic
 
VD1_nop2_reged[28]_carry_eqn = (!VD1_nop2_reged_cout[24] & VD1_nop2_reged_cout[26]) # (VD1_nop2_reged_cout[24] & VD1L7531);
VD1_nop2_reged[28] = VD1_op2_reged[28] $ VD1_nop2_reged[28]_carry_eqn;
 
--VD1_nop2_reged_cout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[28] at LC_X13_Y3_N6
--operation mode is arithmetic
 
VD1_nop2_reged_cout[28]_cout_0 = !VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1_nop2_reged_cout[26];
VD1_nop2_reged_cout[28] = CARRY(VD1_nop2_reged_cout[28]_cout_0);
 
--VD1L1631 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[28]~COUT1_24 at LC_X13_Y3_N6
--operation mode is arithmetic
 
VD1L1631_cout_1 = !VD1_op2_reged[29] & !VD1_op2_reged[28] & !VD1L7531;
VD1L1631 = CARRY(VD1L1631_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[28] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[28] at LC_X8_Y2_N8
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[28] = VD1_eqop2_2_32 & VD1_op2_reged[28] # !VD1_eqop2_2_32 & VD1_nop2_reged[28];
 
 
--VD1_un59_hilo_add28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add28 at LC_X9_Y3_N2
--operation mode is arithmetic
 
VD1_un59_hilo_add28_carry_eqn = (!VD1_un59_hilo_carry_25 & VD1_un59_hilo_carry_27) # (VD1_un59_hilo_carry_25 & VD1L5781);
VD1_un59_hilo_add28 = VD1_op2_reged[28] $ VD1_hilo_60 $ !VD1_un59_hilo_add28_carry_eqn;
 
--VD1_un59_hilo_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_28 at LC_X9_Y3_N2
--operation mode is arithmetic
 
VD1_un59_hilo_carry_28_cout_0 = VD1_op2_reged[28] & VD1_hilo_60 # !VD1_un59_hilo_carry_27 # !VD1_op2_reged[28] & VD1_hilo_60 & !VD1_un59_hilo_carry_27;
VD1_un59_hilo_carry_28 = CARRY(VD1_un59_hilo_carry_28_cout_0);
 
--VD1L7781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_28~COUT1_1 at LC_X9_Y3_N2
--operation mode is arithmetic
 
VD1L7781_cout_1 = VD1_op2_reged[28] & VD1_hilo_60 # !VD1L5781 # !VD1_op2_reged[28] & VD1_hilo_60 & !VD1L5781;
VD1L7781 = CARRY(VD1L7781_cout_1);
 
 
--UD1_shift_out_68[30] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_68[30] at LC_X6_Y17_N1
--operation mode is normal
 
UD1_shift_out_68[30] = PD1_a_o_0 & VD1_b_o_iv_27 # !PD1_a_o_0 & VD1_b_o_iv_28;
 
 
--VD1_un50_hilo_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add12 at LC_X10_Y4_N6
--operation mode is arithmetic
 
VD1_un50_hilo_add12_carry_eqn = (!VD1_un50_hilo_carry_10 & VD1_un50_hilo_carry_11) # (VD1_un50_hilo_carry_10 & VD1L3271);
VD1_un50_hilo_add12 = VD1_nop2_reged[12] $ VD1_hilo_44 $ !VD1_un50_hilo_add12_carry_eqn;
 
--VD1_un50_hilo_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_12 at LC_X10_Y4_N6
--operation mode is arithmetic
 
VD1_un50_hilo_carry_12_cout_0 = VD1_nop2_reged[12] & VD1_hilo_44 # !VD1_un50_hilo_carry_11 # !VD1_nop2_reged[12] & VD1_hilo_44 & !VD1_un50_hilo_carry_11;
VD1_un50_hilo_carry_12 = CARRY(VD1_un50_hilo_carry_12_cout_0);
 
--VD1L5271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_12~COUT1_1 at LC_X10_Y4_N6
--operation mode is arithmetic
 
VD1L5271_cout_1 = VD1_nop2_reged[12] & VD1_hilo_44 # !VD1L3271 # !VD1_nop2_reged[12] & VD1_hilo_44 & !VD1L3271;
VD1L5271 = CARRY(VD1L5271_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[12] at LC_X7_Y5_N0
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[12] = VD1_eqop2_2_32 & VD1_op2_reged[12] # !VD1_eqop2_2_32 & VD1_nop2_reged[12];
 
 
--VD1_hilo_37_iv_0_o3_0_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_o3_0_a[44] at LC_X8_Y11_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_o3_0_a[44] = VD1_hilo_12 & !VD1_hilo_45 & VD1_hilo_37_iv_0_a6_0_1[40] # !VD1_hilo_12 & VD1_hilo_0_sqmuxa # !VD1_hilo_45 & VD1_hilo_37_iv_0_a6_0_1[40];
 
 
--VD1_hilo_37_iv_0_2_a[44] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[44] at LC_X7_Y5_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_2_a[44] = VD1_un59_hilo_add12 & VD1_hilo_37_iv_0_o3_2[34] & !VD1_hilo_44 # !VD1_un59_hilo_add12 & VD1_hilo_37_iv_0_a3_2[62] # VD1_hilo_37_iv_0_o3_2[34] & !VD1_hilo_44;
 
 
--PD1_a_o_3_d_a[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[12] at LC_X23_Y12_N6
--operation mode is normal
 
PD1_a_o_3_d_a[12] = PD1_a_o_sn_m2 & !PB1_r32_o_12 # !PD1_a_o_sn_m2 & !AB1_r32_o_10;
 
 
--VD1_hilo_37_iv_0_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a[24] at LC_X4_Y9_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_a[24] = VD1_add1 & !VD1_un134_hilo_combout[24] # !VD1_add1 & !VD1_hilo_24;
 
 
--VD1_hilo_33_i_m_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[56] at LC_X4_Y7_N1
--operation mode is normal
 
VD1_hilo_33_i_m_a[56] = VD1_addnop2 & !VD1_un50_hilo_add24 # !VD1_addnop2 & !VD1_un59_hilo_add24;
 
 
--VD1_hilo_24_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add24 at LC_X8_Y3_N8
--operation mode is arithmetic
 
VD1_hilo_24_add24_carry_eqn = (!VD1_hilo_24_carry_20 & VD1_hilo_24_carry_23) # (VD1_hilo_24_carry_20 & VD1L915);
VD1_hilo_24_add24 = VD1_hilo_55 $ VD1_un1_op2_reged_1_combout[24] $ !VD1_hilo_24_add24_carry_eqn;
 
--VD1_hilo_24_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_24 at LC_X8_Y3_N8
--operation mode is arithmetic
 
VD1_hilo_24_carry_24_cout_0 = VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] # !VD1_hilo_24_carry_23 # !VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] & !VD1_hilo_24_carry_23;
VD1_hilo_24_carry_24 = CARRY(VD1_hilo_24_carry_24_cout_0);
 
--VD1L125 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_24~COUT1_1 at LC_X8_Y3_N8
--operation mode is arithmetic
 
VD1L125_cout_1 = VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] # !VD1L915 # !VD1_hilo_55 & VD1_un1_op2_reged_1_combout[24] & !VD1L915;
VD1L125 = CARRY(VD1L125_cout_1);
 
 
--VD1_hilo_22_a[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[56] at LC_X4_Y7_N2
--operation mode is normal
 
VD1_hilo_22_a[56] = VD1_hilo[0] & VD1_sign & !VD1_hilo_57 # !VD1_sign & !VD1_un59_hilo_add25 # !VD1_hilo[0] & !VD1_hilo_57;
 
 
--VD1_hilo_15_2[56] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[56] at LC_X4_Y6_N2
--operation mode is normal
 
VD1_hilo_15_2[56] = VD1_sub_or_yn & VD1_un59_hilo_add25 # !VD1_sub_or_yn & VD1_un50_hilo_add25;
 
 
--KB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_24 at LC_X20_Y3_N8
--operation mode is normal
 
KB1_r32_o_24_lut_out = DD1_pc_next_0_iv_1_24 # DD1_un1_pc_next46_0 & DD1_un1_pc_add24;
KB1_r32_o_24 = DFFEAS(KB1_r32_o_24_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_25 at LC_X24_Y6_N7
--operation mode is normal
 
KB1_r32_o_25_lut_out = DD1_pc_next_0_iv_1_25 # DD1_un1_pc_next46_0 & DD1_un1_pc_add25;
KB1_r32_o_25 = DFFEAS(KB1_r32_o_25_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d_a[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[24] at LC_X20_Y3_N1
--operation mode is normal
 
PD1_a_o_3_d_a[24] = PD1_a_o_sn_m2 & !PB1_r32_o_24 # !PD1_a_o_sn_m2 & !AB1_r32_o_22;
 
 
--VD1_un134_hilo_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_combout[23] at LC_X4_Y15_N3
--operation mode is arithmetic
 
VD1_un134_hilo_combout[23]_carry_eqn = (!VD1_un134_hilo_cout[15] & VD1_un134_hilo_cout[21]) # (VD1_un134_hilo_cout[15] & VD1L7891);
VD1_un134_hilo_combout[23] = VD1_hilo_23 $ (VD1_hilo_22 & VD1_un134_hilo_combout[23]_carry_eqn);
 
--VD1_un134_hilo_cout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[23] at LC_X4_Y15_N3
--operation mode is arithmetic
 
VD1_un134_hilo_cout[23]_cout_0 = !VD1_un134_hilo_cout[21] # !VD1_hilo_23 # !VD1_hilo_22;
VD1_un134_hilo_cout[23] = CARRY(VD1_un134_hilo_cout[23]_cout_0);
 
--VD1L1991 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un134_hilo_cout[23]~COUT1_10 at LC_X4_Y15_N3
--operation mode is arithmetic
 
VD1L1991_cout_1 = !VD1L7891 # !VD1_hilo_23 # !VD1_hilo_22;
VD1L1991 = CARRY(VD1L1991_cout_1);
 
 
--VD1_hilo_37_iv_0_2[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2[57] at LC_X4_Y6_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_2[57] = VD1_hilo_37_iv_0_2_a[57] # !VD1_hilo_57 & VD1_hilo_37_iv_0_a3_1[62] # VD1_hilo_37_iv_0_a3_4[62];
 
 
--VD1_un50_hilo_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add25 at LC_X10_Y3_N9
--operation mode is arithmetic
 
VD1_un50_hilo_add25_carry_eqn = (!VD1_un50_hilo_carry_20 & VD1_un50_hilo_carry_24) # (VD1_un50_hilo_carry_20 & VD1L7471);
VD1_un50_hilo_add25 = VD1_nop2_reged[25] $ VD1_hilo_57 $ VD1_un50_hilo_add25_carry_eqn;
 
--VD1_un50_hilo_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_25 at LC_X10_Y3_N9
--operation mode is arithmetic
 
VD1_un50_hilo_carry_25 = CARRY(VD1_nop2_reged[25] & !VD1_hilo_57 & !VD1L7471 # !VD1_nop2_reged[25] & !VD1L7471 # !VD1_hilo_57);
 
 
--VD1_hilo_37_iv_0_5_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_5_a[57] at LC_X4_Y6_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_5_a[57] = VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add26 # !VD1_hilo_58 # !VD1_hilo_37_iv_0_a6_0_1[40] & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add26;
 
 
--PD1_a_o_3_d_a[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[25] at LC_X24_Y6_N1
--operation mode is normal
 
PD1_a_o_3_d_a[25] = PD1_a_o_sn_m2 & !PB1_r32_o_25 # !PD1_a_o_sn_m2 & !AB1_r32_o_23;
 
 
--VD1_un59_hilo_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add23 at LC_X9_Y4_N7
--operation mode is arithmetic
 
VD1_un59_hilo_add23_carry_eqn = (!VD1_un59_hilo_carry_20 & VD1_un59_hilo_carry_22) # (VD1_un59_hilo_carry_20 & VD1L6681);
VD1_un59_hilo_add23 = VD1_hilo_55 $ VD1_op2_reged[23] $ VD1_un59_hilo_add23_carry_eqn;
 
--VD1_un59_hilo_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_23 at LC_X9_Y4_N7
--operation mode is arithmetic
 
VD1_un59_hilo_carry_23_cout_0 = VD1_hilo_55 & !VD1_op2_reged[23] & !VD1_un59_hilo_carry_22 # !VD1_hilo_55 & !VD1_un59_hilo_carry_22 # !VD1_op2_reged[23];
VD1_un59_hilo_carry_23 = CARRY(VD1_un59_hilo_carry_23_cout_0);
 
--VD1L8681 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_23~COUT1_1 at LC_X9_Y4_N7
--operation mode is arithmetic
 
VD1L8681_cout_1 = VD1_hilo_55 & !VD1_op2_reged[23] & !VD1L6681 # !VD1_hilo_55 & !VD1L6681 # !VD1_op2_reged[23];
VD1L8681 = CARRY(VD1L8681_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[22] at LC_X14_Y4_N4
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[22] = VD1_eqop2_2_32 & VD1_op2_reged[22] # !VD1_eqop2_2_32 & VD1_nop2_reged[22];
 
 
--KB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_22 at LC_X24_Y5_N0
--operation mode is normal
 
KB1_r32_o_22_lut_out = DD1_pc_next_0_iv_1_22 # DD1_un1_pc_next46_0 & DD1_un1_pc_add22;
KB1_r32_o_22 = DFFEAS(KB1_r32_o_22_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--KB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_6:pc|r32_o_23 at LC_X22_Y3_N9
--operation mode is normal
 
KB1_r32_o_23_lut_out = DD1_pc_next_0_iv_1_23 # DD1_un1_pc_next46_0 & DD1_un1_pc_add23;
KB1_r32_o_23 = DFFEAS(KB1_r32_o_23_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PD1_a_o_3_d_a[22] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[22] at LC_X24_Y5_N1
--operation mode is normal
 
PD1_a_o_3_d_a[22] = PD1_a_o_sn_m2 & !PB1_r32_o_22 # !PD1_a_o_sn_m2 & !AB1_r32_o_20;
 
 
--VD1_hilo_33_i_m_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_33_i_m_a[55] at LC_X5_Y4_N6
--operation mode is normal
 
VD1_hilo_33_i_m_a[55] = VD1_addnop2 & !VD1_un50_hilo_add23 # !VD1_addnop2 & !VD1_un59_hilo_add23;
 
 
--VD1_hilo_24_add23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_add23 at LC_X8_Y3_N7
--operation mode is arithmetic
 
VD1_hilo_24_add23_carry_eqn = (!VD1_hilo_24_carry_20 & VD1_hilo_24_carry_22) # (VD1_hilo_24_carry_20 & VD1L715);
VD1_hilo_24_add23 = VD1_hilo_54 $ VD1_un1_op2_reged_1_combout[23] $ VD1_hilo_24_add23_carry_eqn;
 
--VD1_hilo_24_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_23 at LC_X8_Y3_N7
--operation mode is arithmetic
 
VD1_hilo_24_carry_23_cout_0 = VD1_hilo_54 & !VD1_un1_op2_reged_1_combout[23] & !VD1_hilo_24_carry_22 # !VD1_hilo_54 & !VD1_hilo_24_carry_22 # !VD1_un1_op2_reged_1_combout[23];
VD1_hilo_24_carry_23 = CARRY(VD1_hilo_24_carry_23_cout_0);
 
--VD1L915 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_24_carry_23~COUT1_1 at LC_X8_Y3_N7
--operation mode is arithmetic
 
VD1L915_cout_1 = VD1_hilo_54 & !VD1_un1_op2_reged_1_combout[23] & !VD1L715 # !VD1_hilo_54 & !VD1L715 # !VD1_un1_op2_reged_1_combout[23];
VD1L915 = CARRY(VD1L915_cout_1);
 
 
--VD1_hilo_22_a[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_22_a[55] at LC_X4_Y7_N6
--operation mode is normal
 
VD1_hilo_22_a[55] = VD1_hilo[0] & VD1_sign & !VD1_hilo_56 # !VD1_sign & !VD1_un59_hilo_add24 # !VD1_hilo[0] & !VD1_hilo_56;
 
 
--VD1_hilo_15_2[55] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_15_2[55] at LC_X4_Y7_N3
--operation mode is normal
 
VD1_hilo_15_2[55] = VD1_sub_or_yn & VD1_un59_hilo_add24 # !VD1_sub_or_yn & VD1_un50_hilo_add24;
 
 
--PD1_a_o_3_d_a[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3_d_a[23] at LC_X22_Y3_N5
--operation mode is normal
 
PD1_a_o_3_d_a[23] = PD1_a_o_sn_m2 & !PB1_r32_o_23 # !PD1_a_o_sn_m2 & !AB1_r32_o_21;
 
 
--UB1_dout_2_i_i_x[22] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[22] at LC_X25_Y13_N6
--operation mode is normal
 
UB1_dout_2_i_i_x[22] = UB1_dout_2_i_i_a2[16] # JE1_q_b[6] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB72L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_22__Z|lpm_latch:U1|q[0]~56 at LC_X25_Y13_N3
--operation mode is normal
 
WB72L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[22] # !UB1_un1_byte_addr_2 & WB72L1;
 
--DB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_22 at LC_X25_Y13_N3
--operation mode is normal
 
DB1_r32_o_22 = DFFEAS(WB72L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[21] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[21] at LC_X30_Y7_N3
--operation mode is normal
 
UB1_dout_2_i_i_x[21] = UB1_dout_2_i_i_a2[16] # JE1_q_b[5] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB62L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_21__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y7_N8
--operation mode is normal
 
WB62L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[21] # !UB1_un1_byte_addr_2 & WB62L1;
 
--DB1_r32_o_21 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_21 at LC_X30_Y7_N8
--operation mode is normal
 
DB1_r32_o_21 = DFFEAS(WB62L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[19] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[19] at LC_X30_Y15_N7
--operation mode is normal
 
UB1_dout_2_i_i_x[19] = UB1_dout_2_i_i_a2[16] # JE1_q_b[3] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB42L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_19__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y15_N8
--operation mode is normal
 
WB42L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[19] # !UB1_un1_byte_addr_2 & WB42L1;
 
--DB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_19 at LC_X30_Y15_N8
--operation mode is normal
 
DB1_r32_o_19 = DFFEAS(WB42L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[18] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[18] at LC_X30_Y9_N4
--operation mode is normal
 
UB1_dout_2_i_i_x[18] = UB1_dout_2_i_i_a2[16] # JE1_q_b[2] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB32L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_18__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y9_N5
--operation mode is normal
 
WB32L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[18] # !UB1_un1_byte_addr_2 & WB32L1;
 
--DB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_18 at LC_X30_Y9_N5
--operation mode is normal
 
DB1_r32_o_18 = DFFEAS(WB32L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[17] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[17] at LC_X26_Y6_N3
--operation mode is normal
 
UB1_dout_2_i_i_x[17] = UB1_dout_2_i_i_a2[16] # JE1_q_b[1] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB22L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_17__Z|lpm_latch:U1|q[0]~56 at LC_X26_Y6_N4
--operation mode is normal
 
WB22L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[17] # !UB1_un1_byte_addr_2 & WB22L1;
 
--DB1_r32_o_17 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_17 at LC_X26_Y6_N4
--operation mode is normal
 
DB1_r32_o_17 = DFFEAS(WB22L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[16] at LC_X30_Y7_N0
--operation mode is normal
 
UB1_dout_2_i_i_x[16] = UB1_dout_2_i_i_a2[16] # JE1_q_b[0] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB12L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_16__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y7_N2
--operation mode is normal
 
WB12L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[16] # !UB1_un1_byte_addr_2 & WB12L1;
 
--DB1_r32_o_16 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_16 at LC_X30_Y7_N2
--operation mode is normal
 
DB1_r32_o_16 = DFFEAS(WB12L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[29] at LC_X23_Y16_N0
--operation mode is normal
 
ED1_r32_o_13_qfbk = ED1_r32_o_13;
DD1_un1_pc_prectl_1_0_a4[29] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_13_qfbk;
 
--ED1_r32_o_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_13 at LC_X23_Y16_N0
--operation mode is normal
 
ED1_r32_o_13 = DFFEAS(DD1_un1_pc_prectl_1_0_a4[29], GLOBAL(E1__clk0), VCC, , C1_G_504, HE1_q_a[5], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--DD1_pc_next_0_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[28] at LC_X21_Y10_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[28] = DD1_pc_next_1_sqmuxa_0_a4 & !KB1_r32_o_28 & !SD1_r32_o_28 # !DD1_pc_next_0_sqmuxa_0_a4 # !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_28 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--PB1_dout_iv_28 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_28 at LC_X26_Y8_N4
--operation mode is normal
 
PB1_dout_iv_28 = HD1_dout_iv_1_28 # FD1_wb_o_28 & HD1_dout7_0_a2;
 
--PB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_28 at LC_X26_Y8_N4
--operation mode is normal
 
PB1_r32_o_28 = DFFEAS(PB1_dout_iv_28, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_un1_pc_prectl_1_0_a4[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[28] at LC_X23_Y16_N1
--operation mode is normal
 
ED1_r32_o_12_qfbk = ED1_r32_o_12;
DD1_un1_pc_prectl_1_0_a4[28] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_a3_0 # CD1_res_7_0_0_a2_16 & ED1_r32_o_12_qfbk;
 
--ED1_r32_o_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_12 at LC_X23_Y16_N1
--operation mode is normal
 
ED1_r32_o_12 = DFFEAS(DD1_un1_pc_prectl_1_0_a4[28], GLOBAL(E1__clk0), VCC, , C1_G_504, HE1_q_a[4], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--DD1_un1_pc_add27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add27 at LC_X23_Y8_N1
--operation mode is arithmetic
 
DD1_un1_pc_add27_carry_eqn = (!DD1_un1_pc_carry_25 & DD1_un1_pc_carry_26) # (DD1_un1_pc_carry_25 & DD1L742);
DD1_un1_pc_add27 = KB1_r32_o_27 $ DD1_un1_pc_prectl_1_0_a4[27] $ DD1_un1_pc_add27_carry_eqn;
 
--DD1_un1_pc_carry_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_27 at LC_X23_Y8_N1
--operation mode is arithmetic
 
DD1_un1_pc_carry_27_cout_0 = KB1_r32_o_27 & !DD1_un1_pc_prectl_1_0_a4[27] & !DD1_un1_pc_carry_26 # !KB1_r32_o_27 & !DD1_un1_pc_carry_26 # !DD1_un1_pc_prectl_1_0_a4[27];
DD1_un1_pc_carry_27 = CARRY(DD1_un1_pc_carry_27_cout_0);
 
--DD1L942 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_27~COUT1_1 at LC_X23_Y8_N1
--operation mode is arithmetic
 
DD1L942_cout_1 = KB1_r32_o_27 & !DD1_un1_pc_prectl_1_0_a4[27] & !DD1L742 # !KB1_r32_o_27 & !DD1L742 # !DD1_un1_pc_prectl_1_0_a4[27];
DD1L942 = CARRY(DD1L942_cout_1);
 
 
--DD1_pc_next_0_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[29] at LC_X22_Y6_N1
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[29] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_29 & !DD1_pc_next_1_sqmuxa_0_a4 # !KB1_r32_o_29 # !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !KB1_r32_o_29;
 
 
--PB1_dout_iv_29 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_29 at LC_X26_Y11_N1
--operation mode is normal
 
PB1_dout_iv_29 = HD1_dout_iv_1_29 # HD1_dout7_0_a2 & FD1_wb_o_29;
 
--PB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_29 at LC_X26_Y11_N1
--operation mode is normal
 
PB1_r32_o_29 = DFFEAS(PB1_dout_iv_29, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_pc_next_0_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_26 at LC_X21_Y10_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_26 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_26 # !DD1_pc_next_0_iv_1_a[26];
 
 
--DD1_un1_pc_add26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add26 at LC_X23_Y8_N0
--operation mode is arithmetic
 
DD1_un1_pc_add26_carry_eqn = DD1_un1_pc_carry_25;
DD1_un1_pc_add26 = KB1_r32_o_26 $ DD1_un1_pc_prectl_1_0_a4[26] $ !DD1_un1_pc_add26_carry_eqn;
 
--DD1_un1_pc_carry_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_26 at LC_X23_Y8_N0
--operation mode is arithmetic
 
DD1_un1_pc_carry_26_cout_0 = KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] # !DD1_un1_pc_carry_25 # !KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] & !DD1_un1_pc_carry_25;
DD1_un1_pc_carry_26 = CARRY(DD1_un1_pc_carry_26_cout_0);
 
--DD1L742 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_26~COUT1_1 at LC_X23_Y8_N0
--operation mode is arithmetic
 
DD1L742_cout_1 = KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] # !DD1_un1_pc_carry_25 # !KB1_r32_o_26 & DD1_un1_pc_prectl_1_0_a4[26] & !DD1_un1_pc_carry_25;
DD1L742 = CARRY(DD1L742_cout_1);
 
 
--DD1_pc_next_0_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_27 at LC_X22_Y4_N8
--operation mode is normal
 
DD1_pc_next_0_iv_1_27 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_27 # !DD1_pc_next_0_iv_1_a[27];
 
 
--UB1_dout_2_i_i_a3_0[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_0[16] at LC_X31_Y9_N6
--operation mode is normal
 
UB1_dout_2_i_i_a3_0[16] = RB1_ctl_o_1 & RB1_ctl_o_2 & RB1_byte_addr_o_0 # !RB1_ctl_o_3;
 
 
--UB1_dout_2_i_i_a2[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2[16] at LC_X29_Y13_N6
--operation mode is normal
 
UB1_dout_2_i_i_a2[16] = !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # UB1_dout_2_i_i_a2_a[16] & UB1_dout_2_i_i_a3_1[15];
 
 
--UB1_un1_ctl_6_2_0_a is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|un1_ctl_6_2_0_a at LC_X31_Y9_N9
--operation mode is normal
 
UB1_un1_ctl_6_2_0_a = RB1_ctl_o_3 & !RB1_ctl_o_1 & !RB1_ctl_o_2 # !RB1_ctl_o_3 & RB1_ctl_o_1;
 
 
--UB1_dout_2_i_i_x[30] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[30] at LC_X32_Y13_N0
--operation mode is normal
 
UB1_dout_2_i_i_x[30] = UB1_dout_2_i_i_a2[16] # KE1_q_b[6] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB53L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_30__Z|lpm_latch:U1|q[0]~56 at LC_X32_Y13_N6
--operation mode is normal
 
WB53L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[30] # !UB1_un1_byte_addr_2 & WB53L1;
 
--DB1_r32_o_30 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_30 at LC_X32_Y13_N6
--operation mode is normal
 
DB1_r32_o_30 = DFFEAS(WB53L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--TD1_lt_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_24 at LC_X16_Y8_N8
--operation mode is arithmetic
 
TD1_lt_24_cout_0 = VD1_b_o_iv_24 & !TD1_lt_23 # !PD1_a_o_24 # !VD1_b_o_iv_24 & !PD1_a_o_24 & !TD1_lt_23;
TD1_lt_24 = CARRY(TD1_lt_24_cout_0);
 
--TD1L781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_24~COUT1_1 at LC_X16_Y8_N8
--operation mode is arithmetic
 
TD1L781_cout_1 = VD1_b_o_iv_24 & !TD1L581 # !PD1_a_o_24 # !VD1_b_o_iv_24 & !PD1_a_o_24 & !TD1L581;
TD1L781 = CARRY(TD1L781_cout_1);
 
 
--TD1_sum_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_25 at LC_X15_Y7_N9
--operation mode is arithmetic
 
TD1_sum_carry_25 = CARRY(VD1_b_o_iv_25 & !TD1L234 # !PD1_a_o_25 # !VD1_b_o_iv_25 & !PD1_a_o_25 & !TD1L234);
 
 
--UB1_dout_2_i_i_x[28] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[28] at LC_X30_Y7_N7
--operation mode is normal
 
UB1_dout_2_i_i_x[28] = UB1_dout_2_i_i_a2[16] # KE1_q_b[4] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB33L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_28__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y7_N6
--operation mode is normal
 
WB33L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[28] # !UB1_un1_byte_addr_2 & WB33L1;
 
--DB1_r32_o_28 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_28 at LC_X30_Y7_N6
--operation mode is normal
 
DB1_r32_o_28 = DFFEAS(WB33L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[29] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[29] at LC_X26_Y5_N7
--operation mode is normal
 
UB1_dout_2_i_i_x[29] = UB1_dout_2_i_i_a2[16] # KE1_q_b[5] & UB1_dout_2_i_i_a3_0[16];
 
 
--WB43L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_29__Z|lpm_latch:U1|q[0]~56 at LC_X26_Y5_N6
--operation mode is normal
 
WB43L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[29] # !UB1_un1_byte_addr_2 & WB43L1;
 
--DB1_r32_o_29 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_29 at LC_X26_Y5_N6
--operation mode is normal
 
DB1_r32_o_29 = DFFEAS(WB43L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_0_0_o2_0_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_0_a[9] at LC_X29_Y9_N3
--operation mode is normal
 
UB1_dout_2_0_0_o2_0_a[9] = RB1_ctl_o_1 & !RB1_ctl_o_3 # !RB1_ctl_o_1 & RB1_ctl_o_2;
 
 
--UB1_dout_2_0_0_o2_1[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_1[9] at LC_X31_Y9_N8
--operation mode is normal
 
UB1_dout_2_0_0_o2_1[9] = RB1_ctl_o_2 & RB1_ctl_o_1 & RB1_byte_addr_o_0 # !UB1_dout_2_0_0_o2_1_a[9] # !RB1_ctl_o_2 & !RB1_byte_addr_o_0 & !UB1_dout_2_0_0_o2_1_a[9];
 
 
--UB1_dout_2_0_0_a2_1_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a2_1_a[9] at LC_X32_Y14_N4
--operation mode is normal
 
UB1_dout_2_0_0_a2_1_a[9] = RB1_ctl_o_1 & !RB1_ctl_o_3;
 
 
--UB1_dout_2_i_i_a3[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3[15] at LC_X29_Y8_N5
--operation mode is normal
 
UB1_dout_2_i_i_a3[15] = RB1_byte_addr_o_0 & RB1_ctl_o_1 & !UB1_dout_2_i_i_a3_a_x[15];
 
 
--UB1_dout_2_i_i_a3_1[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_1[15] at LC_X29_Y13_N4
--operation mode is normal
 
UB1_dout_2_i_i_a3_1[15] = !RB1_byte_addr_o_0 & RB1_byte_addr_o_1 & HE1_q_b[7] # !RB1_byte_addr_o_1 & KE1_q_b[7];
 
 
--YB1_pc_gen_ctl_2_i_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a[2] at LC_X26_Y13_N4
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a[2] = !WB26L2 & YB1_cmp_ctl_2_0_0_a2_0[0] # KE1_q_a[2] & YB1_alu_we_1s_1_o2_0_x[0];
 
 
--YB1_pc_gen_ctl_2_i_0_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_5[2] at LC_X27_Y17_N6
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_5[2] = YB1_pc_gen_ctl_2_i_0_1_x[2] # YB1_pc_gen_ctl_2_i_0_a3_5[2] # YB1_pc_gen_ctl_2_i_0_a3[2] # !YB1_pc_gen_ctl_2_i_0_5_a[2];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_a_x[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_a_x[0] at LC_X27_Y17_N3
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_a_x[0] = !KE1_q_a[7] & !KE1_q_a[4];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_5[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_5[0] at LC_X27_Y19_N7
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_5[0] = YB1_pc_gen_ctl_2_i_m3_0_2[0] # !KE1_q_a[4] & !YB1_pc_gen_ctl_2_i_m3_0_5_a[0] # !YB1_pc_gen_ctl_2_i_m3_0_o2_0_x[0];
 
 
--YB1_pc_gen_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a[1] at LC_X28_Y16_N2
--operation mode is normal
 
YB1_pc_gen_ctl_2_0_0_a[1] = !YB1_pc_gen_ctl_2_0_0_a3[1] & !JE1_q_a[7] # !YB1_fsm_dly_2_0_0_a2_0[2] # !YB1_alu_func_2_0_0_a2_0[1];
 
 
--YB1_cmp_ctl_2_0_0_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_0 at LC_X25_Y16_N5
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_0 = YB1_cmp_ctl_2_0_0_1_Z[0] # YB1_alu_func_2_0_0_a2_0[1] & YB1_cmp_ctl_2_0_0_a2_1[0] & WB34L1;
 
 
--WB34L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1|q[0]~56 at LC_X25_Y16_N9
--operation mode is normal
 
WB34L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_0 # !YB1_un1_muxa_ctl370_x & WB34L1;
 
 
--BD1_res_2_NE_12_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_12_0 at LC_X24_Y11_N1
--operation mode is normal
 
BD1_res_2_NE_12_0 = BD1_res_2_NE_16 # BD1_res_2_NE_7_0 # BD1_res_2_NE_17;
 
 
--BD1_res_2_NE_9_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_9_0 at LC_X24_Y11_N7
--operation mode is normal
 
BD1_res_2_NE_9_0 = BD1_res_2_NE_5 # BD1_res_2_NE_4 # BD1_res_2_NE_1;
 
 
--BD1_res_2_NE_11_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_11_0 at LC_X24_Y11_N8
--operation mode is normal
 
BD1_res_2_NE_11_0 = BD1_N_16 # BD1_res_2_NE_13 # BD1_N_18 # BD1_N_17;
 
 
--BD1_res_2_NE_10_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_10_0 at LC_X24_Y11_N0
--operation mode is normal
 
BD1_res_2_NE_10_0 = BD1_N_15 # BD1_res_2_NE_6 # BD1_res_2_NE_8 # BD1_N_13;
 
 
--BD1_un10_res_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_27 at LC_X23_Y7_N9
--operation mode is normal
 
BD1_un10_res_27 = BD1_un10_res_16 # BD1_un10_res_23 # BD1_un10_res_17;
 
 
--BD1_un10_res_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_28 at LC_X24_Y8_N1
--operation mode is normal
 
BD1_un10_res_28 = BD1_un10_res_20 # BD1_un10_res_21 # BD1_un10_res_19 # BD1_un10_res_18;
 
 
--UB1_dout_2_0_0[10] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[10] at LC_X28_Y7_N6
--operation mode is normal
 
UB1_dout_2_0_0[10] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[2] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_0_0_a_x[10];
 
 
--WB51L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_10__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y7_N7
--operation mode is normal
 
WB51L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[10] # !UB1_un1_byte_addr_2 & WB51L1;
 
--DB1_r32_o_10 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_10 at LC_X28_Y7_N7
--operation mode is normal
 
DB1_r32_o_10 = DFFEAS(WB51L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i[11] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[11] at LC_X28_Y7_N9
--operation mode is normal
 
UB1_dout_2_i_i[11] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[3] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[11];
 
 
--WB61L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_11__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y7_N5
--operation mode is normal
 
WB61L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[11] # !UB1_un1_byte_addr_2 & WB61L1;
 
--DB1_r32_o_11 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_11 at LC_X28_Y7_N5
--operation mode is normal
 
DB1_r32_o_11 = DFFEAS(WB61L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_0_0[12] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0[12] at LC_X27_Y8_N2
--operation mode is normal
 
UB1_dout_2_0_0[12] = UB1_dout_2_0_0_a2_1[9] # UB1_dout_2_0_0_o2_0[9] & KE1_q_b[4] # !UB1_dout_2_0_0_a_x[12];
 
 
--WB71L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_12__Z|lpm_latch:U1|q[0]~56 at LC_X27_Y8_N3
--operation mode is normal
 
WB71L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_0_0[12] # !UB1_un1_byte_addr_2 & WB71L1;
 
--DB1_r32_o_12 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_12 at LC_X27_Y8_N3
--operation mode is normal
 
DB1_r32_o_12 = DFFEAS(WB71L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i[23] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[23] at LC_X29_Y4_N5
--operation mode is normal
 
UB1_dout_2_i_i[23] = UB1_dout_2_i_i_a3_0[16] & JE1_q_b[7] # !RB1_ctl_o_2 & !UB1_dout_2_i_i_a[23] # !UB1_dout_2_i_i_a3_0[16] & !RB1_ctl_o_2 & !UB1_dout_2_i_i_a[23];
 
 
--WB82L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_23__Z|lpm_latch:U1|q[0]~56 at LC_X29_Y4_N2
--operation mode is normal
 
WB82L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[23] # !UB1_un1_byte_addr_2 & WB82L1;
 
--DB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_23 at LC_X29_Y4_N2
--operation mode is normal
 
DB1_r32_o_23 = DFFEAS(WB82L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i[13] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[13] at LC_X27_Y6_N3
--operation mode is normal
 
UB1_dout_2_i_i[13] = UB1_dout_2_0_0_a2_1[9] # UB1_dout_2_0_0_o2_0[9] & KE1_q_b[5] # !UB1_dout_2_i_i_a_x[13];
 
 
--WB81L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_13__Z|lpm_latch:U1|q[0]~56 at LC_X27_Y6_N1
--operation mode is normal
 
WB81L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[13] # !UB1_un1_byte_addr_2 & WB81L1;
 
--DB1_r32_o_13 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_13 at LC_X27_Y6_N1
--operation mode is normal
 
DB1_r32_o_13 = DFFEAS(WB81L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i[14] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[14] at LC_X28_Y7_N2
--operation mode is normal
 
UB1_dout_2_i_i[14] = UB1_dout_2_0_0_a2_1[9] # KE1_q_b[6] & UB1_dout_2_0_0_o2_0[9] # !UB1_dout_2_i_i_a_x[14];
 
 
--WB91L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_14__Z|lpm_latch:U1|q[0]~56 at LC_X28_Y7_N3
--operation mode is normal
 
WB91L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[14] # !UB1_un1_byte_addr_2 & WB91L1;
 
--DB1_r32_o_14 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_14 at LC_X28_Y7_N3
--operation mode is normal
 
DB1_r32_o_14 = DFFEAS(WB91L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[25] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[25] at LC_X25_Y15_N5
--operation mode is normal
 
UB1_dout_2_i_i_x[25] = UB1_dout_2_i_i_a2[16] # UB1_dout_2_i_i_a3_0[16] & KE1_q_b[1];
 
 
--WB03L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_25__Z|lpm_latch:U1|q[0]~56 at LC_X25_Y15_N4
--operation mode is normal
 
WB03L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[25] # !UB1_un1_byte_addr_2 & WB03L1;
 
--DB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_25 at LC_X25_Y15_N4
--operation mode is normal
 
DB1_r32_o_25 = DFFEAS(WB03L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[26] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[26] at LC_X30_Y9_N8
--operation mode is normal
 
UB1_dout_2_i_i_x[26] = UB1_dout_2_i_i_a2[16] # UB1_dout_2_i_i_a3_0[16] & KE1_q_b[2];
 
 
--WB13L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_26__Z|lpm_latch:U1|q[0]~56 at LC_X30_Y9_N9
--operation mode is normal
 
WB13L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[26] # !UB1_un1_byte_addr_2 & WB13L1;
 
--DB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_26 at LC_X30_Y9_N9
--operation mode is normal
 
DB1_r32_o_26 = DFFEAS(WB13L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--YB1_muxa_ctl_2_0_0_a2_0_0[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_0_0[1] at LC_X25_Y18_N1
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_a2_0_0[1] = !KE1_q_a[6] & !KE1_q_a[2] & YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] # !GE1_q_a[3];
 
 
--YB1_ext_ctl_2_i_m3_0_0_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|ext_ctl_2_i_m3_0_0_a[0] at LC_X24_Y17_N7
--operation mode is normal
 
YB1_ext_ctl_2_i_m3_0_0_a[0] = !KE1_q_a[7] & YB1_alu_func_2_0_0_a2_1[4] & !GE1_q_a[0] & GE1_q_a[3];
 
 
--FD1_un23_qa_i_0_a2_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|un23_qa_i_0_a2_a at LC_X27_Y14_N2
--operation mode is normal
 
FD1_r_rdaddress_a[2]_qfbk = FD1_r_rdaddress_a[2];
FD1_un23_qa_i_0_a2_a = !FD1_r_rdaddress_a[2]_qfbk & !FD1_r_rdaddress_a[3];
 
--FD1_r_rdaddress_a[2] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_rdaddress_a[2] at LC_X27_Y14_N2
--operation mode is normal
 
FD1_r_rdaddress_a[2] = DFFEAS(FD1_un23_qa_i_0_a2_a, GLOBAL(E1__clk0), VCC, , !AD1_CurrState_Sreg0_2, JE1_q_a[7], , , VCC);
 
 
--UB1_dout_2_i_i[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i[15] at LC_X29_Y13_N2
--operation mode is normal
 
UB1_dout_2_i_i[15] = UB1_dout_2_i_i_1[15] # !RB1_ctl_o_2 & UB1_dout_2_i_i_a3_1[15];
 
 
--WB02L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_15__Z|lpm_latch:U1|q[0]~56 at LC_X29_Y13_N3
--operation mode is normal
 
WB02L1 = !UB1_un1_ctl_5 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i[15] # !UB1_un1_byte_addr_2 & WB02L1;
 
--DB1_r32_o_15 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_15 at LC_X29_Y13_N3
--operation mode is normal
 
DB1_r32_o_15 = DFFEAS(WB02L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--UB1_dout_2_i_i_x[27] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[27] at LC_X25_Y15_N7
--operation mode is normal
 
UB1_dout_2_i_i_x[27] = UB1_dout_2_i_i_a2[16] # UB1_dout_2_i_i_a3_0[16] & KE1_q_b[3];
 
 
--WB23L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_27__Z|lpm_latch:U1|q[0]~56 at LC_X25_Y15_N6
--operation mode is normal
 
WB23L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[27] # !UB1_un1_byte_addr_2 & WB23L1;
 
--DB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_27 at LC_X25_Y15_N6
--operation mode is normal
 
DB1_r32_o_27 = DFFEAS(WB23L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_count[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count[0] at LC_X32_Y9_N2
--operation mode is arithmetic
 
VD1_count[0]_lut_out = VD1_count[0] $ VD1_un1_rdy_0_sqmuxa_3_combout;
VD1_count[0] = DFFEAS(VD1_count[0]_lut_out, GLOBAL(E1__clk0), VCC, , , , , !VD1_hilo_1_sqmuxa_i, );
 
--VD1_count_cout[0] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[0] at LC_X32_Y9_N2
--operation mode is arithmetic
 
VD1_count_cout[0]_cout_0 = VD1_count[0] & VD1_un1_rdy_0_sqmuxa_3_combout;
VD1_count_cout[0] = CARRY(VD1_count_cout[0]_cout_0);
 
--VD1L501 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|count_cout[0]~COUT1_1 at LC_X32_Y9_N2
--operation mode is arithmetic
 
VD1L501_cout_1 = VD1_count[0] & VD1_un1_rdy_0_sqmuxa_3_combout;
VD1L501 = CARRY(VD1L501_cout_1);
 
 
--VD1_over_carry_28 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_28 at LC_X10_Y10_N2
--operation mode is arithmetic
 
VD1_over_carry_28_cout_0 = PD1_a_o_28 & !VD1_over_carry_27 # !VD1_b_o_iv_28 # !PD1_a_o_28 & !VD1_b_o_iv_28 & !VD1_over_carry_27;
VD1_over_carry_28 = CARRY(VD1_over_carry_28_cout_0);
 
--VD1L5251 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_28~COUT1_1 at LC_X10_Y10_N2
--operation mode is arithmetic
 
VD1L5251_cout_1 = PD1_a_o_28 & !VD1L3251 # !VD1_b_o_iv_28 # !PD1_a_o_28 & !VD1_b_o_iv_28 & !VD1L3251;
VD1L5251 = CARRY(VD1L5251_cout_1);
 
 
--VD1_eqop2_2_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_0 at LC_X11_Y2_N1
--operation mode is normal
 
VD1_eqop2_2_0 = VD1_op2_reged[0] $ VD1_hilo[32];
 
 
--VD1_eqop2_2_NE_125_i_a2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_NE_125_i_a2 at LC_X13_Y2_N9
--operation mode is normal
 
VD1_eqop2_2_NE_125_i_a2 = VD1_hilo_62 & VD1_op2_reged[30] & VD1_hilo_46 $ !VD1_op2_reged[14] # !VD1_hilo_62 & !VD1_op2_reged[30] & VD1_hilo_46 $ !VD1_op2_reged[14];
 
 
--VD1_nop2_reged[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[11] at LC_X12_Y4_N7
--operation mode is arithmetic
 
VD1_nop2_reged[11]_carry_eqn = (!VD1_nop2_reged_cout[5] & VD1_nop2_reged_cout[9]) # (VD1_nop2_reged_cout[5] & VD1L7231);
VD1_nop2_reged[11] = VD1_op2_reged[11] $ (VD1_op2_reged[10] # !VD1_nop2_reged[11]_carry_eqn);
 
--VD1_nop2_reged_cout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[11] at LC_X12_Y4_N7
--operation mode is arithmetic
 
VD1_nop2_reged_cout[11]_cout_0 = VD1_op2_reged[11] # VD1_op2_reged[10] # !VD1_nop2_reged_cout[9];
VD1_nop2_reged_cout[11] = CARRY(VD1_nop2_reged_cout[11]_cout_0);
 
--VD1L1331 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[11]~COUT1_5 at LC_X12_Y4_N7
--operation mode is arithmetic
 
VD1L1331_cout_1 = VD1_op2_reged[11] # VD1_op2_reged[10] # !VD1L7231;
VD1L1331 = CARRY(VD1L1331_cout_1);
 
 
--VD1_nop2_reged[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[12] at LC_X13_Y4_N8
--operation mode is arithmetic
 
VD1_nop2_reged[12]_carry_eqn = (!VD1_nop2_reged_cout[4] & VD1_nop2_reged_cout[10]) # (VD1_nop2_reged_cout[4] & VD1L9231);
VD1_nop2_reged[12] = VD1_op2_reged[12] $ (VD1_nop2_reged[12]_carry_eqn);
 
--VD1_nop2_reged_cout[12] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[12] at LC_X13_Y4_N8
--operation mode is arithmetic
 
VD1_nop2_reged_cout[12]_cout_0 = !VD1_op2_reged[12] & !VD1_op2_reged[13] & !VD1_nop2_reged_cout[10];
VD1_nop2_reged_cout[12] = CARRY(VD1_nop2_reged_cout[12]_cout_0);
 
--VD1L3331 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[12]~COUT1_18 at LC_X13_Y4_N8
--operation mode is arithmetic
 
VD1L3331_cout_1 = !VD1_op2_reged[12] & !VD1_op2_reged[13] & !VD1L9231;
VD1L3331 = CARRY(VD1L3331_cout_1);
 
 
--VD1_nop2_reged[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[10] at LC_X13_Y4_N7
--operation mode is arithmetic
 
VD1_nop2_reged[10]_carry_eqn = (!VD1_nop2_reged_cout[4] & VD1_nop2_reged_cout[8]) # (VD1_nop2_reged_cout[4] & VD1L5231);
VD1_nop2_reged[10] = VD1_op2_reged[10] $ (!VD1_nop2_reged[10]_carry_eqn);
 
--VD1_nop2_reged_cout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[10] at LC_X13_Y4_N7
--operation mode is arithmetic
 
VD1_nop2_reged_cout[10]_cout_0 = VD1_op2_reged[10] # VD1_op2_reged[11] # !VD1_nop2_reged_cout[8];
VD1_nop2_reged_cout[10] = CARRY(VD1_nop2_reged_cout[10]_cout_0);
 
--VD1L9231 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[10]~COUT1_17 at LC_X13_Y4_N7
--operation mode is arithmetic
 
VD1L9231_cout_1 = VD1_op2_reged[10] # VD1_op2_reged[11] # !VD1L5231;
VD1L9231 = CARRY(VD1L9231_cout_1);
 
 
--VD1_nop2_reged[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged[25] at LC_X12_Y3_N4
--operation mode is arithmetic
 
VD1_nop2_reged[25]_carry_eqn = (!VD1_nop2_reged_cout[15] & VD1_nop2_reged_cout[23]) # (VD1_nop2_reged_cout[15] & VD1L3531);
VD1_nop2_reged[25] = VD1_op2_reged[25] $ (VD1_op2_reged[24] # VD1_nop2_reged[25]_carry_eqn);
 
--VD1_nop2_reged_cout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|nop2_reged_cout[25] at LC_X12_Y3_N4
--operation mode is arithmetic
 
VD1_nop2_reged_cout[25] = CARRY(!VD1_op2_reged[24] & !VD1_op2_reged[25] & !VD1L3531);
 
 
--UB1_dout_2_i_i_x[24] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_x[24] at LC_X31_Y15_N3
--operation mode is normal
 
UB1_dout_2_i_i_x[24] = UB1_dout_2_i_i_a2[16] # UB1_dout_2_i_i_a3_0[16] & KE1_q_b[0];
 
 
--WB92L1 is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|SYNLPM_LATR1:dout_1_24__Z|lpm_latch:U1|q[0]~56 at LC_X31_Y15_N4
--operation mode is normal
 
WB92L1 = !UB1_un1_ctl_6_2_0 & UB1_un1_byte_addr_2 & UB1_dout_2_i_i_x[24] # !UB1_un1_byte_addr_2 & WB92L1;
 
--DB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_24 at LC_X31_Y15_N4
--operation mode is normal
 
DB1_r32_o_24 = DFFEAS(WB92L1, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_pc_next_0_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[16] at LC_X28_Y5_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[16] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_16 & !SD1_r32_o_16 # !DD1_pc_next_0_sqmuxa_0_a4 # !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_16 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[16] at LC_X24_Y15_N8
--operation mode is normal
 
ED1_r32_o_14_qfbk = ED1_r32_o_14;
DD1_un1_pc_prectl_1_0_a4[16] = DD1_un1_pc_prectl_1_0_a3[0] & CD1_res_7_0_0_0_14 # CD1_res_7_0_0_o3_0 & ED1_r32_o_14_qfbk;
 
--ED1_r32_o_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg|r32_o_14 at LC_X24_Y15_N8
--operation mode is normal
 
ED1_r32_o_14 = DFFEAS(DD1_un1_pc_prectl_1_0_a4[16], GLOBAL(E1__clk0), VCC, , C1_G_504, HE1_q_a[6], , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, VCC);
 
 
--DD1_pc_next_0_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[17] at LC_X22_Y5_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[17] = FB1_res_7_0_0_17 & !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_17 # !FB1_res_7_0_0_17 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_17;
 
 
--DD1_un1_pc_prectl_1_0_a4[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[17] at LC_X23_Y15_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[17] = FB1_res_7_0_0_17 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--HD1_dout_iv_1_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_16 at LC_X25_Y4_N1
--operation mode is normal
 
HD1_dout_iv_1_16 = LD2_q_b[16] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[16];
 
 
--HD1_dout_iv_1_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_17 at LC_X25_Y7_N3
--operation mode is normal
 
HD1_dout_iv_1_17 = FD1_N_18_i_0_s3 & LD2_q_b[17] # !HD1_dout_iv_1_a[17];
 
 
--DD1_pc_next_0_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[14] at LC_X25_Y11_N3
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[14] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_14 & !FB1_res_7_0_0_14 # !DD1_pc_next_1_sqmuxa_0_a4 # !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_14 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[14] at LC_X25_Y11_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[14] = FB1_res_7_0_0_14 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[15] at LC_X19_Y6_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[15] = SD1_r32_o_15 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_15 # !SD1_r32_o_15 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_15;
 
 
--DD1_un1_pc_prectl_1_0_a4[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[15] at LC_X25_Y10_N3
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[15] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_15;
 
 
--HD1_dout_iv_1_14 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_14 at LC_X23_Y7_N5
--operation mode is normal
 
HD1_dout_iv_1_14 = FD1_N_18_i_0_s3 & LD2_q_b[14] # !HD1_dout_iv_1_a[14];
 
 
--HD1_dout_iv_1_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_15 at LC_X24_Y4_N6
--operation mode is normal
 
HD1_dout_iv_1_15 = FD1_N_18_i_0_s3 & LD2_q_b[15] # !HD1_dout_iv_1_a[15];
 
 
--VD1_un1_op2_reged_1_combout[9] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[9] at LC_X12_Y2_N2
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[9] = VD1_eqop2_2_32 & VD1_op2_reged[9] # !VD1_eqop2_2_32 & VD1_nop2_reged[9];
 
 
--VD1_un59_hilo_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add10 at LC_X9_Y5_N4
--operation mode is arithmetic
 
VD1_un59_hilo_add10_carry_eqn = (!VD1_un59_hilo_carry_5 & VD1_un59_hilo_carry_9) # (VD1_un59_hilo_carry_5 & VD1L3481);
VD1_un59_hilo_add10 = VD1_hilo_42 $ VD1_op2_reged[10] $ !VD1_un59_hilo_add10_carry_eqn;
 
--VD1_un59_hilo_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_10 at LC_X9_Y5_N4
--operation mode is arithmetic
 
VD1_un59_hilo_carry_10 = CARRY(VD1_hilo_42 & VD1_op2_reged[10] # !VD1L3481 # !VD1_hilo_42 & VD1_op2_reged[10] & !VD1L3481);
 
 
--VD1_un50_hilo_add10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add10 at LC_X10_Y4_N4
--operation mode is arithmetic
 
VD1_un50_hilo_add10_carry_eqn = (!VD1_un50_hilo_carry_5 & VD1_un50_hilo_carry_9) # (VD1_un50_hilo_carry_5 & VD1L0271);
VD1_un50_hilo_add10 = VD1_nop2_reged[10] $ VD1_hilo_42 $ !VD1_un50_hilo_add10_carry_eqn;
 
--VD1_un50_hilo_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_10 at LC_X10_Y4_N4
--operation mode is arithmetic
 
VD1_un50_hilo_carry_10 = CARRY(VD1_nop2_reged[10] & VD1_hilo_42 # !VD1L0271 # !VD1_nop2_reged[10] & VD1_hilo_42 & !VD1L0271);
 
 
--VD1_un1_op2_reged_1_combout[10] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[10] at LC_X11_Y4_N4
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[10] = VD1_eqop2_2_32 & VD1_op2_reged[10] # !VD1_eqop2_2_32 & VD1_nop2_reged[10];
 
 
--VD1_un59_hilo_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add11 at LC_X9_Y5_N5
--operation mode is arithmetic
 
VD1_un59_hilo_add11_carry_eqn = VD1_un59_hilo_carry_10;
VD1_un59_hilo_add11 = VD1_op2_reged[11] $ VD1_hilo_43 $ VD1_un59_hilo_add11_carry_eqn;
 
--VD1_un59_hilo_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_11 at LC_X9_Y5_N5
--operation mode is arithmetic
 
VD1_un59_hilo_carry_11_cout_0 = VD1_op2_reged[11] & !VD1_hilo_43 & !VD1_un59_hilo_carry_10 # !VD1_op2_reged[11] & !VD1_un59_hilo_carry_10 # !VD1_hilo_43;
VD1_un59_hilo_carry_11 = CARRY(VD1_un59_hilo_carry_11_cout_0);
 
--VD1L6481 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_11~COUT1_1 at LC_X9_Y5_N5
--operation mode is arithmetic
 
VD1L6481_cout_1 = VD1_op2_reged[11] & !VD1_hilo_43 & !VD1_un59_hilo_carry_10 # !VD1_op2_reged[11] & !VD1_un59_hilo_carry_10 # !VD1_hilo_43;
VD1L6481 = CARRY(VD1L6481_cout_1);
 
 
--VD1_un50_hilo_add11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add11 at LC_X10_Y4_N5
--operation mode is arithmetic
 
VD1_un50_hilo_add11_carry_eqn = VD1_un50_hilo_carry_10;
VD1_un50_hilo_add11 = VD1_hilo_43 $ VD1_nop2_reged[11] $ VD1_un50_hilo_add11_carry_eqn;
 
--VD1_un50_hilo_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_11 at LC_X10_Y4_N5
--operation mode is arithmetic
 
VD1_un50_hilo_carry_11_cout_0 = VD1_hilo_43 & !VD1_nop2_reged[11] & !VD1_un50_hilo_carry_10 # !VD1_hilo_43 & !VD1_un50_hilo_carry_10 # !VD1_nop2_reged[11];
VD1_un50_hilo_carry_11 = CARRY(VD1_un50_hilo_carry_11_cout_0);
 
--VD1L3271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_11~COUT1_1 at LC_X10_Y4_N5
--operation mode is arithmetic
 
VD1L3271_cout_1 = VD1_hilo_43 & !VD1_nop2_reged[11] & !VD1_un50_hilo_carry_10 # !VD1_hilo_43 & !VD1_un50_hilo_carry_10 # !VD1_nop2_reged[11];
VD1L3271 = CARRY(VD1L3271_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[11] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[11] at LC_X9_Y7_N4
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[11] = VD1_eqop2_2_32 & VD1_op2_reged[11] # !VD1_eqop2_2_32 & VD1_nop2_reged[11];
 
 
--VD1_un59_hilo_add12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add12 at LC_X9_Y5_N6
--operation mode is arithmetic
 
VD1_un59_hilo_add12_carry_eqn = (!VD1_un59_hilo_carry_10 & VD1_un59_hilo_carry_11) # (VD1_un59_hilo_carry_10 & VD1L6481);
VD1_un59_hilo_add12 = VD1_op2_reged[12] $ VD1_hilo_44 $ !VD1_un59_hilo_add12_carry_eqn;
 
--VD1_un59_hilo_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_12 at LC_X9_Y5_N6
--operation mode is arithmetic
 
VD1_un59_hilo_carry_12_cout_0 = VD1_op2_reged[12] & VD1_hilo_44 # !VD1_un59_hilo_carry_11 # !VD1_op2_reged[12] & VD1_hilo_44 & !VD1_un59_hilo_carry_11;
VD1_un59_hilo_carry_12 = CARRY(VD1_un59_hilo_carry_12_cout_0);
 
--VD1L8481 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_12~COUT1_1 at LC_X9_Y5_N6
--operation mode is arithmetic
 
VD1L8481_cout_1 = VD1_op2_reged[12] & VD1_hilo_44 # !VD1L6481 # !VD1_op2_reged[12] & VD1_hilo_44 & !VD1L6481;
VD1L8481 = CARRY(VD1L8481_cout_1);
 
 
--DD1_pc_next_0_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[20] at LC_X22_Y13_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[20] = FB1_res_7_0_0_20 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_20 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_20 & !SD1_r32_o_20 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[20] at LC_X22_Y13_N8
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[20] = FB1_res_7_0_0_20 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_un1_pc_add19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add19 at LC_X23_Y9_N3
--operation mode is arithmetic
 
DD1_un1_pc_add19_carry_eqn = (!DD1_un1_pc_carry_15 & DD1_un1_pc_carry_18) # (DD1_un1_pc_carry_15 & DD1L332);
DD1_un1_pc_add19 = DD1_un1_pc_prectl_1_0_a4[19] $ KB1_r32_o_19 $ DD1_un1_pc_add19_carry_eqn;
 
--DD1_un1_pc_carry_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_19 at LC_X23_Y9_N3
--operation mode is arithmetic
 
DD1_un1_pc_carry_19_cout_0 = DD1_un1_pc_prectl_1_0_a4[19] & !KB1_r32_o_19 & !DD1_un1_pc_carry_18 # !DD1_un1_pc_prectl_1_0_a4[19] & !DD1_un1_pc_carry_18 # !KB1_r32_o_19;
DD1_un1_pc_carry_19 = CARRY(DD1_un1_pc_carry_19_cout_0);
 
--DD1L532 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_19~COUT1_1 at LC_X23_Y9_N3
--operation mode is arithmetic
 
DD1L532_cout_1 = DD1_un1_pc_prectl_1_0_a4[19] & !KB1_r32_o_19 & !DD1L332 # !DD1_un1_pc_prectl_1_0_a4[19] & !DD1L332 # !KB1_r32_o_19;
DD1L532 = CARRY(DD1L532_cout_1);
 
 
--DD1_pc_next_0_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[21] at LC_X22_Y9_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[21] = SD1_r32_o_21 & !DD1_pc_next_0_sqmuxa_0_a4 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_21 # !SD1_r32_o_21 & !DD1_pc_next_1_sqmuxa_0_a4 # !FB1_res_7_0_0_21;
 
 
--DD1_un1_pc_prectl_1_0_a4[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[21] at LC_X22_Y9_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[21] = FB1_res_7_0_0_21 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_18 at LC_X19_Y5_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_18 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_18 # !DD1_pc_next_0_iv_1_a[18];
 
 
--DD1_un1_pc_add18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add18 at LC_X23_Y9_N2
--operation mode is arithmetic
 
DD1_un1_pc_add18_carry_eqn = (!DD1_un1_pc_carry_15 & DD1_un1_pc_carry_17) # (DD1_un1_pc_carry_15 & DD1L132);
DD1_un1_pc_add18 = DD1_un1_pc_prectl_1_0_a4[18] $ KB1_r32_o_18 $ !DD1_un1_pc_add18_carry_eqn;
 
--DD1_un1_pc_carry_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_18 at LC_X23_Y9_N2
--operation mode is arithmetic
 
DD1_un1_pc_carry_18_cout_0 = DD1_un1_pc_prectl_1_0_a4[18] & KB1_r32_o_18 # !DD1_un1_pc_carry_17 # !DD1_un1_pc_prectl_1_0_a4[18] & KB1_r32_o_18 & !DD1_un1_pc_carry_17;
DD1_un1_pc_carry_18 = CARRY(DD1_un1_pc_carry_18_cout_0);
 
--DD1L332 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_18~COUT1_1 at LC_X23_Y9_N2
--operation mode is arithmetic
 
DD1L332_cout_1 = DD1_un1_pc_prectl_1_0_a4[18] & KB1_r32_o_18 # !DD1L132 # !DD1_un1_pc_prectl_1_0_a4[18] & KB1_r32_o_18 & !DD1L132;
DD1L332 = CARRY(DD1L332_cout_1);
 
 
--DD1_pc_next_0_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_19 at LC_X22_Y6_N0
--operation mode is normal
 
DD1_pc_next_0_iv_1_19 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_19 # !DD1_pc_next_0_iv_1_a[19];
 
 
--HD1_dout_iv_1_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_21 at LC_X20_Y7_N1
--operation mode is normal
 
HD1_dout_iv_1_21 = FD1_N_18_i_0_s3 & LD2_q_b[21] # !HD1_dout_iv_1_a[21];
 
 
--HD1_dout_iv_1_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_20 at LC_X21_Y7_N8
--operation mode is normal
 
HD1_dout_iv_1_20 = FD1_N_18_i_0_s3 & LD2_q_b[20] # !HD1_dout_iv_1_a[20];
 
 
--VD1_hilo_37_iv_0_2_a[51] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[51] at LC_X5_Y5_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_2_a[51] = VD1_hilo_0_sqmuxa & !VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a3_2[62] # !VD1_hilo_19 # !VD1_hilo_0_sqmuxa & !VD1_un59_hilo_add19 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--PB1_dout_iv_19 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_19 at LC_X26_Y7_N1
--operation mode is normal
 
PB1_dout_iv_19 = HD1_dout_iv_1_19 # HD1_dout7_0_a2 & FD1_wb_o_19;
 
--PB1_r32_o_19 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_19 at LC_X26_Y7_N1
--operation mode is normal
 
PB1_r32_o_19 = DFFEAS(PB1_dout_iv_19, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--PB1_dout_iv_18 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_18 at LC_X21_Y8_N8
--operation mode is normal
 
PB1_dout_iv_18 = HD1_dout_iv_1_18 # FD1_wb_o_18 & HD1_dout7_0_a2;
 
--PB1_r32_o_18 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_18 at LC_X21_Y8_N8
--operation mode is normal
 
PB1_r32_o_18 = DFFEAS(PB1_dout_iv_18, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un1_op2_reged_1_combout[25] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[25] at LC_X11_Y4_N8
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[25] = VD1_eqop2_2_32 & VD1_op2_reged[25] # !VD1_eqop2_2_32 & VD1_nop2_reged[25];
 
 
--VD1_un59_hilo_add27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add27 at LC_X9_Y3_N1
--operation mode is arithmetic
 
VD1_un59_hilo_add27_carry_eqn = (!VD1_un59_hilo_carry_25 & VD1_un59_hilo_carry_26) # (VD1_un59_hilo_carry_25 & VD1L3781);
VD1_un59_hilo_add27 = VD1_op2_reged[27] $ VD1_hilo_59 $ VD1_un59_hilo_add27_carry_eqn;
 
--VD1_un59_hilo_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_27 at LC_X9_Y3_N1
--operation mode is arithmetic
 
VD1_un59_hilo_carry_27_cout_0 = VD1_op2_reged[27] & !VD1_hilo_59 & !VD1_un59_hilo_carry_26 # !VD1_op2_reged[27] & !VD1_un59_hilo_carry_26 # !VD1_hilo_59;
VD1_un59_hilo_carry_27 = CARRY(VD1_un59_hilo_carry_27_cout_0);
 
--VD1L5781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_27~COUT1_1 at LC_X9_Y3_N1
--operation mode is arithmetic
 
VD1L5781_cout_1 = VD1_op2_reged[27] & !VD1_hilo_59 & !VD1L3781 # !VD1_op2_reged[27] & !VD1L3781 # !VD1_hilo_59;
VD1L5781 = CARRY(VD1L5781_cout_1);
 
 
--VD1_un59_hilo_add25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add25 at LC_X9_Y4_N9
--operation mode is arithmetic
 
VD1_un59_hilo_add25_carry_eqn = (!VD1_un59_hilo_carry_20 & VD1_un59_hilo_carry_24) # (VD1_un59_hilo_carry_20 & VD1L0781);
VD1_un59_hilo_add25 = VD1_op2_reged[25] $ VD1_hilo_57 $ VD1_un59_hilo_add25_carry_eqn;
 
--VD1_un59_hilo_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_25 at LC_X9_Y4_N9
--operation mode is arithmetic
 
VD1_un59_hilo_carry_25 = CARRY(VD1_op2_reged[25] & !VD1_hilo_57 & !VD1L0781 # !VD1_op2_reged[25] & !VD1L0781 # !VD1_hilo_57);
 
 
--PB1_dout_iv_26 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_26 at LC_X20_Y8_N7
--operation mode is normal
 
PB1_dout_iv_26 = HD1_dout_iv_1_26 # FD1_wb_o_26 & HD1_dout7_0_a2;
 
--PB1_r32_o_26 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_26 at LC_X20_Y8_N7
--operation mode is normal
 
PB1_r32_o_26 = DFFEAS(PB1_dout_iv_26, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_37_iv_0_a5_0[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[59] at LC_X5_Y2_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_a5_0[59] = !VD1_hilo_59 & VD1_hilo_37_iv_0_a3_1[62];
 
 
--VD1_hilo_37_iv_0_1[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[59] at LC_X5_Y2_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_1[59] = VD1_hilo_37_iv_0_0[59] # !VD1_un59_hilo_add27 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--PB1_dout_iv_27 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_27 at LC_X22_Y7_N9
--operation mode is normal
 
PB1_dout_iv_27 = HD1_dout_iv_1_27 # FD1_wb_o_27 & HD1_dout7_0_a2;
 
--PB1_r32_o_27 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_27 at LC_X22_Y7_N9
--operation mode is normal
 
PB1_r32_o_27 = DFFEAS(PB1_dout_iv_27, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_37_iv_0_6[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6[60] at LC_X7_Y2_N5
--operation mode is normal
 
VD1_hilo_37_iv_0_6[60] = VD1_hilo_37_iv_0_6_a[60] # VD1_hilo_37_iv_0_3[60] # VD1_hilo_37_iv_0_a3_4[57] & !VD1_un50_hilo_add29;
 
 
--VD1_hilo_37_iv_0_a5_0[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[61] at LC_X7_Y3_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a5_0[61] = VD1_hilo_37_iv_0_a3_1[62] & !VD1_hilo_61;
 
 
--VD1_hilo_37_iv_0_1[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[61] at LC_X7_Y2_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_1[61] = VD1_hilo_37_iv_0_0[61] # VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add29;
 
 
--DD1_pc_next_0_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[13] at LC_X24_Y9_N4
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[13] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_13 & !FB1_res_7_0_0_13 # !DD1_pc_next_1_sqmuxa_0_a4 # !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_13 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[13] at LC_X24_Y9_N3
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[13] = FB1_res_7_0_0_13 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--HD1_dout_iv_1_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_13 at LC_X26_Y11_N5
--operation mode is normal
 
HD1_dout_iv_1_13 = FD1_N_18_i_0_s3 & LD2_q_b[13] # !HD1_dout_iv_1_a[13];
 
 
--HD1_dout_iv_1_a[30] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[30] at LC_X22_Y8_N7
--operation mode is normal
 
HD1_dout_iv_1_a[30] = AB1_r32_o_28 & !YD1_mux_fw_1 & !FD1_r_data_30 # !FD1_N_14_i_0_s2 # !AB1_r32_o_28 & !FD1_r_data_30 # !FD1_N_14_i_0_s2;
 
 
--VD1_un59_hilo_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_add24 at LC_X9_Y4_N8
--operation mode is arithmetic
 
VD1_un59_hilo_add24_carry_eqn = (!VD1_un59_hilo_carry_20 & VD1_un59_hilo_carry_23) # (VD1_un59_hilo_carry_20 & VD1L8681);
VD1_un59_hilo_add24 = VD1_hilo_56 $ VD1_op2_reged[24] $ !VD1_un59_hilo_add24_carry_eqn;
 
--VD1_un59_hilo_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_24 at LC_X9_Y4_N8
--operation mode is arithmetic
 
VD1_un59_hilo_carry_24_cout_0 = VD1_hilo_56 & VD1_op2_reged[24] # !VD1_un59_hilo_carry_23 # !VD1_hilo_56 & VD1_op2_reged[24] & !VD1_un59_hilo_carry_23;
VD1_un59_hilo_carry_24 = CARRY(VD1_un59_hilo_carry_24_cout_0);
 
--VD1L0781 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un59_hilo_carry_24~COUT1_1 at LC_X9_Y4_N8
--operation mode is arithmetic
 
VD1L0781_cout_1 = VD1_hilo_56 & VD1_op2_reged[24] # !VD1L8681 # !VD1_hilo_56 & VD1_op2_reged[24] & !VD1L8681;
VD1L0781 = CARRY(VD1L0781_cout_1);
 
 
--VD1_un50_hilo_add24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_add24 at LC_X10_Y3_N8
--operation mode is arithmetic
 
VD1_un50_hilo_add24_carry_eqn = (!VD1_un50_hilo_carry_20 & VD1_un50_hilo_carry_23) # (VD1_un50_hilo_carry_20 & VD1L5471);
VD1_un50_hilo_add24 = VD1_hilo_56 $ VD1_nop2_reged[24] $ !VD1_un50_hilo_add24_carry_eqn;
 
--VD1_un50_hilo_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_24 at LC_X10_Y3_N8
--operation mode is arithmetic
 
VD1_un50_hilo_carry_24_cout_0 = VD1_hilo_56 & VD1_nop2_reged[24] # !VD1_un50_hilo_carry_23 # !VD1_hilo_56 & VD1_nop2_reged[24] & !VD1_un50_hilo_carry_23;
VD1_un50_hilo_carry_24 = CARRY(VD1_un50_hilo_carry_24_cout_0);
 
--VD1L7471 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un50_hilo_carry_24~COUT1_1 at LC_X10_Y3_N8
--operation mode is arithmetic
 
VD1L7471_cout_1 = VD1_hilo_56 & VD1_nop2_reged[24] # !VD1L5471 # !VD1_hilo_56 & VD1_nop2_reged[24] & !VD1L5471;
VD1L7471 = CARRY(VD1L7471_cout_1);
 
 
--VD1_un1_op2_reged_1_combout[24] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[24] at LC_X14_Y4_N7
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[24] = VD1_eqop2_2_32 & VD1_op2_reged[24] # !VD1_eqop2_2_32 & VD1_nop2_reged[24];
 
 
--DD1_pc_next_0_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_24 at LC_X20_Y3_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_24 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_24 # !DD1_pc_next_0_iv_1_a[24];
 
 
--DD1_un1_pc_add24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add24 at LC_X23_Y9_N8
--operation mode is arithmetic
 
DD1_un1_pc_add24_carry_eqn = (!DD1_un1_pc_carry_20 & DD1_un1_pc_carry_23) # (DD1_un1_pc_carry_20 & DD1L242);
DD1_un1_pc_add24 = KB1_r32_o_24 $ DD1_un1_pc_prectl_1_0_a4[24] $ !DD1_un1_pc_add24_carry_eqn;
 
--DD1_un1_pc_carry_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_24 at LC_X23_Y9_N8
--operation mode is arithmetic
 
DD1_un1_pc_carry_24_cout_0 = KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] # !DD1_un1_pc_carry_23 # !KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] & !DD1_un1_pc_carry_23;
DD1_un1_pc_carry_24 = CARRY(DD1_un1_pc_carry_24_cout_0);
 
--DD1L442 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_24~COUT1_1 at LC_X23_Y9_N8
--operation mode is arithmetic
 
DD1L442_cout_1 = KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] # !DD1L242 # !KB1_r32_o_24 & DD1_un1_pc_prectl_1_0_a4[24] & !DD1L242;
DD1L442 = CARRY(DD1L442_cout_1);
 
 
--DD1_pc_next_0_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_25 at LC_X24_Y6_N8
--operation mode is normal
 
DD1_pc_next_0_iv_1_25 = PB1_dout_iv_25 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[25];
 
 
--DD1_un1_pc_add25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add25 at LC_X23_Y9_N9
--operation mode is arithmetic
 
DD1_un1_pc_add25_carry_eqn = (!DD1_un1_pc_carry_20 & DD1_un1_pc_carry_24) # (DD1_un1_pc_carry_20 & DD1L442);
DD1_un1_pc_add25 = KB1_r32_o_25 $ DD1_un1_pc_prectl_1_0_a4[25] $ DD1_un1_pc_add25_carry_eqn;
 
--DD1_un1_pc_carry_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_25 at LC_X23_Y9_N9
--operation mode is arithmetic
 
DD1_un1_pc_carry_25 = CARRY(KB1_r32_o_25 & !DD1_un1_pc_prectl_1_0_a4[25] & !DD1L442 # !KB1_r32_o_25 & !DD1L442 # !DD1_un1_pc_prectl_1_0_a4[25]);
 
 
--PB1_dout_iv_24 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_24 at LC_X23_Y6_N4
--operation mode is normal
 
PB1_dout_iv_24 = HD1_dout_iv_1_24 # HD1_dout7_0_a2 & FD1_wb_o_24;
 
--PB1_r32_o_24 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_24 at LC_X23_Y6_N4
--operation mode is normal
 
PB1_r32_o_24 = DFFEAS(PB1_dout_iv_24, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_hilo_37_iv_0_2_a[57] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_2_a[57] at LC_X4_Y6_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_2_a[57] = VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add25 # !VD1_hilo_25 # !VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_2[62] & !VD1_un59_hilo_add25;
 
 
--PB1_dout_iv_25 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_25 at LC_X24_Y8_N2
--operation mode is normal
 
PB1_dout_iv_25 = HD1_dout_iv_1_25 # FD1_wb_o_25 & HD1_dout7_0_a2;
 
--PB1_r32_o_25 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_25 at LC_X24_Y8_N2
--operation mode is normal
 
PB1_r32_o_25 = DFFEAS(PB1_dout_iv_25, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--DD1_pc_next_0_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_22 at LC_X24_Y5_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_22 = DD1_pc_next_2_sqmuxa_0_a4 & PB1_dout_iv_22 # !DD1_pc_next_0_iv_1_a[22];
 
 
--DD1_un1_pc_add22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add22 at LC_X23_Y9_N6
--operation mode is arithmetic
 
DD1_un1_pc_add22_carry_eqn = (!DD1_un1_pc_carry_20 & DD1_un1_pc_carry_21) # (DD1_un1_pc_carry_20 & DD1L832);
DD1_un1_pc_add22 = DD1_un1_pc_prectl_1_0_a4[22] $ KB1_r32_o_22 $ !DD1_un1_pc_add22_carry_eqn;
 
--DD1_un1_pc_carry_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_22 at LC_X23_Y9_N6
--operation mode is arithmetic
 
DD1_un1_pc_carry_22_cout_0 = DD1_un1_pc_prectl_1_0_a4[22] & KB1_r32_o_22 # !DD1_un1_pc_carry_21 # !DD1_un1_pc_prectl_1_0_a4[22] & KB1_r32_o_22 & !DD1_un1_pc_carry_21;
DD1_un1_pc_carry_22 = CARRY(DD1_un1_pc_carry_22_cout_0);
 
--DD1L042 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_22~COUT1_1 at LC_X23_Y9_N6
--operation mode is arithmetic
 
DD1L042_cout_1 = DD1_un1_pc_prectl_1_0_a4[22] & KB1_r32_o_22 # !DD1L832 # !DD1_un1_pc_prectl_1_0_a4[22] & KB1_r32_o_22 & !DD1L832;
DD1L042 = CARRY(DD1L042_cout_1);
 
 
--DD1_pc_next_0_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_23 at LC_X22_Y3_N3
--operation mode is normal
 
DD1_pc_next_0_iv_1_23 = PB1_dout_iv_23 & DD1_pc_next_2_sqmuxa_0_a4 # !DD1_pc_next_0_iv_1_a[23];
 
 
--DD1_un1_pc_add23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_add23 at LC_X23_Y9_N7
--operation mode is arithmetic
 
DD1_un1_pc_add23_carry_eqn = (!DD1_un1_pc_carry_20 & DD1_un1_pc_carry_22) # (DD1_un1_pc_carry_20 & DD1L042);
DD1_un1_pc_add23 = KB1_r32_o_23 $ DD1_un1_pc_prectl_1_0_a4[23] $ DD1_un1_pc_add23_carry_eqn;
 
--DD1_un1_pc_carry_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_23 at LC_X23_Y9_N7
--operation mode is arithmetic
 
DD1_un1_pc_carry_23_cout_0 = KB1_r32_o_23 & !DD1_un1_pc_prectl_1_0_a4[23] & !DD1_un1_pc_carry_22 # !KB1_r32_o_23 & !DD1_un1_pc_carry_22 # !DD1_un1_pc_prectl_1_0_a4[23];
DD1_un1_pc_carry_23 = CARRY(DD1_un1_pc_carry_23_cout_0);
 
--DD1L242 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_carry_23~COUT1_1 at LC_X23_Y9_N7
--operation mode is arithmetic
 
DD1L242_cout_1 = KB1_r32_o_23 & !DD1_un1_pc_prectl_1_0_a4[23] & !DD1L042 # !KB1_r32_o_23 & !DD1L042 # !DD1_un1_pc_prectl_1_0_a4[23];
DD1L242 = CARRY(DD1L242_cout_1);
 
 
--PB1_dout_iv_22 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_22 at LC_X24_Y7_N2
--operation mode is normal
 
PB1_dout_iv_22 = HD1_dout_iv_1_22 # FD1_wb_o_22 & HD1_dout7_0_a2;
 
--PB1_r32_o_22 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_22 at LC_X24_Y7_N2
--operation mode is normal
 
PB1_r32_o_22 = DFFEAS(PB1_dout_iv_22, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--VD1_un1_op2_reged_1_combout[23] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_op2_reged_1_combout[23] at LC_X15_Y4_N2
--operation mode is normal
 
VD1_un1_op2_reged_1_combout[23] = VD1_eqop2_2_32 & VD1_op2_reged[23] # !VD1_eqop2_2_32 & VD1_nop2_reged[23];
 
 
--PB1_dout_iv_23 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|dout_iv_23 at LC_X23_Y5_N4
--operation mode is normal
 
PB1_dout_iv_23 = HD1_dout_iv_1_23 # HD1_dout7_0_a2 & FD1_wb_o_23;
 
--PB1_r32_o_23 is mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg|r32_o_23 at LC_X23_Y5_N4
--operation mode is normal
 
PB1_r32_o_23 = DFFEAS(PB1_dout_iv_23, GLOBAL(E1__clk0), VCC, , , , , , );
 
 
--HD1_dout_iv_1_28 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_28 at LC_X26_Y8_N3
--operation mode is normal
 
HD1_dout_iv_1_28 = FD1_N_18_i_0_s3 & LD2_q_b[28] # !HD1_dout_iv_1_a[28];
 
 
--DD1_un1_pc_prectl_1_0_a4[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[27] at LC_X28_Y8_N4
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[27] = FB1_res_7_0_0_27 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--HD1_dout_iv_1_29 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_29 at LC_X26_Y11_N0
--operation mode is normal
 
HD1_dout_iv_1_29 = LD2_q_b[29] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[29];
 
 
--DD1_pc_next_0_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[26] at LC_X21_Y10_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[26] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_26 & !SD1_r32_o_26 # !DD1_pc_next_0_sqmuxa_0_a4 # !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_26 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[26] at LC_X23_Y14_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[26] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_26;
 
 
--DD1_pc_next_0_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[27] at LC_X22_Y4_N7
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[27] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_27 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_27 # !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_27;
 
 
--UB1_dout_2_i_i_a2_a[16] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a2_a[16] at LC_X32_Y14_N2
--operation mode is normal
 
UB1_dout_2_i_i_a2_a[16] = !RB1_ctl_o_3 # !RB1_ctl_o_1;
 
 
--TD1_lt_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_23 at LC_X16_Y8_N7
--operation mode is arithmetic
 
TD1_lt_23_cout_0 = PD1_a_o_23 & !TD1_lt_22 # !VD1_b_o_iv_23 # !PD1_a_o_23 & !VD1_b_o_iv_23 & !TD1_lt_22;
TD1_lt_23 = CARRY(TD1_lt_23_cout_0);
 
--TD1L581 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_23~COUT1_1 at LC_X16_Y8_N7
--operation mode is arithmetic
 
TD1L581_cout_1 = PD1_a_o_23 & !TD1L381 # !VD1_b_o_iv_23 # !PD1_a_o_23 & !VD1_b_o_iv_23 & !TD1L381;
TD1L581 = CARRY(TD1L581_cout_1);
 
 
--TD1_sum_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_24 at LC_X15_Y7_N8
--operation mode is arithmetic
 
TD1_sum_carry_24_cout_0 = PD1_a_o_24 & !TD1_sum_carry_23 # !VD1_b_o_iv_24 # !PD1_a_o_24 & !VD1_b_o_iv_24 & !TD1_sum_carry_23;
TD1_sum_carry_24 = CARRY(TD1_sum_carry_24_cout_0);
 
--TD1L234 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_24~COUT1_1 at LC_X15_Y7_N8
--operation mode is arithmetic
 
TD1L234_cout_1 = PD1_a_o_24 & !TD1L034 # !VD1_b_o_iv_24 # !PD1_a_o_24 & !VD1_b_o_iv_24 & !TD1L034;
TD1L234 = CARRY(TD1L234_cout_1);
 
 
--UB1_dout_2_0_0_o2_1_a[9] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_o2_1_a[9] at LC_X31_Y9_N7
--operation mode is normal
 
UB1_dout_2_0_0_o2_1_a[9] = RB1_ctl_o_1 & RB1_ctl_o_3 & !RB1_byte_addr_o_1 # !RB1_ctl_o_3 & !RB1_ctl_o_2 # !RB1_ctl_o_1 & !RB1_byte_addr_o_1 & !RB1_ctl_o_2;
 
 
--UB1_dout_2_i_i_a3_a_x[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a3_a_x[15] at LC_X29_Y8_N4
--operation mode is normal
 
UB1_dout_2_i_i_a3_a_x[15] = RB1_byte_addr_o_1 & !GE1_q_b[7] # !RB1_byte_addr_o_1 & !JE1_q_b[7];
 
 
--YB1_pc_gen_ctl_2_i_0_a3_5[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_5[2] at LC_X26_Y13_N3
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3_5[2] = KE1_q_a[2] & YB1_fsm_dly_2_0_0_a2_x[2] & !YB1_alu_we_1s_1_o2_0_x[0] & YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2];
 
 
--YB1_pc_gen_ctl_2_i_0_a3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3[2] at LC_X27_Y17_N5
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3[2] = YB1_pc_gen_ctl_2_i_0_a2_0_x[2] & GE1_q_a[2] & GE1_q_a[3] # !GE1_q_a[5];
 
 
--YB1_pc_gen_ctl_2_i_0_5_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_5_a[2] at LC_X27_Y17_N2
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_5_a[2] = GE1_q_a[5] & !GE1_q_a[4] # !GE1_q_a[5] & GE1_q_a[4] # !YB1_alu_func_2_0_0_o2_x[3] # !YB1_pc_gen_ctl_2_i_0_a2_0_x[2];
 
 
--YB1_pc_gen_ctl_2_i_0_1_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_1_x[2] at LC_X26_Y17_N1
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_1_x[2] = YB1_pc_gen_ctl_2_i_0_a3_3[2] # YB1_pc_gen_ctl_2_i_0_0_Z[2];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_5_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_5_a[0] at LC_X27_Y19_N2
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_5_a[0] = KE1_q_a[7] & !KE1_q_a[2] & !KE1_q_a[6] # !KE1_q_a[7] & !KE1_q_a[3];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_2[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_2[0] at LC_X27_Y19_N6
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_2[0] = KE1_q_a[5] # !KE1_q_a[4] & YB1_alu_func_2_0_0_a2_0_x[4] # !YB1_pc_gen_ctl_2_i_m3_0_2_a[0];
 
 
--YB1_pc_gen_ctl_2_0_0_a3[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_0_0_a3[1] at LC_X28_Y16_N1
--operation mode is normal
 
YB1_pc_gen_ctl_2_0_0_a3[1] = YB1_alu_func_2_0_0_a2_0[1] & WB16L1 & YB1_cmp_ctl_2_0_0_a2_0[0] # YB1_cmp_ctl_2_0_0_a2_1[0];
 
 
--YB1_cmp_ctl_2_0_0_1_Z[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_Z[0] at LC_X25_Y16_N4
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_1_Z[0] = WB34L1 & YB1_ext_ctl_2_0_0_a2_0_x[2] & YB1_cmp_ctl_2_0_0_a2_0[0] # !YB1_cmp_ctl_2_0_0_1_a[0];
 
 
--YB1_cmp_ctl_2_0_0_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_2 at LC_X26_Y16_N4
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_2 = YB1_alu_func_2_0_0_a2_0_x[0] & YB1_cmp_ctl_2_0_0_a2_x[0] # YB1_alu_func_2_0_0_a2_0[1] & !YB1_cmp_ctl_2_0_0_a[2] # !YB1_alu_func_2_0_0_a2_0_x[0] & YB1_alu_func_2_0_0_a2_0[1] & !YB1_cmp_ctl_2_0_0_a[2];
 
 
--WB54L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_2_|lpm_latch:U1|q[0]~56 at LC_X26_Y16_N5
--operation mode is normal
 
WB54L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_2 # !YB1_un1_muxa_ctl370_x & WB54L1;
 
--BC1_cmp_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_2 at LC_X26_Y16_N5
--operation mode is normal
 
BC1_cmp_ctl_o_2 = DFFEAS(WB54L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--YB1_cmp_ctl_2_0_0_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1 at LC_X27_Y16_N7
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_1 = YB1_alu_func_2_0_0_a2_0[1] & WB44L1 & YB1_cmp_ctl_2_0_0_a2_0[0] # !YB1_cmp_ctl_2_0_0_a[1];
 
 
--WB44L1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_1_|lpm_latch:U1|q[0]~56 at LC_X27_Y16_N8
--operation mode is normal
 
WB44L1 = !YB1_un1_ins_i_22_1_x & YB1_un1_muxa_ctl370_x & YB1_cmp_ctl_2_0_0_1 # !YB1_un1_muxa_ctl370_x & WB44L1;
 
--BC1_cmp_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2|cmp_ctl_o_1 at LC_X27_Y16_N8
--operation mode is normal
 
BC1_cmp_ctl_o_1 = DFFEAS(WB44L1, GLOBAL(E1__clk0), VCC, , C1_G_504, , , !AD1_id2ra_ins_clr_1_0_i_a2_0_a2, );
 
 
--BD1_res_2_NE_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_16 at LC_X22_Y8_N6
--operation mode is normal
 
BD1_res_2_NE_16 = PB1_dout_iv_30 & PB1_dout_iv_14 $ QB1_dout_iv_14 # !QB1_dout_iv_30 # !PB1_dout_iv_30 & QB1_dout_iv_30 # PB1_dout_iv_14 $ QB1_dout_iv_14;
 
 
--BD1_res_2_NE_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_17 at LC_X24_Y4_N3
--operation mode is normal
 
BD1_res_2_NE_17 = PB1_dout_iv_31 & PB1_dout_iv_15 $ QB1_dout_iv_15 # !QB1_dout_iv_31 # !PB1_dout_iv_31 & QB1_dout_iv_31 # PB1_dout_iv_15 $ QB1_dout_iv_15;
 
 
--BD1_res_2_NE_7_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_7_0 at LC_X26_Y11_N9
--operation mode is normal
 
BD1_res_2_NE_7_0 = BD1_res_2_NE_7_0_a # BD1_res_2_12 # QB1_dout_iv_28 $ PB1_dout_iv_28;
 
 
--BD1_res_2_NE_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_4 at LC_X21_Y8_N1
--operation mode is normal
 
BD1_res_2_NE_4 = PB1_dout_iv_2 & PB1_dout_iv_18 $ QB1_dout_iv_18 # !QB1_dout_iv_2 # !PB1_dout_iv_2 & QB1_dout_iv_2 # PB1_dout_iv_18 $ QB1_dout_iv_18;
 
 
--BD1_res_2_NE_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_5 at LC_X26_Y7_N9
--operation mode is normal
 
BD1_res_2_NE_5 = PB1_dout_iv_19 & PB1_dout_iv_3 $ QB1_dout_iv_3 # !QB1_dout_iv_19 # !PB1_dout_iv_19 & QB1_dout_iv_19 # PB1_dout_iv_3 $ QB1_dout_iv_3;
 
 
--BD1_res_2_NE_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_1 at LC_X25_Y7_N6
--operation mode is normal
 
BD1_res_2_NE_1 = BD1_res_2_NE_1_a # BD1_res_2_0 # PB1_dout_iv_16 $ QB1_dout_iv_16;
 
 
--BD1_N_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_18 at LC_X20_Y8_N8
--operation mode is normal
 
BD1_N_18 = QB1_dout_iv_10 & QB1_dout_iv_26 $ PB1_dout_iv_26 # !PB1_dout_iv_10 # !QB1_dout_iv_10 & PB1_dout_iv_10 # QB1_dout_iv_26 $ PB1_dout_iv_26;
 
 
--BD1_res_2_NE_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_13 at LC_X22_Y7_N2
--operation mode is normal
 
BD1_res_2_NE_13 = PB1_dout_iv_27 & QB1_dout_iv_11 $ PB1_dout_iv_11 # !QB1_dout_iv_27 # !PB1_dout_iv_27 & QB1_dout_iv_27 # QB1_dout_iv_11 $ PB1_dout_iv_11;
 
 
--BD1_N_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_16 at LC_X23_Y6_N9
--operation mode is normal
 
BD1_N_16 = PB1_dout_iv_8 & PB1_dout_iv_24 $ QB1_dout_iv_24 # !QB1_dout_iv_8 # !PB1_dout_iv_8 & QB1_dout_iv_8 # PB1_dout_iv_24 $ QB1_dout_iv_24;
 
 
--BD1_N_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_17 at LC_X25_Y6_N7
--operation mode is normal
 
BD1_N_17 = PB1_dout_iv_9 & PB1_dout_iv_25 $ QB1_dout_iv_25 # !QB1_dout_iv_9 # !PB1_dout_iv_9 & QB1_dout_iv_9 # PB1_dout_iv_25 $ QB1_dout_iv_25;
 
 
--BD1_res_2_NE_8 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_8 at LC_X24_Y7_N6
--operation mode is normal
 
BD1_res_2_NE_8 = PB1_dout_iv_6 & PB1_dout_iv_22 $ QB1_dout_iv_22 # !QB1_dout_iv_6 # !PB1_dout_iv_6 & QB1_dout_iv_6 # PB1_dout_iv_22 $ QB1_dout_iv_22;
 
 
--BD1_N_15 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_15 at LC_X23_Y5_N8
--operation mode is normal
 
BD1_N_15 = PB1_dout_iv_7 & PB1_dout_iv_23 $ QB1_dout_iv_23 # !QB1_dout_iv_7 # !PB1_dout_iv_7 & QB1_dout_iv_7 # PB1_dout_iv_23 $ QB1_dout_iv_23;
 
 
--BD1_res_2_NE_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_6 at LC_X21_Y7_N4
--operation mode is normal
 
BD1_res_2_NE_6 = QB1_dout_iv_20 & PB1_dout_iv_4 $ QB1_dout_iv_4 # !PB1_dout_iv_20 # !QB1_dout_iv_20 & PB1_dout_iv_20 # PB1_dout_iv_4 $ QB1_dout_iv_4;
 
 
--BD1_N_13 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|N_13 at LC_X20_Y7_N6
--operation mode is normal
 
BD1_N_13 = PB1_dout_iv_5 & PB1_dout_iv_21 $ QB1_dout_iv_21 # !QB1_dout_iv_5 # !PB1_dout_iv_5 & QB1_dout_iv_5 # PB1_dout_iv_21 $ QB1_dout_iv_21;
 
 
--BD1_un10_res_16 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_16 at LC_X23_Y7_N3
--operation mode is normal
 
BD1_un10_res_16 = PB1_dout_iv_21 # PB1_dout_iv_16 # PB1_dout_iv_1 # PB1_dout_iv_4;
 
 
--BD1_un10_res_17 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_17 at LC_X23_Y7_N8
--operation mode is normal
 
BD1_un10_res_17 = PB1_dout_iv_0 # PB1_dout_iv_27 # PB1_dout_iv_26 # PB1_dout_iv_11;
 
 
--BD1_un10_res_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_23 at LC_X23_Y7_N2
--operation mode is normal
 
BD1_un10_res_23 = PB1_dout_iv_23 # PB1_dout_iv_5 # PB1_dout_iv_20 # !BD1_un10_res_23_a;
 
 
--BD1_un10_res_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_18 at LC_X24_Y8_N5
--operation mode is normal
 
BD1_un10_res_18 = PB1_dout_iv_7 # PB1_dout_iv_22 # PB1_dout_iv_10 # PB1_dout_iv_6;
 
 
--BD1_un10_res_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_19 at LC_X24_Y8_N7
--operation mode is normal
 
BD1_un10_res_19 = PB1_dout_iv_13 # PB1_dout_iv_12 # PB1_dout_iv_28 # PB1_dout_iv_30;
 
 
--BD1_un10_res_20 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_20 at LC_X24_Y8_N6
--operation mode is normal
 
BD1_un10_res_20 = PB1_dout_iv_25 # PB1_dout_iv_9 # PB1_dout_iv_8 # PB1_dout_iv_24;
 
 
--BD1_un10_res_21 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_21 at LC_X24_Y8_N0
--operation mode is normal
 
BD1_un10_res_21 = PB1_dout_iv_17 # PB1_dout_iv_3 # PB1_dout_iv_2 # PB1_dout_iv_18;
 
 
--UB1_dout_2_0_0_a_x[10] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[10] at LC_X28_Y7_N4
--operation mode is normal
 
UB1_dout_2_0_0_a_x[10] = !HE1_q_b[2] # !UB1_dout_2_0_0_o2_1[9];
 
 
--UB1_dout_2_i_i_a_x[11] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[11] at LC_X28_Y7_N8
--operation mode is normal
 
UB1_dout_2_i_i_a_x[11] = !HE1_q_b[3] # !UB1_dout_2_0_0_o2_1[9];
 
 
--UB1_dout_2_0_0_a_x[12] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_0_0_a_x[12] at LC_X27_Y8_N1
--operation mode is normal
 
UB1_dout_2_0_0_a_x[12] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[4];
 
 
--UB1_dout_2_i_i_a[23] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a[23] at LC_X29_Y13_N0
--operation mode is normal
 
UB1_dout_2_i_i_a[23] = !UB1_dout_2_i_i_a3[15] & RB1_ctl_o_1 & RB1_ctl_o_3 # !UB1_dout_2_i_i_a3_1[15];
 
 
--UB1_dout_2_i_i_a_x[13] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[13] at LC_X27_Y6_N6
--operation mode is normal
 
UB1_dout_2_i_i_a_x[13] = !UB1_dout_2_0_0_o2_1[9] # !HE1_q_b[5];
 
 
--UB1_dout_2_i_i_a_x[14] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_a_x[14] at LC_X28_Y7_N1
--operation mode is normal
 
UB1_dout_2_i_i_a_x[14] = !HE1_q_b[6] # !UB1_dout_2_0_0_o2_1[9];
 
 
--YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|muxa_ctl_2_0_0_a2_0_0_a_x[1] at LC_X25_Y18_N0
--operation mode is normal
 
YB1_muxa_ctl_2_0_0_a2_0_0_a_x[1] = GE1_q_a[1] & !GE1_q_a[2];
 
 
--UB1_dout_2_i_i_1[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_1[15] at LC_X29_Y13_N1
--operation mode is normal
 
UB1_dout_2_i_i_1[15] = RB1_ctl_o_2 & !UB1_dout_2_i_i_1_a[15] & RB1_ctl_o_1 # !RB1_ctl_o_2 & UB1_dout_2_i_i_a3[15] # UB1_dout_2_i_i_1_a[15] & RB1_ctl_o_1;
 
 
--VD1_un1_rdy_0_sqmuxa_3_combout is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|un1_rdy_0_sqmuxa_3_combout at LC_X2_Y15_N8
--operation mode is normal
 
VD1_un1_rdy_0_sqmuxa_3_combout = VD1_rdy_0_sqmuxa # !VD1_count[5] & VD1_addnop2110 & !VD1_overflow;
 
 
--VD1_over_carry_27 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_27 at LC_X10_Y10_N1
--operation mode is arithmetic
 
VD1_over_carry_27_cout_0 = VD1_b_o_iv_27 & !VD1_over_carry_26 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !VD1_over_carry_26;
VD1_over_carry_27 = CARRY(VD1_over_carry_27_cout_0);
 
--VD1L3251 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_27~COUT1_1 at LC_X10_Y10_N1
--operation mode is arithmetic
 
VD1L3251_cout_1 = VD1_b_o_iv_27 & !VD1L1251 # !PD1_a_o_27 # !VD1_b_o_iv_27 & !PD1_a_o_27 & !VD1L1251;
VD1L3251 = CARRY(VD1L3251_cout_1);
 
 
--HD1_dout_iv_1_a[16] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[16] at LC_X25_Y4_N4
--operation mode is normal
 
HD1_dout_iv_1_a[16] = FD1_N_14_i_0_s2 & !FD1_r_data_16 & !YD1_mux_fw_1 # !AB1_r32_o_14 # !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_14;
 
 
--HD1_dout_iv_1_a[17] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[17] at LC_X25_Y8_N4
--operation mode is normal
 
HD1_dout_iv_1_a[17] = FD1_r_data_17 & !FD1_N_14_i_0_s2 & !AB1_r32_o_15 # !YD1_mux_fw_1 # !FD1_r_data_17 & !AB1_r32_o_15 # !YD1_mux_fw_1;
 
 
--HD1_dout_iv_1_a[14] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[14] at LC_X25_Y8_N9
--operation mode is normal
 
HD1_dout_iv_1_a[14] = FD1_N_14_i_0_s2 & !FD1_r_data_14 & !YD1_mux_fw_1 # !AB1_r32_o_12 # !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_12;
 
 
--HD1_dout_iv_1_a[15] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[15] at LC_X24_Y4_N1
--operation mode is normal
 
HD1_dout_iv_1_a[15] = FD1_N_14_i_0_s2 & !FD1_r_data_15 & !YD1_mux_fw_1 # !AB1_r32_o_13 # !FD1_N_14_i_0_s2 & !YD1_mux_fw_1 # !AB1_r32_o_13;
 
 
--DD1_un1_pc_prectl_1_0_a4[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[19] at LC_X28_Y8_N5
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[19] = FB1_res_7_0_0_19 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[18] at LC_X19_Y5_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[18] = FB1_res_7_0_0_18 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_18 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_18 & !SD1_r32_o_18 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[18] at LC_X23_Y13_N9
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[18] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_18;
 
 
--DD1_pc_next_0_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[19] at LC_X22_Y6_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[19] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_19 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_19 # !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_19;
 
 
--HD1_dout_iv_1_a[21] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[21] at LC_X20_Y7_N0
--operation mode is normal
 
HD1_dout_iv_1_a[21] = YD1_mux_fw_1 & !AB1_r32_o_19 & !FD1_N_14_i_0_s2 # !FD1_r_data_21 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_21;
 
 
--HD1_dout_iv_1_a[20] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[20] at LC_X21_Y7_N2
--operation mode is normal
 
HD1_dout_iv_1_a[20] = FD1_N_14_i_0_s2 & !FD1_r_data_20 & !AB1_r32_o_18 # !YD1_mux_fw_1 # !FD1_N_14_i_0_s2 & !AB1_r32_o_18 # !YD1_mux_fw_1;
 
 
--HD1_dout_iv_1_19 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_19 at LC_X26_Y7_N0
--operation mode is normal
 
HD1_dout_iv_1_19 = FD1_N_18_i_0_s3 & LD2_q_b[19] # !HD1_dout_iv_1_a[19];
 
 
--HD1_dout_iv_1_18 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_18 at LC_X21_Y8_N7
--operation mode is normal
 
HD1_dout_iv_1_18 = FD1_N_18_i_0_s3 & LD2_q_b[18] # !HD1_dout_iv_1_a[18];
 
 
--HD1_dout_iv_1_26 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_26 at LC_X20_Y8_N6
--operation mode is normal
 
HD1_dout_iv_1_26 = LD2_q_b[26] & FD1_N_18_i_0_s3 # !HD1_dout_iv_1_a[26];
 
 
--VD1_hilo_37_iv_0_0[59] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[59] at LC_X5_Y2_N8
--operation mode is normal
 
VD1_hilo_37_iv_0_0[59] = VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_4[62] & !VD1_hilo_59 # !VD1_hilo_27 # !VD1_hilo_0_sqmuxa & VD1_hilo_37_iv_0_a3_4[62] & !VD1_hilo_59;
 
 
--HD1_dout_iv_1_27 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_27 at LC_X22_Y7_N1
--operation mode is normal
 
HD1_dout_iv_1_27 = FD1_N_18_i_0_s3 & LD2_q_b[27] # !HD1_dout_iv_1_a[27];
 
 
--VD1_hilo_37_iv_0_3[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_3[60] at LC_X7_Y2_N4
--operation mode is normal
 
VD1_hilo_37_iv_0_3[60] = VD1_hilo_37_iv_0_1[60] # VD1_hilo_37_iv_0_a5_0[60] # !VD1_hilo_61 & VD1_hilo_37_iv_0_a6_0_1[40];
 
 
--VD1_hilo_37_iv_0_6_a[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_6_a[60] at LC_X7_Y2_N3
--operation mode is normal
 
VD1_hilo_37_iv_0_6_a[60] = VD1_un50_hilo_add28 & VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add29 # !VD1_un50_hilo_add28 & VD1_hilo_37_iv_0_a2_6_0[37] # VD1_hilo_37_iv_0_a6_1_0[40] & !VD1_un59_hilo_add29;
 
 
--VD1_hilo_37_iv_0_0[61] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[61] at LC_X7_Y2_N7
--operation mode is normal
 
VD1_hilo_37_iv_0_0[61] = VD1_hilo_61 & VD1_hilo_0_sqmuxa & !VD1_hilo_29 # !VD1_hilo_61 & VD1_hilo_37_iv_0_a3_4[62] # VD1_hilo_0_sqmuxa & !VD1_hilo_29;
 
 
--HD1_dout_iv_1_a[13] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[13] at LC_X26_Y11_N4
--operation mode is normal
 
HD1_dout_iv_1_a[13] = YD1_mux_fw_1 & !AB1_r32_o_11 & !FD1_r_data_13 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_13 # !FD1_N_14_i_0_s2;
 
 
--DD1_pc_next_0_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[24] at LC_X20_Y3_N6
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[24] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_24 & !FB1_res_7_0_0_24 # !DD1_pc_next_1_sqmuxa_0_a4 # !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_24 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[24] at LC_X24_Y13_N7
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[24] = FB1_res_7_0_0_24 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[25] at LC_X24_Y6_N5
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[25] = DD1_pc_next_1_sqmuxa_0_a4 & !FB1_res_7_0_0_25 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_25 # !DD1_pc_next_1_sqmuxa_0_a4 & !DD1_pc_next_0_sqmuxa_0_a4 # !SD1_r32_o_25;
 
 
--DD1_un1_pc_prectl_1_0_a4[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[25] at LC_X24_Y6_N0
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[25] = DD1_un1_pc_prectl_1_0_a3[0] & FB1_res_7_0_0_25;
 
 
--HD1_dout_iv_1_24 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_24 at LC_X23_Y6_N5
--operation mode is normal
 
HD1_dout_iv_1_24 = FD1_N_18_i_0_s3 & LD2_q_b[24] # !HD1_dout_iv_1_a[24];
 
 
--HD1_dout_iv_1_25 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_25 at LC_X24_Y8_N8
--operation mode is normal
 
HD1_dout_iv_1_25 = FD1_N_18_i_0_s3 & LD2_q_b[25] # !HD1_dout_iv_1_a[25];
 
 
--DD1_pc_next_0_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[22] at LC_X24_Y5_N9
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[22] = DD1_pc_next_0_sqmuxa_0_a4 & !SD1_r32_o_22 & !FB1_res_7_0_0_22 # !DD1_pc_next_1_sqmuxa_0_a4 # !DD1_pc_next_0_sqmuxa_0_a4 & !FB1_res_7_0_0_22 # !DD1_pc_next_1_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[22] at LC_X24_Y5_N3
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[22] = FB1_res_7_0_0_22 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--DD1_pc_next_0_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_iv_1_a[23] at LC_X22_Y3_N2
--operation mode is normal
 
DD1_pc_next_0_iv_1_a[23] = FB1_res_7_0_0_23 & !DD1_pc_next_1_sqmuxa_0_a4 & !SD1_r32_o_23 # !DD1_pc_next_0_sqmuxa_0_a4 # !FB1_res_7_0_0_23 & !SD1_r32_o_23 # !DD1_pc_next_0_sqmuxa_0_a4;
 
 
--DD1_un1_pc_prectl_1_0_a4[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_prectl_1_0_a4[23] at LC_X24_Y13_N1
--operation mode is normal
 
DD1_un1_pc_prectl_1_0_a4[23] = FB1_res_7_0_0_23 & DD1_un1_pc_prectl_1_0_a3[0];
 
 
--HD1_dout_iv_1_22 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_22 at LC_X24_Y7_N1
--operation mode is normal
 
HD1_dout_iv_1_22 = FD1_N_18_i_0_s3 & LD2_q_b[22] # !HD1_dout_iv_1_a[22];
 
 
--HD1_dout_iv_1_23 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_23 at LC_X23_Y5_N3
--operation mode is normal
 
HD1_dout_iv_1_23 = FD1_N_18_i_0_s3 & LD2_q_b[23] # !HD1_dout_iv_1_a[23];
 
 
--HD1_dout_iv_1_a[28] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[28] at LC_X26_Y8_N2
--operation mode is normal
 
HD1_dout_iv_1_a[28] = FD1_r_data_28 & !FD1_N_14_i_0_s2 & !AB1_r32_o_26 # !YD1_mux_fw_1 # !FD1_r_data_28 & !AB1_r32_o_26 # !YD1_mux_fw_1;
 
 
--HD1_dout_iv_1_a[29] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[29] at LC_X26_Y11_N3
--operation mode is normal
 
HD1_dout_iv_1_a[29] = YD1_mux_fw_1 & !AB1_r32_o_27 & !FD1_r_data_29 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_29 # !FD1_N_14_i_0_s2;
 
 
--TD1_lt_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_22 at LC_X16_Y8_N6
--operation mode is arithmetic
 
TD1_lt_22_cout_0 = VD1_b_o_iv_22 & !TD1_lt_21 # !PD1_a_o_22 # !VD1_b_o_iv_22 & !PD1_a_o_22 & !TD1_lt_21;
TD1_lt_22 = CARRY(TD1_lt_22_cout_0);
 
--TD1L381 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_22~COUT1_1 at LC_X16_Y8_N6
--operation mode is arithmetic
 
TD1L381_cout_1 = VD1_b_o_iv_22 & !TD1L181 # !PD1_a_o_22 # !VD1_b_o_iv_22 & !PD1_a_o_22 & !TD1L181;
TD1L381 = CARRY(TD1L381_cout_1);
 
 
--TD1_sum_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_23 at LC_X15_Y7_N7
--operation mode is arithmetic
 
TD1_sum_carry_23_cout_0 = VD1_b_o_iv_23 & !TD1_sum_carry_22 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !TD1_sum_carry_22;
TD1_sum_carry_23 = CARRY(TD1_sum_carry_23_cout_0);
 
--TD1L034 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_23~COUT1_1 at LC_X15_Y7_N7
--operation mode is arithmetic
 
TD1L034_cout_1 = VD1_b_o_iv_23 & !TD1L824 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !TD1L824;
TD1L034 = CARRY(TD1L034_cout_1);
 
 
--YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_5_0_x[2] at LC_X26_Y13_N2
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3_5_0_x[2] = !JE1_q_a[0] & JE1_q_a[4];
 
 
--YB1_pc_gen_ctl_2_i_0_a2_0_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a2_0_x[2] at LC_X26_Y17_N5
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a2_0_x[2] = !KE1_q_a[6] & YB1_fsm_dly_2_0_0_a2_x[2] & !KE1_q_a[2];
 
 
--YB1_pc_gen_ctl_2_i_0_a3_3[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_3[2] at LC_X26_Y17_N7
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3_3[2] = KE1_q_a[2] & JE1_q_a[4] & YB1_fsm_dly_2_0_0_a2_x[2] & !WB26L2;
 
 
--YB1_pc_gen_ctl_2_i_0_0_Z[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_0_Z[2] at LC_X26_Y17_N6
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_0_Z[2] = YB1_pc_gen_ctl_2_i_0_a3_2[2] # YB1_pc_gen_ctl_2_0_0_a2_x[1] & GE1_q_a[3] & YB1_pc_gen_ctl_2_i_0_a2_0_x[2];
 
 
--YB1_pc_gen_ctl_2_i_m3_0_2_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_m3_0_2_a[0] at LC_X27_Y18_N9
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_m3_0_2_a[0] = KE1_q_a[7] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB06L2 # !KE1_q_a[7] & !YB1_alu_func_2_0_0_a2_2_x[1] & !YB1_fsm_dly_2_0_0_o2_x[2] # !WB06L2;
 
 
--YB1_cmp_ctl_2_0_0_1_a[0] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_a[0] at LC_X25_Y16_N8
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_1_a[0] = !KE1_q_a[3] & KE1_q_a[7] # KE1_q_a[2] # !YB1_cmp_ctl_2_0_0_a2_x[0];
 
 
--YB1_cmp_ctl_2_0_0_a[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a[2] at LC_X26_Y16_N6
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a[2] = YB1_ext_ctl_2_0_0_o2[2] & !WB54L1 & JE1_q_a[4] # !YB1_pc_gen_ctl_2_i_0_a2_1[2] # !YB1_ext_ctl_2_0_0_o2[2] & JE1_q_a[4] # !YB1_pc_gen_ctl_2_i_0_a2_1[2];
 
 
--YB1_cmp_ctl_2_0_0_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_a[1] at LC_X25_Y16_N3
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_a[1] = !YB1_cmp_ctl_2_0_0_1_Z[1] & !YB1_ext_ctl_2_0_0_a2_0_x[2] # !KE1_q_a[2] # !KE1_q_a[4];
 
 
--BD1_res_2_12 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_12 at LC_X26_Y11_N8
--operation mode is normal
 
BD1_res_2_12 = QB1_dout_iv_12 $ (HD1_dout_iv_1_12 # FD1_wb_o_12 & HD1_dout7_0_a2);
 
 
--BD1_res_2_NE_7_0_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_7_0_a at LC_X26_Y11_N2
--operation mode is normal
 
BD1_res_2_NE_7_0_a = PB1_dout_iv_13 & PB1_dout_iv_29 $ QB1_dout_iv_29 # !QB1_dout_iv_13 # !PB1_dout_iv_13 & QB1_dout_iv_13 # PB1_dout_iv_29 $ QB1_dout_iv_29;
 
 
--BD1_res_2_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_0 at LC_X25_Y7_N5
--operation mode is normal
 
BD1_res_2_0 = QB1_dout_iv_0 $ (HD1_dout_iv_1_0 # FD1_wb_o_0 & HD1_dout7_0_a2);
 
 
--BD1_res_2_NE_1_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|res_2_NE_1_a at LC_X25_Y7_N8
--operation mode is normal
 
BD1_res_2_NE_1_a = QB1_dout_iv_17 & QB1_dout_iv_1 $ PB1_dout_iv_1 # !PB1_dout_iv_17 # !QB1_dout_iv_17 & PB1_dout_iv_17 # QB1_dout_iv_1 $ PB1_dout_iv_1;
 
 
--BD1_un10_res_23_a is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp|un10_res_23_a at LC_X23_Y7_N1
--operation mode is normal
 
BD1_un10_res_23_a = !PB1_dout_iv_29 & !PB1_dout_iv_19 & !PB1_dout_iv_15 & !PB1_dout_iv_14;
 
 
--UB1_dout_2_i_i_1_a[15] is mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl|dout_2_i_i_1_a[15] at LC_X29_Y13_N8
--operation mode is normal
 
UB1_dout_2_i_i_1_a[15] = UB1_dout_2_i_i_o3_0[7] & RB1_ctl_o_2 & !HE1_q_b[7] # !UB1_dout_2_i_i_o3_0[7] & KE1_q_b[7] $ RB1_ctl_o_2;
 
 
--VD1_over_carry_26 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_26 at LC_X10_Y10_N0
--operation mode is arithmetic
 
VD1_over_carry_26_cout_0 = PD1_a_o_26 & !VD1_over_carry_25 # !VD1_b_o_iv_26 # !PD1_a_o_26 & !VD1_b_o_iv_26 & !VD1_over_carry_25;
VD1_over_carry_26 = CARRY(VD1_over_carry_26_cout_0);
 
--VD1L1251 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_26~COUT1_1 at LC_X10_Y10_N0
--operation mode is arithmetic
 
VD1L1251_cout_1 = PD1_a_o_26 & !VD1_over_carry_25 # !VD1_b_o_iv_26 # !PD1_a_o_26 & !VD1_b_o_iv_26 & !VD1_over_carry_25;
VD1L1251 = CARRY(VD1L1251_cout_1);
 
 
--HD1_dout_iv_1_a[19] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[19] at LC_X26_Y7_N8
--operation mode is normal
 
HD1_dout_iv_1_a[19] = YD1_mux_fw_1 & !AB1_r32_o_17 & !FD1_r_data_19 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_19 # !FD1_N_14_i_0_s2;
 
 
--HD1_dout_iv_1_a[18] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[18] at LC_X21_Y8_N6
--operation mode is normal
 
HD1_dout_iv_1_a[18] = AB1_r32_o_16 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_18 # !AB1_r32_o_16 & !FD1_N_14_i_0_s2 # !FD1_r_data_18;
 
 
--HD1_dout_iv_1_a[26] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[26] at LC_X20_Y8_N5
--operation mode is normal
 
HD1_dout_iv_1_a[26] = FD1_r_data_26 & !FD1_N_14_i_0_s2 & !AB1_r32_o_24 # !YD1_mux_fw_1 # !FD1_r_data_26 & !AB1_r32_o_24 # !YD1_mux_fw_1;
 
 
--HD1_dout_iv_1_a[27] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[27] at LC_X22_Y7_N0
--operation mode is normal
 
HD1_dout_iv_1_a[27] = YD1_mux_fw_1 & !AB1_r32_o_25 & !FD1_r_data_27 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_27 # !FD1_N_14_i_0_s2;
 
 
--VD1_hilo_37_iv_0_a5_0[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_a5_0[60] at LC_X7_Y2_N6
--operation mode is normal
 
VD1_hilo_37_iv_0_a5_0[60] = !VD1_hilo_60 & VD1_hilo_37_iv_0_a3_1[62];
 
 
--VD1_hilo_37_iv_0_1[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_1[60] at LC_X7_Y2_N2
--operation mode is normal
 
VD1_hilo_37_iv_0_1[60] = VD1_hilo_37_iv_0_0[60] # !VD1_un59_hilo_add28 & VD1_hilo_37_iv_0_a3_2[62];
 
 
--HD1_dout_iv_1_a[24] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[24] at LC_X23_Y6_N1
--operation mode is normal
 
HD1_dout_iv_1_a[24] = YD1_mux_fw_1 & !AB1_r32_o_22 & !FD1_N_14_i_0_s2 # !FD1_r_data_24 # !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_24;
 
 
--HD1_dout_iv_1_a[25] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[25] at LC_X25_Y6_N5
--operation mode is normal
 
HD1_dout_iv_1_a[25] = AB1_r32_o_23 & !YD1_mux_fw_1 & !FD1_N_14_i_0_s2 # !FD1_r_data_25 # !AB1_r32_o_23 & !FD1_N_14_i_0_s2 # !FD1_r_data_25;
 
 
--HD1_dout_iv_1_a[22] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[22] at LC_X24_Y7_N9
--operation mode is normal
 
HD1_dout_iv_1_a[22] = YD1_mux_fw_1 & !AB1_r32_o_20 & !FD1_r_data_22 # !FD1_N_14_i_0_s2 # !YD1_mux_fw_1 & !FD1_r_data_22 # !FD1_N_14_i_0_s2;
 
 
--HD1_dout_iv_1_a[23] is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout_iv_1_a[23] at LC_X23_Y5_N2
--operation mode is normal
 
HD1_dout_iv_1_a[23] = FD1_r_data_23 & !FD1_N_14_i_0_s2 & !AB1_r32_o_21 # !YD1_mux_fw_1 # !FD1_r_data_23 & !AB1_r32_o_21 # !YD1_mux_fw_1;
 
 
--TD1_lt_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_21 at LC_X16_Y8_N5
--operation mode is arithmetic
 
TD1_lt_21_cout_0 = PD1_a_o_21 & !TD1_lt_20 # !VD1_b_o_iv_21 # !PD1_a_o_21 & !VD1_b_o_iv_21 & !TD1_lt_20;
TD1_lt_21 = CARRY(TD1_lt_21_cout_0);
 
--TD1L181 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_21~COUT1_1 at LC_X16_Y8_N5
--operation mode is arithmetic
 
TD1L181_cout_1 = PD1_a_o_21 & !TD1_lt_20 # !VD1_b_o_iv_21 # !PD1_a_o_21 & !VD1_b_o_iv_21 & !TD1_lt_20;
TD1L181 = CARRY(TD1L181_cout_1);
 
 
--TD1_sum_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_22 at LC_X15_Y7_N6
--operation mode is arithmetic
 
TD1_sum_carry_22_cout_0 = PD1_a_o_22 & !TD1_sum_carry_21 # !VD1_b_o_iv_22 # !PD1_a_o_22 & !VD1_b_o_iv_22 & !TD1_sum_carry_21;
TD1_sum_carry_22 = CARRY(TD1_sum_carry_22_cout_0);
 
--TD1L824 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_22~COUT1_1 at LC_X15_Y7_N6
--operation mode is arithmetic
 
TD1L824_cout_1 = PD1_a_o_22 & !TD1L624 # !VD1_b_o_iv_22 # !PD1_a_o_22 & !VD1_b_o_iv_22 & !TD1L624;
TD1L824 = CARRY(TD1L824_cout_1);
 
 
--YB1_pc_gen_ctl_2_i_0_a3_2[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_2[2] at LC_X26_Y17_N0
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3_2[2] = KE1_q_a[3] & !KE1_q_a[5] & !KE1_q_a[4] & YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2];
 
 
--YB1_pc_gen_ctl_2_i_0_a2_1[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a2_1[2] at LC_X26_Y13_N7
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a2_1[2] = !JE1_q_a[3] & !JE1_q_a[2] & !JE1_q_a[1] & KE1_q_a[2];
 
 
--YB1_cmp_ctl_2_0_0_1_Z[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_Z[1] at LC_X25_Y16_N6
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_1_Z[1] = YB1_cmp_ctl_2_0_0_1_a[1] & YB1_cmp_ctl_2_0_0_a2_x[0] & !YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x # !YB1_cmp_ctl_2_0_0_1_a[1] & YB1_ext_ctl_2_0_0_a2_0_x[2] # YB1_cmp_ctl_2_0_0_a2_x[0] & !YB1_muxa_ctl350_1_0_a2_0_a3_0_o2_x;
 
 
--VD1_over_carry_25 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_25 at LC_X10_Y11_N9
--operation mode is arithmetic
 
VD1_over_carry_25 = CARRY(PD1_a_o_25 & VD1_b_o_iv_25 & !VD1L8151 # !PD1_a_o_25 & VD1_b_o_iv_25 # !VD1L8151);
 
 
--VD1_hilo_37_iv_0_0[60] is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_37_iv_0_0[60] at LC_X7_Y2_N9
--operation mode is normal
 
VD1_hilo_37_iv_0_0[60] = VD1_hilo_60 & VD1_hilo_0_sqmuxa & !VD1_hilo_28 # !VD1_hilo_60 & VD1_hilo_37_iv_0_a3_4[62] # VD1_hilo_0_sqmuxa & !VD1_hilo_28;
 
 
--TD1_lt_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_20 at LC_X16_Y8_N4
--operation mode is arithmetic
 
TD1_lt_20 = CARRY(VD1_b_o_iv_20 & !TD1L871 # !PD1_a_o_20 # !VD1_b_o_iv_20 & !PD1_a_o_20 & !TD1L871);
 
 
--TD1_sum_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_21 at LC_X15_Y7_N5
--operation mode is arithmetic
 
TD1_sum_carry_21_cout_0 = VD1_b_o_iv_21 & !TD1_sum_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !TD1_sum_carry_20;
TD1_sum_carry_21 = CARRY(TD1_sum_carry_21_cout_0);
 
--TD1L624 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_21~COUT1_1 at LC_X15_Y7_N5
--operation mode is arithmetic
 
TD1L624_cout_1 = VD1_b_o_iv_21 & !TD1_sum_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !TD1_sum_carry_20;
TD1L624 = CARRY(TD1L624_cout_1);
 
 
--YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|pc_gen_ctl_2_i_0_a3_2_a_x[2] at LC_X26_Y17_N3
--operation mode is normal
 
YB1_pc_gen_ctl_2_i_0_a3_2_a_x[2] = !KE1_q_a[6] & !KE1_q_a[2];
 
 
--YB1_cmp_ctl_2_0_0_1_a[1] is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|cmp_ctl_2_0_0_1_a[1] at LC_X25_Y16_N7
--operation mode is normal
 
YB1_cmp_ctl_2_0_0_1_a[1] = YB1_cmp_ctl_2_0_0_a2_x[2] & JE1_q_a[0] & !WB44L1 # !YB1_cmp_ctl_2_0_0_a2_1[0] # !YB1_cmp_ctl_2_0_0_a2_x[2] & !WB44L1 # !YB1_cmp_ctl_2_0_0_a2_1[0];
 
 
--VD1_over_carry_24 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_24 at LC_X10_Y11_N8
--operation mode is arithmetic
 
VD1_over_carry_24_cout_0 = VD1_b_o_iv_24 & PD1_a_o_24 & !VD1_over_carry_23 # !VD1_b_o_iv_24 & PD1_a_o_24 # !VD1_over_carry_23;
VD1_over_carry_24 = CARRY(VD1_over_carry_24_cout_0);
 
--VD1L8151 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_24~COUT1_1 at LC_X10_Y11_N8
--operation mode is arithmetic
 
VD1L8151_cout_1 = VD1_b_o_iv_24 & PD1_a_o_24 & !VD1L6151 # !VD1_b_o_iv_24 & PD1_a_o_24 # !VD1L6151;
VD1L8151 = CARRY(VD1L8151_cout_1);
 
 
--TD1_lt_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_19 at LC_X16_Y8_N3
--operation mode is arithmetic
 
TD1_lt_19_cout_0 = PD1_a_o_19 & !TD1_lt_18 # !VD1_b_o_iv_19 # !PD1_a_o_19 & !VD1_b_o_iv_19 & !TD1_lt_18;
TD1_lt_19 = CARRY(TD1_lt_19_cout_0);
 
--TD1L871 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_19~COUT1_1 at LC_X16_Y8_N3
--operation mode is arithmetic
 
TD1L871_cout_1 = PD1_a_o_19 & !TD1L671 # !VD1_b_o_iv_19 # !PD1_a_o_19 & !VD1_b_o_iv_19 & !TD1L671;
TD1L871 = CARRY(TD1L871_cout_1);
 
 
--TD1_sum_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_20 at LC_X15_Y7_N4
--operation mode is arithmetic
 
TD1_sum_carry_20 = CARRY(VD1_b_o_iv_20 & PD1_a_o_20 & !TD1L324 # !VD1_b_o_iv_20 & PD1_a_o_20 # !TD1L324);
 
 
--VD1_over_carry_23 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_23 at LC_X10_Y11_N7
--operation mode is arithmetic
 
VD1_over_carry_23_cout_0 = VD1_b_o_iv_23 & !VD1_over_carry_22 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !VD1_over_carry_22;
VD1_over_carry_23 = CARRY(VD1_over_carry_23_cout_0);
 
--VD1L6151 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_23~COUT1_1 at LC_X10_Y11_N7
--operation mode is arithmetic
 
VD1L6151_cout_1 = VD1_b_o_iv_23 & !VD1L4151 # !PD1_a_o_23 # !VD1_b_o_iv_23 & !PD1_a_o_23 & !VD1L4151;
VD1L6151 = CARRY(VD1L6151_cout_1);
 
 
--TD1_lt_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_18 at LC_X16_Y8_N2
--operation mode is arithmetic
 
TD1_lt_18_cout_0 = PD1_a_o_18 & VD1_b_o_iv_18 & !TD1_lt_17 # !PD1_a_o_18 & VD1_b_o_iv_18 # !TD1_lt_17;
TD1_lt_18 = CARRY(TD1_lt_18_cout_0);
 
--TD1L671 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_18~COUT1_1 at LC_X16_Y8_N2
--operation mode is arithmetic
 
TD1L671_cout_1 = PD1_a_o_18 & VD1_b_o_iv_18 & !TD1L471 # !PD1_a_o_18 & VD1_b_o_iv_18 # !TD1L471;
TD1L671 = CARRY(TD1L671_cout_1);
 
 
--TD1_sum_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_19 at LC_X15_Y7_N3
--operation mode is arithmetic
 
TD1_sum_carry_19_cout_0 = PD1_a_o_19 & VD1_b_o_iv_19 & !TD1_sum_carry_18 # !PD1_a_o_19 & VD1_b_o_iv_19 # !TD1_sum_carry_18;
TD1_sum_carry_19 = CARRY(TD1_sum_carry_19_cout_0);
 
--TD1L324 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_19~COUT1_1 at LC_X15_Y7_N3
--operation mode is arithmetic
 
TD1L324_cout_1 = PD1_a_o_19 & VD1_b_o_iv_19 & !TD1L124 # !PD1_a_o_19 & VD1_b_o_iv_19 # !TD1L124;
TD1L324 = CARRY(TD1L324_cout_1);
 
 
--VD1_over_carry_22 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_22 at LC_X10_Y11_N6
--operation mode is arithmetic
 
VD1_over_carry_22_cout_0 = PD1_a_o_22 & !VD1_over_carry_21 # !VD1_b_o_iv_22 # !PD1_a_o_22 & !VD1_b_o_iv_22 & !VD1_over_carry_21;
VD1_over_carry_22 = CARRY(VD1_over_carry_22_cout_0);
 
--VD1L4151 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_22~COUT1_1 at LC_X10_Y11_N6
--operation mode is arithmetic
 
VD1L4151_cout_1 = PD1_a_o_22 & !VD1L2151 # !VD1_b_o_iv_22 # !PD1_a_o_22 & !VD1_b_o_iv_22 & !VD1L2151;
VD1L4151 = CARRY(VD1L4151_cout_1);
 
 
--TD1_lt_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_17 at LC_X16_Y8_N1
--operation mode is arithmetic
 
TD1_lt_17_cout_0 = VD1_b_o_iv_17 & PD1_a_o_17 & !TD1_lt_16 # !VD1_b_o_iv_17 & PD1_a_o_17 # !TD1_lt_16;
TD1_lt_17 = CARRY(TD1_lt_17_cout_0);
 
--TD1L471 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_17~COUT1_1 at LC_X16_Y8_N1
--operation mode is arithmetic
 
TD1L471_cout_1 = VD1_b_o_iv_17 & PD1_a_o_17 & !TD1L271 # !VD1_b_o_iv_17 & PD1_a_o_17 # !TD1L271;
TD1L471 = CARRY(TD1L471_cout_1);
 
 
--TD1_sum_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_18 at LC_X15_Y7_N2
--operation mode is arithmetic
 
TD1_sum_carry_18_cout_0 = PD1_a_o_18 & !TD1_sum_carry_17 # !VD1_b_o_iv_18 # !PD1_a_o_18 & !VD1_b_o_iv_18 & !TD1_sum_carry_17;
TD1_sum_carry_18 = CARRY(TD1_sum_carry_18_cout_0);
 
--TD1L124 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_18~COUT1_1 at LC_X15_Y7_N2
--operation mode is arithmetic
 
TD1L124_cout_1 = PD1_a_o_18 & !TD1L914 # !VD1_b_o_iv_18 # !PD1_a_o_18 & !VD1_b_o_iv_18 & !TD1L914;
TD1L124 = CARRY(TD1L124_cout_1);
 
 
--VD1_over_carry_21 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_21 at LC_X10_Y11_N5
--operation mode is arithmetic
 
VD1_over_carry_21_cout_0 = VD1_b_o_iv_21 & !VD1_over_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !VD1_over_carry_20;
VD1_over_carry_21 = CARRY(VD1_over_carry_21_cout_0);
 
--VD1L2151 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_21~COUT1_1 at LC_X10_Y11_N5
--operation mode is arithmetic
 
VD1L2151_cout_1 = VD1_b_o_iv_21 & !VD1_over_carry_20 # !PD1_a_o_21 # !VD1_b_o_iv_21 & !PD1_a_o_21 & !VD1_over_carry_20;
VD1L2151 = CARRY(VD1L2151_cout_1);
 
 
--TD1_lt_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_16 at LC_X16_Y8_N0
--operation mode is arithmetic
 
TD1_lt_16_cout_0 = VD1_b_o_iv_16 & !TD1_lt_15 # !PD1_a_o_16 # !VD1_b_o_iv_16 & !PD1_a_o_16 & !TD1_lt_15;
TD1_lt_16 = CARRY(TD1_lt_16_cout_0);
 
--TD1L271 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_16~COUT1_1 at LC_X16_Y8_N0
--operation mode is arithmetic
 
TD1L271_cout_1 = VD1_b_o_iv_16 & !TD1_lt_15 # !PD1_a_o_16 # !VD1_b_o_iv_16 & !PD1_a_o_16 & !TD1_lt_15;
TD1L271 = CARRY(TD1L271_cout_1);
 
 
--TD1_sum_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_17 at LC_X15_Y7_N1
--operation mode is arithmetic
 
TD1_sum_carry_17_cout_0 = PD1_a_o_17 & VD1_b_o_iv_17 & !TD1_sum_carry_16 # !PD1_a_o_17 & VD1_b_o_iv_17 # !TD1_sum_carry_16;
TD1_sum_carry_17 = CARRY(TD1_sum_carry_17_cout_0);
 
--TD1L914 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_17~COUT1_1 at LC_X15_Y7_N1
--operation mode is arithmetic
 
TD1L914_cout_1 = PD1_a_o_17 & VD1_b_o_iv_17 & !TD1L714 # !PD1_a_o_17 & VD1_b_o_iv_17 # !TD1L714;
TD1L914 = CARRY(TD1L914_cout_1);
 
 
--VD1_over_carry_20 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_20 at LC_X10_Y11_N4
--operation mode is arithmetic
 
VD1_over_carry_20 = CARRY(VD1_b_o_iv_20 & PD1_a_o_20 & !VD1L9051 # !VD1_b_o_iv_20 & PD1_a_o_20 # !VD1L9051);
 
 
--TD1_lt_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_15 at LC_X16_Y9_N9
--operation mode is arithmetic
 
TD1_lt_15 = CARRY(VD1_b_o_iv_15 & PD1_a_o_15 & !TD1L961 # !VD1_b_o_iv_15 & PD1_a_o_15 # !TD1L961);
 
 
--TD1_sum_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_16 at LC_X15_Y7_N0
--operation mode is arithmetic
 
TD1_sum_carry_16_cout_0 = PD1_a_o_16 & !TD1_sum_carry_15 # !VD1_b_o_iv_16 # !PD1_a_o_16 & !VD1_b_o_iv_16 & !TD1_sum_carry_15;
TD1_sum_carry_16 = CARRY(TD1_sum_carry_16_cout_0);
 
--TD1L714 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_16~COUT1_1 at LC_X15_Y7_N0
--operation mode is arithmetic
 
TD1L714_cout_1 = PD1_a_o_16 & !TD1_sum_carry_15 # !VD1_b_o_iv_16 # !PD1_a_o_16 & !VD1_b_o_iv_16 & !TD1_sum_carry_15;
TD1L714 = CARRY(TD1L714_cout_1);
 
 
--VD1_over_carry_19 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_19 at LC_X10_Y11_N3
--operation mode is arithmetic
 
VD1_over_carry_19_cout_0 = PD1_a_o_19 & VD1_b_o_iv_19 & !VD1_over_carry_18 # !PD1_a_o_19 & VD1_b_o_iv_19 # !VD1_over_carry_18;
VD1_over_carry_19 = CARRY(VD1_over_carry_19_cout_0);
 
--VD1L9051 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_19~COUT1_1 at LC_X10_Y11_N3
--operation mode is arithmetic
 
VD1L9051_cout_1 = PD1_a_o_19 & VD1_b_o_iv_19 & !VD1L7051 # !PD1_a_o_19 & VD1_b_o_iv_19 # !VD1L7051;
VD1L9051 = CARRY(VD1L9051_cout_1);
 
 
--TD1_lt_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_14 at LC_X16_Y9_N8
--operation mode is arithmetic
 
TD1_lt_14_cout_0 = PD1_a_o_14 & VD1_b_o_iv_14 & !TD1_lt_13 # !PD1_a_o_14 & VD1_b_o_iv_14 # !TD1_lt_13;
TD1_lt_14 = CARRY(TD1_lt_14_cout_0);
 
--TD1L961 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_14~COUT1_1 at LC_X16_Y9_N8
--operation mode is arithmetic
 
TD1L961_cout_1 = PD1_a_o_14 & VD1_b_o_iv_14 & !TD1L761 # !PD1_a_o_14 & VD1_b_o_iv_14 # !TD1L761;
TD1L961 = CARRY(TD1L961_cout_1);
 
 
--TD1_sum_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_15 at LC_X15_Y8_N9
--operation mode is arithmetic
 
TD1_sum_carry_15 = CARRY(PD1_a_o_15 & VD1_b_o_iv_15 & !TD1L414 # !PD1_a_o_15 & VD1_b_o_iv_15 # !TD1L414);
 
 
--VD1_over_carry_18 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_18 at LC_X10_Y11_N2
--operation mode is arithmetic
 
VD1_over_carry_18_cout_0 = VD1_b_o_iv_18 & PD1_a_o_18 & !VD1_over_carry_17 # !VD1_b_o_iv_18 & PD1_a_o_18 # !VD1_over_carry_17;
VD1_over_carry_18 = CARRY(VD1_over_carry_18_cout_0);
 
--VD1L7051 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_18~COUT1_1 at LC_X10_Y11_N2
--operation mode is arithmetic
 
VD1L7051_cout_1 = VD1_b_o_iv_18 & PD1_a_o_18 & !VD1L5051 # !VD1_b_o_iv_18 & PD1_a_o_18 # !VD1L5051;
VD1L7051 = CARRY(VD1L7051_cout_1);
 
 
--TD1_lt_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_13 at LC_X16_Y9_N7
--operation mode is arithmetic
 
TD1_lt_13_cout_0 = PD1_a_o_13 & !TD1_lt_12 # !VD1_b_o_iv_13 # !PD1_a_o_13 & !VD1_b_o_iv_13 & !TD1_lt_12;
TD1_lt_13 = CARRY(TD1_lt_13_cout_0);
 
--TD1L761 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_13~COUT1_1 at LC_X16_Y9_N7
--operation mode is arithmetic
 
TD1L761_cout_1 = PD1_a_o_13 & !TD1L561 # !VD1_b_o_iv_13 # !PD1_a_o_13 & !VD1_b_o_iv_13 & !TD1L561;
TD1L761 = CARRY(TD1L761_cout_1);
 
 
--TD1_sum_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_14 at LC_X15_Y8_N8
--operation mode is arithmetic
 
TD1_sum_carry_14_cout_0 = VD1_b_o_iv_14 & PD1_a_o_14 & !TD1_sum_carry_13 # !VD1_b_o_iv_14 & PD1_a_o_14 # !TD1_sum_carry_13;
TD1_sum_carry_14 = CARRY(TD1_sum_carry_14_cout_0);
 
--TD1L414 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_14~COUT1_1 at LC_X15_Y8_N8
--operation mode is arithmetic
 
TD1L414_cout_1 = VD1_b_o_iv_14 & PD1_a_o_14 & !TD1L214 # !VD1_b_o_iv_14 & PD1_a_o_14 # !TD1L214;
TD1L414 = CARRY(TD1L414_cout_1);
 
 
--VD1_over_carry_17 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_17 at LC_X10_Y11_N1
--operation mode is arithmetic
 
VD1_over_carry_17_cout_0 = PD1_a_o_17 & VD1_b_o_iv_17 & !VD1_over_carry_16 # !PD1_a_o_17 & VD1_b_o_iv_17 # !VD1_over_carry_16;
VD1_over_carry_17 = CARRY(VD1_over_carry_17_cout_0);
 
--VD1L5051 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_17~COUT1_1 at LC_X10_Y11_N1
--operation mode is arithmetic
 
VD1L5051_cout_1 = PD1_a_o_17 & VD1_b_o_iv_17 & !VD1L3051 # !PD1_a_o_17 & VD1_b_o_iv_17 # !VD1L3051;
VD1L5051 = CARRY(VD1L5051_cout_1);
 
 
--TD1_lt_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_12 at LC_X16_Y9_N6
--operation mode is arithmetic
 
TD1_lt_12_cout_0 = PD1_a_o_12 & VD1_b_o_iv_12 & !TD1_lt_11 # !PD1_a_o_12 & VD1_b_o_iv_12 # !TD1_lt_11;
TD1_lt_12 = CARRY(TD1_lt_12_cout_0);
 
--TD1L561 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_12~COUT1_1 at LC_X16_Y9_N6
--operation mode is arithmetic
 
TD1L561_cout_1 = PD1_a_o_12 & VD1_b_o_iv_12 & !TD1L361 # !PD1_a_o_12 & VD1_b_o_iv_12 # !TD1L361;
TD1L561 = CARRY(TD1L561_cout_1);
 
 
--TD1_sum_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_13 at LC_X15_Y8_N7
--operation mode is arithmetic
 
TD1_sum_carry_13_cout_0 = VD1_b_o_iv_13 & !TD1_sum_carry_12 # !PD1_a_o_13 # !VD1_b_o_iv_13 & !PD1_a_o_13 & !TD1_sum_carry_12;
TD1_sum_carry_13 = CARRY(TD1_sum_carry_13_cout_0);
 
--TD1L214 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_13~COUT1_1 at LC_X15_Y8_N7
--operation mode is arithmetic
 
TD1L214_cout_1 = VD1_b_o_iv_13 & !TD1L014 # !PD1_a_o_13 # !VD1_b_o_iv_13 & !PD1_a_o_13 & !TD1L014;
TD1L214 = CARRY(TD1L214_cout_1);
 
 
--VD1_over_carry_16 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_16 at LC_X10_Y11_N0
--operation mode is arithmetic
 
VD1_over_carry_16_cout_0 = PD1_a_o_16 & !VD1_over_carry_15 # !VD1_b_o_iv_16 # !PD1_a_o_16 & !VD1_b_o_iv_16 & !VD1_over_carry_15;
VD1_over_carry_16 = CARRY(VD1_over_carry_16_cout_0);
 
--VD1L3051 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_16~COUT1_1 at LC_X10_Y11_N0
--operation mode is arithmetic
 
VD1L3051_cout_1 = PD1_a_o_16 & !VD1_over_carry_15 # !VD1_b_o_iv_16 # !PD1_a_o_16 & !VD1_b_o_iv_16 & !VD1_over_carry_15;
VD1L3051 = CARRY(VD1L3051_cout_1);
 
 
--TD1_lt_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_11 at LC_X16_Y9_N5
--operation mode is arithmetic
 
TD1_lt_11_cout_0 = VD1_b_o_iv_11 & PD1_a_o_11 & !TD1_lt_10 # !VD1_b_o_iv_11 & PD1_a_o_11 # !TD1_lt_10;
TD1_lt_11 = CARRY(TD1_lt_11_cout_0);
 
--TD1L361 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_11~COUT1_1 at LC_X16_Y9_N5
--operation mode is arithmetic
 
TD1L361_cout_1 = VD1_b_o_iv_11 & PD1_a_o_11 & !TD1_lt_10 # !VD1_b_o_iv_11 & PD1_a_o_11 # !TD1_lt_10;
TD1L361 = CARRY(TD1L361_cout_1);
 
 
--TD1_sum_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_12 at LC_X15_Y8_N6
--operation mode is arithmetic
 
TD1_sum_carry_12_cout_0 = VD1_b_o_iv_12 & PD1_a_o_12 & !TD1_sum_carry_11 # !VD1_b_o_iv_12 & PD1_a_o_12 # !TD1_sum_carry_11;
TD1_sum_carry_12 = CARRY(TD1_sum_carry_12_cout_0);
 
--TD1L014 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_12~COUT1_1 at LC_X15_Y8_N6
--operation mode is arithmetic
 
TD1L014_cout_1 = VD1_b_o_iv_12 & PD1_a_o_12 & !TD1L804 # !VD1_b_o_iv_12 & PD1_a_o_12 # !TD1L804;
TD1L014 = CARRY(TD1L014_cout_1);
 
 
--VD1_over_carry_15 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_15 at LC_X10_Y12_N9
--operation mode is arithmetic
 
VD1_over_carry_15 = CARRY(PD1_a_o_15 & VD1_b_o_iv_15 & !VD1L0051 # !PD1_a_o_15 & VD1_b_o_iv_15 # !VD1L0051);
 
 
--TD1_lt_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_10 at LC_X16_Y9_N4
--operation mode is arithmetic
 
TD1_lt_10 = CARRY(PD1_a_o_10 & VD1_b_o_iv_10 & !TD1L061 # !PD1_a_o_10 & VD1_b_o_iv_10 # !TD1L061);
 
 
--TD1_sum_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_11 at LC_X15_Y8_N5
--operation mode is arithmetic
 
TD1_sum_carry_11_cout_0 = PD1_a_o_11 & VD1_b_o_iv_11 & !TD1_sum_carry_10 # !PD1_a_o_11 & VD1_b_o_iv_11 # !TD1_sum_carry_10;
TD1_sum_carry_11 = CARRY(TD1_sum_carry_11_cout_0);
 
--TD1L804 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_11~COUT1_1 at LC_X15_Y8_N5
--operation mode is arithmetic
 
TD1L804_cout_1 = PD1_a_o_11 & VD1_b_o_iv_11 & !TD1_sum_carry_10 # !PD1_a_o_11 & VD1_b_o_iv_11 # !TD1_sum_carry_10;
TD1L804 = CARRY(TD1L804_cout_1);
 
 
--VD1_over_carry_14 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_14 at LC_X10_Y12_N8
--operation mode is arithmetic
 
VD1_over_carry_14_cout_0 = VD1_b_o_iv_14 & PD1_a_o_14 & !VD1_over_carry_13 # !VD1_b_o_iv_14 & PD1_a_o_14 # !VD1_over_carry_13;
VD1_over_carry_14 = CARRY(VD1_over_carry_14_cout_0);
 
--VD1L0051 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_14~COUT1_1 at LC_X10_Y12_N8
--operation mode is arithmetic
 
VD1L0051_cout_1 = VD1_b_o_iv_14 & PD1_a_o_14 & !VD1L8941 # !VD1_b_o_iv_14 & PD1_a_o_14 # !VD1L8941;
VD1L0051 = CARRY(VD1L0051_cout_1);
 
 
--TD1_lt_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_9 at LC_X16_Y9_N3
--operation mode is arithmetic
 
TD1_lt_9_cout_0 = PD1_a_o_9 & !TD1_lt_8 # !VD1_b_o_iv_9 # !PD1_a_o_9 & !VD1_b_o_iv_9 & !TD1_lt_8;
TD1_lt_9 = CARRY(TD1_lt_9_cout_0);
 
--TD1L061 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_9~COUT1_1 at LC_X16_Y9_N3
--operation mode is arithmetic
 
TD1L061_cout_1 = PD1_a_o_9 & !TD1L851 # !VD1_b_o_iv_9 # !PD1_a_o_9 & !VD1_b_o_iv_9 & !TD1L851;
TD1L061 = CARRY(TD1L061_cout_1);
 
 
--TD1_sum_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_10 at LC_X15_Y8_N4
--operation mode is arithmetic
 
TD1_sum_carry_10 = CARRY(VD1_b_o_iv_10 & PD1_a_o_10 & !TD1L504 # !VD1_b_o_iv_10 & PD1_a_o_10 # !TD1L504);
 
 
--VD1_over_carry_13 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_13 at LC_X10_Y12_N7
--operation mode is arithmetic
 
VD1_over_carry_13_cout_0 = PD1_a_o_13 & VD1_b_o_iv_13 & !VD1_over_carry_12 # !PD1_a_o_13 & VD1_b_o_iv_13 # !VD1_over_carry_12;
VD1_over_carry_13 = CARRY(VD1_over_carry_13_cout_0);
 
--VD1L8941 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_13~COUT1_1 at LC_X10_Y12_N7
--operation mode is arithmetic
 
VD1L8941_cout_1 = PD1_a_o_13 & VD1_b_o_iv_13 & !VD1L6941 # !PD1_a_o_13 & VD1_b_o_iv_13 # !VD1L6941;
VD1L8941 = CARRY(VD1L8941_cout_1);
 
 
--TD1_lt_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_8 at LC_X16_Y9_N2
--operation mode is arithmetic
 
TD1_lt_8_cout_0 = PD1_a_o_8 & VD1_b_o_iv_8 & !TD1_lt_7 # !PD1_a_o_8 & VD1_b_o_iv_8 # !TD1_lt_7;
TD1_lt_8 = CARRY(TD1_lt_8_cout_0);
 
--TD1L851 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_8~COUT1_1 at LC_X16_Y9_N2
--operation mode is arithmetic
 
TD1L851_cout_1 = PD1_a_o_8 & VD1_b_o_iv_8 & !TD1L651 # !PD1_a_o_8 & VD1_b_o_iv_8 # !TD1L651;
TD1L851 = CARRY(TD1L851_cout_1);
 
 
--TD1_sum_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_9 at LC_X15_Y8_N3
--operation mode is arithmetic
 
TD1_sum_carry_9_cout_0 = VD1_b_o_iv_9 & !TD1_sum_carry_8 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !TD1_sum_carry_8;
TD1_sum_carry_9 = CARRY(TD1_sum_carry_9_cout_0);
 
--TD1L504 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_9~COUT1_1 at LC_X15_Y8_N3
--operation mode is arithmetic
 
TD1L504_cout_1 = VD1_b_o_iv_9 & !TD1L304 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !TD1L304;
TD1L504 = CARRY(TD1L504_cout_1);
 
 
--VD1_over_carry_12 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_12 at LC_X10_Y12_N6
--operation mode is arithmetic
 
VD1_over_carry_12_cout_0 = VD1_b_o_iv_12 & PD1_a_o_12 & !VD1_over_carry_11 # !VD1_b_o_iv_12 & PD1_a_o_12 # !VD1_over_carry_11;
VD1_over_carry_12 = CARRY(VD1_over_carry_12_cout_0);
 
--VD1L6941 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_12~COUT1_1 at LC_X10_Y12_N6
--operation mode is arithmetic
 
VD1L6941_cout_1 = VD1_b_o_iv_12 & PD1_a_o_12 & !VD1L4941 # !VD1_b_o_iv_12 & PD1_a_o_12 # !VD1L4941;
VD1L6941 = CARRY(VD1L6941_cout_1);
 
 
--TD1_lt_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_7 at LC_X16_Y9_N1
--operation mode is arithmetic
 
TD1_lt_7_cout_0 = PD1_a_o_7 & !TD1_lt_6 # !VD1_b_o_iv_7 # !PD1_a_o_7 & !VD1_b_o_iv_7 & !TD1_lt_6;
TD1_lt_7 = CARRY(TD1_lt_7_cout_0);
 
--TD1L651 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_7~COUT1_1 at LC_X16_Y9_N1
--operation mode is arithmetic
 
TD1L651_cout_1 = PD1_a_o_7 & !TD1L451 # !VD1_b_o_iv_7 # !PD1_a_o_7 & !VD1_b_o_iv_7 & !TD1L451;
TD1L651 = CARRY(TD1L651_cout_1);
 
 
--TD1_sum_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_8 at LC_X15_Y8_N2
--operation mode is arithmetic
 
TD1_sum_carry_8_cout_0 = VD1_b_o_iv_8 & PD1_a_o_8 & !TD1_sum_carry_7 # !VD1_b_o_iv_8 & PD1_a_o_8 # !TD1_sum_carry_7;
TD1_sum_carry_8 = CARRY(TD1_sum_carry_8_cout_0);
 
--TD1L304 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_8~COUT1_1 at LC_X15_Y8_N2
--operation mode is arithmetic
 
TD1L304_cout_1 = VD1_b_o_iv_8 & PD1_a_o_8 & !TD1L104 # !VD1_b_o_iv_8 & PD1_a_o_8 # !TD1L104;
TD1L304 = CARRY(TD1L304_cout_1);
 
 
--VD1_over_carry_11 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_11 at LC_X10_Y12_N5
--operation mode is arithmetic
 
VD1_over_carry_11_cout_0 = PD1_a_o_11 & VD1_b_o_iv_11 & !VD1_over_carry_10 # !PD1_a_o_11 & VD1_b_o_iv_11 # !VD1_over_carry_10;
VD1_over_carry_11 = CARRY(VD1_over_carry_11_cout_0);
 
--VD1L4941 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_11~COUT1_1 at LC_X10_Y12_N5
--operation mode is arithmetic
 
VD1L4941_cout_1 = PD1_a_o_11 & VD1_b_o_iv_11 & !VD1_over_carry_10 # !PD1_a_o_11 & VD1_b_o_iv_11 # !VD1_over_carry_10;
VD1L4941 = CARRY(VD1L4941_cout_1);
 
 
--TD1_lt_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_6 at LC_X16_Y9_N0
--operation mode is arithmetic
 
TD1_lt_6_cout_0 = PD1_a_o_6 & VD1_b_o_iv_6 & !TD1_lt_5 # !PD1_a_o_6 & VD1_b_o_iv_6 # !TD1_lt_5;
TD1_lt_6 = CARRY(TD1_lt_6_cout_0);
 
--TD1L451 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_6~COUT1_1 at LC_X16_Y9_N0
--operation mode is arithmetic
 
TD1L451_cout_1 = PD1_a_o_6 & VD1_b_o_iv_6 & !TD1_lt_5 # !PD1_a_o_6 & VD1_b_o_iv_6 # !TD1_lt_5;
TD1L451 = CARRY(TD1L451_cout_1);
 
 
--TD1_sum_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_7 at LC_X15_Y8_N1
--operation mode is arithmetic
 
TD1_sum_carry_7_cout_0 = VD1_b_o_iv_7 & !TD1_sum_carry_6 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !TD1_sum_carry_6;
TD1_sum_carry_7 = CARRY(TD1_sum_carry_7_cout_0);
 
--TD1L104 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_7~COUT1_1 at LC_X15_Y8_N1
--operation mode is arithmetic
 
TD1L104_cout_1 = VD1_b_o_iv_7 & !TD1L993 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !TD1L993;
TD1L104 = CARRY(TD1L104_cout_1);
 
 
--VD1_over_carry_10 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_10 at LC_X10_Y12_N4
--operation mode is arithmetic
 
VD1_over_carry_10 = CARRY(PD1_a_o_10 & !VD1L1941 # !VD1_b_o_iv_10 # !PD1_a_o_10 & !VD1_b_o_iv_10 & !VD1L1941);
 
 
--TD1_lt_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_5 at LC_X16_Y10_N9
--operation mode is arithmetic
 
TD1_lt_5 = CARRY(PD1_a_o_5 & !TD1L151 # !VD1_b_o_iv_5 # !PD1_a_o_5 & !VD1_b_o_iv_5 & !TD1L151);
 
 
--TD1_sum_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_6 at LC_X15_Y8_N0
--operation mode is arithmetic
 
TD1_sum_carry_6_cout_0 = PD1_a_o_6 & !TD1_sum_carry_5 # !VD1_b_o_iv_6 # !PD1_a_o_6 & !VD1_b_o_iv_6 & !TD1_sum_carry_5;
TD1_sum_carry_6 = CARRY(TD1_sum_carry_6_cout_0);
 
--TD1L993 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_6~COUT1_1 at LC_X15_Y8_N0
--operation mode is arithmetic
 
TD1L993_cout_1 = PD1_a_o_6 & !TD1_sum_carry_5 # !VD1_b_o_iv_6 # !PD1_a_o_6 & !VD1_b_o_iv_6 & !TD1_sum_carry_5;
TD1L993 = CARRY(TD1L993_cout_1);
 
 
--VD1_over_carry_9 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_9 at LC_X10_Y12_N3
--operation mode is arithmetic
 
VD1_over_carry_9_cout_0 = VD1_b_o_iv_9 & !VD1_over_carry_8 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !VD1_over_carry_8;
VD1_over_carry_9 = CARRY(VD1_over_carry_9_cout_0);
 
--VD1L1941 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_9~COUT1_1 at LC_X10_Y12_N3
--operation mode is arithmetic
 
VD1L1941_cout_1 = VD1_b_o_iv_9 & !VD1L9841 # !PD1_a_o_9 # !VD1_b_o_iv_9 & !PD1_a_o_9 & !VD1L9841;
VD1L1941 = CARRY(VD1L1941_cout_1);
 
 
--TD1_lt_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_4 at LC_X16_Y10_N8
--operation mode is arithmetic
 
TD1_lt_4_cout_0 = VD1_b_o_iv_4 & !TD1_lt_3 # !PD1_a_o_4 # !VD1_b_o_iv_4 & !PD1_a_o_4 & !TD1_lt_3;
TD1_lt_4 = CARRY(TD1_lt_4_cout_0);
 
--TD1L151 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_4~COUT1_1 at LC_X16_Y10_N8
--operation mode is arithmetic
 
TD1L151_cout_1 = VD1_b_o_iv_4 & !TD1L941 # !PD1_a_o_4 # !VD1_b_o_iv_4 & !PD1_a_o_4 & !TD1L941;
TD1L151 = CARRY(TD1L151_cout_1);
 
 
--TD1_sum_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_5 at LC_X15_Y9_N9
--operation mode is arithmetic
 
TD1_sum_carry_5 = CARRY(PD1_a_o_5 & VD1_b_o_iv_5 & !TD1L693 # !PD1_a_o_5 & VD1_b_o_iv_5 # !TD1L693);
 
 
--VD1_over_carry_8 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_8 at LC_X10_Y12_N2
--operation mode is arithmetic
 
VD1_over_carry_8_cout_0 = VD1_b_o_iv_8 & PD1_a_o_8 & !VD1_over_carry_7 # !VD1_b_o_iv_8 & PD1_a_o_8 # !VD1_over_carry_7;
VD1_over_carry_8 = CARRY(VD1_over_carry_8_cout_0);
 
--VD1L9841 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_8~COUT1_1 at LC_X10_Y12_N2
--operation mode is arithmetic
 
VD1L9841_cout_1 = VD1_b_o_iv_8 & PD1_a_o_8 & !VD1L7841 # !VD1_b_o_iv_8 & PD1_a_o_8 # !VD1L7841;
VD1L9841 = CARRY(VD1L9841_cout_1);
 
 
--TD1_lt_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_3 at LC_X16_Y10_N7
--operation mode is arithmetic
 
TD1_lt_3_cout_0 = PD1_a_o_3 & !TD1_lt_2 # !VD1_b_o_iv_3 # !PD1_a_o_3 & !VD1_b_o_iv_3 & !TD1_lt_2;
TD1_lt_3 = CARRY(TD1_lt_3_cout_0);
 
--TD1L941 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_3~COUT1_1 at LC_X16_Y10_N7
--operation mode is arithmetic
 
TD1L941_cout_1 = PD1_a_o_3 & !TD1L741 # !VD1_b_o_iv_3 # !PD1_a_o_3 & !VD1_b_o_iv_3 & !TD1L741;
TD1L941 = CARRY(TD1L941_cout_1);
 
 
--TD1_sum_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_4 at LC_X15_Y9_N8
--operation mode is arithmetic
 
TD1_sum_carry_4_cout_0 = VD1_b_o_iv_4 & PD1_a_o_4 & !TD1_sum_carry_3 # !VD1_b_o_iv_4 & PD1_a_o_4 # !TD1_sum_carry_3;
TD1_sum_carry_4 = CARRY(TD1_sum_carry_4_cout_0);
 
--TD1L693 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_4~COUT1_1 at LC_X15_Y9_N8
--operation mode is arithmetic
 
TD1L693_cout_1 = VD1_b_o_iv_4 & PD1_a_o_4 & !TD1L493 # !VD1_b_o_iv_4 & PD1_a_o_4 # !TD1L493;
TD1L693 = CARRY(TD1L693_cout_1);
 
 
--VD1_over_carry_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_7 at LC_X10_Y12_N1
--operation mode is arithmetic
 
VD1_over_carry_7_cout_0 = VD1_b_o_iv_7 & !VD1_over_carry_6 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !VD1_over_carry_6;
VD1_over_carry_7 = CARRY(VD1_over_carry_7_cout_0);
 
--VD1L7841 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_7~COUT1_1 at LC_X10_Y12_N1
--operation mode is arithmetic
 
VD1L7841_cout_1 = VD1_b_o_iv_7 & !VD1L5841 # !PD1_a_o_7 # !VD1_b_o_iv_7 & !PD1_a_o_7 & !VD1L5841;
VD1L7841 = CARRY(VD1L7841_cout_1);
 
 
--TD1_lt_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_2 at LC_X16_Y10_N6
--operation mode is arithmetic
 
TD1_lt_2_cout_0 = VD1_b_o_iv_2 & !TD1_lt_1 # !PD1_a_o_2 # !VD1_b_o_iv_2 & !PD1_a_o_2 & !TD1_lt_1;
TD1_lt_2 = CARRY(TD1_lt_2_cout_0);
 
--TD1L741 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_2~COUT1_1 at LC_X16_Y10_N6
--operation mode is arithmetic
 
TD1L741_cout_1 = VD1_b_o_iv_2 & !TD1L541 # !PD1_a_o_2 # !VD1_b_o_iv_2 & !PD1_a_o_2 & !TD1L541;
TD1L741 = CARRY(TD1L741_cout_1);
 
 
--TD1_sum_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_3 at LC_X15_Y9_N7
--operation mode is arithmetic
 
TD1_sum_carry_3_cout_0 = VD1_b_o_iv_3 & !TD1_sum_carry_2 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !TD1_sum_carry_2;
TD1_sum_carry_3 = CARRY(TD1_sum_carry_3_cout_0);
 
--TD1L493 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_3~COUT1_1 at LC_X15_Y9_N7
--operation mode is arithmetic
 
TD1L493_cout_1 = VD1_b_o_iv_3 & !TD1L293 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !TD1L293;
TD1L493 = CARRY(TD1L493_cout_1);
 
 
--VD1_over_carry_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_6 at LC_X10_Y12_N0
--operation mode is arithmetic
 
VD1_over_carry_6_cout_0 = PD1_a_o_6 & !VD1_over_carry_5 # !VD1_b_o_iv_6 # !PD1_a_o_6 & !VD1_b_o_iv_6 & !VD1_over_carry_5;
VD1_over_carry_6 = CARRY(VD1_over_carry_6_cout_0);
 
--VD1L5841 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_6~COUT1_1 at LC_X10_Y12_N0
--operation mode is arithmetic
 
VD1L5841_cout_1 = PD1_a_o_6 & !VD1_over_carry_5 # !VD1_b_o_iv_6 # !PD1_a_o_6 & !VD1_b_o_iv_6 & !VD1_over_carry_5;
VD1L5841 = CARRY(VD1L5841_cout_1);
 
 
--TD1_lt_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_1 at LC_X16_Y10_N5
--operation mode is arithmetic
 
TD1_lt_1_cout_0 = VD1_b_o_iv_1 & PD1_a_o_1 & !TD1_lt_0 # !VD1_b_o_iv_1 & PD1_a_o_1 # !TD1_lt_0;
TD1_lt_1 = CARRY(TD1_lt_1_cout_0);
 
--TD1L541 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_1~COUT1_1 at LC_X16_Y10_N5
--operation mode is arithmetic
 
TD1L541_cout_1 = VD1_b_o_iv_1 & PD1_a_o_1 & !TD1_lt_0 # !VD1_b_o_iv_1 & PD1_a_o_1 # !TD1_lt_0;
TD1L541 = CARRY(TD1L541_cout_1);
 
 
--TD1_sum_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_2 at LC_X15_Y9_N6
--operation mode is arithmetic
 
TD1_sum_carry_2_cout_0 = PD1_a_o_2 & !TD1_sum_carry_1 # !VD1_b_o_iv_2 # !PD1_a_o_2 & !VD1_b_o_iv_2 & !TD1_sum_carry_1;
TD1_sum_carry_2 = CARRY(TD1_sum_carry_2_cout_0);
 
--TD1L293 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_2~COUT1_1 at LC_X15_Y9_N6
--operation mode is arithmetic
 
TD1L293_cout_1 = PD1_a_o_2 & !TD1L093 # !VD1_b_o_iv_2 # !PD1_a_o_2 & !VD1_b_o_iv_2 & !TD1L093;
TD1L293 = CARRY(TD1L293_cout_1);
 
 
--VD1_over_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_5 at LC_X10_Y13_N9
--operation mode is arithmetic
 
VD1_over_carry_5 = CARRY(PD1_a_o_5 & VD1_b_o_iv_5 & !VD1L2841 # !PD1_a_o_5 & VD1_b_o_iv_5 # !VD1L2841);
 
 
--TD1_lt_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|lt_0 at LC_X16_Y10_N4
--operation mode is arithmetic
 
TD1_lt_0 = CARRY(!PD1_a_o_0 & VD1_b_o_iv_0);
 
 
--TD1_sum_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_1 at LC_X15_Y9_N5
--operation mode is arithmetic
 
TD1_sum_carry_1_cout_0 = VD1_b_o_iv_1 & !TD1_sum_carry_0 # !PD1_a_o_1 # !VD1_b_o_iv_1 & !PD1_a_o_1 & !TD1_sum_carry_0;
TD1_sum_carry_1 = CARRY(TD1_sum_carry_1_cout_0);
 
--TD1L093 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_1~COUT1_1 at LC_X15_Y9_N5
--operation mode is arithmetic
 
TD1L093_cout_1 = VD1_b_o_iv_1 & !TD1_sum_carry_0 # !PD1_a_o_1 # !VD1_b_o_iv_1 & !PD1_a_o_1 & !TD1_sum_carry_0;
TD1L093 = CARRY(TD1L093_cout_1);
 
 
--VD1_over_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_4 at LC_X10_Y13_N8
--operation mode is arithmetic
 
VD1_over_carry_4_cout_0 = PD1_a_o_4 & !VD1_over_carry_3 # !VD1_b_o_iv_4 # !PD1_a_o_4 & !VD1_b_o_iv_4 & !VD1_over_carry_3;
VD1_over_carry_4 = CARRY(VD1_over_carry_4_cout_0);
 
--VD1L2841 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_4~COUT1_1 at LC_X10_Y13_N8
--operation mode is arithmetic
 
VD1L2841_cout_1 = PD1_a_o_4 & !VD1L0841 # !VD1_b_o_iv_4 # !PD1_a_o_4 & !VD1_b_o_iv_4 & !VD1L0841;
VD1L2841 = CARRY(VD1L2841_cout_1);
 
 
--TD1_sum_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum_carry_0 at LC_X15_Y9_N4
--operation mode is arithmetic
 
TD1_sum_carry_0 = CARRY(PD1_a_o_0 # !VD1_b_o_iv_0);
 
 
--VD1_over_carry_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_3 at LC_X10_Y13_N7
--operation mode is arithmetic
 
VD1_over_carry_3_cout_0 = VD1_b_o_iv_3 & !VD1_over_carry_2 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !VD1_over_carry_2;
VD1_over_carry_3 = CARRY(VD1_over_carry_3_cout_0);
 
--VD1L0841 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_3~COUT1_1 at LC_X10_Y13_N7
--operation mode is arithmetic
 
VD1L0841_cout_1 = VD1_b_o_iv_3 & !VD1L8741 # !PD1_a_o_3 # !VD1_b_o_iv_3 & !PD1_a_o_3 & !VD1L8741;
VD1L0841 = CARRY(VD1L0841_cout_1);
 
 
--VD1_over_carry_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_2 at LC_X10_Y13_N6
--operation mode is arithmetic
 
VD1_over_carry_2_cout_0 = VD1_b_o_iv_2 & PD1_a_o_2 & !VD1_over_carry_1 # !VD1_b_o_iv_2 & PD1_a_o_2 # !VD1_over_carry_1;
VD1_over_carry_2 = CARRY(VD1_over_carry_2_cout_0);
 
--VD1L8741 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_2~COUT1_1 at LC_X10_Y13_N6
--operation mode is arithmetic
 
VD1L8741_cout_1 = VD1_b_o_iv_2 & PD1_a_o_2 & !VD1L6741 # !VD1_b_o_iv_2 & PD1_a_o_2 # !VD1L6741;
VD1L8741 = CARRY(VD1L8741_cout_1);
 
 
--VD1_over_carry_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_1 at LC_X10_Y13_N5
--operation mode is arithmetic
 
VD1_over_carry_1_cout_0 = PD1_a_o_1 & VD1_b_o_iv_1 & !VD1_over_carry_0 # !PD1_a_o_1 & VD1_b_o_iv_1 # !VD1_over_carry_0;
VD1_over_carry_1 = CARRY(VD1_over_carry_1_cout_0);
 
--VD1L6741 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_1~COUT1_1 at LC_X10_Y13_N5
--operation mode is arithmetic
 
VD1L6741_cout_1 = PD1_a_o_1 & VD1_b_o_iv_1 & !VD1_over_carry_0 # !PD1_a_o_1 & VD1_b_o_iv_1 # !VD1_over_carry_0;
VD1L6741 = CARRY(VD1L6741_cout_1);
 
 
--VD1_over_carry_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|over_carry_0 at LC_X10_Y13_N4
--operation mode is arithmetic
 
VD1_over_carry_0 = CARRY(!VD1_b_o_iv_0 & PD1_a_o_0);
 
 
--~GND is ~GND at LC_X16_Y19_N2
--operation mode is normal
 
~GND = GND;
 
 
--clk is clk at PIN_28
--operation mode is input
 
clk = INPUT();
 
 
--rst is rst at PIN_159
--operation mode is input
 
rst = INPUT();
 
 
--ser_txd is ser_txd at PIN_176
--operation mode is output
 
ser_txd = OUTPUT(N1_txd);
 
 
--seg7led1[6] is seg7led1[6] at PIN_167
--operation mode is output
 
seg7led1[6] = OUTPUT(H1_N_62_i);
 
 
--seg7led1[5] is seg7led1[5] at PIN_168
--operation mode is output
 
seg7led1[5] = OUTPUT(H1_N_60_i);
 
 
--seg7led1[4] is seg7led1[4] at PIN_164
--operation mode is output
 
seg7led1[4] = OUTPUT(H1_N_58_i);
 
 
--seg7led1[3] is seg7led1[3] at PIN_160
--operation mode is output
 
seg7led1[3] = OUTPUT(H1_m18_0);
 
 
--seg7led1[2] is seg7led1[2] at PIN_161
--operation mode is output
 
seg7led1[2] = OUTPUT(H1_m15_0);
 
 
--seg7led1[1] is seg7led1[1] at PIN_166
--operation mode is output
 
seg7led1[1] = OUTPUT(H1_m11_0);
 
 
--seg7led1[0] is seg7led1[0] at PIN_169
--operation mode is output
 
seg7led1[0] = OUTPUT(H1_N_44_i);
 
 
--seg7led2[6] is seg7led2[6] at PIN_173
--operation mode is output
 
seg7led2[6] = OUTPUT(H1_N_31_i);
 
 
--seg7led2[5] is seg7led2[5] at PIN_174
--operation mode is output
 
seg7led2[5] = OUTPUT(H1_N_29_i);
 
 
--seg7led2[4] is seg7led2[4] at PIN_162
--operation mode is output
 
seg7led2[4] = OUTPUT(H1_N_27_i);
 
 
--seg7led2[3] is seg7led2[3] at PIN_165
--operation mode is output
 
seg7led2[3] = OUTPUT(H1_m18);
 
 
--seg7led2[2] is seg7led2[2] at PIN_163
--operation mode is output
 
seg7led2[2] = OUTPUT(H1_m15);
 
 
--seg7led2[1] is seg7led2[1] at PIN_170
--operation mode is output
 
seg7led2[1] = OUTPUT(H1_m11);
 
 
--seg7led2[0] is seg7led2[0] at PIN_175
--operation mode is output
 
seg7led2[0] = OUTPUT(H1_N_13_i);
 
 
--lcd_data[7] is lcd_data[7] at PIN_144
--operation mode is output
 
lcd_data[7] = OUTPUT(F1_lcd_data_7);
 
 
--lcd_data[6] is lcd_data[6] at PIN_143
--operation mode is output
 
lcd_data[6] = OUTPUT(F1_lcd_data_6);
 
 
--lcd_data[5] is lcd_data[5] at PIN_141
--operation mode is output
 
lcd_data[5] = OUTPUT(F1_lcd_data_5);
 
 
--lcd_data[4] is lcd_data[4] at PIN_140
--operation mode is output
 
lcd_data[4] = OUTPUT(F1_lcd_data_4);
 
 
--lcd_data[3] is lcd_data[3] at PIN_139
--operation mode is output
 
lcd_data[3] = OUTPUT(F1_lcd_data_3);
 
 
--lcd_data[2] is lcd_data[2] at PIN_138
--operation mode is output
 
lcd_data[2] = OUTPUT(F1_lcd_data_2);
 
 
--lcd_data[1] is lcd_data[1] at PIN_137
--operation mode is output
 
lcd_data[1] = OUTPUT(F1_lcd_data_1);
 
 
--lcd_data[0] is lcd_data[0] at PIN_136
--operation mode is output
 
lcd_data[0] = OUTPUT(F1_lcd_data_0);
 
 
--lcd_rs is lcd_rs at PIN_133
--operation mode is output
 
lcd_rs = OUTPUT(F1_cmd_2);
 
 
--lcd_rw is lcd_rw at PIN_134
--operation mode is output
 
lcd_rw = OUTPUT(F1_cmd_3);
 
 
--lcd_en is lcd_en at PIN_135
--operation mode is output
 
lcd_en = OUTPUT(F1_cmd_4);
 
 
--led1 is led1 at PIN_1
--operation mode is output
 
led1 = OUTPUT(F1_cmd_5);
 
 
--led2 is led2 at PIN_2
--operation mode is output
 
led2 = OUTPUT(F1_cmd_6);
 
 
--key1 is key1 at PIN_156
--operation mode is input
 
key1 = INPUT();
 
 
--key2 is key2 at PIN_158
--operation mode is input
 
key2 = INPUT();
 
 
--ser_rxd is ser_rxd at PIN_177
--operation mode is input
 
ser_rxd = INPUT();
 
 
 
 
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[/] [mips789/] [branches/] [avendor/] [quartus2/] [mips_top.fit.eqn] - Blame information for rev 51

Line No.	Rev	Author	Line
1	15	mcupro	`--N1_txd is mips_sys:isys\|mips_dvc:imips_dvc\|uart0:iuart0\|uart_write:uart_txd\|txd at LC_X16_Y3_N2`
2			`--operation mode is normal`
3
4			`N1_txd_lut_out = N1_txd_1_a & N1_txd # !N1_txd_1_a & N1_txd_8 # !sys_rst;`
5			`N1_txd = DFFEAS(N1_txd_lut_out, GLOBAL(E1__clk0), VCC, , , , , , );`
6
7
8			`--H1_N_62_i is mips_sys:isys\|mips_dvc:imips_dvc\|seg7led_cv:iseg7_cv\|N_62_i at LC_X34_Y14_N6`
9			`--operation mode is normal`
10
11			`F1_seg7data[7]_qfbk = F1_seg7data[7];`
12			`H1_N_62_i = F1_seg7data[7]_qfbk # F1_seg7data[6] & !F1_seg7data[4] # !F1_seg7data[5] # !F1_seg7data[6] & F1_seg7data[5];`
13
14			`--F1_seg7data[7] is mips_sys:isys\|mips_dvc:imips_dvc\|seg7data[7] at LC_X34_Y14_N6`
15			`--operation mode is normal`
16
17			`F1_seg7data[7] = DFFEAS(H1_N_62_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_7, , !sys_rst, VCC);`
18
19
20			`--H1_N_60_i is mips_sys:isys\|mips_dvc:imips_dvc\|seg7led_cv:iseg7_cv\|N_60_i at LC_X34_Y14_N9`
21			`--operation mode is normal`
22
23			`F1_seg7data[6]_qfbk = F1_seg7data[6];`
24			`H1_N_60_i = F1_seg7data[7] & F1_seg7data[5] # !F1_seg7data[6]_qfbk # !F1_seg7data[7] & F1_seg7data[5] & F1_seg7data[6]_qfbk & !F1_seg7data[4] # !F1_seg7data[5] & F1_seg7data[6]_qfbk # !F1_seg7data[4];`
25
26			`--F1_seg7data[6] is mips_sys:isys\|mips_dvc:imips_dvc\|seg7data[6] at LC_X34_Y14_N9`
27			`--operation mode is normal`
28
29			`F1_seg7data[6] = DFFEAS(H1_N_60_i, GLOBAL(E1__clk0), VCC, , C1_G_594, CB1_r32_o_6, , !sys_rst, VCC);`
30
31
32			`--H1_N_58_i is mips_sys:isys\|mips_dvc:imips_dvc\|seg7led_cv:iseg7_cv\|N_58_i at LC_X34_Y14_N8`
33			`--operation mode is normal`
34
35			`F1_seg7data[5]_qfbk = F1_seg7data[5];`
36			`H1_N_58_i = F1_seg7data[5]_qfbk & F1_seg7data[7] # !F1_seg7data[4] # !F1_seg7data[5]_qfbk & F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[4];`
37
38			`--F1_seg7data[5] is mips_sys:isys\|mips_dvc:imips_dvc\|seg7data[5] at LC_X34_Y14_N8`
39			`--operation mode is normal`
40