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mcupro |
Fitter report for mips_top
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Mon Oct 13 12:02:00 2008
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Version 4.2 Build 157 12/07/2004 SJ Full Version
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Fitter Summary
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3. Fitter Settings
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4. Fitter Device Options
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5. Fitter Equations
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6. Pin-Out File
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7. Fitter Resource Usage Summary
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8. Input Pins
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9. Output Pins
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10. I/O Bank Usage
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11. All Package Pins
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12. PLL Summary
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13. PLL Usage
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14. Output Pin Default Load For Reported TCO
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15. Fitter Resource Utilization by Entity
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16. Delay Chain Summary
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17. Pad To Core Delay Chain Fanout
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18. Control Signals
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19. Global & Other Fast Signals
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20. Non-Global High Fan-Out Signals
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21. Fitter RAM Summary
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22. Interconnect Usage Summary
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23. LAB Logic Elements
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24. LAB-wide Signals
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25. LAB Signals Sourced
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26. LAB Signals Sourced Out
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27. LAB Distinct Inputs
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28. Fitter Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2004 Altera Corporation
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Any megafunction design, and related netlist (encrypted or decrypted),
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support information, device programming or simulation file, and any other
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associated documentation or information provided by Altera or a partner
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under Altera's Megafunction Partnership Program may be used only
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to program PLD devices (but not masked PLD devices) from Altera. Any
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other use of such megafunction design, netlist, support information,
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device programming or simulation file, or any other related documentation
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or information is prohibited for any other purpose, including, but not
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limited to modification, reverse engineering, de-compiling, or use with
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any other silicon devices, unless such use is explicitly licensed under
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a separate agreement with Altera or a megafunction partner. Title to the
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intellectual property, including patents, copyrights, trademarks, trade
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secrets, or maskworks, embodied in any such megafunction design, netlist,
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support information, device programming or simulation file, or any other
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related documentation or information provided by Altera or a megafunction
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partner, remains with Altera, the megafunction partner, or their respective
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licensors. No other licenses, including any licenses needed under any third
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party's intellectual property, are provided herein.
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+------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+------------------------------------------+
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; Fitter Status ; Successful - Mon Oct 13 12:02:00 2008 ;
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; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
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; Revision Name ; mips_top ;
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; Top-level Entity Name ; mips_top ;
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; Family ; Cyclone ;
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; Device ; EP1C6Q240C6 ;
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; Timing Models ; Final ;
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; Total logic elements ; 3,468 / 5,980 ( 57 % ) ;
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; Total pins ; 33 / 185 ( 17 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 71,680 / 92,160 ( 77 % ) ;
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; Total PLLs ; 1 / 2 ( 50 % ) ;
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+-----------------------+------------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------+
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; Fitter Settings ;
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+----------------------------------------------------+--------------------------------+--------------------------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------+--------------------------------+--------------------------------+
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; Device ; EP1C6Q240C6 ; ;
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; Use smart compilation ; Normal ; Normal ;
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; Placement Effort Multiplier ; 1.0 ; 1.0 ;
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; Router Effort Multiplier ; 1.0 ; 1.0 ;
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; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
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; Optimize Fast-Corner Timing ; Off ; Off ;
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; Optimize Timing ; Normal compilation ; Normal compilation ;
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; Optimize IOC Register Placement for Timing ; On ; On ;
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; Limit to One Fitting Attempt ; Off ; Off ;
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; Final Placement Optimizations ; Automatically ; Automatically ;
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; Fitter Initial Placement Seed ; 1 ; 1 ;
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; Slow Slew Rate ; Off ; Off ;
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; PCI I/O ; Off ; Off ;
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; Weak Pull-Up Resistor ; Off ; Off ;
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; Enable Bus-Hold Circuitry ; Off ; Off ;
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; Auto Global Memory Control Signals ; Off ; Off ;
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; Auto Packed Registers -- Cyclone ; Auto ; Auto ;
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; Auto Delay Chains ; On ; On ;
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; Auto Merge PLLs ; On ; On ;
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; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
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; Perform Register Duplication ; Off ; Off ;
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; Perform Register Retiming ; Off ; Off ;
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; Fitter Effort ; Auto Fit ; Auto Fit ;
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; Physical Synthesis Effort Level ; Normal ; Normal ;
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; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
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; Auto Register Duplication ; Off ; Off ;
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; Auto Global Clock ; On ; On ;
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; Auto Global Register Control Signals ; On ; On ;
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+----------------------------------------------------+--------------------------------+--------------------------------+
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+--------------------------------------------------------------------+
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; Fitter Device Options ;
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+----------------------------------------------+---------------------+
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; Option ; Setting ;
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+----------------------------------------------+---------------------+
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; Enable user-supplied start-up clock (CLKUSR) ; Off ;
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; Enable device-wide reset (DEV_CLRn) ; Off ;
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; Enable device-wide output enable (DEV_OE) ; Off ;
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; Enable INIT_DONE output ; Off ;
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; Configuration scheme ; Active Serial ;
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; Error detection CRC ; Off ;
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; Reserve all unused pins ; As input tri-stated ;
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; Base pin-out file on sameframe device ; Off ;
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+----------------------------------------------+---------------------+
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+------------------+
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; Fitter Equations ;
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+------------------+
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The equations can be found in E:/mips789/mips789/quartus2/mips_top.fit.eqn.
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+--------------+
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; Pin-Out File ;
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+--------------+
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The pin-out file can be found in E:/mips789/mips789/quartus2/mips_top.pin.
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+------------------------------------------------------------------------------------+
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; Fitter Resource Usage Summary ;
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+-----------------------------------------+------------------------------------------+
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; Resource ; Usage ;
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+-----------------------------------------+------------------------------------------+
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; Total logic elements ; 3,468 / 5,980 ( 57 % ) ;
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; -- Combinational with no register ; 2605 ;
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; -- Register only ; 104 ;
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; -- Combinational with a register ; 759 ;
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; ; ;
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; Logic element usage by number of inputs ; ;
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; -- 4 input functions ; 1701 ;
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; -- 3 input functions ; 1277 ;
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; -- 2 input functions ; 377 ;
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; -- 1 input functions ; 103 ;
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; -- 0 input functions ; 1 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- arithmetic mode ; 437 ;
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; -- qfbk mode ; 158 ;
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; -- register cascade mode ; 0 ;
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; -- synchronous clear/load mode ; 414 ;
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; -- asynchronous clear/load mode ; 1 ;
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; ; ;
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; Total LABs ; 451 / 598 ( 75 % ) ;
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; Logic elements in carry chains ; 460 ;
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; User inserted logic elements ; 0 ;
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; Virtual pins ; 0 ;
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; I/O pins ; 33 / 185 ( 17 % ) ;
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; -- Clock pins ; 1 / 2 ( 50 % ) ;
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; Global signals ; 1 ;
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; M4Ks ; 19 / 20 ( 95 % ) ;
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; Total memory bits ; 71,680 / 92,160 ( 77 % ) ;
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; Total RAM block bits ; 87,552 / 92,160 ( 95 % ) ;
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; Global clocks ; 1 / 8 ( 12 % ) ;
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; Maximum fan-out node ; pll50:Ipll|altpll:altpll_component|_clk0 ;
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; Maximum fan-out ; 882 ;
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; Total fan-out ; 13803 ;
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; Average fan-out ; 3.92 ;
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+-----------------------------------------+------------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Input Pins ;
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+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
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+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
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; clk ; 28 ; 1 ; 0 ; 12 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
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; key1 ; 156 ; 3 ; 35 ; 13 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
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; key2 ; 158 ; 3 ; 35 ; 13 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
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; rst ; 159 ; 3 ; 35 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
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; ser_rxd ; 177 ; 3 ; 35 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
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+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Output Pins ;
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+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;
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+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+
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; lcd_data[0] ; 136 ; 3 ; 35 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[1] ; 137 ; 3 ; 35 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[2] ; 138 ; 3 ; 35 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[3] ; 139 ; 3 ; 35 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[4] ; 140 ; 3 ; 35 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[5] ; 141 ; 3 ; 35 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[6] ; 143 ; 3 ; 35 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_data[7] ; 144 ; 3 ; 35 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_en ; 135 ; 3 ; 35 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_rs ; 133 ; 3 ; 35 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; lcd_rw ; 134 ; 3 ; 35 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; led1 ; 1 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; led2 ; 2 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[0] ; 169 ; 3 ; 35 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[1] ; 166 ; 3 ; 35 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[2] ; 161 ; 3 ; 35 ; 14 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[3] ; 160 ; 3 ; 35 ; 14 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[4] ; 164 ; 3 ; 35 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[5] ; 168 ; 3 ; 35 ; 17 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led1[6] ; 167 ; 3 ; 35 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[0] ; 175 ; 3 ; 35 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[1] ; 170 ; 3 ; 35 ; 17 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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| 229 |
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; seg7led2[2] ; 163 ; 3 ; 35 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[3] ; 165 ; 3 ; 35 ; 16 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[4] ; 162 ; 3 ; 35 ; 15 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[5] ; 174 ; 3 ; 35 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; seg7led2[6] ; 173 ; 3 ; 35 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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; ser_txd ; 176 ; 3 ; 35 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ;
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+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+
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+------------------------------------------------------------+
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; I/O Bank Usage ;
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+----------+------------------+---------------+--------------+
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; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
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+----------+------------------+---------------+--------------+
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; 1 ; 5 / 44 ( 11 % ) ; 3.3V ; -- ;
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; 2 ; 0 / 48 ( 0 % ) ; 3.3V ; -- ;
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; 3 ; 30 / 45 ( 66 % ) ; 3.3V ; -- ;
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; 4 ; 0 / 48 ( 0 % ) ; 3.3V ; -- ;
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+----------+------------------+---------------+--------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; All Package Pins ;
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+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+
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; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ;
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+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+
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; 1 ; 0 ; 1 ; led1 ; output ; LVTTL ; ; Row I/O ; Y ;
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; 2 ; 1 ; 1 ; led2 ; output ; LVTTL ; ; Row I/O ; Y ;
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; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 7 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 8 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
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; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;
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; 10 ; ; ; GND ; gnd ; ; ; -- ; ;
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|
|
; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 266 |
|
|
; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 267 |
|
|
; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 268 |
|
|
; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 269 |
|
|
; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 270 |
|
|
; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 271 |
|
|
; 17 ; 14 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 272 |
|
|
; 18 ; 15 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 273 |
|
|
; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 274 |
|
|
; 20 ; 17 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 275 |
|
|
; 21 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 276 |
|
|
; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;
|
| 277 |
|
|
; 23 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 278 |
|
|
; 24 ; 20 ; 1 ; *~nCSO~ / GND* ; output ; LVTTL ; ; Row I/O ; N ;
|
| 279 |
|
|
; 25 ; 21 ; 1 ; ^DATA0 ; input ; ; ; -- ; ;
|
| 280 |
|
|
; 26 ; 22 ; 1 ; ^nCONFIG ; ; ; ; -- ; ;
|
| 281 |
|
|
; 27 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; ;
|
| 282 |
|
|
; 28 ; 23 ; 1 ; clk ; input ; LVTTL ; ; Row I/O ; Y ;
|
| 283 |
|
|
; 29 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ;
|
| 284 |
|
|
; 30 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ;
|
| 285 |
|
|
; 31 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; ;
|
| 286 |
|
|
; 32 ; 25 ; 1 ; ^nCEO ; ; ; ; -- ; ;
|
| 287 |
|
|
; 33 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ;
|
| 288 |
|
|
; 34 ; 27 ; 1 ; ^MSEL0 ; ; ; ; -- ; ;
|
| 289 |
|
|
; 35 ; 28 ; 1 ; ^MSEL1 ; ; ; ; -- ; ;
|
| 290 |
|
|
; 36 ; 29 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ;
|
| 291 |
|
|
; 37 ; 30 ; 1 ; *~ASDO~ / GND* ; output ; LVTTL ; ; Row I/O ; N ;
|
| 292 |
|
|
; 38 ; 31 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 293 |
|
|
; 39 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 294 |
|
|
; 40 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 295 |
|
|
; 41 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 296 |
|
|
; 42 ; 34 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 297 |
|
|
; 43 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 298 |
|
|
; 44 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 299 |
|
|
; 45 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 300 |
|
|
; 46 ; 38 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 301 |
|
|
; 47 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 302 |
|
|
; 48 ; 40 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 303 |
|
|
; 49 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 304 |
|
|
; 50 ; 42 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 305 |
|
|
; 51 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ;
|
| 306 |
|
|
; 52 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 307 |
|
|
; 53 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 308 |
|
|
; 54 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 309 |
|
|
; 55 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 310 |
|
|
; 56 ; 46 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 311 |
|
|
; 57 ; 47 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 312 |
|
|
; 58 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 313 |
|
|
; 59 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 314 |
|
|
; 60 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 315 |
|
|
; 61 ; 51 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 316 |
|
|
; 62 ; 52 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 317 |
|
|
; 63 ; 53 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 318 |
|
|
; 64 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 319 |
|
|
; 65 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 320 |
|
|
; 66 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 321 |
|
|
; 67 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 322 |
|
|
; 68 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 323 |
|
|
; 69 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 324 |
|
|
; 70 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;
|
| 325 |
|
|
; 71 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 326 |
|
|
; 72 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 327 |
|
|
; 73 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 328 |
|
|
; 74 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 329 |
|
|
; 75 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 330 |
|
|
; 76 ; 62 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 331 |
|
|
; 77 ; 63 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 332 |
|
|
; 78 ; 64 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 333 |
|
|
; 79 ; 65 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 334 |
|
|
; 80 ; 66 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 335 |
|
|
; 81 ; 67 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 336 |
|
|
; 82 ; 68 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 337 |
|
|
; 83 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 338 |
|
|
; 84 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 339 |
|
|
; 85 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 340 |
|
|
; 86 ; 72 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 341 |
|
|
; 87 ; 73 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 342 |
|
|
; 88 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 343 |
|
|
; 89 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 344 |
|
|
; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 345 |
|
|
; 91 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 346 |
|
|
; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;
|
| 347 |
|
|
; 93 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 348 |
|
|
; 94 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 349 |
|
|
; 95 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 350 |
|
|
; 96 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 351 |
|
|
; 97 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 352 |
|
|
; 98 ; 80 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 353 |
|
|
; 99 ; 81 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 354 |
|
|
; 100 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 355 |
|
|
; 101 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 356 |
|
|
; 102 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 357 |
|
|
; 103 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 358 |
|
|
; 104 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 359 |
|
|
; 105 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 360 |
|
|
; 106 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 361 |
|
|
; 107 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 362 |
|
|
; 108 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 363 |
|
|
; 109 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 364 |
|
|
; 110 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 365 |
|
|
; 111 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 366 |
|
|
; 112 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ;
|
| 367 |
|
|
; 113 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 368 |
|
|
; 114 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 369 |
|
|
; 115 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 370 |
|
|
; 116 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 371 |
|
|
; 117 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 372 |
|
|
; 118 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 373 |
|
|
; 119 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 374 |
|
|
; 120 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 375 |
|
|
; 121 ; 99 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 376 |
|
|
; 122 ; 100 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 377 |
|
|
; 123 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 378 |
|
|
; 124 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 379 |
|
|
; 125 ; 103 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 380 |
|
|
; 126 ; 104 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 381 |
|
|
; 127 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 382 |
|
|
; 128 ; 106 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 383 |
|
|
; 129 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 384 |
|
|
; 130 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;
|
| 385 |
|
|
; 131 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 386 |
|
|
; 132 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 387 |
|
|
; 133 ; 109 ; 3 ; lcd_rs ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 388 |
|
|
; 134 ; 110 ; 3 ; lcd_rw ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 389 |
|
|
; 135 ; 111 ; 3 ; lcd_en ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 390 |
|
|
; 136 ; 112 ; 3 ; lcd_data[0] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 391 |
|
|
; 137 ; 113 ; 3 ; lcd_data[1] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 392 |
|
|
; 138 ; 114 ; 3 ; lcd_data[2] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 393 |
|
|
; 139 ; 115 ; 3 ; lcd_data[3] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 394 |
|
|
; 140 ; 116 ; 3 ; lcd_data[4] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 395 |
|
|
; 141 ; 117 ; 3 ; lcd_data[5] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 396 |
|
|
; 142 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 397 |
|
|
; 143 ; 118 ; 3 ; lcd_data[6] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 398 |
|
|
; 144 ; 119 ; 3 ; lcd_data[7] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 399 |
|
|
; 145 ; 120 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ;
|
| 400 |
|
|
; 146 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ;
|
| 401 |
|
|
; 147 ; 122 ; 3 ; #TCK ; input ; ; ; -- ; ;
|
| 402 |
|
|
; 148 ; 123 ; 3 ; #TMS ; input ; ; ; -- ; ;
|
| 403 |
|
|
; 149 ; 124 ; 3 ; #TDO ; output ; ; ; -- ; ;
|
| 404 |
|
|
; 150 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; ;
|
| 405 |
|
|
; 151 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ;
|
| 406 |
|
|
; 152 ; 125 ; 3 ; GND+ ; ; ; ; Row I/O ; ;
|
| 407 |
|
|
; 153 ; 126 ; 3 ; GND+ ; ; ; ; Row I/O ; ;
|
| 408 |
|
|
; 154 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; ;
|
| 409 |
|
|
; 155 ; 127 ; 3 ; #TDI ; input ; ; ; -- ; ;
|
| 410 |
|
|
; 156 ; 128 ; 3 ; key1 ; input ; LVTTL ; ; Row I/O ; Y ;
|
| 411 |
|
|
; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;
|
| 412 |
|
|
; 158 ; 129 ; 3 ; key2 ; input ; LVTTL ; ; Row I/O ; Y ;
|
| 413 |
|
|
; 159 ; 130 ; 3 ; rst ; input ; LVTTL ; ; Row I/O ; Y ;
|
| 414 |
|
|
; 160 ; 131 ; 3 ; seg7led1[3] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 415 |
|
|
; 161 ; 132 ; 3 ; seg7led1[2] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 416 |
|
|
; 162 ; 133 ; 3 ; seg7led2[4] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 417 |
|
|
; 163 ; 134 ; 3 ; seg7led2[2] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 418 |
|
|
; 164 ; 135 ; 3 ; seg7led1[4] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 419 |
|
|
; 165 ; 136 ; 3 ; seg7led2[3] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 420 |
|
|
; 166 ; 137 ; 3 ; seg7led1[1] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 421 |
|
|
; 167 ; 138 ; 3 ; seg7led1[6] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 422 |
|
|
; 168 ; 139 ; 3 ; seg7led1[5] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 423 |
|
|
; 169 ; 140 ; 3 ; seg7led1[0] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 424 |
|
|
; 170 ; 141 ; 3 ; seg7led2[1] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 425 |
|
|
; 171 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 426 |
|
|
; 172 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ;
|
| 427 |
|
|
; 173 ; 142 ; 3 ; seg7led2[6] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 428 |
|
|
; 174 ; 143 ; 3 ; seg7led2[5] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 429 |
|
|
; 175 ; 144 ; 3 ; seg7led2[0] ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 430 |
|
|
; 176 ; 145 ; 3 ; ser_txd ; output ; LVTTL ; ; Row I/O ; Y ;
|
| 431 |
|
|
; 177 ; 146 ; 3 ; ser_rxd ; input ; LVTTL ; ; Row I/O ; Y ;
|
| 432 |
|
|
; 178 ; 147 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 433 |
|
|
; 179 ; 148 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 434 |
|
|
; 180 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ;
|
| 435 |
|
|
; 181 ; 150 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 436 |
|
|
; 182 ; 151 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 437 |
|
|
; 183 ; 152 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 438 |
|
|
; 184 ; 153 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 439 |
|
|
; 185 ; 154 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 440 |
|
|
; 186 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 441 |
|
|
; 187 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 442 |
|
|
; 188 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 443 |
|
|
; 189 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;
|
| 444 |
|
|
; 190 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 445 |
|
|
; 191 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 446 |
|
|
; 192 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 447 |
|
|
; 193 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 448 |
|
|
; 194 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 449 |
|
|
; 195 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 450 |
|
|
; 196 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 451 |
|
|
; 197 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 452 |
|
|
; 198 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 453 |
|
|
; 199 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 454 |
|
|
; 200 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 455 |
|
|
; 201 ; 166 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 456 |
|
|
; 202 ; 167 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 457 |
|
|
; 203 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 458 |
|
|
; 204 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 459 |
|
|
; 205 ; 170 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 460 |
|
|
; 206 ; 171 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 461 |
|
|
; 207 ; 172 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 462 |
|
|
; 208 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 463 |
|
|
; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;
|
| 464 |
|
|
; 210 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 465 |
|
|
; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 466 |
|
|
; 212 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 467 |
|
|
; 213 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 468 |
|
|
; 214 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 469 |
|
|
; 215 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 470 |
|
|
; 216 ; 177 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 471 |
|
|
; 217 ; 178 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 472 |
|
|
; 218 ; 179 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 473 |
|
|
; 219 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 474 |
|
|
; 220 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 475 |
|
|
; 221 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 476 |
|
|
; 222 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 477 |
|
|
; 223 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 478 |
|
|
; 224 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 479 |
|
|
; 225 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 480 |
|
|
; 226 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 481 |
|
|
; 227 ; 188 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 482 |
|
|
; 228 ; 189 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 483 |
|
|
; 229 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ;
|
| 484 |
|
|
; 230 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 485 |
|
|
; 231 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ;
|
| 486 |
|
|
; 232 ; ; ; GND ; gnd ; ; ; -- ; ;
|
| 487 |
|
|
; 233 ; 190 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 488 |
|
|
; 234 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 489 |
|
|
; 235 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 490 |
|
|
; 236 ; 193 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 491 |
|
|
; 237 ; 194 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 492 |
|
|
; 238 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 493 |
|
|
; 239 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 494 |
|
|
; 240 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ;
|
| 495 |
|
|
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+
|
| 496 |
|
|
|
| 497 |
|
|
|
| 498 |
|
|
+----------------------------------------------------------------------+
|
| 499 |
|
|
; PLL Summary ;
|
| 500 |
|
|
+-----------------------------+----------------------------------------+
|
| 501 |
|
|
; Name ; pll50:Ipll|altpll:altpll_component|pll ;
|
| 502 |
|
|
+-----------------------------+----------------------------------------+
|
| 503 |
|
|
; PLL type ; - ;
|
| 504 |
|
|
; Scan chain ; None ;
|
| 505 |
|
|
; PLL mode ; Normal ;
|
| 506 |
|
|
; Feedback source ; -- ;
|
| 507 |
|
|
; Compensate clock ; clock0 ;
|
| 508 |
|
|
; Switchover on loss of clock ; -- ;
|
| 509 |
|
|
; Switchover counter ; -- ;
|
| 510 |
|
|
; Primary clock ; -- ;
|
| 511 |
|
|
; Input frequency 0 ; 25.0 MHz ;
|
| 512 |
|
|
; Input frequency 1 ; -- ;
|
| 513 |
|
|
; Nominal VCO frequency ; 800.0 MHz ;
|
| 514 |
|
|
; Freq min lock ; 15.34 MHz ;
|
| 515 |
|
|
; Freq max lock ; 31.25 MHz ;
|
| 516 |
|
|
; Clock Offset ; 0 ps ;
|
| 517 |
|
|
; M VCO Tap ; 0 ;
|
| 518 |
|
|
; M Initial ; 1 ;
|
| 519 |
|
|
; M value ; 32 ;
|
| 520 |
|
|
; N value ; 1 ;
|
| 521 |
|
|
; M counter delay ; -- ;
|
| 522 |
|
|
; N counter delay ; -- ;
|
| 523 |
|
|
; M2 value ; -- ;
|
| 524 |
|
|
; N2 value ; -- ;
|
| 525 |
|
|
; SS counter ; -- ;
|
| 526 |
|
|
; Downspread ; -- ;
|
| 527 |
|
|
; Spread frequency ; -- ;
|
| 528 |
|
|
; Charge pump current ; -- ;
|
| 529 |
|
|
; Loop filter resistance ; -- ;
|
| 530 |
|
|
; Loop filter capacitance ; -- ;
|
| 531 |
|
|
; Freq zero ; -- ;
|
| 532 |
|
|
; Bandwidth ; -- ;
|
| 533 |
|
|
; Freq pole ; -- ;
|
| 534 |
|
|
; enable0 counter ; -- ;
|
| 535 |
|
|
; enable1 counter ; -- ;
|
| 536 |
|
|
; Real time reconfigurable ; -- ;
|
| 537 |
|
|
; Scan chain MIF file ; -- ;
|
| 538 |
|
|
; Preserve counter order ; Off ;
|
| 539 |
|
|
; PLL location ; PLL_1 ;
|
| 540 |
|
|
; Inclk0 signal ; clk ;
|
| 541 |
|
|
; Inclk1 signal ; -- ;
|
| 542 |
|
|
+-----------------------------+----------------------------------------+
|
| 543 |
|
|
|
| 544 |
|
|
|
| 545 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 546 |
|
|
; PLL Usage ;
|
| 547 |
|
|
+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------+
|
| 548 |
|
|
; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Delay ; Duty Cycle ; Counter ; Counter Delay ; Counter Value ; High / Low ; Initial ; VCO Tap ;
|
| 549 |
|
|
+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------+
|
| 550 |
|
|
; pll50:Ipll|altpll:altpll_component|_clk0 ; clock0 ; 2 ; 1 ; 50.0 MHz ; 0 (0 ps) ; 0 ps ; 50/50 ; G1 ; -- ; 16 ; 8/8 Even ; 1 ; 0 ;
|
| 551 |
|
|
+------------------------------------------+--------------+------+-----+------------------+-------------+-------+------------+---------+---------------+---------------+------------+---------+---------+
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
+------------------------------------------------------------------+
|
| 555 |
|
|
; Output Pin Default Load For Reported TCO ;
|
| 556 |
|
|
+---------------------+-------+------------------------------------+
|
| 557 |
|
|
; I/O Standard ; Load ; Termination Resistance ;
|
| 558 |
|
|
+---------------------+-------+------------------------------------+
|
| 559 |
|
|
; LVTTL ; 10 pF ; Not Available ;
|
| 560 |
|
|
; LVCMOS ; 10 pF ; Not Available ;
|
| 561 |
|
|
; 2.5 V ; 10 pF ; Not Available ;
|
| 562 |
|
|
; 1.8 V ; 10 pF ; Not Available ;
|
| 563 |
|
|
; 1.5 V ; 10 pF ; Not Available ;
|
| 564 |
|
|
; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
|
| 565 |
|
|
; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
|
| 566 |
|
|
; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
|
| 567 |
|
|
; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
|
| 568 |
|
|
; Differential SSTL-2 ; 30 pF ; (See SSTL-2) ;
|
| 569 |
|
|
; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
|
| 570 |
|
|
; LVDS ; 4 pF ; 100 Ohm (Differential) ;
|
| 571 |
|
|
; RSDS ; 0 pF ; 100 Ohm (Differential) ;
|
| 572 |
|
|
+---------------------+-------+------------------------------------+
|
| 573 |
|
|
|
| 574 |
|
|
|
| 575 |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 576 |
|
|
; Fitter Resource Utilization by Entity ;
|
| 577 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 578 |
|
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
|
| 579 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 580 |
|
|
; |mips_top ; 3468 (3) ; 863 ; 71680 ; 33 ; 0 ; 2605 (1) ; 107 (1) ; 756 (1) ; 460 (0) ; |mips_top ;
|
| 581 |
|
|
; |mem_array:ram_8k| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k ;
|
| 582 |
|
|
; |ram2048x8_0:ram0| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0 ;
|
| 583 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component ;
|
| 584 |
|
|
; |altsyncram_eht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated ;
|
| 585 |
|
|
; |ram2048x8_1:ram1| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1 ;
|
| 586 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component ;
|
| 587 |
|
|
; |altsyncram_fht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated ;
|
| 588 |
|
|
; |ram2048x8_2:ram2| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2 ;
|
| 589 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component ;
|
| 590 |
|
|
; |altsyncram_ght1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated ;
|
| 591 |
|
|
; |ram2048x8_3:ram3| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3 ;
|
| 592 |
|
|
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component ;
|
| 593 |
|
|
; |altsyncram_hht1:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated ;
|
| 594 |
|
|
; |mips_sys:isys| ; 3465 (44) ; 861 ; 6144 ; 31 ; 0 ; 2604 (44) ; 106 (0) ; 755 (0) ; 460 (0) ; |mips_top|mips_sys:isys ;
|
| 595 |
|
|
; |mips_core:mips_core| ; 3085 (31) ; 604 ; 2048 ; 0 ; 0 ; 2481 (31) ; 55 (0) ; 549 (0) ; 363 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core ;
|
| 596 |
|
|
; |decode_pipe:decoder_pipe| ; 251 (0) ; 52 ; 0 ; 0 ; 0 ; 199 (0) ; 6 (0) ; 46 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe ;
|
| 597 |
|
|
; |decoder:idecoder| ; 199 (184) ; 0 ; 0 ; 0 ; 0 ; 199 (184) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder ;
|
| 598 |
|
|
; |SYNLPM_LATR1:cmp_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_ ;
|
| 599 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:cmp_ctl_1_0_|lpm_latch:U1 ;
|
| 600 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_ ;
|
| 601 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_0_|lpm_latch:U1 ;
|
| 602 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_1__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z ;
|
| 603 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_1__Z|lpm_latch:U1 ;
|
| 604 |
|
|
; |SYNLPM_LATR1:fsm_dly_1_2__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z ;
|
| 605 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATR1:fsm_dly_1_2__Z|lpm_latch:U1 ;
|
| 606 |
|
|
; |SYNLPM_LATRS1:alu_func_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_ ;
|
| 607 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_2_|lpm_latch:U1 ;
|
| 608 |
|
|
; |SYNLPM_LATRS1:alu_func_1_3_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_ ;
|
| 609 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:alu_func_1_3_|lpm_latch:U1 ;
|
| 610 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_ ;
|
| 611 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_0_|lpm_latch:U1 ;
|
| 612 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_ ;
|
| 613 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_1_|lpm_latch:U1 ;
|
| 614 |
|
|
; |SYNLPM_LATRS1:dmem_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_ ;
|
| 615 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:dmem_ctl_1_2_|lpm_latch:U1 ;
|
| 616 |
|
|
; |SYNLPM_LATRS1:ext_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_ ;
|
| 617 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:ext_ctl_1_0_|lpm_latch:U1 ;
|
| 618 |
|
|
; |SYNLPM_LATRS1:muxa_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_ ;
|
| 619 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxa_ctl_1_1_|lpm_latch:U1 ;
|
| 620 |
|
|
; |SYNLPM_LATRS1:muxb_ctl_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_ ;
|
| 621 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:muxb_ctl_1_1_|lpm_latch:U1 ;
|
| 622 |
|
|
; |SYNLPM_LATRS1:pc_gen_ctl_1_0_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_ ;
|
| 623 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_0_|lpm_latch:U1 ;
|
| 624 |
|
|
; |SYNLPM_LATRS1:pc_gen_ctl_1_2_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_ ;
|
| 625 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:pc_gen_ctl_1_2_|lpm_latch:U1 ;
|
| 626 |
|
|
; |SYNLPM_LATRS1:rd_sel_1_1_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_ ;
|
| 627 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|decoder:idecoder|SYNLPM_LATRS1:rd_sel_1_1_|lpm_latch:U1 ;
|
| 628 |
|
|
; |pipelinedregs:pipereg| ; 52 (0) ; 52 ; 0 ; 0 ; 0 ; 0 (0) ; 6 (0) ; 46 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg ;
|
| 629 |
|
|
; |alu_func_reg_clr:U16| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16 ;
|
| 630 |
|
|
; |alu_func_reg_clr_cls:U26| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr_cls:U26 ;
|
| 631 |
|
|
; |alu_we_reg_clr:U24| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr:U24 ;
|
| 632 |
|
|
; |alu_we_reg_clr_cls:U6| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_we_reg_clr_cls:U6 ;
|
| 633 |
|
|
; |cmp_ctl_reg_clr_cls:U2| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|cmp_ctl_reg_clr_cls:U2 ;
|
| 634 |
|
|
; |dmem_ctl_reg:U9| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9 ;
|
| 635 |
|
|
; |dmem_ctl_reg_clr:U15| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr:U15 ;
|
| 636 |
|
|
; |dmem_ctl_reg_clr_cls:U3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg_clr_cls:U3 ;
|
| 637 |
|
|
; |ext_ctl_reg_clr_cls:U4| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|ext_ctl_reg_clr_cls:U4 ;
|
| 638 |
|
|
; |muxa_ctl_reg_clr:U17| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17 ;
|
| 639 |
|
|
; |muxa_ctl_reg_clr_cls:U7| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr_cls:U7 ;
|
| 640 |
|
|
; |muxb_ctl_reg_clr:U14| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr:U14 ;
|
| 641 |
|
|
; |muxb_ctl_reg_clr_cls:U1| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxb_ctl_reg_clr_cls:U1 ;
|
| 642 |
|
|
; |pc_gen_ctl_reg_clr_cls:U8| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|pc_gen_ctl_reg_clr_cls:U8 ;
|
| 643 |
|
|
; |rd_sel_reg_clr_cls:U5| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|rd_sel_reg_clr_cls:U5 ;
|
| 644 |
|
|
; |wb_mux_ctl_reg:U18| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18 ;
|
| 645 |
|
|
; |wb_mux_ctl_reg_1:U21| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_1:U21 ;
|
| 646 |
|
|
; |wb_mux_ctl_reg_clr:U13| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr:U13 ;
|
| 647 |
|
|
; |wb_mux_ctl_reg_clr_cls:U10| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg_clr_cls:U10 ;
|
| 648 |
|
|
; |wb_we_reg:U12| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12 ;
|
| 649 |
|
|
; |wb_we_reg_1:U20| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_1:U20 ;
|
| 650 |
|
|
; |wb_we_reg_2:U22| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_2:U22 ;
|
| 651 |
|
|
; |wb_we_reg_clr:U19| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr:U19 ;
|
| 652 |
|
|
; |wb_we_reg_clr_cls:U11| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg_clr_cls:U11 ;
|
| 653 |
|
|
; |exec_stage:iexec_stage| ; 1941 (1) ; 179 ; 0 ; 0 ; 0 ; 1762 (1) ; 2 (0) ; 177 (0) ; 331 (1) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage ;
|
| 654 |
|
|
; |alu_muxa:i_alu_muxa| ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 128 (128) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa ;
|
| 655 |
|
|
; |alu_muxb:i_alu_muxb| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb ;
|
| 656 |
|
|
; |big_alu:MIPS_alu| ; 1711 (95) ; 115 ; 0 ; 0 ; 0 ; 1596 (95) ; 1 (0) ; 114 (0) ; 301 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu ;
|
| 657 |
|
|
; |alu:mips_alu| ; 240 (240) ; 0 ; 0 ; 0 ; 0 ; 240 (240) ; 0 (0) ; 0 (0) ; 98 (98) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu ;
|
| 658 |
|
|
; |muldiv_ff:muldiv_ff| ; 769 (769) ; 115 ; 0 ; 0 ; 0 ; 654 (654) ; 1 (1) ; 114 (114) ; 203 (203) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff ;
|
| 659 |
|
|
; |shifter_tak:mips_shifter| ; 607 (607) ; 0 ; 0 ; 0 ; 0 ; 607 (607) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter ;
|
| 660 |
|
|
; |fwd_mux_2:dmem_fw_mux| ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux ;
|
| 661 |
|
|
; |r32_reg:pc_nxt| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; 29 (29) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg:pc_nxt ;
|
| 662 |
|
|
; |r32_reg_cls:spc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|r32_reg_cls:spc ;
|
| 663 |
|
|
; |forward:iforward| ; 16 (0) ; 10 ; 0 ; 0 ; 0 ; 6 (0) ; 1 (0) ; 9 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward ;
|
| 664 |
|
|
; |forward_node_fw_alu_rs:fw_alu_rs| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs ;
|
| 665 |
|
|
; |forward_node_fw_alu_rs_1:fw_alu_rt| ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt ;
|
| 666 |
|
|
; |forward_node_fw_alu_rs_3:fw_cmp_rt| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt ;
|
| 667 |
|
|
; |fw_latch5:fw_reg_rns| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5:fw_reg_rns ;
|
| 668 |
|
|
; |fw_latch5_1:fw_reg_rnt| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 4 (4) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|forward:iforward|fw_latch5_1:fw_reg_rnt ;
|
| 669 |
|
|
; |mem_module:MEM_CTL| ; 140 (0) ; 6 ; 0 ; 0 ; 0 ; 134 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL ;
|
| 670 |
|
|
; |infile_dmem_ctl_reg:dmem_ctl_post| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post ;
|
| 671 |
|
|
; |mem_addr_ctl:i_mem_addr_ctl| ; 11 (3) ; 0 ; 0 ; 0 ; 0 ; 11 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl ;
|
| 672 |
|
|
; |SYNLPM_LATRS1:wr_en_1_0_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_ ;
|
| 673 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1 ;
|
| 674 |
|
|
; |SYNLPM_LATRS1:wr_en_1_1_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_ ;
|
| 675 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1 ;
|
| 676 |
|
|
; |SYNLPM_LATRS1:wr_en_1_2_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_ ;
|
| 677 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1 ;
|
| 678 |
|
|
; |SYNLPM_LATRS1:wr_en_1_3_| ; 2 (0) ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_ ;
|
| 679 |
|
|
; |lpm_latch:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1 ;
|
| 680 |
|
|
; |mem_din_ctl:i_mem_din_ctl| ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_din_ctl:i_mem_din_ctl ;
|
| 681 |
|
|
; |mem_dout_ctl:i_mem_dout_ctl| ; 90 (90) ; 0 ; 0 ; 0 ; 0 ; 90 (90) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_dout_ctl:i_mem_dout_ctl ;
|
| 682 |
|
|
; |r32_reg_1:alu_pass0| ; 30 (30) ; 30 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 30 (30) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0 ;
|
| 683 |
|
|
; |r32_reg_2:alu_pass1| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1 ;
|
| 684 |
|
|
; |r32_reg_3:cop_data_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg ;
|
| 685 |
|
|
; |r32_reg_4:cop_dout_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg ;
|
| 686 |
|
|
; |r32_reg_5:ext_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_5:ext_reg ;
|
| 687 |
|
|
; |r32_reg_6:pc| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_6:pc ;
|
| 688 |
|
|
; |r32_reg_7:rs_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_7:rs_reg ;
|
| 689 |
|
|
; |r32_reg_8:rt_reg| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg ;
|
| 690 |
|
|
; |r5_reg:rnd_pass0| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg:rnd_pass0 ;
|
| 691 |
|
|
; |r5_reg_1:rnd_pass1| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1 ;
|
| 692 |
|
|
; |r5_reg_2:rnd_pass2| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 3 (3) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|r5_reg_2:rnd_pass2 ;
|
| 693 |
|
|
; |rf_stage:iRF_stage| ; 437 (0) ; 88 ; 2048 ; 0 ; 0 ; 349 (0) ; 12 (0) ; 76 (0) ; 32 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage ;
|
| 694 |
|
|
; |compare:i_cmp| ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 36 (36) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|compare:i_cmp ;
|
| 695 |
|
|
; |ctl_FSM:MIAN_FSM| ; 35 (33) ; 14 ; 0 ; 0 ; 0 ; 21 (19) ; 1 (1) ; 13 (13) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM ;
|
| 696 |
|
|
; |SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z ;
|
| 697 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATR1:next_delay_counter_Sreg0_3__Z|lpm_latch:U1 ;
|
| 698 |
|
|
; |SYNLPM_LATS1:next_delay_counter_Sreg0_5_| ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_ ;
|
| 699 |
|
|
; |lpm_latch:U1| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|SYNLPM_LATS1:next_delay_counter_Sreg0_5_|lpm_latch:U1 ;
|
| 700 |
|
|
; |ext:i_ext| ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ext:i_ext ;
|
| 701 |
|
|
; |fwd_mux:rf_fwd_rt| ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; 65 (65) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux:rf_fwd_rt ;
|
| 702 |
|
|
; |fwd_mux_1:rs_fwd_rs| ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 64 (64) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs ;
|
| 703 |
|
|
; |pc_gen:i_pc_gen| ; 133 (133) ; 0 ; 0 ; 0 ; 0 ; 133 (133) ; 0 (0) ; 0 (0) ; 32 (32) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen ;
|
| 704 |
|
|
; |r32_reg_clr_cls:ins_reg| ; 26 (26) ; 26 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 18 (18) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|r32_reg_clr_cls:ins_reg ;
|
| 705 |
|
|
; |reg_array:reg_bank_cZ| ; 62 (62) ; 48 ; 2048 ; 0 ; 0 ; 14 (14) ; 3 (3) ; 45 (45) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ ;
|
| 706 |
|
|
; |altsyncram:reg_bank_1_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z ;
|
| 707 |
|
|
; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated ;
|
| 708 |
|
|
; |altsyncram:reg_bank_I_1_Z| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z ;
|
| 709 |
|
|
; |altsyncram_3mc1:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated ;
|
| 710 |
|
|
; |mips_dvc:imips_dvc| ; 336 (108) ; 257 ; 4096 ; 0 ; 0 ; 79 (24) ; 51 (36) ; 206 (48) ; 97 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc ;
|
| 711 |
|
|
; |seg7led_cv:iseg7_cv| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv ;
|
| 712 |
|
|
; |tmr0:mips_tmr0| ; 75 (75) ; 64 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 64 (64) ; 32 (32) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0 ;
|
| 713 |
|
|
; |uart0:iuart0| ; 147 (0) ; 109 ; 4096 ; 0 ; 0 ; 38 (0) ; 15 (0) ; 94 (0) ; 65 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0 ;
|
| 714 |
|
|
; |rxd_d:rxd_rdy_hold_lw| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|rxd_d:rxd_rdy_hold_lw ;
|
| 715 |
|
|
; |uart_read:uart_rd_tak| ; 55 (55) ; 42 ; 0 ; 0 ; 0 ; 13 (13) ; 14 (14) ; 28 (28) ; 19 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak ;
|
| 716 |
|
|
; |uart_write:uart_txd| ; 91 (53) ; 66 ; 4096 ; 0 ; 0 ; 25 (16) ; 1 (1) ; 65 (36) ; 46 (19) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd ;
|
| 717 |
|
|
; |fifo512_cyclone:fifo| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo ;
|
| 718 |
|
|
; |scfifo_Z1:scfifo_component| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component ;
|
| 719 |
|
|
; |scfifo:U1| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1 ;
|
| 720 |
|
|
; |scfifo_e4u:auto_generated| ; 38 (0) ; 29 ; 4096 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated ;
|
| 721 |
|
|
; |a_dpfifo_lqr:dpfifo| ; 38 (2) ; 29 ; 4096 ; 0 ; 0 ; 9 (2) ; 0 (0) ; 29 (0) ; 27 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo ;
|
| 722 |
|
|
; |a_fefifo_s7f:fifo_state| ; 18 (9) ; 11 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 11 (2) ; 9 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state ;
|
| 723 |
|
|
; |cntr_cc7:count_usedw| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw ;
|
| 724 |
|
|
; |cntr_ud8:rd_ptr_count| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:rd_ptr_count ;
|
| 725 |
|
|
; |cntr_ud8:wr_ptr| ; 9 (9) ; 9 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; 9 (9) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|cntr_ud8:wr_ptr ;
|
| 726 |
|
|
; |dpram_4cm:FIFOram| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram ;
|
| 727 |
|
|
; |altsyncram_ihc1:altsyncram1| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1 ;
|
| 728 |
|
|
; |pll50:Ipll| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll ;
|
| 729 |
|
|
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |mips_top|pll50:Ipll|altpll:altpll_component ;
|
| 730 |
|
|
+----------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
+--------------------------------------------------------------------------------------+
|
| 734 |
|
|
; Delay Chain Summary ;
|
| 735 |
|
|
+-------------+----------+---------------+---------------+-----------------------+-----+
|
| 736 |
|
|
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
|
| 737 |
|
|
+-------------+----------+---------------+---------------+-----------------------+-----+
|
| 738 |
|
|
; clk ; Input ; -- ; -- ; -- ; -- ;
|
| 739 |
|
|
; rst ; Input ; ON ; ON ; -- ; -- ;
|
| 740 |
|
|
; ser_txd ; Output ; -- ; -- ; -- ; -- ;
|
| 741 |
|
|
; seg7led1[6] ; Output ; -- ; -- ; -- ; -- ;
|
| 742 |
|
|
; seg7led1[5] ; Output ; -- ; -- ; -- ; -- ;
|
| 743 |
|
|
; seg7led1[4] ; Output ; -- ; -- ; -- ; -- ;
|
| 744 |
|
|
; seg7led1[3] ; Output ; -- ; -- ; -- ; -- ;
|
| 745 |
|
|
; seg7led1[2] ; Output ; -- ; -- ; -- ; -- ;
|
| 746 |
|
|
; seg7led1[1] ; Output ; -- ; -- ; -- ; -- ;
|
| 747 |
|
|
; seg7led1[0] ; Output ; -- ; -- ; -- ; -- ;
|
| 748 |
|
|
; seg7led2[6] ; Output ; -- ; -- ; -- ; -- ;
|
| 749 |
|
|
; seg7led2[5] ; Output ; -- ; -- ; -- ; -- ;
|
| 750 |
|
|
; seg7led2[4] ; Output ; -- ; -- ; -- ; -- ;
|
| 751 |
|
|
; seg7led2[3] ; Output ; -- ; -- ; -- ; -- ;
|
| 752 |
|
|
; seg7led2[2] ; Output ; -- ; -- ; -- ; -- ;
|
| 753 |
|
|
; seg7led2[1] ; Output ; -- ; -- ; -- ; -- ;
|
| 754 |
|
|
; seg7led2[0] ; Output ; -- ; -- ; -- ; -- ;
|
| 755 |
|
|
; lcd_data[7] ; Output ; -- ; -- ; -- ; -- ;
|
| 756 |
|
|
; lcd_data[6] ; Output ; -- ; -- ; -- ; -- ;
|
| 757 |
|
|
; lcd_data[5] ; Output ; -- ; -- ; -- ; -- ;
|
| 758 |
|
|
; lcd_data[4] ; Output ; -- ; -- ; -- ; -- ;
|
| 759 |
|
|
; lcd_data[3] ; Output ; -- ; -- ; -- ; -- ;
|
| 760 |
|
|
; lcd_data[2] ; Output ; -- ; -- ; -- ; -- ;
|
| 761 |
|
|
; lcd_data[1] ; Output ; -- ; -- ; -- ; -- ;
|
| 762 |
|
|
; lcd_data[0] ; Output ; -- ; -- ; -- ; -- ;
|
| 763 |
|
|
; lcd_rs ; Output ; -- ; -- ; -- ; -- ;
|
| 764 |
|
|
; lcd_rw ; Output ; -- ; -- ; -- ; -- ;
|
| 765 |
|
|
; lcd_en ; Output ; -- ; -- ; -- ; -- ;
|
| 766 |
|
|
; led1 ; Output ; -- ; -- ; -- ; -- ;
|
| 767 |
|
|
; led2 ; Output ; -- ; -- ; -- ; -- ;
|
| 768 |
|
|
; key1 ; Input ; ON ; ON ; -- ; -- ;
|
| 769 |
|
|
; key2 ; Input ; ON ; ON ; -- ; -- ;
|
| 770 |
|
|
; ser_rxd ; Input ; OFF ; ON ; -- ; -- ;
|
| 771 |
|
|
+-------------+----------+---------------+---------------+-----------------------+-----+
|
| 772 |
|
|
|
| 773 |
|
|
|
| 774 |
|
|
+-----------------------------------------------------------------------------------------------------------------+
|
| 775 |
|
|
; Pad To Core Delay Chain Fanout ;
|
| 776 |
|
|
+-----------------------------------------------------------------------------------+-------------------+---------+
|
| 777 |
|
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
| 778 |
|
|
+-----------------------------------------------------------------------------------+-------------------+---------+
|
| 779 |
|
|
; clk ; ; ;
|
| 780 |
|
|
; rst ; ; ;
|
| 781 |
|
|
; - r_rst ; 0 ; ON ;
|
| 782 |
|
|
; mips_sys:isys|key1_in ; ; ;
|
| 783 |
|
|
; - mips_sys:isys|mips_dvc:imips_dvc|r_key1_Z ; 0 ; ON ;
|
| 784 |
|
|
; mips_sys:isys|key2_in ; ; ;
|
| 785 |
|
|
; - mips_sys:isys|mips_dvc:imips_dvc|r_key2_Z ; 0 ; ON ;
|
| 786 |
|
|
; mips_sys:isys|ser_rxd_in ; ; ;
|
| 787 |
|
|
; - mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|rxq1_Z ; 1 ; ON ;
|
| 788 |
|
|
+-----------------------------------------------------------------------------------+-------------------+---------+
|
| 789 |
|
|
|
| 790 |
|
|
|
| 791 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 792 |
|
|
; Control Signals ;
|
| 793 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
|
| 794 |
|
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
| 795 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
|
| 796 |
|
|
; clk ; PIN_28 ; 1 ; Clock ; no ; -- ; -- ;
|
| 797 |
|
|
; mips_sys:isys|G_451_x ; LC_X14_Y3_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
|
| 798 |
|
|
; mips_sys:isys|G_504 ; LC_X29_Y17_N4 ; 53 ; Clock enable ; no ; -- ; -- ;
|
| 799 |
|
|
; mips_sys:isys|G_505 ; LC_X3_Y14_N5 ; 65 ; Clock enable ; no ; -- ; -- ;
|
| 800 |
|
|
; mips_sys:isys|G_570_x ; LC_X33_Y5_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
| 801 |
|
|
; mips_sys:isys|G_578 ; LC_X33_Y16_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
|
| 802 |
|
|
; mips_sys:isys|G_586 ; LC_X16_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
|
| 803 |
|
|
; mips_sys:isys|G_594 ; LC_X33_Y9_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
| 804 |
|
|
; mips_sys:isys|G_602 ; LC_X33_Y9_N4 ; 32 ; Clock enable ; no ; -- ; -- ;
|
| 805 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12|wb_we_o_0 ; LC_X27_Y12_N8 ; 10 ; Write enable ; no ; -- ; -- ;
|
| 806 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|addop2_0_sqmuxa_1_i ; LC_X2_Y15_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
|
| 807 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|finish_0_sqmuxa_i ; LC_X2_Y15_N7 ; 1 ; Clock enable ; no ; -- ; -- ;
|
| 808 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_i ; LC_X32_Y9_N0 ; 6 ; Sync. clear ; no ; -- ; -- ;
|
| 809 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|mul_0_sqmuxa_i ; LC_X9_Y14_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
| 810 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i ; LC_X8_Y13_N4 ; 34 ; Clock enable ; no ; -- ; -- ;
|
| 811 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sub_or_yn_0_sqmuxa_1_i ; LC_X3_Y14_N2 ; 1 ; Clock enable ; no ; -- ; -- ;
|
| 812 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_0_|lpm_latch:U1|q[0]~95 ; LC_X13_Y9_N4 ; 5 ; Write enable ; no ; -- ; -- ;
|
| 813 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95 ; LC_X13_Y9_N5 ; 5 ; Write enable ; no ; -- ; -- ;
|
| 814 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_2_|lpm_latch:U1|q[0]~85 ; LC_X13_Y9_N9 ; 5 ; Write enable ; no ; -- ; -- ;
|
| 815 |
|
|
; mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_3_|lpm_latch:U1|q[0]~85 ; LC_X14_Y9_N1 ; 5 ; Write enable ; no ; -- ; -- ;
|
| 816 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2 ; LC_X30_Y16_N7 ; 55 ; Clock enable ; no ; -- ; -- ;
|
| 817 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|NET1640_i ; LC_X27_Y14_N9 ; 16 ; Sync. clear ; no ; -- ; -- ;
|
| 818 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2 ; LC_X27_Y14_N6 ; 54 ; Sync. clear ; no ; -- ; -- ;
|
| 819 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|cmd[1] ; LC_X34_Y13_N7 ; 1 ; Async. clear ; no ; -- ; -- ;
|
| 820 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2 ; LC_X33_Y9_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
| 821 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|cntrlde ; LC_X32_Y6_N0 ; 32 ; Clock enable ; no ; -- ; -- ;
|
| 822 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1 ; LC_X31_Y3_N8 ; 33 ; Sync. load ; no ; -- ; -- ;
|
| 823 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|bit_ctr23_i_i ; LC_X33_Y15_N7 ; 3 ; Sync. clear ; no ; -- ; -- ;
|
| 824 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|clk_ctr27_i_i ; LC_X33_Y15_N4 ; 16 ; Sync. clear ; no ; -- ; -- ;
|
| 825 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_read:uart_rd_tak|int_req ; LC_X33_Y15_N9 ; 1 ; Clock enable ; no ; -- ; -- ;
|
| 826 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_i ; LC_X16_Y3_N7 ; 3 ; Sync. clear ; no ; -- ; -- ;
|
| 827 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_i ; LC_X15_Y3_N8 ; 16 ; Sync. clear ; no ; -- ; -- ;
|
| 828 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|_~14 ; LC_X22_Y2_N6 ; 9 ; Clock enable ; no ; -- ; -- ;
|
| 829 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_rreq ; LC_X22_Y2_N9 ; 10 ; Clock enable ; no ; -- ; -- ;
|
| 830 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|valid_wreq ; LC_X22_Y2_N8 ; 18 ; Write enable ; no ; -- ; -- ;
|
| 831 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2 ; LC_X33_Y9_N1 ; 33 ; Clock enable ; no ; -- ; -- ;
|
| 832 |
|
|
; pll50:Ipll|altpll:altpll_component|_clk0 ; PLL_1 ; 882 ; Clock ; yes ; Global clock ; GCLK3 ;
|
| 833 |
|
|
; sys_rst ; LC_X33_Y13_N2 ; 185 ; Clock enable, Sync. clear ; no ; -- ; -- ;
|
| 834 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
+---------------------------------------------------------------------------------------------------------+
|
| 838 |
|
|
; Global & Other Fast Signals ;
|
| 839 |
|
|
+------------------------------------------+----------+---------+----------------------+------------------+
|
| 840 |
|
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
| 841 |
|
|
+------------------------------------------+----------+---------+----------------------+------------------+
|
| 842 |
|
|
; pll50:Ipll|altpll:altpll_component|_clk0 ; PLL_1 ; 882 ; Global clock ; GCLK3 ;
|
| 843 |
|
|
+------------------------------------------+----------+---------+----------------------+------------------+
|
| 844 |
|
|
|
| 845 |
|
|
|
| 846 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------+
|
| 847 |
|
|
; Non-Global High Fan-Out Signals ;
|
| 848 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+---------+
|
| 849 |
|
|
; Name ; Fan-Out ;
|
| 850 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+---------+
|
| 851 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_2 ; 242 ;
|
| 852 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_1 ; 225 ;
|
| 853 |
|
|
; sys_rst ; 186 ;
|
| 854 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_0 ; 159 ;
|
| 855 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_2_sqmuxa ; 65 ;
|
| 856 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_sn_m2 ; 65 ;
|
| 857 |
|
|
; mips_sys:isys|G_505 ; 65 ;
|
| 858 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2 ; 65 ;
|
| 859 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_3 ; 62 ;
|
| 860 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_31 ; 58 ;
|
| 861 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|CurrState_Sreg0_2 ; 58 ;
|
| 862 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out586 ; 58 ;
|
| 863 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_1_sqmuxa_1 ; 54 ;
|
| 864 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|ctl_FSM:MIAN_FSM|id2ra_ins_clr_1_0_i_a2_0_a2 ; 54 ;
|
| 865 |
|
|
; mips_sys:isys|G_504 ; 53 ;
|
| 866 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_0 ; 51 ;
|
| 867 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out587 ; 48 ;
|
| 868 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[4] ; 47 ;
|
| 869 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[3] ; 45 ;
|
| 870 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m25_0 ; 45 ;
|
| 871 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|alu_func_reg_clr:U16|alu_func_o_4 ; 45 ;
|
| 872 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[2] ; 41 ;
|
| 873 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|a_o_4 ; 38 ;
|
| 874 |
|
|
; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_2:fw_cmp_rs|mux_fw_1 ; 35 ;
|
| 875 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|sign ; 35 ;
|
| 876 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0 ; 35 ;
|
| 877 |
|
|
; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1 ; 35 ;
|
| 878 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|fwd_mux_1:rs_fwd_rs|dout7_0_a2 ; 34 ;
|
| 879 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|eqop2_2_32 ; 34 ;
|
| 880 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_3_sqmuxa ; 34 ;
|
| 881 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[7] ; 34 ;
|
| 882 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|op1_sign_reged_0_sqmuxa_i ; 34 ;
|
| 883 |
|
|
; mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_3:fw_cmp_rt|mux_fw_1 ; 34 ;
|
| 884 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_sn_m31_i ; 34 ;
|
| 885 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|hilo_0_sqmuxa ; 33 ;
|
| 886 |
|
|
; mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|muxa_ctl_reg_clr:U17|muxa_ctl_o_1 ; 33 ;
|
| 887 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o18 ; 33 ;
|
| 888 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|sum13_0_a2 ; 33 ;
|
| 889 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|tmr0:mips_tmr0|un1_ld_1 ; 33 ;
|
| 890 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7 ; 33 ;
|
| 891 |
|
|
; ~GND ; 32 ;
|
| 892 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_14_i_0_s2 ; 32 ;
|
| 893 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|N_18_i_0_s3 ; 32 ;
|
| 894 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_0_sqmuxa_0_a4 ; 32 ;
|
| 895 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_1_sqmuxa_0_a4 ; 32 ;
|
| 896 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|pc_next_2_sqmuxa_0_a4 ; 32 ;
|
| 897 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|pc_gen:i_pc_gen|un1_pc_next46_0 ; 32 ;
|
| 898 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|q_a[5] ; 32 ;
|
| 899 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxa:i_alu_muxa|un6_a_o ; 32 ;
|
| 900 |
|
|
; mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa ; 32 ;
|
| 901 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+---------+
|
| 902 |
|
|
|
| 903 |
|
|
|
| 904 |
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 905 |
|
|
; Fitter RAM Summary ;
|
| 906 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------+
|
| 907 |
|
|
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Bits ; M4Ks ; MIF ; Location ;
|
| 908 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------+
|
| 909 |
|
|
; mem_array:ram_8k|ram2048x8_0:ram0|altsyncram:altsyncram_component|altsyncram_eht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram0.mif ; M4K_X17_Y5, M4K_X17_Y13, M4K_X17_Y14, M4K_X17_Y10 ;
|
| 910 |
|
|
; mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram1.mif ; M4K_X17_Y18, M4K_X17_Y11, M4K_X17_Y20, M4K_X17_Y7 ;
|
| 911 |
|
|
; mem_array:ram_8k|ram2048x8_2:ram2|altsyncram:altsyncram_component|altsyncram_ght1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram2.mif ; M4K_X17_Y17, M4K_X17_Y4, M4K_X17_Y15, M4K_X17_Y8 ;
|
| 912 |
|
|
; mem_array:ram_8k|ram2048x8_3:ram3|altsyncram:altsyncram_component|altsyncram_hht1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 2048 ; 8 ; 2048 ; 8 ; yes ; no ; yes ; no ; 16384 ; 16384 ; 4 ; qu2_ram3.mif ; M4K_X17_Y6, M4K_X17_Y16, M4K_X17_Y19, M4K_X17_Y12 ;
|
| 913 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_1_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 1024 ; 1 ; None ; M4K_X17_Y3 ;
|
| 914 |
|
|
; mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|altsyncram:reg_bank_I_1_Z|altsyncram_3mc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 1024 ; 1 ; None ; M4K_X17_Y9 ;
|
| 915 |
|
|
; mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 8 ; 512 ; 8 ; yes ; no ; yes ; no ; 4096 ; 4096 ; 1 ; None ; M4K_X17_Y2 ;
|
| 916 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+---------------------+------+--------------+---------------------------------------------------+
|
| 917 |
|
|
|
| 918 |
|
|
|
| 919 |
|
|
+------------------------------------------------------+
|
| 920 |
|
|
; Interconnect Usage Summary ;
|
| 921 |
|
|
+----------------------------+-------------------------+
|
| 922 |
|
|
; Interconnect Resource Type ; Usage ;
|
| 923 |
|
|
+----------------------------+-------------------------+
|
| 924 |
|
|
; C4s ; 5,731 / 16,320 ( 35 % ) ;
|
| 925 |
|
|
; Direct links ; 234 / 21,944 ( 1 % ) ;
|
| 926 |
|
|
; Global clocks ; 1 / 8 ( 12 % ) ;
|
| 927 |
|
|
; LAB clocks ; 37 / 240 ( 15 % ) ;
|
| 928 |
|
|
; LUT chains ; 562 / 5,382 ( 10 % ) ;
|
| 929 |
|
|
; Local interconnects ; 7,130 / 21,944 ( 32 % ) ;
|
| 930 |
|
|
; M4K buffers ; 136 / 720 ( 18 % ) ;
|
| 931 |
|
|
; R4s ; 5,627 / 14,640 ( 38 % ) ;
|
| 932 |
|
|
+----------------------------+-------------------------+
|
| 933 |
|
|
|
| 934 |
|
|
|
| 935 |
|
|
+----------------------------------------------------------------------------+
|
| 936 |
|
|
; LAB Logic Elements ;
|
| 937 |
|
|
+--------------------------------------------+-------------------------------+
|
| 938 |
|
|
; Number of Logic Elements (Average = 7.69) ; Number of LABs (Total = 451) ;
|
| 939 |
|
|
+--------------------------------------------+-------------------------------+
|
| 940 |
|
|
; 1 ; 8 ;
|
| 941 |
|
|
; 2 ; 13 ;
|
| 942 |
|
|
; 3 ; 45 ;
|
| 943 |
|
|
; 4 ; 17 ;
|
| 944 |
|
|
; 5 ; 21 ;
|
| 945 |
|
|
; 6 ; 25 ;
|
| 946 |
|
|
; 7 ; 32 ;
|
| 947 |
|
|
; 8 ; 36 ;
|
| 948 |
|
|
; 9 ; 76 ;
|
| 949 |
|
|
; 10 ; 178 ;
|
| 950 |
|
|
+--------------------------------------------+-------------------------------+
|
| 951 |
|
|
|
| 952 |
|
|
|
| 953 |
|
|
+--------------------------------------------------------------------+
|
| 954 |
|
|
; LAB-wide Signals ;
|
| 955 |
|
|
+------------------------------------+-------------------------------+
|
| 956 |
|
|
; LAB-wide Signals (Average = 1.14) ; Number of LABs (Total = 451) ;
|
| 957 |
|
|
+------------------------------------+-------------------------------+
|
| 958 |
|
|
; 1 Async. clear ; 1 ;
|
| 959 |
|
|
; 1 Clock ; 267 ;
|
| 960 |
|
|
; 1 Clock enable ; 142 ;
|
| 961 |
|
|
; 1 Sync. clear ; 99 ;
|
| 962 |
|
|
; 1 Sync. load ; 3 ;
|
| 963 |
|
|
; 2 Clock enables ; 4 ;
|
| 964 |
|
|
+------------------------------------+-------------------------------+
|
| 965 |
|
|
|
| 966 |
|
|
|
| 967 |
|
|
+-----------------------------------------------------------------------------+
|
| 968 |
|
|
; LAB Signals Sourced ;
|
| 969 |
|
|
+---------------------------------------------+-------------------------------+
|
| 970 |
|
|
; Number of Signals Sourced (Average = 8.33) ; Number of LABs (Total = 451) ;
|
| 971 |
|
|
+---------------------------------------------+-------------------------------+
|
| 972 |
|
|
; 0 ; 7 ;
|
| 973 |
|
|
; 1 ; 7 ;
|
| 974 |
|
|
; 2 ; 13 ;
|
| 975 |
|
|
; 3 ; 37 ;
|
| 976 |
|
|
; 4 ; 20 ;
|
| 977 |
|
|
; 5 ; 23 ;
|
| 978 |
|
|
; 6 ; 23 ;
|
| 979 |
|
|
; 7 ; 29 ;
|
| 980 |
|
|
; 8 ; 22 ;
|
| 981 |
|
|
; 9 ; 50 ;
|
| 982 |
|
|
; 10 ; 116 ;
|
| 983 |
|
|
; 11 ; 30 ;
|
| 984 |
|
|
; 12 ; 34 ;
|
| 985 |
|
|
; 13 ; 24 ;
|
| 986 |
|
|
; 14 ; 8 ;
|
| 987 |
|
|
; 15 ; 3 ;
|
| 988 |
|
|
; 16 ; 1 ;
|
| 989 |
|
|
; 17 ; 3 ;
|
| 990 |
|
|
; 18 ; 0 ;
|
| 991 |
|
|
; 19 ; 1 ;
|
| 992 |
|
|
+---------------------------------------------+-------------------------------+
|
| 993 |
|
|
|
| 994 |
|
|
|
| 995 |
|
|
+---------------------------------------------------------------------------------+
|
| 996 |
|
|
; LAB Signals Sourced Out ;
|
| 997 |
|
|
+-------------------------------------------------+-------------------------------+
|
| 998 |
|
|
; Number of Signals Sourced Out (Average = 4.17) ; Number of LABs (Total = 451) ;
|
| 999 |
|
|
+-------------------------------------------------+-------------------------------+
|
| 1000 |
|
|
; 0 ; 7 ;
|
| 1001 |
|
|
; 1 ; 45 ;
|
| 1002 |
|
|
; 2 ; 75 ;
|
| 1003 |
|
|
; 3 ; 121 ;
|
| 1004 |
|
|
; 4 ; 43 ;
|
| 1005 |
|
|
; 5 ; 50 ;
|
| 1006 |
|
|
; 6 ; 28 ;
|
| 1007 |
|
|
; 7 ; 24 ;
|
| 1008 |
|
|
; 8 ; 18 ;
|
| 1009 |
|
|
; 9 ; 8 ;
|
| 1010 |
|
|
; 10 ; 23 ;
|
| 1011 |
|
|
; 11 ; 1 ;
|
| 1012 |
|
|
; 12 ; 2 ;
|
| 1013 |
|
|
; 13 ; 3 ;
|
| 1014 |
|
|
; 14 ; 1 ;
|
| 1015 |
|
|
; 15 ; 1 ;
|
| 1016 |
|
|
; 16 ; 0 ;
|
| 1017 |
|
|
; 17 ; 1 ;
|
| 1018 |
|
|
+-------------------------------------------------+-------------------------------+
|
| 1019 |
|
|
|
| 1020 |
|
|
|
| 1021 |
|
|
+------------------------------------------------------------------------------+
|
| 1022 |
|
|
; LAB Distinct Inputs ;
|
| 1023 |
|
|
+----------------------------------------------+-------------------------------+
|
| 1024 |
|
|
; Number of Distinct Inputs (Average = 14.32) ; Number of LABs (Total = 451) ;
|
| 1025 |
|
|
+----------------------------------------------+-------------------------------+
|
| 1026 |
|
|
; 0 ; 0 ;
|
| 1027 |
|
|
; 1 ; 0 ;
|
| 1028 |
|
|
; 2 ; 4 ;
|
| 1029 |
|
|
; 3 ; 3 ;
|
| 1030 |
|
|
; 4 ; 15 ;
|
| 1031 |
|
|
; 5 ; 8 ;
|
| 1032 |
|
|
; 6 ; 16 ;
|
| 1033 |
|
|
; 7 ; 16 ;
|
| 1034 |
|
|
; 8 ; 6 ;
|
| 1035 |
|
|
; 9 ; 19 ;
|
| 1036 |
|
|
; 10 ; 26 ;
|
| 1037 |
|
|
; 11 ; 19 ;
|
| 1038 |
|
|
; 12 ; 31 ;
|
| 1039 |
|
|
; 13 ; 18 ;
|
| 1040 |
|
|
; 14 ; 25 ;
|
| 1041 |
|
|
; 15 ; 26 ;
|
| 1042 |
|
|
; 16 ; 25 ;
|
| 1043 |
|
|
; 17 ; 31 ;
|
| 1044 |
|
|
; 18 ; 30 ;
|
| 1045 |
|
|
; 19 ; 50 ;
|
| 1046 |
|
|
; 20 ; 40 ;
|
| 1047 |
|
|
; 21 ; 41 ;
|
| 1048 |
|
|
; 22 ; 1 ;
|
| 1049 |
|
|
+----------------------------------------------+-------------------------------+
|
| 1050 |
|
|
|
| 1051 |
|
|
|
| 1052 |
|
|
+-----------------+
|
| 1053 |
|
|
; Fitter Messages ;
|
| 1054 |
|
|
+-----------------+
|
| 1055 |
|
|
Info: *******************************************************************
|
| 1056 |
|
|
Info: Running Quartus II Fitter
|
| 1057 |
|
|
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
|
| 1058 |
|
|
Info: Processing started: Mon Oct 13 11:59:20 2008
|
| 1059 |
|
|
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off mips_top -c mips_top
|
| 1060 |
|
|
Info: Selected device EP1C6Q240C6 for design "mips_top"
|
| 1061 |
|
|
Info: Implementing parameter values for PLL "pll50:Ipll|altpll:altpll_component|pll"
|
| 1062 |
|
|
Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll50:Ipll|altpll:altpll_component|_clk0 port
|
| 1063 |
|
|
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
| 1064 |
|
|
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
|
| 1065 |
|
|
Info: Device EP1C12Q240C6 is compatible
|
| 1066 |
|
|
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
|
| 1067 |
|
|
Info: Performing register packing on registers with non-logic cell location assignments
|
| 1068 |
|
|
Info: Completed register packing on registers with non-logic cell location assignments
|
| 1069 |
|
|
Info: Completed User Assigned Global Signals Promotion Operation
|
| 1070 |
|
|
Info: Promoted PLL clock signals
|
| 1071 |
|
|
Info: Promoted signal "pll50:Ipll|altpll:altpll_component|_clk0" to use global clock
|
| 1072 |
|
|
Info: Completed PLL Placement Operation
|
| 1073 |
|
|
Info: Completed Auto Global Promotion Operation
|
| 1074 |
|
|
Info: Starting register packing
|
| 1075 |
|
|
Info: Started Fast Input/Output/OE register processing
|
| 1076 |
|
|
Info: Finished Fast Input/Output/OE register processing
|
| 1077 |
|
|
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
|
| 1078 |
|
|
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
|
| 1079 |
|
|
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
|
| 1080 |
|
|
Info: Finished register packing
|
| 1081 |
|
|
Warning: Following nodes are assigned to locations or regions, but do not exist in design
|
| 1082 |
|
|
Warning: Node "FLASH_ADDR[0]" is assigned to location or region, but does not exist in design
|
| 1083 |
|
|
Warning: Node "FLASH_ADDR[10]" is assigned to location or region, but does not exist in design
|
| 1084 |
|
|
Warning: Node "FLASH_ADDR[11]" is assigned to location or region, but does not exist in design
|
| 1085 |
|
|
Warning: Node "FLASH_ADDR[12]" is assigned to location or region, but does not exist in design
|
| 1086 |
|
|
Warning: Node "FLASH_ADDR[13]" is assigned to location or region, but does not exist in design
|
| 1087 |
|
|
Warning: Node "FLASH_ADDR[14]" is assigned to location or region, but does not exist in design
|
| 1088 |
|
|
Warning: Node "FLASH_ADDR[15]" is assigned to location or region, but does not exist in design
|
| 1089 |
|
|
Warning: Node "FLASH_ADDR[16]" is assigned to location or region, but does not exist in design
|
| 1090 |
|
|
Warning: Node "FLASH_ADDR[17]" is assigned to location or region, but does not exist in design
|
| 1091 |
|
|
Warning: Node "FLASH_ADDR[18]" is assigned to location or region, but does not exist in design
|
| 1092 |
|
|
Warning: Node "FLASH_ADDR[19]" is assigned to location or region, but does not exist in design
|
| 1093 |
|
|
Warning: Node "FLASH_ADDR[1]" is assigned to location or region, but does not exist in design
|
| 1094 |
|
|
Warning: Node "FLASH_ADDR[2]" is assigned to location or region, but does not exist in design
|
| 1095 |
|
|
Warning: Node "FLASH_ADDR[3]" is assigned to location or region, but does not exist in design
|
| 1096 |
|
|
Warning: Node "FLASH_ADDR[4]" is assigned to location or region, but does not exist in design
|
| 1097 |
|
|
Warning: Node "FLASH_ADDR[5]" is assigned to location or region, but does not exist in design
|
| 1098 |
|
|
Warning: Node "FLASH_ADDR[6]" is assigned to location or region, but does not exist in design
|
| 1099 |
|
|
Warning: Node "FLASH_ADDR[7]" is assigned to location or region, but does not exist in design
|
| 1100 |
|
|
Warning: Node "FLASH_ADDR[8]" is assigned to location or region, but does not exist in design
|
| 1101 |
|
|
Warning: Node "FLASH_ADDR[9]" is assigned to location or region, but does not exist in design
|
| 1102 |
|
|
Warning: Node "FLASH_BYTE" is assigned to location or region, but does not exist in design
|
| 1103 |
|
|
Warning: Node "FLASH_CE" is assigned to location or region, but does not exist in design
|
| 1104 |
|
|
Warning: Node "FLASH_DQ[0]" is assigned to location or region, but does not exist in design
|
| 1105 |
|
|
Warning: Node "FLASH_DQ[10]" is assigned to location or region, but does not exist in design
|
| 1106 |
|
|
Warning: Node "FLASH_DQ[11]" is assigned to location or region, but does not exist in design
|
| 1107 |
|
|
Warning: Node "FLASH_DQ[12]" is assigned to location or region, but does not exist in design
|
| 1108 |
|
|
Warning: Node "FLASH_DQ[13]" is assigned to location or region, but does not exist in design
|
| 1109 |
|
|
Warning: Node "FLASH_DQ[14]" is assigned to location or region, but does not exist in design
|
| 1110 |
|
|
Warning: Node "FLASH_DQ[15]" is assigned to location or region, but does not exist in design
|
| 1111 |
|
|
Warning: Node "FLASH_DQ[1]" is assigned to location or region, but does not exist in design
|
| 1112 |
|
|
Warning: Node "FLASH_DQ[2]" is assigned to location or region, but does not exist in design
|
| 1113 |
|
|
Warning: Node "FLASH_DQ[3]" is assigned to location or region, but does not exist in design
|
| 1114 |
|
|
Warning: Node "FLASH_DQ[4]" is assigned to location or region, but does not exist in design
|
| 1115 |
|
|
Warning: Node "FLASH_DQ[5]" is assigned to location or region, but does not exist in design
|
| 1116 |
|
|
Warning: Node "FLASH_DQ[6]" is assigned to location or region, but does not exist in design
|
| 1117 |
|
|
Warning: Node "FLASH_DQ[7]" is assigned to location or region, but does not exist in design
|
| 1118 |
|
|
Warning: Node "FLASH_DQ[8]" is assigned to location or region, but does not exist in design
|
| 1119 |
|
|
Warning: Node "FLASH_DQ[9]" is assigned to location or region, but does not exist in design
|
| 1120 |
|
|
Warning: Node "FLASH_OE" is assigned to location or region, but does not exist in design
|
| 1121 |
|
|
Warning: Node "FLASH_RESET" is assigned to location or region, but does not exist in design
|
| 1122 |
|
|
Warning: Node "FLASH_WE" is assigned to location or region, but does not exist in design
|
| 1123 |
|
|
Warning: Node "sd_addr[0]" is assigned to location or region, but does not exist in design
|
| 1124 |
|
|
Warning: Node "sd_addr[10]" is assigned to location or region, but does not exist in design
|
| 1125 |
|
|
Warning: Node "sd_addr[11]" is assigned to location or region, but does not exist in design
|
| 1126 |
|
|
Warning: Node "sd_addr[1]" is assigned to location or region, but does not exist in design
|
| 1127 |
|
|
Warning: Node "sd_addr[2]" is assigned to location or region, but does not exist in design
|
| 1128 |
|
|
Warning: Node "sd_addr[3]" is assigned to location or region, but does not exist in design
|
| 1129 |
|
|
Warning: Node "sd_addr[4]" is assigned to location or region, but does not exist in design
|
| 1130 |
|
|
Warning: Node "sd_addr[5]" is assigned to location or region, but does not exist in design
|
| 1131 |
|
|
Warning: Node "sd_addr[6]" is assigned to location or region, but does not exist in design
|
| 1132 |
|
|
Warning: Node "sd_addr[7]" is assigned to location or region, but does not exist in design
|
| 1133 |
|
|
Warning: Node "sd_addr[8]" is assigned to location or region, but does not exist in design
|
| 1134 |
|
|
Warning: Node "sd_addr[9]" is assigned to location or region, but does not exist in design
|
| 1135 |
|
|
Warning: Node "sd_ba[0]" is assigned to location or region, but does not exist in design
|
| 1136 |
|
|
Warning: Node "sd_ba[1]" is assigned to location or region, but does not exist in design
|
| 1137 |
|
|
Warning: Node "sd_cas" is assigned to location or region, but does not exist in design
|
| 1138 |
|
|
Warning: Node "sd_cke" is assigned to location or region, but does not exist in design
|
| 1139 |
|
|
Warning: Node "sd_clk" is assigned to location or region, but does not exist in design
|
| 1140 |
|
|
Warning: Node "sd_cs" is assigned to location or region, but does not exist in design
|
| 1141 |
|
|
Warning: Node "sd_data[0]" is assigned to location or region, but does not exist in design
|
| 1142 |
|
|
Warning: Node "sd_data[10]" is assigned to location or region, but does not exist in design
|
| 1143 |
|
|
Warning: Node "sd_data[11]" is assigned to location or region, but does not exist in design
|
| 1144 |
|
|
Warning: Node "sd_data[12]" is assigned to location or region, but does not exist in design
|
| 1145 |
|
|
Warning: Node "sd_data[13]" is assigned to location or region, but does not exist in design
|
| 1146 |
|
|
Warning: Node "sd_data[14]" is assigned to location or region, but does not exist in design
|
| 1147 |
|
|
Warning: Node "sd_data[15]" is assigned to location or region, but does not exist in design
|
| 1148 |
|
|
Warning: Node "sd_data[1]" is assigned to location or region, but does not exist in design
|
| 1149 |
|
|
Warning: Node "sd_data[2]" is assigned to location or region, but does not exist in design
|
| 1150 |
|
|
Warning: Node "sd_data[3]" is assigned to location or region, but does not exist in design
|
| 1151 |
|
|
Warning: Node "sd_data[4]" is assigned to location or region, but does not exist in design
|
| 1152 |
|
|
Warning: Node "sd_data[5]" is assigned to location or region, but does not exist in design
|
| 1153 |
|
|
Warning: Node "sd_data[6]" is assigned to location or region, but does not exist in design
|
| 1154 |
|
|
Warning: Node "sd_data[7]" is assigned to location or region, but does not exist in design
|
| 1155 |
|
|
Warning: Node "sd_data[8]" is assigned to location or region, but does not exist in design
|
| 1156 |
|
|
Warning: Node "sd_data[9]" is assigned to location or region, but does not exist in design
|
| 1157 |
|
|
Warning: Node "sd_dqm[0]" is assigned to location or region, but does not exist in design
|
| 1158 |
|
|
Warning: Node "sd_dqm[1]" is assigned to location or region, but does not exist in design
|
| 1159 |
|
|
Warning: Node "sd_ras" is assigned to location or region, but does not exist in design
|
| 1160 |
|
|
Warning: Node "sd_we" is assigned to location or region, but does not exist in design
|
| 1161 |
|
|
Warning: Node "uart_rxd_usb" is assigned to location or region, but does not exist in design
|
| 1162 |
|
|
Warning: Node "uart_txd_usb" is assigned to location or region, but does not exist in design
|
| 1163 |
|
|
Info: Fitter placement preparation operations beginning
|
| 1164 |
|
|
Info: Fitter placement preparation operations ending: elapsed time = 26 seconds
|
| 1165 |
|
|
Info: Fitter placement operations beginning
|
| 1166 |
|
|
Info: Fitter placement was successful
|
| 1167 |
|
|
Info: Estimated most critical path is register to memory delay of 16.886 ns
|
| 1168 |
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y8; Fanout = 6; REG Node = 'mips_sys:isys|mips_core:mips_core|r5_reg_1:rnd_pass1|r5_o_4'
|
| 1169 |
|
|
Info: 2: + IC(0.787 ns) + CELL(0.340 ns) = 1.127 ns; Loc. = LAB_X26_Y10; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw_a'
|
| 1170 |
|
|
Info: 3: + IC(0.463 ns) + CELL(0.088 ns) = 1.678 ns; Loc. = LAB_X26_Y10; Fanout = 5; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un14_mux_fw'
|
| 1171 |
|
|
Info: 4: + IC(1.202 ns) + CELL(0.088 ns) = 2.968 ns; Loc. = LAB_X21_Y12; Fanout = 35; COMB Node = 'mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1'
|
| 1172 |
|
|
Info: 5: + IC(0.422 ns) + CELL(0.088 ns) = 3.478 ns; Loc. = LAB_X21_Y12; Fanout = 65; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7'
|
| 1173 |
|
|
Info: 6: + IC(0.211 ns) + CELL(0.340 ns) = 4.029 ns; Loc. = LAB_X21_Y12; Fanout = 32; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|alu_muxb:i_alu_muxb|b_o_1_sqmuxa'
|
| 1174 |
|
|
Info: 7: + IC(1.037 ns) + CELL(0.340 ns) = 5.406 ns; Loc. = LAB_X21_Y5; Fanout = 2; COMB Node = 'mips_sys:isys|mips_core:mips_core|BUS15471_i_m[16]'
|
| 1175 |
|
|
Info: 8: + IC(0.422 ns) + CELL(0.088 ns) = 5.916 ns; Loc. = LAB_X21_Y5; Fanout = 27; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|muldiv_ff:muldiv_ff|b_o_iv_16'
|
| 1176 |
|
|
Info: 9: + IC(1.040 ns) + CELL(0.340 ns) = 7.296 ns; Loc. = LAB_X21_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79_a[8]'
|
| 1177 |
|
|
Info: 10: + IC(0.422 ns) + CELL(0.088 ns) = 7.806 ns; Loc. = LAB_X21_Y13; Fanout = 4; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_79[8]'
|
| 1178 |
|
|
Info: 11: + IC(0.285 ns) + CELL(0.225 ns) = 8.316 ns; Loc. = LAB_X21_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74_a[0]'
|
| 1179 |
|
|
Info: 12: + IC(0.882 ns) + CELL(0.088 ns) = 9.286 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_74[0]'
|
| 1180 |
|
|
Info: 13: + IC(0.285 ns) + CELL(0.225 ns) = 9.796 ns; Loc. = LAB_X19_Y13; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_86[0]'
|
| 1181 |
|
|
Info: 14: + IC(1.084 ns) + CELL(0.225 ns) = 11.105 ns; Loc. = LAB_X14_Y9; Fanout = 1; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_a[0]'
|
| 1182 |
|
|
Info: 15: + IC(0.422 ns) + CELL(0.088 ns) = 11.615 ns; Loc. = LAB_X14_Y9; Fanout = 2; COMB Node = 'mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_0'
|
| 1183 |
|
|
Info: 16: + IC(0.285 ns) + CELL(0.225 ns) = 12.125 ns; Loc. = LAB_X14_Y9; Fanout = 7; COMB Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|infile_dmem_ctl_reg:dmem_ctl_post|c_0_d0'
|
| 1184 |
|
|
Info: 17: + IC(0.422 ns) + CELL(0.088 ns) = 12.635 ns; Loc. = LAB_X14_Y9; Fanout = 4; COMB Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|un1_wr_en46_3_combout'
|
| 1185 |
|
|
Info: 18: + IC(0.000 ns) + CELL(2.508 ns) = 15.143 ns; Loc. = LAB_X13_Y9; Fanout = 9; COMB LOOP Node = 'mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95'
|
| 1186 |
|
|
Info: Loc. = LAB_X13_Y9; Node "mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~95"
|
| 1187 |
|
|
Info: Loc. = LAB_X13_Y9; Node "mips_sys:isys|mips_core:mips_core|mem_module:MEM_CTL|mem_addr_ctl:i_mem_addr_ctl|SYNLPM_LATRS1:wr_en_1_1_|lpm_latch:U1|q[0]~94"
|
| 1188 |
|
|
Info: 19: + IC(1.432 ns) + CELL(0.311 ns) = 16.886 ns; Loc. = M4K_X17_Y20; Fanout = 0; MEM Node = 'mem_array:ram_8k|ram2048x8_1:ram1|altsyncram:altsyncram_component|altsyncram_fht1:auto_generated|ram_block1a3~portb_we_reg'
|
| 1189 |
|
|
Info: Total cell delay = 5.783 ns ( 34.25 % )
|
| 1190 |
|
|
Info: Total interconnect delay = 11.103 ns ( 65.75 % )
|
| 1191 |
|
|
Info: Estimated interconnect usage is 39% of the available device resources
|
| 1192 |
|
|
Info: Fitter placement operations ending: elapsed time = 36 seconds
|
| 1193 |
|
|
Info: Fitter routing operations beginning
|
| 1194 |
|
|
Info: Fitter routing operations ending: elapsed time = 46 seconds
|
| 1195 |
|
|
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
| 1196 |
|
|
Info: Completed Fixed Delay Chain Operation
|
| 1197 |
|
|
Info: Started post-fitting delay annotation
|
| 1198 |
|
|
Info: Delay annotation completed successfully
|
| 1199 |
|
|
Info: Completed Auto Delay Chain Operation
|
| 1200 |
|
|
Info: Quartus II Fitter was successful. 0 errors, 82 warnings
|
| 1201 |
|
|
Info: Processing ended: Mon Oct 13 12:02:00 2008
|
| 1202 |
|
|
Info: Elapsed time: 00:02:40
|
| 1203 |
|
|
|
| 1204 |
|
|
|
