Subversion Repositories mips789

--N1_txd is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd

--operation mode is normal

N1_txd_lut_out = N1_txd_1_a & N1_txd # !N1_txd_1_a & N1_txd_8 # !sys_rst;

N1_txd = DFFEAS(N1_txd_lut_out, E1__clk0, VCC, , , , , , );

--H1_N_62_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_62_i

--operation mode is normal

H1_N_62_i = F1_seg7data[7] # F1_seg7data[6] & !F1_seg7data[4] # !F1_seg7data[5] # !F1_seg7data[6] & F1_seg7data[5];

--H1_N_60_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_60_i

--operation mode is normal

H1_N_60_i = F1_seg7data[5] & F1_seg7data[7] # !F1_seg7data[4] & F1_seg7data[6] # !F1_seg7data[5] & F1_seg7data[6] & !F1_seg7data[7] # !F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[4];

--H1_N_58_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_58_i

--operation mode is normal

H1_N_58_i = F1_seg7data[5] & F1_seg7data[7] # !F1_seg7data[4] # !F1_seg7data[5] & F1_seg7data[6] & F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[4];

--H1_m18_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18_0

--operation mode is normal

H1_m18_0 = F1_seg7data[4] & F1_seg7data[6] $ F1_seg7data[5] # !F1_seg7data[4] & F1_seg7data[6] & F1_seg7data[5] # F1_seg7data[7] # !F1_seg7data[6] & !F1_seg7data[7] # !F1_seg7data[5];

--H1_m15_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15_0

--operation mode is normal

H1_m15_0 = F1_seg7data[6] & !F1_seg7data[5] & F1_seg7data[4] # !F1_seg7data[7] # !F1_seg7data[6] & F1_seg7data[4] # F1_seg7data[7] # !F1_seg7data[5];

--H1_m11_0 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11_0

--operation mode is normal

H1_m11_0 = F1_seg7data[5] & F1_seg7data[4] & !F1_seg7data[7] # !F1_seg7data[4] & !F1_seg7data[6] # !F1_seg7data[5] & F1_seg7data[4] $ !F1_seg7data[7] # !F1_seg7data[6];

--H1_N_44_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_44_i

--operation mode is normal

H1_N_44_i = F1_seg7data[6] & F1_seg7data[7] & F1_seg7data[5] # !F1_seg7data[7] & F1_seg7data[4] # !F1_seg7data[6] & F1_seg7data[5] $ F1_seg7data[7] # !F1_seg7data[4];

--H1_N_31_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_31_i

--operation mode is normal

H1_N_31_i = F1_seg7data[3] # F1_seg7data[2] & !F1_seg7data[0] # !F1_seg7data[1] # !F1_seg7data[2] & F1_seg7data[1];

--H1_N_29_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_29_i

--operation mode is normal

H1_N_29_i = F1_seg7data[1] & F1_seg7data[3] # !F1_seg7data[0] & F1_seg7data[2] # !F1_seg7data[1] & F1_seg7data[2] & !F1_seg7data[3] # !F1_seg7data[2] & F1_seg7data[3] # !F1_seg7data[0];

--H1_N_27_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_27_i

--operation mode is normal

H1_N_27_i = F1_seg7data[1] & F1_seg7data[3] # !F1_seg7data[0] # !F1_seg7data[1] & F1_seg7data[2] & F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[0];

--H1_m18 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m18

--operation mode is normal

H1_m18 = F1_seg7data[0] & F1_seg7data[2] $ F1_seg7data[1] # !F1_seg7data[0] & F1_seg7data[2] & F1_seg7data[1] # F1_seg7data[3] # !F1_seg7data[2] & !F1_seg7data[3] # !F1_seg7data[1];

--H1_m15 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m15

--operation mode is normal

H1_m15 = F1_seg7data[2] & !F1_seg7data[1] & F1_seg7data[0] # !F1_seg7data[3] # !F1_seg7data[2] & F1_seg7data[0] # F1_seg7data[3] # !F1_seg7data[1];

--H1_m11 is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|m11

--operation mode is normal

H1_m11 = F1_seg7data[1] & F1_seg7data[0] & !F1_seg7data[3] # !F1_seg7data[0] & !F1_seg7data[2] # !F1_seg7data[1] & F1_seg7data[0] $ !F1_seg7data[3] # !F1_seg7data[2];

--H1_N_13_i is mips_sys:isys|mips_dvc:imips_dvc|seg7led_cv:iseg7_cv|N_13_i

--operation mode is normal

H1_N_13_i = F1_seg7data[2] & F1_seg7data[3] & F1_seg7data[1] # !F1_seg7data[3] & F1_seg7data[0] # !F1_seg7data[2] & F1_seg7data[1] $ F1_seg7data[3] # !F1_seg7data[0];

--F1_lcd_data_7 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_7

--operation mode is normal

F1_lcd_data_7_lut_out = CB1_r32_o_7;

F1_lcd_data_7 = DFFEAS(F1_lcd_data_7_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_6 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_6

--operation mode is normal

F1_lcd_data_6_lut_out = CB1_r32_o_6;

F1_lcd_data_6 = DFFEAS(F1_lcd_data_6_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_5 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_5

--operation mode is normal

F1_lcd_data_5_lut_out = CB1_r32_o_5;

F1_lcd_data_5 = DFFEAS(F1_lcd_data_5_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_4 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_4

--operation mode is normal

F1_lcd_data_4_lut_out = CB1_r32_o_4;

F1_lcd_data_4 = DFFEAS(F1_lcd_data_4_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_3 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_3

--operation mode is normal

F1_lcd_data_3_lut_out = CB1_r32_o_3;

F1_lcd_data_3 = DFFEAS(F1_lcd_data_3_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_2

--operation mode is normal

F1_lcd_data_2_lut_out = CB1_r32_o_2;

F1_lcd_data_2 = DFFEAS(F1_lcd_data_2_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_1 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_1

--operation mode is normal

F1_lcd_data_1_lut_out = CB1_r32_o_1;

F1_lcd_data_1 = DFFEAS(F1_lcd_data_1_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_lcd_data_0 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0

--operation mode is normal

F1_lcd_data_0_lut_out = CB1_r32_o_0;

F1_lcd_data_0 = DFFEAS(F1_lcd_data_0_lut_out, E1__clk0, VCC, , F1_lcd_data_0_sqmuxa_0_a2, , , , );

--F1_cmd_2 is mips_sys:isys|mips_dvc:imips_dvc|cmd_2

--operation mode is normal

F1_cmd_2_lut_out = CB1_r32_o_2;

F1_cmd_2 = DFFEAS(F1_cmd_2_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );

--F1_cmd_3 is mips_sys:isys|mips_dvc:imips_dvc|cmd_3

--operation mode is normal

F1_cmd_3_lut_out = CB1_r32_o_3;

F1_cmd_3 = DFFEAS(F1_cmd_3_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );

--F1_cmd_4 is mips_sys:isys|mips_dvc:imips_dvc|cmd_4

--operation mode is normal

F1_cmd_4_lut_out = CB1_r32_o_4;

F1_cmd_4 = DFFEAS(F1_cmd_4_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );

--F1_cmd_5 is mips_sys:isys|mips_dvc:imips_dvc|cmd_5

--operation mode is normal

F1_cmd_5_lut_out = CB1_r32_o_5;

F1_cmd_5 = DFFEAS(F1_cmd_5_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );

--F1_cmd_6 is mips_sys:isys|mips_dvc:imips_dvc|cmd_6

--operation mode is normal

F1_cmd_6_lut_out = CB1_r32_o_6;

F1_cmd_6 = DFFEAS(F1_cmd_6_lut_out, E1__clk0, VCC, , C1_G_602, , , !sys_rst, );

--E1__clk0 is pll50:Ipll|altpll:altpll_component|_clk0

E1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--sys_rst is sys_rst

--operation mode is normal

sys_rst_lut_out = r_rst;

sys_rst = DFFEAS(sys_rst_lut_out, E1__clk0, VCC, , , , , , );

--N1_txd_8 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_8

--operation mode is normal

N1_txd_8 = N1_ua_state[2] & N1_tx_sr[0] # !N1_ua_state[2] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state[1];

--N1_txd_1_a is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|txd_1_a

--operation mode is normal

N1_txd_1_a = N1_ua_state_i[0] & !N1_ua_state[1] & !N1_bit_ctr23_i_0_o2 # !N1_clk_ctr_equ15_0_a2;

--F1_seg7data[6] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[6]

--operation mode is normal

F1_seg7data[6]_lut_out = CB1_r32_o_6;

F1_seg7data[6] = DFFEAS(F1_seg7data[6]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[5] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[5]

--operation mode is normal

F1_seg7data[5]_lut_out = CB1_r32_o_5;

F1_seg7data[5] = DFFEAS(F1_seg7data[5]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[4] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[4]

--operation mode is normal

F1_seg7data[4]_lut_out = CB1_r32_o_4;

F1_seg7data[4] = DFFEAS(F1_seg7data[4]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[7] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[7]

--operation mode is normal

F1_seg7data[7]_lut_out = CB1_r32_o_7;

F1_seg7data[7] = DFFEAS(F1_seg7data[7]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[2] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[2]

--operation mode is normal

F1_seg7data[2]_lut_out = CB1_r32_o_2;

F1_seg7data[2] = DFFEAS(F1_seg7data[2]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[1] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[1]

--operation mode is normal

F1_seg7data[1]_lut_out = CB1_r32_o_1;

F1_seg7data[1] = DFFEAS(F1_seg7data[1]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[0] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[0]

--operation mode is normal

F1_seg7data[0]_lut_out = CB1_r32_o_0;

F1_seg7data[0] = DFFEAS(F1_seg7data[0]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--F1_seg7data[3] is mips_sys:isys|mips_dvc:imips_dvc|seg7data[3]

--operation mode is normal

F1_seg7data[3]_lut_out = CB1_r32_o_3;

F1_seg7data[3] = DFFEAS(F1_seg7data[3]_lut_out, E1__clk0, VCC, , C1_G_594, , , !sys_rst, );

--CB1_dout_2_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_7

--operation mode is normal

CB1_dout_2_7 = ND1_dout7 & FD1_wb_o_7 # !ND1_dout7 & !ND1_dout_2_a_7;

--CB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_7

--operation mode is normal

CB1_r32_o_7 = DFFEAS(CB1_dout_2_7, E1__clk0, VCC, , , , , , );

--F1_lcd_data_0_sqmuxa_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2

--operation mode is normal

F1_lcd_data_0_sqmuxa_0_a2 = !AB1_r32_o_2 & AB1_r32_o_3 & F1_lcd_data_0_sqmuxa_0_a2_a & F1_wr_cmd_0_a2_0;

--CB1_dout_2_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_6

--operation mode is normal

CB1_dout_2_6 = ND1_dout7 & FD1_wb_o_6 # !ND1_dout7 & !ND1_dout_2_a_6;

--CB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_6

--operation mode is normal

CB1_r32_o_6 = DFFEAS(CB1_dout_2_6, E1__clk0, VCC, , , , , , );

--CB1_dout_2_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_5

--operation mode is normal

CB1_dout_2_5 = ND1_dout7 & FD1_wb_o_5 # !ND1_dout7 & !ND1_dout_2_a_5;

--CB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_5

--operation mode is normal

CB1_r32_o_5 = DFFEAS(CB1_dout_2_5, E1__clk0, VCC, , , , , , );

--CB1_dout_2_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_4

--operation mode is normal

CB1_dout_2_4 = ND1_dout7 & FD1_wb_o_4 # !ND1_dout7 & !ND1_dout_2_a_4;

--CB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_4

--operation mode is normal

CB1_r32_o_4 = DFFEAS(CB1_dout_2_4, E1__clk0, VCC, , , , , , );

--CB1_dout_2_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_3

--operation mode is normal

CB1_dout_2_3 = ND1_dout7 & FD1_wb_o_3 # !ND1_dout7 & !ND1_dout_2_a_3;

--CB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_3

--operation mode is normal

CB1_r32_o_3 = DFFEAS(CB1_dout_2_3, E1__clk0, VCC, , , , , , );

--CB1_dout_2_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_2

--operation mode is normal

CB1_dout_2_2 = ND1_dout7 & FD1_wb_o_2 # !ND1_dout7 & !ND1_dout_2_a_2;

--CB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_2

--operation mode is normal

CB1_r32_o_2 = DFFEAS(CB1_dout_2_2, E1__clk0, VCC, , , , , , );

--CB1_dout_2_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_1

--operation mode is normal

CB1_dout_2_1 = ND1_dout7 & FD1_wb_o_1 # !ND1_dout7 & !ND1_dout_2_a_1;

--CB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_1

--operation mode is normal

CB1_r32_o_1 = DFFEAS(CB1_dout_2_1, E1__clk0, VCC, , , , , , );

--CB1_dout_2_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|dout_2_0

--operation mode is normal

CB1_dout_2_0 = ND1_dout7 & FD1_wb_o_0 # !ND1_dout7 & !ND1_dout_2_a_0;

--CB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_3:cop_data_reg|r32_o_0

--operation mode is normal

CB1_r32_o_0 = DFFEAS(CB1_dout_2_0, E1__clk0, VCC, , , , , , );

--C1_G_602 is mips_sys:isys|G_602

--operation mode is normal

C1_G_602 = !AB1_r32_o_3 & F1_wr_tmr_data_0_a2_0 & F1_wr_cmd_0_a2_0 # !sys_rst;

--r_rst is r_rst

--operation mode is normal

r_rst_lut_out = rst;

r_rst = DFFEAS(r_rst_lut_out, E1__clk0, VCC, , , , , , );

--N1_ua_state[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[1]

--operation mode is normal

N1_ua_state[1]_lut_out = U1_b_non_empty & N1_ua_state[1] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state_i[0] # !U1_b_non_empty & N1_ua_state[1] & !N1_clk_ctr_equ15_0_a2;

N1_ua_state[1] = DFFEAS(N1_ua_state[1]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--N1_ua_state[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[2]

--operation mode is normal

N1_ua_state[2]_lut_out = N1_clk_ctr_equ15_0_a2 & N1_ua_state[1] # N1_ua_state[2] & N1_ua_state_ns_0_a[2] # !N1_clk_ctr_equ15_0_a2 & N1_ua_state[2];

N1_ua_state[2] = DFFEAS(N1_ua_state[2]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--N1_tx_sr[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[0]

--operation mode is normal

N1_tx_sr[0]_lut_out = N1_read_request_ff & Y1_q_b[0] # !N1_read_request_ff & N1_tx_sr[1];

N1_tx_sr[0] = DFFEAS(N1_tx_sr[0]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );

--N1_clk_ctr_equ15_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2

--operation mode is normal

N1_clk_ctr_equ15_0_a2 = N1_clk_ctr26_i_0_a2 & N1_clk_ctr_equ15_0_a2_7;

--N1_ua_state_i[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_i[0]

--operation mode is normal

N1_ua_state_i[0]_lut_out = !N1_ua_state[7] & U1_b_non_empty # N1_ua_state_i[0];

N1_ua_state_i[0] = DFFEAS(N1_ua_state_i[0]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--N1_bit_ctr23_i_0_o2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|bit_ctr23_i_0_o2

--operation mode is normal

N1_bit_ctr23_i_0_o2 = N1_ua_state[3] # N1_ua_state[2];

--C1_G_594 is mips_sys:isys|G_594

--operation mode is normal

C1_G_594 = !AB1_r32_o_3 & C1_G_594_a & F1_wr_cmd_0_a2_0 # !sys_rst;

--FD1_wb_o_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_7

--operation mode is normal

FD1_wb_o_7 = TC1_wb_mux_ctl_o_0 & F1_dout_7 # DB1_r32_o_7 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_7;

--FD1_r_data_7 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_7

--operation mode is normal

FD1_r_data_7 = DFFEAS(FD1_wb_o_7, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_7

--operation mode is normal

ND1_dout_2_a_7 = XD1_mux_fw_1 & !AB1_r32_o_5 # !XD1_mux_fw_1 & !QB1_r32_o_7;

--ND1_dout7 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout7

--operation mode is normal

ND1_dout7 = MC1_wb_we_o_0 & !WD1_un30_mux_fw & !XD1_un17_mux_fw_NE & !XD1_mux_fw_1;

--AB1_c_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_2

--operation mode is normal

AB1_c_2 = MD1_c_1_4 # UD1_shift_out_4 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add4;

--AB1_r32_o_2 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_2

--operation mode is normal

AB1_r32_o_2 = DFFEAS(AB1_c_2, E1__clk0, VCC, , , , , , );

--AB1_c_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_3

--operation mode is normal

AB1_c_3 = MD1_c_2_5 # UD1_shift_out_5 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add5;

--AB1_r32_o_3 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_3

--operation mode is normal

AB1_r32_o_3 = DFFEAS(AB1_c_3, E1__clk0, VCC, , , , , , );

--F1_lcd_data_0_sqmuxa_0_a2_a is mips_sys:isys|mips_dvc:imips_dvc|lcd_data_0_sqmuxa_0_a2_a

--operation mode is normal

F1_lcd_data_0_sqmuxa_0_a2_a = sys_rst & !JC1_dmem_ctl_o_2 & AB1_r32_o_0 & !AB1_r32_o_1;

--F1_wr_cmd_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_cmd_0_a2_0

--operation mode is normal

F1_wr_cmd_0_a2_0 = JC1_dmem_ctl_o_0 & !JC1_dmem_ctl_o_1 & F1_rd_uartdata_0_a2_0;

--FD1_wb_o_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_6

--operation mode is normal

FD1_wb_o_6 = TC1_wb_mux_ctl_o_0 & F1_dout_6 # DB1_r32_o_6 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_6;

--FD1_r_data_6 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_6

--operation mode is normal

FD1_r_data_6 = DFFEAS(FD1_wb_o_6, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_6 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_6

--operation mode is normal

ND1_dout_2_a_6 = XD1_mux_fw_1 & !AB1_r32_o_4 # !XD1_mux_fw_1 & !QB1_r32_o_6;

--FD1_wb_o_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_5

--operation mode is normal

FD1_wb_o_5 = TC1_wb_mux_ctl_o_0 & F1_dout_5 # DB1_r32_o_5 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_5;

--FD1_r_data_5 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_5

--operation mode is normal

FD1_r_data_5 = DFFEAS(FD1_wb_o_5, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_5

--operation mode is normal

ND1_dout_2_a_5 = XD1_mux_fw_1 & !AB1_r32_o_3 # !XD1_mux_fw_1 & !QB1_r32_o_5;

--FD1_wb_o_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_4

--operation mode is normal

FD1_wb_o_4 = TC1_wb_mux_ctl_o_0 & F1_dout_4 # DB1_r32_o_4 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_4;

--FD1_r_data_4 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_4

--operation mode is normal

FD1_r_data_4 = DFFEAS(FD1_wb_o_4, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_4

--operation mode is normal

ND1_dout_2_a_4 = XD1_mux_fw_1 & !AB1_r32_o_2 # !XD1_mux_fw_1 & !QB1_r32_o_4;

--FD1_wb_o_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_3

--operation mode is normal

FD1_wb_o_3 = TC1_wb_mux_ctl_o_0 & F1_dout_3 # DB1_r32_o_3 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_3;

--FD1_r_data_3 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_3

--operation mode is normal

FD1_r_data_3 = DFFEAS(FD1_wb_o_3, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_3 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_3

--operation mode is normal

ND1_dout_2_a_3 = XD1_mux_fw_1 & !AB1_r32_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_3;

--FD1_wb_o_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_2

--operation mode is normal

FD1_wb_o_2 = TC1_wb_mux_ctl_o_0 & F1_dout_2 # DB1_r32_o_2 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_2;

--FD1_r_data_2 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_2

--operation mode is normal

FD1_r_data_2 = DFFEAS(FD1_wb_o_2, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_2 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_2

--operation mode is normal

ND1_dout_2_a_2 = XD1_mux_fw_1 & !AB1_r32_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_2;

--FD1_wb_o_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_1

--operation mode is normal

FD1_wb_o_1 = TC1_wb_mux_ctl_o_0 & F1_dout_1 # DB1_r32_o_1 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_1;

--FD1_r_data_1 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_1

--operation mode is normal

FD1_r_data_1 = DFFEAS(FD1_wb_o_1, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_1 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_1

--operation mode is normal

ND1_dout_2_a_1 = XD1_mux_fw_1 & !RB1_byte_addr_o_1 # !XD1_mux_fw_1 & !QB1_r32_o_1;

--FD1_wb_o_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|wb_o_0

--operation mode is normal

FD1_wb_o_0 = TC1_wb_mux_ctl_o_0 & F1_dout_0 # DB1_r32_o_0 # !TC1_wb_mux_ctl_o_0 & BB1_r32_o_0;

--FD1_r_data_0 is mips_sys:isys|mips_core:mips_core|rf_stage:iRF_stage|reg_array:reg_bank_cZ|r_data_0

--operation mode is normal

FD1_r_data_0 = DFFEAS(FD1_wb_o_0, E1__clk0, VCC, , , , , , );

--ND1_dout_2_a_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|fwd_mux_2:dmem_fw_mux|dout_2_a_0

--operation mode is normal

ND1_dout_2_a_0 = XD1_mux_fw_1 & !RB1_byte_addr_o_0 # !XD1_mux_fw_1 & !QB1_r32_o_0;

--F1_wr_tmr_data_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|wr_tmr_data_0_a2_0

--operation mode is normal

F1_wr_tmr_data_0_a2_0 = JC1_dmem_ctl_o_2 & AB1_r32_o_0 & !AB1_r32_o_1 & AB1_r32_o_2;

--U1_b_non_empty is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|a_fefifo_s7f:fifo_state|b_non_empty

--operation mode is normal

U1_b_non_empty_lut_out = F1_wr_uartdata_0_a2 # U1_b_full # U1_b_non_empty & U1L9;

U1_b_non_empty = DFFEAS(U1_b_non_empty_lut_out, E1__clk0, VCC, , , , , , );

--N1_ua_state_ns_0_a[2] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state_ns_0_a[2]

--operation mode is normal

N1_ua_state_ns_0_a[2] = !N1_bit_ctr[0] # !N1_bit_ctr[2] # !N1_bit_ctr[1];

--Y1_q_b[0] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|fifo512_cyclone:fifo|scfifo_Z1:scfifo_component|scfifo:U1|scfifo_e4u:auto_generated|a_dpfifo_lqr:dpfifo|dpram_4cm:FIFOram|altsyncram_ihc1:altsyncram1|q_b[0]

--RAM Block Operation Mode: Simple Dual-Port

--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1

--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered

Y1_q_b[0]_PORT_A_data_in = CB1_r32_o_0;

Y1_q_b[0]_PORT_A_data_in_reg = DFFE(Y1_q_b[0]_PORT_A_data_in, Y1_q_b[0]_clock_0, , , );

Y1_q_b[0]_PORT_A_address = BUS(W2_safe_q[0], W2_safe_q[1], W2_safe_q[2], W2_safe_q[3], W2_safe_q[4], W2_safe_q[5], W2_safe_q[6], W2_safe_q[7], W2_safe_q[8]);

Y1_q_b[0]_PORT_A_address_reg = DFFE(Y1_q_b[0]_PORT_A_address, Y1_q_b[0]_clock_0, , , );

Y1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8]);

Y1_q_b[0]_PORT_B_address_reg = DFFE(Y1_q_b[0]_PORT_B_address, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);

Y1_q_b[0]_PORT_A_write_enable = T1_valid_wreq;

Y1_q_b[0]_PORT_A_write_enable_reg = DFFE(Y1_q_b[0]_PORT_A_write_enable, Y1_q_b[0]_clock_0, , , );

Y1_q_b[0]_PORT_B_read_enable = VCC;

Y1_q_b[0]_PORT_B_read_enable_reg = DFFE(Y1_q_b[0]_PORT_B_read_enable, Y1_q_b[0]_clock_1, , , Y1_q_b[0]_clock_enable_1);

Y1_q_b[0]_clock_0 = E1__clk0;

Y1_q_b[0]_clock_1 = E1__clk0;

Y1_q_b[0]_clock_enable_1 = T1_valid_rreq;

Y1_q_b[0]_PORT_B_data_out = MEMORY(Y1_q_b[0]_PORT_A_data_in_reg, , Y1_q_b[0]_PORT_A_address_reg, Y1_q_b[0]_PORT_B_address_reg, Y1_q_b[0]_PORT_A_write_enable_reg, Y1_q_b[0]_PORT_B_read_enable_reg, , , Y1_q_b[0]_clock_0, Y1_q_b[0]_clock_1, , Y1_q_b[0]_clock_enable_1, , );

Y1_q_b[0] = Y1_q_b[0]_PORT_B_data_out[0];

--N1_tx_sr[1] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|tx_sr[1]

--operation mode is normal

N1_tx_sr[1]_lut_out = N1_read_request_ff & Y1_q_b[1] # !N1_read_request_ff & N1_tx_sr[2];

N1_tx_sr[1] = DFFEAS(N1_tx_sr[1]_lut_out, E1__clk0, VCC, , C1_G_586, , , !sys_rst, );

--N1_read_request_ff is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|read_request_ff

--operation mode is normal

N1_read_request_ff_lut_out = U1_b_non_empty & !N1_ua_state_i[0];

N1_read_request_ff = DFFEAS(N1_read_request_ff_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--C1_G_586 is mips_sys:isys|G_586

--operation mode is normal

C1_G_586 = N1_read_request_ff # N1_bit_ctr23_i_0_o2 & N1_clk_ctr_equ15_0_a2 # !sys_rst;

--N1_clk_ctr26_i_0_a2 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr26_i_0_a2

--operation mode is normal

N1_clk_ctr26_i_0_a2 = !N1_clk_ctr[15] & !N1_clk_ctr[6] & N1_clk_ctr[0] & N1_clk_ctr26_i_0_a2_a;

--N1_clk_ctr_equ15_0_a2_7 is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|clk_ctr_equ15_0_a2_7

--operation mode is normal

N1_clk_ctr_equ15_0_a2_7 = !N1_clk_ctr[5] & N1_clk_ctr[4] & N1_clk_ctr_equ15_0_a2_4 & N1_clk_ctr_equ15_0_a2_7_a;

--N1_ua_state[7] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[7]

--operation mode is normal

N1_ua_state[7]_lut_out = N1_ua_state[6] & N1_clk_ctr_equ15_0_a2;

N1_ua_state[7] = DFFEAS(N1_ua_state[7]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--N1_ua_state[3] is mips_sys:isys|mips_dvc:imips_dvc|uart0:iuart0|uart_write:uart_txd|ua_state[3]

--operation mode is normal

N1_ua_state[3]_lut_out = N1_ua_state[3] & !N1_clk_ctr_equ15_0_a2 # !N1_ua_state[3] & N1_ua_state[2] & !N1_ua_state_ns_0_a[2] & N1_clk_ctr_equ15_0_a2;

N1_ua_state[3] = DFFEAS(N1_ua_state[3]_lut_out, E1__clk0, VCC, , , , , !sys_rst, );

--C1_G_594_a is mips_sys:isys|G_594_a

--operation mode is normal

C1_G_594_a = !JC1_dmem_ctl_o_2 & AB1_r32_o_0 & AB1_r32_o_1 & AB1_r32_o_2;

--F1_dout_7 is mips_sys:isys|mips_dvc:imips_dvc|dout_7

--operation mode is normal

F1_dout_7_lut_out = K1_cntr_7 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[7];

F1_dout_7 = DFFEAS(F1_dout_7_lut_out, E1__clk0, VCC, , , , , , );

--DB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_7

--operation mode is normal

DB1_r32_o_7_lut_out = WB21L1;

DB1_r32_o_7 = DFFEAS(DB1_r32_o_7_lut_out, E1__clk0, VCC, , , , , , );

--BB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_7

--operation mode is normal

BB1_r32_o_7_lut_out = AB1_r32_o_5;

BB1_r32_o_7 = DFFEAS(BB1_r32_o_7_lut_out, E1__clk0, VCC, , , , , , );

--TC1_wb_mux_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_mux_ctl_reg:U18|wb_mux_ctl_o_0

--operation mode is normal

TC1_wb_mux_ctl_o_0_lut_out = WC1_wb_mux_ctl_o_0;

TC1_wb_mux_ctl_o_0 = DFFEAS(TC1_wb_mux_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );

--QB1_dout_iv_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_7

--operation mode is normal

QB1_dout_iv_7 = GD1_dout_iv_1_7 # FD1_wb_o_7 & GD1_dout7_0_a2;

--QB1_r32_o_7 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_7

--operation mode is normal

QB1_r32_o_7 = DFFEAS(QB1_dout_iv_7, E1__clk0, VCC, , , , , , );

--AB1_c_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_5

--operation mode is normal

AB1_c_5 = MD1_c_0_6 # UD1_shift_out_sn_m31_i & !MD1_c_a_7 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_6;

--AB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_5

--operation mode is normal

AB1_r32_o_5 = DFFEAS(AB1_c_5, E1__clk0, VCC, , , , , , );

--XD1_mux_fw_1 is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|mux_fw_1

--operation mode is normal

XD1_mux_fw_1 = !XD1_mux_fw_1_a & !XD1_un1_mux_fw_NE_2 & !XD1_un1_mux_fw_NE_1 & !WD1_un14_mux_fw;

--MC1_wb_we_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|wb_we_reg:U12|wb_we_o_0

--operation mode is normal

MC1_wb_we_o_0_lut_out = VC1_wb_we_o_0 # XC1_wb_we_o_0;

MC1_wb_we_o_0 = DFFEAS(MC1_wb_we_o_0_lut_out, E1__clk0, VCC, , , , , , );

--WD1_un30_mux_fw is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs:fw_alu_rs|un30_mux_fw

--operation mode is normal

WD1_un30_mux_fw = !NB1_r5_o_3 & !NB1_r5_o_0 & !NB1_r5_o_1 & WD1_un30_mux_fw_a;

--XD1_un17_mux_fw_NE is mips_sys:isys|mips_core:mips_core|forward:iforward|forward_node_fw_alu_rs_1:fw_alu_rt|un17_mux_fw_NE

--operation mode is normal

XD1_un17_mux_fw_NE = XD1_un17_mux_fw_NE_1 # XD1_un17_mux_fw_NE_a # BE1_q_4 $ NB1_r5_o_4;

--TD1_alu_out_sn_m14_0_0_a4_0 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|alu_out_sn_m14_0_0_a4_0

--operation mode is normal

TD1_alu_out_sn_m14_0_0_a4_0 = !TD1_alu_out_sn_m14_0_0_a4_0_a & !RC1_alu_func_o_4 & RC1_alu_func_o_1 # !RC1_alu_func_o_0;

--MD1_c_1_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_1_4

--operation mode is normal

MD1_c_1_4 = MD1_c_0_Z[4] # TD1_alu_out_sn_m14_0_0 & TD1_alu_out_7_0_0_m2_1;

--TD1_un1_a_add4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add4

--operation mode is arithmetic

TD1_un1_a_add4_carry_eqn = TD1_un1_a_carry_3;

TD1_un1_a_add4 = PD1_a_o_4 $ TD1_un1_b_1_combout[4] $ !TD1_un1_a_add4_carry_eqn;

--TD1_un1_a_carry_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_4

--operation mode is arithmetic

TD1_un1_a_carry_4 = CARRY(PD1_a_o_4 & TD1_un1_b_1_combout[4] # !TD1_un1_a_carry_3 # !PD1_a_o_4 & TD1_un1_b_1_combout[4] & !TD1_un1_a_carry_3);

--UD1_shift_out_4 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_4

--operation mode is normal

UD1_shift_out_4 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[4] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[4];

--MD1_c_2_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|c_2_5

--operation mode is normal

MD1_c_2_5 = MD1_c_0_Z[5] # TD1_alu_out_sn_m14_0_0 & MD1_c_2_a[5] # TD1_alu_out_7_0_0_m2_2;

--TD1_un1_a_add5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_add5

--operation mode is arithmetic

TD1_un1_a_add5_carry_eqn = TD1_un1_a_carry_4;

TD1_un1_a_add5 = PD1_a_o_5 $ TD1_un1_b_1_combout[5] $ TD1_un1_a_add5_carry_eqn;

--TD1_un1_a_carry_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|alu:mips_alu|un1_a_carry_5

--operation mode is arithmetic

TD1_un1_a_carry_5 = CARRY(PD1_a_o_5 & !TD1_un1_b_1_combout[5] & !TD1_un1_a_carry_4 # !PD1_a_o_5 & !TD1_un1_a_carry_4 # !TD1_un1_b_1_combout[5]);

--UD1_shift_out_5 is mips_sys:isys|mips_core:mips_core|exec_stage:iexec_stage|big_alu:MIPS_alu|shifter_tak:mips_shifter|shift_out_5

--operation mode is normal

UD1_shift_out_5 = UD1_shift_out_sn_m31_i & !UD1_shift_out_a[5] # !UD1_shift_out_sn_m31_i & UD1_shift_out_89[5];

--JC1_dmem_ctl_o_2 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_2

--operation mode is normal

JC1_dmem_ctl_o_2_lut_out = QC1_dmem_ctl_o_2;

JC1_dmem_ctl_o_2 = DFFEAS(JC1_dmem_ctl_o_2_lut_out, E1__clk0, VCC, , , , , , );

--AB1_c_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_0

--operation mode is normal

AB1_c_0 = MD1_c_0_1 # UD1_shift_out_sn_m31_i & !MD1_c_a_2 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_1;

--AB1_r32_o_0 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_0

--operation mode is normal

AB1_r32_o_0 = DFFEAS(AB1_c_0, E1__clk0, VCC, , , , , , );

--AB1_c_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_1

--operation mode is normal

AB1_c_1 = MD1_c_1_3 # UD1_shift_out_3 # TD1_alu_out_sn_m14_0_0_a4_0 & TD1_un1_a_add3;

--AB1_r32_o_1 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_1

--operation mode is normal

AB1_r32_o_1 = DFFEAS(AB1_c_1, E1__clk0, VCC, , , , , , );

--JC1_dmem_ctl_o_0 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_0

--operation mode is normal

JC1_dmem_ctl_o_0_lut_out = QC1_dmem_ctl_o_0;

JC1_dmem_ctl_o_0 = DFFEAS(JC1_dmem_ctl_o_0_lut_out, E1__clk0, VCC, , , , , , );

--JC1_dmem_ctl_o_1 is mips_sys:isys|mips_core:mips_core|decode_pipe:decoder_pipe|pipelinedregs:pipereg|dmem_ctl_reg:U9|dmem_ctl_o_1

--operation mode is normal

JC1_dmem_ctl_o_1_lut_out = QC1_dmem_ctl_o_1;

JC1_dmem_ctl_o_1 = DFFEAS(JC1_dmem_ctl_o_1_lut_out, E1__clk0, VCC, , , , , , );

--F1_rd_uartdata_0_a2_0 is mips_sys:isys|mips_dvc:imips_dvc|rd_uartdata_0_a2_0

--operation mode is normal

F1_rd_uartdata_0_a2_0 = F1_dout_0_0_a3_6_5_9[0] & F1_rd_status_29_0_a2_0_8 & F1_dout_0_0_a3_6_5_12[0] & F1_rd_uartdata_0_a2_0_a;

--F1_dout_6 is mips_sys:isys|mips_dvc:imips_dvc|dout_6

--operation mode is normal

F1_dout_6_lut_out = K1_cntr_6 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[6];

F1_dout_6 = DFFEAS(F1_dout_6_lut_out, E1__clk0, VCC, , , , , , );

--DB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_6

--operation mode is normal

DB1_r32_o_6_lut_out = WB11L1;

DB1_r32_o_6 = DFFEAS(DB1_r32_o_6_lut_out, E1__clk0, VCC, , , , , , );

--BB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_6

--operation mode is normal

BB1_r32_o_6_lut_out = AB1_r32_o_4;

BB1_r32_o_6 = DFFEAS(BB1_r32_o_6_lut_out, E1__clk0, VCC, , , , , , );

--QB1_dout_iv_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_6

--operation mode is normal

QB1_dout_iv_6 = GD1_dout_iv_1_6 # FD1_wb_o_6 & GD1_dout7_0_a2;

--QB1_r32_o_6 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_6

--operation mode is normal

QB1_r32_o_6 = DFFEAS(QB1_dout_iv_6, E1__clk0, VCC, , , , , , );

--AB1_c_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|c_4

--operation mode is normal

AB1_c_4 = UD1_shift_out_sn_m31_i & UD1_shift_out_92_0 # !UD1_shift_out_sn_m31_i & UD1_shift_out_89_5 # !MD1_c_a_6;

--AB1_r32_o_4 is mips_sys:isys|mips_core:mips_core|r32_reg_1:alu_pass0|r32_o_4

--operation mode is normal

AB1_r32_o_4 = DFFEAS(AB1_c_4, E1__clk0, VCC, , , , , , );

--F1_dout_5 is mips_sys:isys|mips_dvc:imips_dvc|dout_5

--operation mode is normal

F1_dout_5_lut_out = K1_cntr_5 & F1_dout_0_0_a3_4[0] # !F1_dout_0_0_a[5];

F1_dout_5 = DFFEAS(F1_dout_5_lut_out, E1__clk0, VCC, , , , , , );

--DB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_4:cop_dout_reg|r32_o_5

--operation mode is normal

DB1_r32_o_5_lut_out = WB01L1;

DB1_r32_o_5 = DFFEAS(DB1_r32_o_5_lut_out, E1__clk0, VCC, , , , , , );

--BB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_2:alu_pass1|r32_o_5

--operation mode is normal

BB1_r32_o_5_lut_out = AB1_r32_o_3;

BB1_r32_o_5 = DFFEAS(BB1_r32_o_5_lut_out, E1__clk0, VCC, , , , , , );

--QB1_dout_iv_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|dout_iv_5

--operation mode is normal

QB1_dout_iv_5 = GD1_dout_iv_1_5 # FD1_wb_o_5 & GD1_dout7_0_a2;

--QB1_r32_o_5 is mips_sys:isys|mips_core:mips_core|r32_reg_8:rt_reg|r32_o_5

--operation mode is normal

QB1_r32_o_5 = DFFEAS(QB1_dout_iv_5, E1__clk0, VCC, , , , , , );

--F1_dout_4 is mips_sys:isys|mips_dvc:imips_dvc|dout_4

--operation mode is normal