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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [RF_components.v] - Blame information for rev 53

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1 35 mcupro 
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via       *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
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`include "mips789_defs.v"
15 10 mcupro 
module ext(
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        input [31:0] ins_i ,
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        output reg [31:0] res ,
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        input [2:0]ctl
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    );
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    wire [25:0] instr25_0;
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    assign instr25_0 = ins_i[25:0] ;
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    wire[15:0] sign = {
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            instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
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            instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
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            instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
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            instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15]};
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    always @ (*)
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    case (ctl)
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        `EXT_SIGN    :res ={sign,instr25_0[15:0]};//sign
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        `EXT_UNSIGN  :res ={16'b0,instr25_0[15:0]};//zeroext
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        `EXT_J       :res ={4'b0,instr25_0[25:0],2'b0};//jmp
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        `EXT_B       :res ={sign[13:0],instr25_0[15:0],2'B0};//brach
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        `EXT_SA      :res ={27'b0,instr25_0[10:6]} ;//sll,srl
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        `EXT_S2H     :res ={instr25_0[15:0],16'B0};//shift to high
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        default: res=0;
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    endcase
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endmodule
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module compare (
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        input [31:0] s,
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        input [31:0] t,
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        input [2:0]ctl,
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        output reg res
48 35 mcupro 
    );
49 10 mcupro 
    always @ (*)
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    case  (ctl)
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        `CMP_BEQ:   res = (s==t);
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        `CMP_BNE:   res = (s!=t);
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        `CMP_BLTZ:  res = s[31];
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        `CMP_BGTZ:  res = ~s[31] && (|s[30:0]);
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        `CMP_BLEZ:  res = s[31] |(~|s);
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        `CMP_BGEZ:  res = ~s[31];
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        default res=1'B0;
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    endcase
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endmodule
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module pc_gen(
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        input [2:0]ctl,
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        output reg   [31:0]pc_next,
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        input [3:0] pc_prectl,
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        input check,
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        input [31:0]s,
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        input [31:0]pc,
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        input [31:0]zz_spc,
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        input [31:0]imm,
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        input [31:0]irq
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    );
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    wire [32:0] br_addr = pc + imm ;
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    always @ (*)
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        if(pc_prectl == `PC_IGN )
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        begin
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            case (ctl)
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                `PC_RET         :       pc_next = zz_spc ;
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                `PC_J           :       pc_next ={pc[31:28],imm[27:0]};
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                `PC_JR          :       pc_next = s;
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                `PC_BC          :       pc_next = (check)?({br_addr[31:0]}):(pc+4);
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                `PC_NEXT        :       pc_next = pc+ 4 ;
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                default                 pc_next = pc + 4;
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            endcase
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        end
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        else
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        begin
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            case (pc_prectl)
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                `PC_KEP         : pc_next=pc;
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                `PC_IRQ         : pc_next=irq;
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                `PC_RST         : pc_next='d0;
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                default           pc_next =0;
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            endcase
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        end
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endmodule
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module reg_array(
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        data,
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        wraddress,
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        rdaddress_a,
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        rdaddress_b,
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        wren,
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        clock,
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        qa,
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        qb,
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        rd_clk_cls
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    );
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    input       [31:0]  data;
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    input       [4:0]  wraddress;
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    input       [4:0]  rdaddress_a;
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    input       [4:0]  rdaddress_b;
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    reg [31:0]  r_data;
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    reg [4:0]  r_wraddress;
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    reg [4:0]  r_rdaddress_a;
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    reg [4:0]  r_rdaddress_b;
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    input rd_clk_cls;
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    input       wren;
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    reg r_wren;
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    input       clock;
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    output      [31:0]  qa;
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    output      [31:0]  qb;
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    reg [31:0]reg_bank[0:31];
130 35 mcupro 
    integer i;
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    initial
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    begin
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        for(i=0;i<32;i=i+1)
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            reg_bank[i]=0;
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    end
136 10 mcupro 
 
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    assign qa=(r_rdaddress_a==0)?0:
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           ((r_wraddress==r_rdaddress_a)&&(1==r_wren))?r_data:
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           reg_bank[r_rdaddress_a];
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    assign qb=(r_rdaddress_b==0)?0:
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           ((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data:
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           reg_bank[r_rdaddress_b];
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    always@(posedge clock)
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        if (~rd_clk_cls)
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        begin
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            r_rdaddress_a <=rdaddress_a;
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            r_rdaddress_b<=rdaddress_b;
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        end
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    always@(posedge clock)
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    begin
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        r_data <=data;
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        r_wraddress<=wraddress;
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        r_wren<=wren;
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    end
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    always@(posedge clock)
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        if (r_wren)
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            reg_bank[r_wraddress] <= r_data ;
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endmodule

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