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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [altera/] [mips_top.v] - Blame information for rev 10

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Line No. Rev Author Line
1 10 mcupro
 
2
module mips_top (
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 input clk,
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 input rst,
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 input ser_rxd,
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 output ser_txd,
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 output [6:0]seg7led1,
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 output [6:0]seg7led2,
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 output [7:0] lcd_data,
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 output lcd_rs,
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 output lcd_rw,
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 output lcd_en,
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 output led1,
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 output led2,
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 input  key1,
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 input  key2
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);
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wire [31:0] data2core;
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wire [31:0] data2mem;
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wire [31:0] ins2core;
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wire [31:0] mem_Addr;
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wire [31:0] pc;
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wire [3:0] wr_en;
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wire CLK;
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reg r_rst;
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always @(posedge CLK) if (~rst) r_rst<=1'b1; else r_rst<=1'b0;
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wire sys_rst = r_rst;
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 mips_pll Ipll(
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        .inclk0(clk),
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        .c0(CLK)
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        );
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mem_array ram_8k
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(
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        .clk(CLK),
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        .din(data2mem),
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        .dout(data2core),
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        .ins_o(ins2core),
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        .pc_i(pc),
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        .rd_addr_i(mem_Addr),
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        .wr_addr_i(mem_Addr),
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        .wren(wr_en)
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);
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 mips_sys isys
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(
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        .zz_addr_o(mem_Addr),
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        .zz_din(data2core),
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        .zz_dout(data2mem),
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        .zz_ins_i(ins2core),
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        .zz_pc_o(pc),
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        .zz_wr_en_o(wr_en),
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  .clk(CLK),
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  .rst(sys_rst),
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  .ser_rxd(ser_rxd),
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  .ser_txd(ser_txd),
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  .seg7led1(seg7led1),
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  .seg7led2(seg7led2),
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        .lcd_data(lcd_data),
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        .lcd_rs(lcd_rs),
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        .lcd_rw(lcd_rw),
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        .lcd_en(lcd_en),
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        .led1(led1),
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        .led2(led2),
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        .key1(key1),
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        .key2(key2)
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);
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endmodule
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