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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [altera/] [pll25.v] - Blame information for rev 51

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1 15 mcupro
// megafunction wizard: %ALTPLL%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altpll 
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// ============================================================
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// File Name: pll25.v
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// Megafunction Name(s):
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//                      altpll
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 4.2 Build 157 12/07/2004 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2004 Altera Corporation
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//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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//support information,  device programming or simulation file,  and any other
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//associated  documentation or information  provided by  Altera  or a partner
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//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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//other  use  of such  megafunction  design,  netlist,  support  information,
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//device programming or simulation file,  or any other  related documentation
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//or information  is prohibited  for  any  other purpose,  including, but not
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//limited to  modification,  reverse engineering,  de-compiling, or use  with
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//any other  silicon devices,  unless such use is  explicitly  licensed under
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//a separate agreement with  Altera  or a megafunction partner.  Title to the
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//intellectual property,  including patents,  copyrights,  trademarks,  trade
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//support  information,  device programming or simulation file,  or any other
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//related documentation or information provided by  Altera  or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module pll25 (
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        inclk0,
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        c0);
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        input     inclk0;
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        output    c0;
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        wire [5:0] sub_wire0;
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        wire [0:0] sub_wire4 = 1'h0;
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        wire [0:0] sub_wire1 = sub_wire0[0:0];
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        wire  c0 = sub_wire1;
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        wire  sub_wire2 = inclk0;
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        wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
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        altpll  altpll_component (
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                                .inclk (sub_wire3),
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                                .clk (sub_wire0)
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                                // synopsys translate_off
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                                ,
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                                .activeclock (),
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                                .areset (),
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                                .clkbad (),
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                                .clkena (),
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                                .clkloss (),
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                                .clkswitch (),
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                                .enable0 (),
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                                .enable1 (),
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                                .extclk (),
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                                .extclkena (),
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                                .fbin (),
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                                .locked (),
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                                .pfdena (),
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                                .pllena (),
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                                .scanaclr (),
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                                .scanclk (),
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                                .scandata (),
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                                .scandataout (),
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                                .scandone (),
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                                .scanread (),
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                                .scanwrite (),
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                                .sclkout0 (),
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                                .sclkout1 ()
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                                // synopsys translate_on
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                                );
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        defparam
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                altpll_component.clk0_duty_cycle = 50,
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                altpll_component.lpm_type = "altpll",
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                altpll_component.clk0_multiply_by = 1,
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                altpll_component.inclk0_input_frequency = 40000,
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                altpll_component.clk0_divide_by = 1,
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                altpll_component.pll_type = "AUTO",
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                altpll_component.intended_device_family = "Cyclone",
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                altpll_component.operation_mode = "NORMAL",
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                altpll_component.compensate_clock = "CLK0",
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                altpll_component.clk0_phase_shift = "0";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
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// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
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// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
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// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
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// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
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// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
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// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
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// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000"
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// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
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// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
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// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
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// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
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// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
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// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
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// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
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// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
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// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
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// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
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// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
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// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
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// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.v TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.inc FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.cmp FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25.bsf FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25_inst.v FALSE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL pll25_bb.v FALSE FALSE

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