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`include "include.h"
module ctl_FSM (
        clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
        id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
        pc_prectl, ra2exec_ctl_clr, rst    ,zz_is_nop
    );
 
    parameter
 
        ID_CUR   = 1,
        ID_LD    = 5,
        ID_MUL   = 2,
        ID_NOI   = 6,
        ID_RET   = 4,
        ONE          = 1,
        PC_IGN   = 1,
        PC_IRQ   = 4,
        PC_KEP   = 2,
        PC_RST   = 8,
        ZERO     = 0;
 
    input   clk;
    input   [2:0] id_cmd;
    input   irq;
    input   rst;
    output  iack;
    output zz_is_nop;
    output  id2ra_ctl_clr;
    output  id2ra_ctl_cls;
    output  id2ra_ins_clr;
    output  id2ra_ins_cls;
    output  [3:0] pc_prectl;
    output  ra2exec_ctl_clr;
 
    wire    clk;
    reg     iack;
    reg zz_is_nop;
    reg     id2ra_ctl_clr;
    reg     id2ra_ctl_cls;
    reg     id2ra_ins_clr;
    reg     id2ra_ins_cls;
    wire    [2:0] id_cmd;
    wire    irq;
    reg     [3:0] pc_prectl;
    reg     ra2exec_ctl_clr;
    wire    rst;
    reg riack;
 
    reg  [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
 
 
    reg [3:0] CurrState_Sreg0;
    reg [3:0] NextState_Sreg0;
 
 
    always @ (*)
    begin : Sreg0_NextState
        case (CurrState_Sreg0) // synopsys parallel_case full_case
            `IDLE:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl=PC_IGN;
                iack = riack;
                                if (~rst)
                NextState_Sreg0 = `RST;
                                else
                if ((irq)&&(~iack))
                    NextState_Sreg0 = `IRQ;
                else
                    if (id_cmd ==ID_NOI)
                        NextState_Sreg0 = `NOI;
                    else
                        if (id_cmd==ID_CUR)
                            NextState_Sreg0 = `CUR;
                        else
                            if (id_cmd==ID_MUL)
                                NextState_Sreg0 = `MUL;
                            else
                                if (id_cmd==ID_LD)
                                    NextState_Sreg0 = `LD;
                                else
                                    if (id_cmd==ID_RET)
                                        NextState_Sreg0 = `RET;
                                    else
                                        NextState_Sreg0 = `IDLE;
            end
            `MUL:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack = riack;
                                       if (~rst)
                NextState_Sreg0 = `RST;
                else
                NextState_Sreg0 = `D2_MUL_DLY;
                next_delay_counter_Sreg0 = 34;
                zz_is_nop =0;
            end
            `CUR:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ONE;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ONE;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_KEP;
                iack = riack;
                       if (~rst)
                NextState_Sreg0 = `RST;
                else
                            NextState_Sreg0 = `NOI;
                zz_is_nop = 1;
            end
            `RET:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl =PC_IGN;
                iack =ZERO;
                riack =ZERO;
                if (~rst)
                NextState_Sreg0 = `RST;
                else
                                NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `IRQ:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_IRQ;
                iack =ONE;
                riack=ONE;
                        if (~rst)
                NextState_Sreg0 = `RST;
                else
                NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `RST:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                zz_is_nop = ONE;
                riack=ZERO;
                if (~rst)
                NextState_Sreg0 = `RST;
                else
                NextState_Sreg0 = `IDLE;
 
            end
            `LD:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                                if (~rst)
                NextState_Sreg0 = `RST;
                else
                NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `NOI:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                iack=riack;
                pc_prectl=PC_IGN;
                zz_is_nop = ZERO;
                                       if (~rst)
                NextState_Sreg0 = `RST;
                else
                if (id_cmd ==ID_NOI)
                    NextState_Sreg0 = `NOI;
                else if (id_cmd==ID_CUR)
                    NextState_Sreg0 = `CUR;
                else if (id_cmd==ID_MUL)
                    NextState_Sreg0 = `MUL;
                else if (id_cmd==ID_LD)
                    NextState_Sreg0 = `LD;
                else if (id_cmd==ID_RET)
                    NextState_Sreg0 = `RET;
                else
                    NextState_Sreg0 = `IDLE;
            end
            `D2_MUL_DLY:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                zz_is_nop = ONE;
       if (~rst)
                NextState_Sreg0 = `RST;
                else
                if (delay_counter_Sreg0 == 0)
                    NextState_Sreg0 = `IDLE;
                else
                begin
                    NextState_Sreg0 = `D2_MUL_DLY;
                    if (delay_counter_Sreg0 != 0)
                        next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
                end
            end
 
            default :     //the same as RST
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                riack=ZERO;
                zz_is_nop = ONE;
       if (~rst)
                NextState_Sreg0 = `RST;
                else
                NextState_Sreg0 =`IDLE;
            end
 
        endcase
    end
 
    always @ (posedge clk/* or negedge rst*/)
    begin : Sreg0_CurrentState
        if (~rst)
            CurrState_Sreg0 <= `RST;
        else
            CurrState_Sreg0 <= NextState_Sreg0;
    end
 
    always @ (posedge clk /*or negedge rst*/)
    begin : Sreg0_RegOutput
        if (~rst)
        begin
            delay_counter_Sreg0 <= 40   ;       // Initialization in the reset state or default value required!!
        end
        else
        begin
            delay_counter_Sreg0 <= next_delay_counter_Sreg0;
        end
    end
endmodule
 

Line No.	Rev	Author	Line
1	10	mcupro	`include "include.h"
2			`module ctl_FSM (`
3			`clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,`
4			`id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,`
5			`pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop`
6			`);`
7
8			`parameter`
9
10			`ID_CUR = 1,`
11			`ID_LD = 5,`
12			`ID_MUL = 2,`
13			`ID_NOI = 6,`
14			`ID_RET = 4,`
15			`ONE = 1,`
16			`PC_IGN = 1,`
17			`PC_IRQ = 4,`
18			`PC_KEP = 2,`
19			`PC_RST = 8,`
20			`ZERO = 0;`
21
22			`input clk;`
23			`input [2:0] id_cmd;`
24			`input irq;`
25			`input rst;`
26			`output iack;`
27			`output zz_is_nop;`
28			`output id2ra_ctl_clr;`
29			`output id2ra_ctl_cls;`
30			`output id2ra_ins_clr;`
31			`output id2ra_ins_cls;`
32			`output [3:0] pc_prectl;`
33			`output ra2exec_ctl_clr;`
34
35			`wire clk;`
36			`reg iack;`
37			`reg zz_is_nop;`
38			`reg id2ra_ctl_clr;`
39			`reg id2ra_ctl_cls;`
40			`reg id2ra_ins_clr;`
41			`reg id2ra_ins_cls;`
42			`wire [2:0] id_cmd;`
43			`wire irq;`
44			`reg [3:0] pc_prectl;`
45			`reg ra2exec_ctl_clr;`
46			`wire rst;`
47			`reg riack;`
48
49			`reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;`
50
51
52			`reg [3:0] CurrState_Sreg0;`
53			`reg [3:0] NextState_Sreg0;`
54
55
56			`always @ (*)`
57			`begin : Sreg0_NextState`
58			`case (CurrState_Sreg0) // synopsys parallel_case full_case`
59			`IDLE:
60			`begin`
61			`id2ra_ins_clr=ZERO;`
62			`id2ra_ins_cls=ZERO;`
63			`id2ra_ctl_clr=ZERO;`
64			`id2ra_ctl_cls=ZERO;`
65			`ra2exec_ctl_clr =ZERO;`
66			`pc_prectl=PC_IGN;`
67	15	mcupro	`iack = riack;`
68			`if (~rst)`
69			NextState_Sreg0 = `RST;
70			`else`
71	10	mcupro	`if ((irq)&&(~iack))`
72	15	mcupro	NextState_Sreg0 = `IRQ;
73	10	mcupro	`else`
74			`if (id_cmd ==ID_NOI)`
75	15	mcupro	NextState_Sreg0 = `NOI;
76	10	mcupro	`else`
77			`if (id_cmd==ID_CUR)`
78	15	mcupro	NextState_Sreg0 = `CUR;
79	10	mcupro	`else`
80			`if (id_cmd==ID_MUL)`
81	15	mcupro	NextState_Sreg0 = `MUL;
82	10	mcupro	`else`
83			`if (id_cmd==ID_LD)`
84	15	mcupro	NextState_Sreg0 = `LD;
85	10	mcupro	`else`
86			`if (id_cmd==ID_RET)`
87	15	mcupro	NextState_Sreg0 = `RET;
88	10	mcupro	`else`
89	15	mcupro	NextState_Sreg0 = `IDLE;
90	10	mcupro	`end`
91			`MUL:
92			`begin`
93			`id2ra_ins_clr=ONE;`
94			`id2ra_ins_cls=ZERO;`
95			`id2ra_ctl_clr=ONE;`
96			`id2ra_ctl_cls=ZERO;`
97			`ra2exec_ctl_clr=ZERO;`
98			`pc_prectl =PC_KEP;`
99			`iack = riack;`
100	15	mcupro	`if (~rst)`
101			NextState_Sreg0 = `RST;
102			`else`
103			NextState_Sreg0 = `D2_MUL_DLY;
104			`next_delay_counter_Sreg0 = 34;`
105	10	mcupro	`zz_is_nop =0;`
106			`end`
107			`CUR:
108			`begin`
109			`id2ra_ins_clr=ZERO;`
110			`id2ra_ins_cls=ONE;`
111			`id2ra_ctl_clr=ZERO;`
112			`id2ra_ctl_cls=ONE;`
113			`ra2exec_ctl_clr=ONE;`
114			`pc_prectl =PC_KEP;`
115			`iack = riack;`
116	15	mcupro	`if (~rst)`
117			NextState_Sreg0 = `RST;
118			`else`
119			NextState_Sreg0 = `NOI;
120	10	mcupro	`zz_is_nop = 1;`
121			`end`
122			`RET:
123			`begin`
124			`id2ra_ins_clr=ZERO;`
125			`id2ra_ins_cls=ZERO;`
126			`id2ra_ctl_clr=ZERO;`
127			`id2ra_ctl_cls=ZERO;`
128			`ra2exec_ctl_clr =ZERO;`
129			`pc_prectl =PC_IGN;`
130			`iack =ZERO;`
131			`riack =ZERO;`
132	15	mcupro	`if (~rst)`
133			NextState_Sreg0 = `RST;
134			`else`
135			NextState_Sreg0 = `IDLE;
136	10	mcupro	`zz_is_nop = ZERO;`
137			`end`
138			`IRQ:
139			`begin`
140			`id2ra_ins_clr=ONE;`
141			`id2ra_ins_cls=ZERO;`
142			`id2ra_ctl_clr=ONE;`
143			`id2ra_ctl_cls=ZERO;`
144			`ra2exec_ctl_clr=ONE;`
145			`pc_prectl =PC_IRQ;`
146			`iack =ONE;`
147			`riack=ONE;`
148	15	mcupro	`if (~rst)`
149			NextState_Sreg0 = `RST;
150			`else`
151			NextState_Sreg0 = `IDLE;
152	10	mcupro	`zz_is_nop = ZERO;`
153			`end`
154			`RST:
155			`begin`
156			`id2ra_ins_clr=ONE;`
157			`id2ra_ins_cls=ZERO;`
158			`id2ra_ctl_clr=ONE;`
159			`id2ra_ctl_cls=ZERO;`
160			`ra2exec_ctl_clr=ONE;`
161			`pc_prectl=PC_RST;`
162	15	mcupro	`iack=ZERO;`
163			`zz_is_nop = ONE;`
164	10	mcupro	`riack=ZERO;`
165	15	mcupro	`if (~rst)`
166			NextState_Sreg0 = `RST;
167			`else`
168			NextState_Sreg0 = `IDLE;
169
170	10	mcupro	`end`
171			`LD:
172			`begin`
173			`id2ra_ins_clr=ONE;`
174			`id2ra_ins_cls=ZERO;`
175			`id2ra_ctl_clr=ONE;`
176			`id2ra_ctl_cls=ZERO;`
177			`ra2exec_ctl_clr=ZERO;`
178			`pc_prectl =PC_KEP;`
179			`iack=riack;`
180	15	mcupro	`if (~rst)`
181			NextState_Sreg0 = `RST;
182			`else`
183			NextState_Sreg0 = `IDLE;
184	10	mcupro	`zz_is_nop = ZERO;`
185			`end`
186			`NOI:
187			`begin`
188			`id2ra_ins_clr=ZERO;`
189			`id2ra_ins_cls=ZERO;`
190			`id2ra_ctl_clr=ZERO;`
191			`id2ra_ctl_cls=ZERO;`
192			`ra2exec_ctl_clr =ZERO;`
193			`iack=riack;`
194			`pc_prectl=PC_IGN;`
195			`zz_is_nop = ZERO;`
196	15	mcupro	`if (~rst)`
197			NextState_Sreg0 = `RST;
198			`else`
199	10	mcupro	`if (id_cmd ==ID_NOI)`
200	15	mcupro	NextState_Sreg0 = `NOI;
201	10	mcupro	`else if (id_cmd==ID_CUR)`
202	15	mcupro	NextState_Sreg0 = `CUR;
203	10	mcupro	`else if (id_cmd==ID_MUL)`
204	15	mcupro	NextState_Sreg0 = `MUL;
205	10	mcupro	`else if (id_cmd==ID_LD)`
206	15	mcupro	NextState_Sreg0 = `LD;
207	10	mcupro	`else if (id_cmd==ID_RET)`
208	15	mcupro	NextState_Sreg0 = `RET;
209	10	mcupro	`else`
210	15	mcupro	NextState_Sreg0 = `IDLE;
211	10	mcupro	`end`
212			`D2_MUL_DLY:
213			`begin`
214			`id2ra_ins_clr=ONE;`
215			`id2ra_ins_cls=ZERO;`
216			`id2ra_ctl_clr=ONE;`
217			`id2ra_ctl_cls=ZERO;`
218			`ra2exec_ctl_clr=ZERO;`
219			`pc_prectl =PC_KEP;`
220			`iack=riack;`
221			`zz_is_nop = ONE;`
222	15	mcupro	`if (~rst)`
223			NextState_Sreg0 = `RST;
224			`else`
225	10	mcupro	`if (delay_counter_Sreg0 == 0)`
226	15	mcupro	NextState_Sreg0 = `IDLE;
227	10	mcupro	`else`
228			`begin`
229	15	mcupro	NextState_Sreg0 = `D2_MUL_DLY;
230	10	mcupro	`if (delay_counter_Sreg0 != 0)`
231	15	mcupro	`next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;`
232	10	mcupro	`end`
233			`end`
234
235			`default : //the same as RST`
236			`begin`
237			`id2ra_ins_clr=ONE;`
238			`id2ra_ins_cls=ZERO;`
239			`id2ra_ctl_clr=ONE;`
240			`id2ra_ctl_cls=ZERO;`
241			`ra2exec_ctl_clr=ONE;`
242			`pc_prectl=PC_RST;`
243			`iack=ZERO;`
244			`riack=ZERO;`
245			`zz_is_nop = ONE;`
246	15	mcupro	`if (~rst)`
247			NextState_Sreg0 = `RST;
248			`else`
249			NextState_Sreg0 =`IDLE;
250	10	mcupro	`end`
251
252			`endcase`
253			`end`
254
255			`always @ (posedge clk/* or negedge rst*/)`
256			`begin : Sreg0_CurrentState`
257	15	mcupro	`if (~rst)`
258	10	mcupro	CurrState_Sreg0 <= `RST;
259			`else`
260			`CurrState_Sreg0 <= NextState_Sreg0;`
261			`end`
262
263			`always @ (posedge clk /or negedge rst/)`
264			`begin : Sreg0_RegOutput`
265	15	mcupro	`if (~rst)`
266	10	mcupro	`begin`
267			`delay_counter_Sreg0 <= 40 ; // Initialization in the reset state or default value required!!`
268			`end`
269			`else`
270			`begin`
271			`delay_counter_Sreg0 <= next_delay_counter_Sreg0;`
272			`end`
273	15	mcupro	`end`
274			`endmodule`
275	10	mcupro

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