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/******************************************************************
 *                                                                *
 *    Author: Liwei                                               *
 *                                                                *
 *    This file is part of the "mips789" project.                 *
 *    Downloaded from:                                            *
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
 *                                                                *
 *    If you encountered any problem, please contact me via       *
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
 *                                                                *
 ******************************************************************/
 
`include "mips789_defs.v"
module ctl_FSM (
        clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
        id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
        pc_prectl, ra2exec_ctl_clr, rst    ,zz_is_nop
    );
 
    parameter
 
        ID_CUR   = 1,
        ID_LD    = 5,
        ID_MUL   = 2,
        ID_NOI   = 6,
        ID_RET   = 4,
        ONE          = 1,
        PC_IGN   = 1,
        PC_IRQ   = 4,
        PC_KEP   = 2,
        PC_RST   = 8,
        ZERO     = 0;
 
    input   clk;
    input   [2:0] id_cmd;
    input   irq;
    input   rst;
    output  iack;
    output zz_is_nop;
    output  id2ra_ctl_clr;
    output  id2ra_ctl_cls;
    output  id2ra_ins_clr;
    output  id2ra_ins_cls;
    output  [3:0] pc_prectl;
    output  ra2exec_ctl_clr;
 
    wire    clk;
    reg     iack;
    reg zz_is_nop;
    reg     id2ra_ctl_clr;
    reg     id2ra_ctl_cls;
    reg     id2ra_ins_clr;
    reg     id2ra_ins_cls;
    wire    [2:0] id_cmd;
    wire    irq;
    reg     [3:0] pc_prectl;
    reg     ra2exec_ctl_clr;
    wire    rst;
    reg riack;
 
    reg  [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
 
    reg [3:0] CurrState_Sreg0;
    reg [3:0] NextState_Sreg0;
 
    always @ (*)
    begin : Sreg0_NextState
        case (CurrState_Sreg0)
            `IDLE:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl=PC_IGN;
                iack = riack;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    if ((irq)&&(~iack))
                        NextState_Sreg0 = `IRQ;
                    else
                        if (id_cmd ==ID_NOI)
                            NextState_Sreg0 = `NOI;
                        else
                            if (id_cmd==ID_CUR)
                                NextState_Sreg0 = `CUR;
                            else
                                if (id_cmd==ID_MUL)
                                    NextState_Sreg0 = `MUL;
                                else
                                    if (id_cmd==ID_LD)
                                        NextState_Sreg0 = `LD;
                                    else
                                        if (id_cmd==ID_RET)
                                            NextState_Sreg0 = `RET;
                                        else
                                            NextState_Sreg0 = `IDLE;
            end
            `MUL:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack = riack;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `D2_MUL_DLY;
                next_delay_counter_Sreg0 = 34;
                zz_is_nop =0;
            end
            `CUR:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ONE;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ONE;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_KEP;
                iack = riack;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `NOI;
                zz_is_nop = 1;
            end
            `RET:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl =PC_IGN;
                iack =ZERO;
                riack =ZERO;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `IRQ:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_IRQ;
                iack =ONE;
                riack=ONE;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `RST:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                zz_is_nop = ONE;
                riack=ZERO;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `IDLE;
            end
            `LD:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 = `IDLE;
                zz_is_nop = ZERO;
            end
            `NOI:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                iack=riack;
                pc_prectl=PC_IGN;
                zz_is_nop = ZERO;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    if (id_cmd ==ID_NOI)
                        NextState_Sreg0 = `NOI;
                    else if (id_cmd==ID_CUR)
                        NextState_Sreg0 = `CUR;
                    else if (id_cmd==ID_MUL)
                        NextState_Sreg0 = `MUL;
                    else if (id_cmd==ID_LD)
                        NextState_Sreg0 = `LD;
                    else if (id_cmd==ID_RET)
                        NextState_Sreg0 = `RET;
                    else
                        NextState_Sreg0 = `IDLE;
            end
            `D2_MUL_DLY:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                zz_is_nop = ONE;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    if (delay_counter_Sreg0 == 0)
                        NextState_Sreg0 = `IDLE;
                    else
                    begin
                        NextState_Sreg0 = `D2_MUL_DLY;
                      //  if (delay_counter_Sreg0 != 0)
                            next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
                    end
            end
 
            default :     //the same as RST
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                riack=ZERO;
                zz_is_nop = ONE;
                if (~rst)
                    NextState_Sreg0 = `RST;
                else
                    NextState_Sreg0 =`IDLE;
            end
 
        endcase
    end
 
    always @ (posedge clk)
    begin : Sreg0_CurrentState
        if (~rst)
            CurrState_Sreg0 <= `RST;
        else
            CurrState_Sreg0 <= NextState_Sreg0;
    end
 
    always @ (posedge clk )
    begin : Sreg0_RegOutput
        if (~rst)
        begin
            delay_counter_Sreg0 <=40;   // Initialization in the reset state or default value required!!
        end
        else
        begin
            delay_counter_Sreg0 <= next_delay_counter_Sreg0;
        end
    end
endmodule
 

Line No.	Rev	Author	Line
1	35	mcupro	`/******************************************************************`
2			`* *`
3			`* Author: Liwei *`
4			`* *`
5			`* This file is part of the "mips789" project. *`
6			`* Downloaded from: *`
7			`* http://www.opencores.org/pdownloads.cgi/list/mips789 *`
8			`* *`
9			`* If you encountered any problem, please contact me via *`
10			`* Email:mcupro@opencores.org or mcupro@163.com *`
11			`* *`
12			`******************************************************************/`
13
14			`include "mips789_defs.v"
15	10	mcupro	`module ctl_FSM (`
16			`clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,`
17			`id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,`
18			`pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop`
19			`);`
20
21			`parameter`
22
23			`ID_CUR = 1,`
24			`ID_LD = 5,`
25			`ID_MUL = 2,`
26			`ID_NOI = 6,`
27			`ID_RET = 4,`
28			`ONE = 1,`
29			`PC_IGN = 1,`
30			`PC_IRQ = 4,`
31			`PC_KEP = 2,`
32			`PC_RST = 8,`
33			`ZERO = 0;`
34
35			`input clk;`
36			`input [2:0] id_cmd;`
37			`input irq;`
38			`input rst;`
39			`output iack;`
40			`output zz_is_nop;`
41			`output id2ra_ctl_clr;`
42			`output id2ra_ctl_cls;`
43			`output id2ra_ins_clr;`
44			`output id2ra_ins_cls;`
45			`output [3:0] pc_prectl;`
46			`output ra2exec_ctl_clr;`
47
48			`wire clk;`
49			`reg iack;`
50			`reg zz_is_nop;`
51			`reg id2ra_ctl_clr;`
52			`reg id2ra_ctl_cls;`
53			`reg id2ra_ins_clr;`
54			`reg id2ra_ins_cls;`
55			`wire [2:0] id_cmd;`
56			`wire irq;`
57			`reg [3:0] pc_prectl;`
58			`reg ra2exec_ctl_clr;`
59			`wire rst;`
60			`reg riack;`
61
62			`reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;`
63
64			`reg [3:0] CurrState_Sreg0;`
65			`reg [3:0] NextState_Sreg0;`
66
67			`always @ (*)`
68			`begin : Sreg0_NextState`
69	35	mcupro	`case (CurrState_Sreg0)`
70	10	mcupro	`IDLE:
71			`begin`
72			`id2ra_ins_clr=ZERO;`
73			`id2ra_ins_cls=ZERO;`
74			`id2ra_ctl_clr=ZERO;`
75			`id2ra_ctl_cls=ZERO;`
76			`ra2exec_ctl_clr =ZERO;`
77			`pc_prectl=PC_IGN;`
78	35	mcupro	`iack = riack;`
79			`if (~rst)`
80			NextState_Sreg0 = `RST;
81	10	mcupro	`else`
82	35	mcupro	`if ((irq)&&(~iack))`
83			NextState_Sreg0 = `IRQ;
84	10	mcupro	`else`
85	35	mcupro	`if (id_cmd ==ID_NOI)`
86			NextState_Sreg0 = `NOI;
87	10	mcupro	`else`
88	35	mcupro	`if (id_cmd==ID_CUR)`
89			NextState_Sreg0 = `CUR;
90	10	mcupro	`else`
91	35	mcupro	`if (id_cmd==ID_MUL)`
92			NextState_Sreg0 = `MUL;
93	10	mcupro	`else`
94	35	mcupro	`if (id_cmd==ID_LD)`
95			NextState_Sreg0 = `LD;
96	10	mcupro	`else`
97	35	mcupro	`if (id_cmd==ID_RET)`
98			NextState_Sreg0 = `RET;
99			`else`
100			NextState_Sreg0 = `IDLE;
101	10	mcupro	`end`
102			`MUL:
103			`begin`
104			`id2ra_ins_clr=ONE;`
105			`id2ra_ins_cls=ZERO;`
106			`id2ra_ctl_clr=ONE;`
107			`id2ra_ctl_cls=ZERO;`
108			`ra2exec_ctl_clr=ZERO;`
109			`pc_prectl =PC_KEP;`
110			`iack = riack;`
111	35	mcupro	`if (~rst)`
112			NextState_Sreg0 = `RST;
113	15	mcupro	`else`
114	35	mcupro	NextState_Sreg0 = `D2_MUL_DLY;
115	15	mcupro	`next_delay_counter_Sreg0 = 34;`
116	10	mcupro	`zz_is_nop =0;`
117			`end`
118			`CUR:
119			`begin`
120			`id2ra_ins_clr=ZERO;`
121			`id2ra_ins_cls=ONE;`
122			`id2ra_ctl_clr=ZERO;`
123			`id2ra_ctl_cls=ONE;`
124			`ra2exec_ctl_clr=ONE;`
125			`pc_prectl =PC_KEP;`
126			`iack = riack;`
127	35	mcupro	`if (~rst)`
128			NextState_Sreg0 = `RST;
129	15	mcupro	`else`
130	35	mcupro	NextState_Sreg0 = `NOI;
131	10	mcupro	`zz_is_nop = 1;`
132			`end`
133			`RET:
134			`begin`
135			`id2ra_ins_clr=ZERO;`
136			`id2ra_ins_cls=ZERO;`
137			`id2ra_ctl_clr=ZERO;`
138			`id2ra_ctl_cls=ZERO;`
139			`ra2exec_ctl_clr =ZERO;`
140			`pc_prectl =PC_IGN;`
141			`iack =ZERO;`
142			`riack =ZERO;`
143	15	mcupro	`if (~rst)`
144	35	mcupro	NextState_Sreg0 = `RST;
145	15	mcupro	`else`
146	35	mcupro	NextState_Sreg0 = `IDLE;
147	10	mcupro	`zz_is_nop = ZERO;`
148			`end`
149			`IRQ:
150			`begin`
151			`id2ra_ins_clr=ONE;`
152			`id2ra_ins_cls=ZERO;`
153			`id2ra_ctl_clr=ONE;`
154			`id2ra_ctl_cls=ZERO;`
155			`ra2exec_ctl_clr=ONE;`
156			`pc_prectl =PC_IRQ;`
157			`iack =ONE;`
158			`riack=ONE;`
159	35	mcupro	`if (~rst)`
160			NextState_Sreg0 = `RST;
161	15	mcupro	`else`
162	35	mcupro	NextState_Sreg0 = `IDLE;
163	10	mcupro	`zz_is_nop = ZERO;`
164			`end`
165			`RST:
166			`begin`
167			`id2ra_ins_clr=ONE;`
168			`id2ra_ins_cls=ZERO;`
169			`id2ra_ctl_clr=ONE;`
170			`id2ra_ctl_cls=ZERO;`
171			`ra2exec_ctl_clr=ONE;`
172			`pc_prectl=PC_RST;`
173	35	mcupro	`iack=ZERO;`
174	15	mcupro	`zz_is_nop = ONE;`
175	10	mcupro	`riack=ZERO;`
176	15	mcupro	`if (~rst)`
177	35	mcupro	NextState_Sreg0 = `RST;
178	15	mcupro	`else`
179	35	mcupro	NextState_Sreg0 = `IDLE;
180	10	mcupro	`end`
181			`LD:
182			`begin`
183			`id2ra_ins_clr=ONE;`
184			`id2ra_ins_cls=ZERO;`
185			`id2ra_ctl_clr=ONE;`
186			`id2ra_ctl_cls=ZERO;`
187			`ra2exec_ctl_clr=ZERO;`
188			`pc_prectl =PC_KEP;`
189			`iack=riack;`
190	35	mcupro	`if (~rst)`
191			NextState_Sreg0 = `RST;
192	15	mcupro	`else`
193	35	mcupro	NextState_Sreg0 = `IDLE;
194	10	mcupro	`zz_is_nop = ZERO;`
195			`end`
196			`NOI:
197			`begin`
198			`id2ra_ins_clr=ZERO;`
199			`id2ra_ins_cls=ZERO;`
200			`id2ra_ctl_clr=ZERO;`
201			`id2ra_ctl_cls=ZERO;`
202			`ra2exec_ctl_clr =ZERO;`
203			`iack=riack;`
204			`pc_prectl=PC_IGN;`
205			`zz_is_nop = ZERO;`
206	35	mcupro	`if (~rst)`
207			NextState_Sreg0 = `RST;
208	15	mcupro	`else`
209	35	mcupro	`if (id_cmd ==ID_NOI)`
210			NextState_Sreg0 = `NOI;
211			`else if (id_cmd==ID_CUR)`
212			NextState_Sreg0 = `CUR;
213			`else if (id_cmd==ID_MUL)`
214			NextState_Sreg0 = `MUL;
215			`else if (id_cmd==ID_LD)`
216			NextState_Sreg0 = `LD;
217			`else if (id_cmd==ID_RET)`
218			NextState_Sreg0 = `RET;
219			`else`
220			NextState_Sreg0 = `IDLE;
221	10	mcupro	`end`
222			`D2_MUL_DLY:
223			`begin`
224			`id2ra_ins_clr=ONE;`
225			`id2ra_ins_cls=ZERO;`
226			`id2ra_ctl_clr=ONE;`
227			`id2ra_ctl_cls=ZERO;`
228			`ra2exec_ctl_clr=ZERO;`
229			`pc_prectl =PC_KEP;`
230			`iack=riack;`
231			`zz_is_nop = ONE;`
232	35	mcupro	`if (~rst)`
233			NextState_Sreg0 = `RST;
234	15	mcupro	`else`
235	35	mcupro	`if (delay_counter_Sreg0 == 0)`
236			NextState_Sreg0 = `IDLE;
237			`else`
238			`begin`
239			NextState_Sreg0 = `D2_MUL_DLY;
240			`// if (delay_counter_Sreg0 != 0)`
241			`next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;`
242			`end`
243	10	mcupro	`end`
244
245			`default : //the same as RST`
246			`begin`
247			`id2ra_ins_clr=ONE;`
248			`id2ra_ins_cls=ZERO;`
249			`id2ra_ctl_clr=ONE;`
250			`id2ra_ctl_cls=ZERO;`
251			`ra2exec_ctl_clr=ONE;`
252			`pc_prectl=PC_RST;`
253			`iack=ZERO;`
254			`riack=ZERO;`
255			`zz_is_nop = ONE;`
256	35	mcupro	`if (~rst)`
257			NextState_Sreg0 = `RST;
258	15	mcupro	`else`
259	35	mcupro	NextState_Sreg0 =`IDLE;
260	10	mcupro	`end`
261
262			`endcase`
263			`end`
264
265	35	mcupro	`always @ (posedge clk)`
266	10	mcupro	`begin : Sreg0_CurrentState`
267	15	mcupro	`if (~rst)`
268	10	mcupro	CurrState_Sreg0 <= `RST;
269			`else`
270			`CurrState_Sreg0 <= NextState_Sreg0;`
271			`end`
272
273	35	mcupro	`always @ (posedge clk )`
274	10	mcupro	`begin : Sreg0_RegOutput`
275	15	mcupro	`if (~rst)`
276	10	mcupro	`begin`
277	35	mcupro	`delay_counter_Sreg0 <=40; // Initialization in the reset state or default value required!!`
278	10	mcupro	`end`
279			`else`
280			`begin`
281			`delay_counter_Sreg0 <= next_delay_counter_Sreg0;`
282			`end`
283	35	mcupro	`end`
284	15	mcupro	`endmodule`
285	10	mcupro

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