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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [dvc.v] - Blame information for rev 55

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1 35 mcupro 
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via       *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
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14 35 mcupro 
`include "mips789_defs.v"
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module tmr0 (
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        input clk,
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        input clr,
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        input[31:0] din ,
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        input ld,
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        input tmr_en,
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        output tmr_req,
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        output [31:0] cntr_o
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    );
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    reg [31:0]s_cntr;
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    reg [31:0]cntr;
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    assign cntr_o=cntr;
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    always @(posedge clk)
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        if (ld)
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            s_cntr<= din;
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    always @(posedge clk)
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        if (ld)
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            cntr<=din;
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        else if (cntr==0)
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            cntr<=s_cntr;
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        else if (tmr_en)
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            cntr<=cntr-1;
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    wire w_irq = cntr==0;
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    tmr_d itmr_d(
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              .clr(clr),
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              .clk(clk),
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              .d(w_irq),
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              .q(tmr_req)
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          );
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endmodule
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module tmr_d(input clr,input clk,input d,output reg q );
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    always @(posedge clk)
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        if      (clr) q<=0;
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        else          q<=d|q;
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endmodule
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module seg7led_cv(
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        input [7:0] data,
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        output reg [6:0] seg7led2,
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        output reg [6:0] seg7led1
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    );
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    always @(*)
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    begin
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        seg7led2= seg(data[3:0]) ;
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        seg7led1= seg(data[7:4]) ;
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    end
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    function [7:0] seg;
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        input [3:0] addr;
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        begin
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            case(addr)
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                0: seg = 7'b0111111;
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                1: seg = 7'b0000110;
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                2: seg = 7'b1011011;
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                3: seg = 7'b1001111;
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                4: seg = 7'b1100110;
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                5: seg = 7'b1101101;
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                6: seg = 7'b1111100;
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                7: seg = 7'b0000111;
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                8: seg = 7'b1111111;
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                9: seg = 7'b1100111;
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                10: seg = 7'b1110111;
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                11: seg = 7'b1111100;
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                12: seg = 7'b1011000;
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                13: seg = 7'b1011110;
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                14: seg = 7'b1111001;
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                15: seg = 7'b1110001;
96 35 mcupro 
                                default  seg = 7'bx;
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            endcase
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        end
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    endfunction
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endmodule

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