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/******************************************************************
 *                                                                *
 *    Author: Liwei                                               *
 *                                                                *
 *    This file is part of the "mips789" project.                 *
 *    Downloaded from:                                            *
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
 *                                                                *
 *    If you encountered any problem, please contact me via       *
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
 *                                                                *
 ******************************************************************/
 
`ifndef INCLUDE_H
`define INCLUDE_H
 
 `define   FRQ                    50000000
 `define   SER_RATE               19200
 
 `define   FW_ALU                 3'b001
 `define   FW_MEM                 3'b010
 `define   FW_NOP                 3'b100
 
 `define   ALU_MFHI               6
 `define   ALU_MFLO               7
 `define   ALU_MULTTU             8
 `define   ALU_MULT               9
 `define   ALU_DIVU               10
 `define   ALU_DIV                11
 
 
 `define   DMEM_SB                1
 `define   DMEM_LBS               2
 `define   DMEM_LB                3
 `define   DMEM_LBU               4
 `define   DMEM_SW                5
 `define   DMEM_LW                6
 `define   DMEM_SH                7
 `define   DMEM_LHS               8
 `define   DMEM_LH                9
 `define   DMEM_LHU               10
 `define   DMEM_NOP               0
 
 `define   ALU_SRL                1
 `define   ALU_SLL                2
 `define   ALU_SRA                4
 
 `define   WB_ALU                 0
 `define   WB_MEM                 1
 `define   WB_NOP                 0
 
 `define   RD_RD                  1
 `define   RD_RT                  2
 `define   RD_R31                 3
 `define   RD_NOP                 0
 `define   RD_ZR                  0
 
 `define   EXT_CTL_LEN            3
 `define   RD_SEL_LEN             2
 `define   CMP_CTL_LEN            3
 `define   PC_GEN_CTL_LEN         3
 `define   FSM_CTL_LEN            3
 `define   MUXA_CTL_LEN           2
 `define   MUXB_CTL_LEN           2
 `define   ALU_FUNC_LEN           5
 `define   ALU_WE_LEN             1
 `define   DMEM_CTL_LEN           4
 `define   WB_MUX_CTL_LEN         1
 `define   WB_WE_LEN              1
 `define   INS_LEN                32
 `define   PC_LEN                 32
 `define   SPC_LEN                32
 `define   R32_LEN                32
 `define   R5_LEN                 5
 `define   R1_LEN                 1
 `define   R2_LEN                 2
 `define   R3_LEN                 3
 `define   R4_LEN                 4
 
 `define   ALU_ADD                12
 `define   ALU_ADDU               13
 `define   ALU_SUB                14
 `define   ALU_SUBU               15
 `define   ALU_SLTU               16
 `define   ALU_SLT                17
 `define   ALU_OR                 18
 `define   ALU_AND                19
 `define   ALU_XOR                20
 `define   ALU_NOR                21
 `define   ALU_PA                 22
 `define   ALU_PB                 23
 
 `define   D2_MUL_DLY             4'b0000
 `define   IDLE                   4'b0001
 `define   MUL                    4'b0010
 `define   CUR                    4'b0011
 `define   RET                    4'b0100
 `define   IRQ                    4'b0101
 `define   RST                    4'b0110
 `define   LD                     4'b0111
 `define   NOI                    4'b1000
 
 
 `define   ALU_NOP                0
 `define   ALU_MTLO               30
 `define   ALU_MTHI               31
 `define   ALU_MULTU              8
 `define   PC_IGN                 1
 `define   PC_KEP                 2
 `define   PC_IRQ                 4
 `define   PC_RST                 8
 `define   PC_J                   1
 `define   PC_JR                  2
 `define   PC_BC                  4
 `define   PC_NEXT                5
 `define   PC_NOP                 0
 `define   PC_RET                 6
 `define   PC_SPC                 6
 `define   RF                     13
 `define   EXEC                   10
 `define   DMEM                   4
 `define   WB                     2
 `define   MUXA_PC                1
 `define   MUXA_RS                2
 `define   MUXA_EXT               3
 `define   MUXA_SPC               0
 `define   MUXA_NOP               0
 `define   MUXB_RT                1
 `define   MUXB_EXT               2
 `define   MUXB_NOP               0
 
 `define   CMP_BEQ                1
 `define   CMP_BNE                2
 `define   CMP_BLEZ               3
 `define   CMP_BGEZ               4
 `define   CMP_BGTZ               5
 `define   CMP_BLTZ               6
 `define   CMP_NOP                0
 
 `define   FSM_CUR                1
 `define   FSM_MUL                2
 `define   FSM_RET                4
 `define   FSM_NOP                0
 `define   FSM_LD                 5
 `define   FSM_NOI                6
 
 `define   REG_NOP                0
 `define   REG_CLR                1
 `define   REG_KEP                2
 
 `define   EXT_SIGN               1
 `define   EXT_UNSIGN             2
 `define   EXT_J                  3
 `define   EXT_B                  4
 `define   EXT_SA                 5
 `define   EXT_S2H                6
 `define   EXT_NOP                0
 
 `define   EN                     1
 `define   DIS                    0
 `define   IGN                    0
 
 `define   UART_DATA_ADDR         'H80_00_00_28
 `define   CMD_ADDR               'H80_00_00_14
 `define   STATUS_ADDR            'H80_00_00_18
 `define   SEG7LED_ADDR           'H80_00_00_1C
 `define   SIM_DIS_ADDR           'H80_00_00_20
 `define   LCD_DATA_ADDR          'H80_00_00_24
 `define   IRQ_MASK_ADDR          'H80_00_00_34
 `define   TMR_IRQ_ADDR           'H80_00_00_28
 `define   TMR_DATA_ADDR          'H80_00_00_34
 `define   KEY1_IRQ_ADDR          'H80_00_00_2C
 `define   KEY2_IRQ_ADDR          'H80_00_00_30
 
 `define   COUNTER_VALUE1         (`FRQ/`SER_RATE/2-1)
 `define   COUNTER_VALUE2         (`COUNTER_VALUE1*2+1)
 `define   COUNTER_VALUE3         (`COUNTER_VALUE1+3)
 
   `define ALTERA
 
`else
 
 
`endif

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Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [mips789_defs.v] - Blame information for rev 60

Line No.	Rev	Author	Line
1	31	mcupro	`/******************************************************************`
2			`* *`
3			`* Author: Liwei *`
4			`* *`
5			`* This file is part of the "mips789" project. *`
6			`* Downloaded from: *`
7			`* http://www.opencores.org/pdownloads.cgi/list/mips789 *`
8			`* *`
9			`* If you encountered any problem, please contact me via *`
10			`* Email:mcupro@opencores.org or mcupro@163.com *`
11			`* *`
12			`******************************************************************/`
13
14			`ifndef INCLUDE_H
15			`define INCLUDE_H
16
17			`define FRQ 50000000
18			`define SER_RATE 19200
19
20			`define FW_ALU 3'b001
21			`define FW_MEM 3'b010
22			`define FW_NOP 3'b100
23
24			`define ALU_MFHI 6
25			`define ALU_MFLO 7
26			`define ALU_MULTTU 8
27			`define ALU_MULT 9
28			`define ALU_DIVU 10
29			`define ALU_DIV 11
30
31
32			`define DMEM_SB 1
33			`define DMEM_LBS 2
34			`define DMEM_LB 3
35			`define DMEM_LBU 4
36			`define DMEM_SW 5
37			`define DMEM_LW 6
38			`define DMEM_SH 7
39			`define DMEM_LHS 8
40			`define DMEM_LH 9
41			`define DMEM_LHU 10
42			`define DMEM_NOP 0
43
44			`define ALU_SRL 1
45			`define ALU_SLL 2
46			`define ALU_SRA 4
47
48			`define WB_ALU 0
49			`define WB_MEM 1
50			`define WB_NOP 0
51
52			`define RD_RD 1
53			`define RD_RT 2
54			`define RD_R31 3
55			`define RD_NOP 0
56			`define RD_ZR 0
57
58			`define EXT_CTL_LEN 3
59			`define RD_SEL_LEN 2
60			`define CMP_CTL_LEN 3
61			`define PC_GEN_CTL_LEN 3
62			`define FSM_CTL_LEN 3
63			`define MUXA_CTL_LEN 2
64			`define MUXB_CTL_LEN 2
65			`define ALU_FUNC_LEN 5
66			`define ALU_WE_LEN 1
67			`define DMEM_CTL_LEN 4
68			`define WB_MUX_CTL_LEN 1
69			`define WB_WE_LEN 1
70			`define INS_LEN 32
71			`define PC_LEN 32
72			`define SPC_LEN 32
73			`define R32_LEN 32
74			`define R5_LEN 5
75			`define R1_LEN 1
76			`define R2_LEN 2
77			`define R3_LEN 3
78			`define R4_LEN 4
79
80			`define ALU_ADD 12
81			`define ALU_ADDU 13
82			`define ALU_SUB 14
83			`define ALU_SUBU 15
84			`define ALU_SLTU 16
85			`define ALU_SLT 17
86			`define ALU_OR 18
87			`define ALU_AND 19
88			`define ALU_XOR 20
89			`define ALU_NOR 21
90			`define ALU_PA 22
91			`define ALU_PB 23
92
93			`define D2_MUL_DLY 4'b0000
94			`define IDLE 4'b0001
95			`define MUL 4'b0010
96			`define CUR 4'b0011
97			`define RET 4'b0100
98			`define IRQ 4'b0101
99			`define RST 4'b0110
100			`define LD 4'b0111
101			`define NOI 4'b1000
102
103
104			`define ALU_NOP 0
105			`define ALU_MTLO 30
106			`define ALU_MTHI 31
107			`define ALU_MULTU 8
108			`define PC_IGN 1
109			`define PC_KEP 2
110			`define PC_IRQ 4
111			`define PC_RST 8
112			`define PC_J 1
113			`define PC_JR 2
114			`define PC_BC 4
115			`define PC_NEXT 5
116			`define PC_NOP 0
117			`define PC_RET 6
118			`define PC_SPC 6
119			`define RF 13
120			`define EXEC 10
121			`define DMEM 4
122			`define WB 2
123			`define MUXA_PC 1
124			`define MUXA_RS 2
125			`define MUXA_EXT 3
126			`define MUXA_SPC 0
127			`define MUXA_NOP 0
128			`define MUXB_RT 1
129			`define MUXB_EXT 2
130			`define MUXB_NOP 0
131
132			`define CMP_BEQ 1
133			`define CMP_BNE 2
134			`define CMP_BLEZ 3
135			`define CMP_BGEZ 4
136			`define CMP_BGTZ 5
137			`define CMP_BLTZ 6
138			`define CMP_NOP 0
139
140			`define FSM_CUR 1
141			`define FSM_MUL 2
142			`define FSM_RET 4
143			`define FSM_NOP 0
144			`define FSM_LD 5
145			`define FSM_NOI 6
146
147			`define REG_NOP 0
148			`define REG_CLR 1
149			`define REG_KEP 2
150
151			`define EXT_SIGN 1
152			`define EXT_UNSIGN 2
153			`define EXT_J 3
154			`define EXT_B 4
155			`define EXT_SA 5
156			`define EXT_S2H 6
157			`define EXT_NOP 0
158
159			`define EN 1
160			`define DIS 0
161			`define IGN 0
162
163			`define UART_DATA_ADDR 'H80_00_00_28
164			`define CMD_ADDR 'H80_00_00_14
165			`define STATUS_ADDR 'H80_00_00_18
166			`define SEG7LED_ADDR 'H80_00_00_1C
167			`define SIM_DIS_ADDR 'H80_00_00_20
168			`define LCD_DATA_ADDR 'H80_00_00_24
169			`define IRQ_MASK_ADDR 'H80_00_00_34
170			`define TMR_IRQ_ADDR 'H80_00_00_28
171			`define TMR_DATA_ADDR 'H80_00_00_34
172			`define KEY1_IRQ_ADDR 'H80_00_00_2C
173			`define KEY2_IRQ_ADDR 'H80_00_00_30
174
175			`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1)
176			`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
177			`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
178
179			`define ALTERA
180
181			`else
182
183
184			`endif