OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [mips_core.v] - Blame information for rev 60

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 35 mcupro
/******************************************************************
2
 *                                                                *
3
 *    Author: Liwei                                               *
4
 *                                                                *
5
 *    This file is part of the "mips789" project.                 *
6
 *    Downloaded from:                                            *
7
 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
8
 *                                                                *
9
 *    If you encountered any problem, please contact me via       *
10
 *    Email:mcupro@opencores.org  or mcupro@163.com               *
11
 *                                                                *
12
 ******************************************************************/
13 10 mcupro
 
14 35 mcupro
`include "mips789_defs.v"
15
 
16 10 mcupro
module mips_core (
17
        clk,irq_i,rst,cop_dout,irq_addr,
18
        zz_din,zz_ins_i,iack_o,cop_addr_o,
19
        cop_data_o,cop_mem_ctl_o,zz_addr_o,
20
        zz_dout,zz_pc_o,zz_wr_en_o
21
    );
22
 
23
    input clk;
24
    wire clk;
25
    input irq_i;
26
    wire irq_i;
27
    input rst;
28
    wire rst;
29
    input [31:0] cop_dout;
30
    wire [31:0] cop_dout;
31
    input [31:0] irq_addr;
32
    wire [31:0] irq_addr;
33
    input [31:0] zz_din;
34
    wire [31:0] zz_din;
35
    input [31:0] zz_ins_i;
36
    wire [31:0] zz_ins_i;
37
    output [31:0] zz_addr_o;
38
    wire [31:0] zz_addr_o;
39
    output [31:0] zz_dout;
40
    wire [31:0] zz_dout;
41
    output [31:0] zz_pc_o;
42
    wire [31:0] zz_pc_o;
43
    output [3:0] zz_wr_en_o;
44
    wire [3:0] zz_wr_en_o;
45
    output iack_o;
46
    wire iack_o;
47
    output [31:0] cop_addr_o;
48
    wire [31:0] cop_addr_o;
49
    output [31:0] cop_data_o;
50
    wire [31:0] cop_data_o;
51
    output [3:0] cop_mem_ctl_o;
52
    wire [3:0] cop_mem_ctl_o;
53
 
54
 
55
    wire NET1375;
56
    wire NET1572;
57
    wire NET1606;
58
    wire NET1640;
59
    wire NET21531;
60
    wire NET457;
61
    wire NET767;
62
    wire [2:0] BUS109;
63
    wire [2:0] BUS1158;
64
    wire [2:0] BUS117;
65
    wire [2:0] BUS1196;
66
    wire [31:0] BUS15471;
67
    wire [4:0] BUS1724;
68
    wire [4:0] BUS1726;
69
    wire [4:0] BUS18211;
70
    wire [2:0] BUS197;
71
    wire [2:0] BUS2140;
72
    wire [2:0] BUS2156;
73
    wire [31:0] BUS22401;
74
    wire [31:0] BUS24839;
75
    wire [31:0] BUS27031;
76
    wire [2:0] BUS271;
77
    wire [31:0] BUS28013;
78
    wire [1:0] BUS371;
79
    wire [31:0] BUS422;
80
    wire [1:0] BUS5832;
81
    wire [1:0] BUS5840;
82
    wire [3:0] BUS5985;
83
    wire [2:0] BUS5993;
84
    wire [4:0] BUS6275;
85
    wire [31:0] BUS7101;
86
    wire [31:0] BUS7117;
87
    wire [31:0] BUS7160;
88
    wire [31:0] BUS7219;
89
    wire [31:0] BUS7231;
90
    wire [4:0] BUS748;
91
    wire [4:0] BUS756;
92
    wire [4:0] BUS775;
93
    wire [31:0] BUS7772;
94
    wire [31:0] BUS7780;
95
    wire [31:0] BUS9589;
96
    wire [31:0] BUS9884;
97
 
98
 
99
    mem_module MEM_CTL
100
               (
101
                   .Zz_addr(zz_addr_o),
102
                   .Zz_dout(zz_dout),
103
                   .Zz_wr_en(zz_wr_en_o),
104
                   .clk(clk),
105
                   .din(BUS9884),
106
                   .dmem_addr_i(BUS9589),
107
                   .dmem_ctl(BUS5985),
108
                   .dout(BUS22401),
109
                   .zZ_din(zz_din)
110
               );
111
 
112
    assign NET21531 = NET1572 | iack_o;
113
 
114
    rf_stage iRF_stage
115
             (
116
                 .clk(clk),
117
                 .cmp_ctl_i(BUS109),
118
                 .ext_ctl_i(BUS117),
119
                 .ext_o(BUS7219),
120
                 .fw_alu_i(cop_addr_o),
121
                 .fw_cmp_rs(BUS2140),
122
                 .fw_cmp_rt(BUS2156),
123
                 .fw_mem_i(BUS15471),
124
                 .iack_o(iack_o),
125
                 .id2ra_ctl_clr_o(NET1606),
126
                 .id2ra_ctl_cls_o(NET1572),
127
                 .id_cmd(BUS197),
128
                 .ins_i(zz_ins_i),
129
                 .irq_addr_i(irq_addr),
130
                 .irq_i(irq_i),
131
                 .pc_gen_ctl(BUS271),
132
                 .pc_i(BUS27031),
133
                 .pc_next(zz_pc_o),
134
                 .ra2ex_ctl_clr_o(NET1640),
135
                 .rd_index_o(BUS775),
136
                 .rd_sel_i(BUS371),
137
                 .rs_n_o(BUS748),
138
                 .rs_o(BUS24839),
139
                 .rst_i(rst),
140
                 .rt_n_o(BUS756),
141
                 .rt_o(BUS7160),
142
                 .wb_addr_i(BUS18211),
143
                 .wb_din_i(BUS15471),
144
                 .wb_we_i(NET1375),
145
                 .zz_spc_i(BUS28013)
146
             );
147
 
148
 
149
 
150
    exec_stage iexec_stage
151
               (
152
                   .alu_func(BUS6275),
153
                   .alu_ur_o(BUS9589),
154
                   .clk(clk),
155
                   .dmem_data_ur_o(BUS9884),
156
                   .dmem_fw_ctl(BUS5993),
157
                   .ext_i(BUS7231),
158
                   .fw_alu(cop_addr_o),
159
                   .fw_dmem(BUS15471),
160
                   .muxa_ctl_i(BUS5832),
161
                   .muxa_fw_ctl(BUS1158),
162
                   .muxb_ctl_i(BUS5840),
163
                   .muxb_fw_ctl(BUS1196),
164
                   .pc_i(BUS27031),
165
                   .rs_i(BUS7101),
166
                   .rst(rst),
167
                   .rt_i(BUS7117),
168
                   .spc_cls_i(NET21531),
169
                   .zz_spc_o(BUS28013)
170
               );
171
 
172
 
173
 
174
    r32_reg alu_pass0
175
            (
176
                .clk(clk),
177
                .r32_i(BUS9589),
178
                .r32_o(cop_addr_o)
179
            );
180
 
181
 
182
 
183
    r32_reg alu_pass1
184
            (
185
                .clk(clk),
186
                .r32_i(cop_addr_o),
187
                .r32_o(BUS422)
188
            );
189
 
190
 
191
 
192
    or32 cop_data_or
193
         (
194
             .a(cop_dout),
195
             .b(BUS7772),
196
             .c(BUS7780)
197
         );
198
 
199
 
200
 
201
    r32_reg cop_data_reg
202
            (
203
                .clk(clk),
204
                .r32_i(BUS9884),
205
                .r32_o(cop_data_o)
206
            );
207
 
208
 
209
 
210
    r32_reg cop_dout_reg
211
            (
212
                .clk(clk),
213
                .r32_i(BUS22401),
214
                .r32_o(BUS7772)
215
            );
216
 
217
 
218
 
219
    decode_pipe decoder_pipe
220
                (
221
                    .alu_func_o(BUS6275),
222
                    .alu_we_o(NET767),
223
                    .clk(clk),
224
                    .cmp_ctl_o(BUS109),
225
                    .dmem_ctl_o(cop_mem_ctl_o),
226
                    .dmem_ctl_ur_o(BUS5985),
227
                    .ext_ctl_o(BUS117),
228
                    .fsm_dly(BUS197),
229
                    .id2ra_ctl_clr(NET1606),
230
                    .id2ra_ctl_cls(NET1572),
231
                    .ins_i(zz_ins_i),
232
                    .muxa_ctl_o(BUS5832),
233
                    .muxb_ctl_o(BUS5840),
234
                    .pc_gen_ctl_o(BUS271),
235
                    .ra2ex_ctl_clr(NET1640),
236
                    .rd_sel_o(BUS371),
237
                    .wb_mux_ctl_o(NET457),
238
                    .wb_we_o(NET1375)
239
                );
240
 
241
 
242
 
243
    r32_reg ext_reg
244
            (
245
                .clk(clk),
246
                .r32_i(BUS7219),
247
                .r32_o(BUS7231)
248
            );
249
 
250
 
251
 
252
    forward iforward
253
            (
254
                .alu_rs_fw(BUS1158),
255
                .alu_rt_fw(BUS1196),
256
                .alu_we(NET767),
257
                .clk(clk),
258
                .cmp_rs_fw(BUS2140),
259
                .cmp_rt_fw(BUS2156),
260
                .dmem_fw(BUS5993),
261
                .fw_alu_rn(BUS1724),
262
                .fw_mem_rn(BUS18211),
263
                .mem_We(NET1375),
264
                .rns_i(BUS748),
265
                .rnt_i(BUS756)
266
            );
267
 
268
 
269
 
270
    r32_reg pc
271
            (
272
                .clk(clk),
273
                .r32_i(zz_pc_o),
274
                .r32_o(BUS27031)
275
            );
276
 
277
 
278
 
279
    r5_reg rnd_pass0
280
           (
281
               .clk(clk),
282
               .r5_i(BUS775),
283
               .r5_o(BUS1726)
284
           );
285
 
286
 
287
 
288
    r5_reg rnd_pass1
289
           (
290
               .clk(clk),
291
               .r5_i(BUS1726),
292
               .r5_o(BUS1724)
293
           );
294
 
295
 
296
 
297
    r5_reg rnd_pass2
298
           (
299
               .clk(clk),
300
               .r5_i(BUS1724),
301
               .r5_o(BUS18211)
302
           );
303
 
304
 
305
 
306
    r32_reg rs_reg
307
            (
308
                .clk(clk),
309
                .r32_i(BUS24839),
310
                .r32_o(BUS7101)
311
            );
312
 
313
 
314
 
315
    r32_reg rt_reg
316
            (
317
                .clk(clk),
318
                .r32_i(BUS7160),
319
                .r32_o(BUS7117)
320
            );
321
 
322
 
323
 
324
    wb_mux wb_mux
325
           (
326
               .alu_i(BUS422),
327
               .dmem_i(BUS7780),
328
               .sel(NET457),
329
               .wb_o(BUS15471)
330
           );
331
 
332
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.