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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [ram_module.v.bak] - Blame information for rev 53

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`include "include.h"
/*
module mem_array
    (
        input clk,
        input [31:0] pc_i,
        output [31:0] ins_o,
        input [3:0] wren,
        input [31:0]din,
        input [31:0]wr_addr_i,
        input [31:0]rd_addr_i,
        output [31:0]dout
    );
    wire [29:0] rd_addr,pc,wr_addr;
    wire [31:0]dout_w;
    assign dout = dout_w;
    assign rd_addr=rd_addr_i[31:2];
    assign wr_addr=wr_addr_i[31:2];
    assign pc= pc_i[31:2];
 
 
 
 `ifdef DEBUG
 
    sim_syn_ram3 ram3 (
                     .data(din[31:31-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[3]),
                     .clock(clk),
                     .qa(ins_o[31:31-7]),
                     .qb(dout_w[31:31-7])
                 );
 
    sim_syn_ram2 ram2(
                     .data(din[31-8:31-8-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[2]),
                     .clock(clk),
                     .qa(ins_o[31-8:31-8-7]),
                     .qb(dout_w[31-8:31-7-8])
                 );
 
    sim_syn_ram1 ram1(
                     .data(din[31-16:31-16-7]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[1]),
                     .clock(clk),
                     .qa(ins_o[31-16:31-7-16]),
                     .qb(dout_w[31-16:31-7-16])
                 );
 
    sim_syn_ram0 ram0(
                     .data(din[31-24:31-7-24]),
                     .wraddress(wr_addr),
                     .rdaddress_a(pc),
                     .rdaddress_b(rd_addr),
                     .wren(wren[0]),
                     .clock(clk),
                     .qa(ins_o[31-24:31-7-24]),
                     .qb(dout_w[31-24:31-7-24])
                 );
 
 
 `else
    ram4096x8_3 ram3(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[31:24]),
                    .address_b(wr_addr),
                    .wren_b(wren[3]),
                    .clock(clk),
                    .q_a(ins_o[31:24]),
                    .q_b(dout_w[31:24])
                );
 
    ram4096x8_2 ram2(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[23:16]),
                    .address_b(wr_addr),
                    .wren_b(wren[2]),
                    .clock(clk),
                    .q_a(ins_o[23:16]),
                    .q_b(dout_w[23:16])
                );
 
    ram4096x8_1 ram1(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[15:8]),
                    .address_b(wr_addr),
                    .wren_b(wren[1]),
                    .clock(clk),
                    .q_a(ins_o[15:8]),
                    .q_b(dout_w[15:8])
                );
 
    ram4096x8_0 ram0(
                    .data_a(32'b0),
                    .wren_a(1'b0),
                    .address_a(32'b0),
                    .data_b(din[7:0]),
                    .address_b(wr_addr),
                    .wren_b(wren[0]),
                    .clock(clk),
                    .q_a(ins_o[7:0]),
                    .q_b(dout_w[7:0])
                );
// `endif
 
endmodule
                                           */

Line No.	Rev	Author	Line
1	10	mcupro	`include "include.h"
2			`/*`
3			`module mem_array`
4			`(`
5			`input clk,`
6			`input [31:0] pc_i,`
7			`output [31:0] ins_o,`
8			`input [3:0] wren,`
9			`input [31:0]din,`
10			`input [31:0]wr_addr_i,`
11			`input [31:0]rd_addr_i,`
12			`output [31:0]dout`
13			`);`
14			`wire [29:0] rd_addr,pc,wr_addr;`
15			`wire [31:0]dout_w;`
16			`assign dout = dout_w;`
17			`assign rd_addr=rd_addr_i[31:2];`
18			`assign wr_addr=wr_addr_i[31:2];`
19			`assign pc= pc_i[31:2];`
20
21
22
23			`ifdef DEBUG
24
25			`sim_syn_ram3 ram3 (`
26			`.data(din[31:31-7]),`
27			`.wraddress(wr_addr),`
28			`.rdaddress_a(pc),`
29			`.rdaddress_b(rd_addr),`
30			`.wren(wren[3]),`
31			`.clock(clk),`
32			`.qa(ins_o[31:31-7]),`
33			`.qb(dout_w[31:31-7])`
34			`);`
35
36			`sim_syn_ram2 ram2(`
37			`.data(din[31-8:31-8-7]),`
38			`.wraddress(wr_addr),`
39			`.rdaddress_a(pc),`
40			`.rdaddress_b(rd_addr),`
41			`.wren(wren[2]),`
42			`.clock(clk),`
43			`.qa(ins_o[31-8:31-8-7]),`
44			`.qb(dout_w[31-8:31-7-8])`
45			`);`
46
47			`sim_syn_ram1 ram1(`
48			`.data(din[31-16:31-16-7]),`
49			`.wraddress(wr_addr),`
50			`.rdaddress_a(pc),`
51			`.rdaddress_b(rd_addr),`
52			`.wren(wren[1]),`
53			`.clock(clk),`
54			`.qa(ins_o[31-16:31-7-16]),`
55			`.qb(dout_w[31-16:31-7-16])`
56			`);`
57
58			`sim_syn_ram0 ram0(`
59			`.data(din[31-24:31-7-24]),`
60			`.wraddress(wr_addr),`
61			`.rdaddress_a(pc),`
62			`.rdaddress_b(rd_addr),`
63			`.wren(wren[0]),`
64			`.clock(clk),`
65			`.qa(ins_o[31-24:31-7-24]),`
66			`.qb(dout_w[31-24:31-7-24])`
67			`);`
68
69
70			`else
71			`ram4096x8_3 ram3(`
72			`.data_a(32'b0),`
73			`.wren_a(1'b0),`
74			`.address_a(32'b0),`
75			`.data_b(din[31:24]),`
76			`.address_b(wr_addr),`
77			`.wren_b(wren[3]),`
78			`.clock(clk),`
79			`.q_a(ins_o[31:24]),`
80			`.q_b(dout_w[31:24])`
81			`);`
82
83			`ram4096x8_2 ram2(`
84			`.data_a(32'b0),`
85			`.wren_a(1'b0),`
86			`.address_a(32'b0),`
87			`.data_b(din[23:16]),`
88			`.address_b(wr_addr),`
89			`.wren_b(wren[2]),`
90			`.clock(clk),`
91			`.q_a(ins_o[23:16]),`
92			`.q_b(dout_w[23:16])`
93			`);`
94
95			`ram4096x8_1 ram1(`
96			`.data_a(32'b0),`
97			`.wren_a(1'b0),`
98			`.address_a(32'b0),`
99			`.data_b(din[15:8]),`
100			`.address_b(wr_addr),`
101			`.wren_b(wren[1]),`
102			`.clock(clk),`
103			`.q_a(ins_o[15:8]),`
104			`.q_b(dout_w[15:8])`
105			`);`
106
107			`ram4096x8_0 ram0(`
108			`.data_a(32'b0),`
109			`.wren_a(1'b0),`
110			`.address_a(32'b0),`
111			`.data_b(din[7:0]),`
112			`.address_b(wr_addr),`
113			`.wren_b(wren[0]),`
114			`.clock(clk),`
115			`.q_a(ins_o[7:0]),`
116			`.q_b(dout_w[7:0])`
117			`);`
118			// `endif
119
120			`endmodule`
121			`*/`

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[/] [mips789/] [branches/] [avendor/] [rtl/] [verilog/] [ram_module.v.bak] - Blame information for rev 53