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module synplicity_altsyncram4_r_w_reg_array (wren_a,wren_b,data_a,address_a,address_b,clock0,clock1,clocken0,clocken1,q_b);
input wren_a;
input wren_b;
input [31:0]data_a;
input [4:0]address_a;
input [4:0]address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
output [31:0]q_b;
endmodule
 

Line No.	Rev	Author	Line
1	10	mcupro	`module synplicity_altsyncram4_r_w_reg_array (wren_a,wren_b,data_a,address_a,address_b,clock0,clock1,clocken0,clocken1,q_b);`
2			`input wren_a;`
3			`input wren_b;`
4			`input [31:0]data_a;`
5			`input [4:0]address_a;`
6			`input [4:0]address_b;`
7			`input clock0;`
8			`input clock1;`
9			`input clocken0;`
10			`input clocken1;`
11			`output [31:0]q_b;`
12			`endmodule`
13

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[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [mips_core/] [verif/] [mips_core_bb.v] - Blame information for rev 51