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[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [mips_sys/] [verif/] [mips_sys_bb.v] - Blame information for rev 51

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1 10 mcupro
module synplicity_altsyncram4_r_w_reg_array (wren_a,wren_b,data_a,address_a,address_b,clock0,clock1,clocken0,clocken1,q_b);
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input wren_a;
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input wren_b;
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input [31:0]data_a;
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input [4:0]address_a;
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input [4:0]address_b;
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input clock0;
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input clock1;
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input clocken0;
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input clocken1;
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output [31:0]q_b;
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endmodule
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module scfifo_Z1 (data,clock,wrreq,rdreq,aclr,sclr,q,usedw,full,empty,almost_full,almost_empty);
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input [7:0]data;
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input clock;
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input wrreq;
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input rdreq;
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input aclr;
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input sclr;
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output [7:0]q;
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output [8:0]usedw;
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output full;
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output empty;
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output almost_full;
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output almost_empty;
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endmodule
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