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[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [AutoConstraint_r5_reg_cls.sdc] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mcupro
2			`#Begin clock constraint`
3			`define_clock -name {b:r5_reg_cls\|clk} -period 10000000.000 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 5000000.000 -route 0.000`
4			`#End clock constraint`