Subversion Repositories mips789

#Program: Synplify Pro 8.1

#OS: Windows_NT

$ Start of Compile

#Fri Oct 10 10:26:44 2008

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005

Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v"

@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v"

@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v"

@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v"

@I::"E:\mips789\mips789\rtl\verilog\EXEC_stage.v"

@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":694:80:694:92|Read parallel_case directive

@I::"E:\mips789\mips789\rtl\verilog\RF_components.v"

@I:"E:\mips789\mips789\rtl\verilog\RF_components.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\RF_stage.v"

@I:"E:\mips789\mips789\rtl\verilog\RF_stage.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\ctl_fsm.v"

@I:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":"E:\mips789\mips789\rtl\verilog\include.h"

@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:43:58:55|Read parallel_case directive

@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:57:58:65|Read full_case directive

@W: CG286 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Case statement has both a full_case directive and a default clause.  The full_case directive is ignored.

@I::"E:\mips789\mips789\rtl\verilog\decode_pipe.v"

@I:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":"E:\mips789\mips789\rtl\verilog\include.h"

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:34:31:46|Read parallel_case directive

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":34:45:34:57|Read parallel_case directive

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":533:47:533:59|Read parallel_case directive

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":835:49:835:61|Read parallel_case directive

@I::"E:\mips789\mips789\rtl\verilog\dvc.v"

@I:"E:\mips789\mips789\rtl\verilog\dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\fifo.v"

@I:"E:\mips789\mips789\rtl\verilog\fifo.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\forward.v"

@I:"E:\mips789\mips789\rtl\verilog\forward.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\mem_module.v"

@I:"E:\mips789\mips789\rtl\verilog\mem_module.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\mips_core.v"

@I:"E:\mips789\mips789\rtl\verilog\mips_core.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\mips_dvc.v"

@I:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\mips_sys.v"

@I:"E:\mips789\mips789\rtl\verilog\mips_sys.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\mips_uart.v"

@I:"E:\mips789\mips789\rtl\verilog\mips_uart.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\ram_module.v"

@I:"E:\mips789\mips789\rtl\verilog\ram_module.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\sim_ram.v"

@I::"E:\mips789\mips789\rtl\verilog\ulit.v"

@I:"E:\mips789\mips789\rtl\verilog\ulit.v":"E:\mips789\mips789\rtl\verilog\include.h"

@I::"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v"

@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":39:12:39:24|Read directive translate_off

@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":41:12:41:23|Read directive translate_on

@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":74:16:74:28|Read directive translate_off

@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":81:16:81:27|Read directive translate_on

Verilog syntax check successful!

Options changed - recompiling

Selecting top level module mips_sys

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <30> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <29> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <28> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <27> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <26> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <25> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <24> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <23> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <22> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <21> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <20> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <19> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <18> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <17> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <16> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <15> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <14> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <13> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <12> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <11> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <10> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <9> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <8> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <7> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <6> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <5> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <4> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <3> of dmem_addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <2> of dmem_addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <31> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <30> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <29> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <28> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <27> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <26> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <25> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <24> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <23> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <22> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <21> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <20> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <19> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <18> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <17> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <16> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <15> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <14> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <13> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <12> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <11> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <10> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <9> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <8> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <7> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <6> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <5> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <4> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <3> of addr_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <2> of addr_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl

@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt

@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi

@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM

@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt

@W: CL113 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Feedback mux created for signal iack.

@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt

@N: CL201 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":224:4:224:9|Trying to extract state machine for register CurrState_Sreg0

Extracted state machine for register CurrState_Sreg0

State machine has 9 reachable states with original encodings of:

   0000

   0001

   0010

   0011

   0100

   0101

   0110

   0111

   1000

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":50:7:50:12|Synthesizing module pc_gen

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":30:7:30:13|Synthesizing module compare

@W: CG133 :"E:\mips789\mips789\rtl\verilog\RF_components.v":36:14:36:16|No assignment to sum

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":2:7:2:9|Synthesizing module ext

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <26> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":104:7:104:21|Synthesizing module r32_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":104:167:104:171|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <31> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <30> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <29> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <28> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <27> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <26> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <6> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <5> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <4> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <3> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <2> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <1> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <0> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel

@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":90:7:90:15|Synthesizing module reg_array

@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32

@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32

@N:"E:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux

@N:"E:\mips789\mips789\rtl\verilog\RF_stage.v":3:7:3:14|Synthesizing module rf_stage

@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":91:24:91:29|Port width mismatch for port ins_no.  Formal has width 101, Actual 1

@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":90:24:90:29|Port width mismatch for port clk_no.  Formal has width 101, Actual 1

@W: CL168 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":87:12:87:18|Pruning instance CAL_CPI - not in use ...

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":521:7:521:15|Synthesizing module muldiv_ff

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqz

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s

@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register START_SECTION.over[32:0]

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":233:7:233:9|Synthesizing module alu

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":238:16:238:16|No assignment to wire c

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":266:4:266:14|Synthesizing module shifter_tak

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <31> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <30> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <29> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <28> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <27> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <26> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <25> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <24> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <23> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <22> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <21> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <20> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <19> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <18> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <17> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <16> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <15> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <14> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <13> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <12> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <11> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <10> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <9> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <8> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <7> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <6> of shift_amount[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <5> of shift_amount[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":138:7:138:13|Synthesizing module big_alu

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":188:7:188:14|Synthesizing module alu_muxa

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":212:7:212:14|Synthesizing module alu_muxb

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":150:7:150:13|Synthesizing module r32_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":173:7:173:17|Synthesizing module r32_reg_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":173:132:173:136|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":3:7:3:16|Synthesizing module exec_stage

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt

@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <15> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <14> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <13> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <12> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <11> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <10> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <9> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <8> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <7> of ins_i[31:0] is unused

@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <6> of ins_i[31:0] is unused

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module muxb_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:28|Synthesizing module wb_mux_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":94:216:94:227|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":95:7:95:23|Synthesizing module wb_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":95:181:95:187|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":141:7:141:15|Synthesizing module wb_we_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:24|Synthesizing module wb_mux_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module muxb_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:22|Synthesizing module dmem_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:22|Synthesizing module alu_func_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxa_ctl_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:20|Synthesizing module wb_mux_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":118:7:118:19|Synthesizing module wb_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:25|Synthesizing module cmp_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":86:195:86:203|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:20|Synthesizing module alu_we_reg_clr

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:26|Synthesizing module alu_func_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":91:202:91:211|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:26|Synthesizing module dmem_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":93:202:93:211|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:25|Synthesizing module ext_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":84:195:84:203|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:24|Synthesizing module rd_sel_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":85:188:85:195|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:24|Synthesizing module alu_we_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":92:188:92:195|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxa_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":87:7:87:28|Synthesizing module pc_gen_ctl_reg_clr_cls

@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":87:216:87:227|Removing redundant assignment

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:18|Synthesizing module dmem_ctl_reg

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs

@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe

@N:"E:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node

@N:"E:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5

@N:"E:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:12|Synthesizing module r5_reg

@N:"E:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux

@N:"E:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read

@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|Trying to extract state machine for register ua_state

Extracted state machine for register ua_state

State machine has 5 reachable states with original encodings of:

   000

   001

   010

   011

   100

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d

@N:"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo

        lpm_width=32'b00000000000000000000000000001000

        lpm_widthu=32'b00000000000000000000000000001001

        lpm_numwords=32'b00000000000000000000001000000000

        lpm_showahead=24'b010011110100011001000110

        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101

        almost_full_value=32'b00000000000000000000000000000000

        almost_empty_value=32'b00000000000000000000000000000000

        underflow_checking=16'b0100111101001110

        overflow_checking=16'b0100111101001110

        allow_rwcycle_when_full=24'b010011110100011001000110

        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111

        use_eab=16'b0100111101001110

        add_ram_output_register=24'b010011110100011001000110

        maximum_depth=32'b00000000000000000000000000000000

        lpm_type=48'b011100110110001101100110011010010110011001101111

   Generated name = scfifo_Z1

@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write

@W: CG133 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|No assignment to write_done_n

@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|Trying to extract state machine for register ua_state

Extracted state machine for register ua_state

State machine has 8 reachable states with original encodings of:

   000

   001

   010

   011

   100

   101

   110

   111

@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0

@W:"E:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|No assignment to wire w_rxd_clr

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d

@N:"E:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0

@N:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc

@N:"E:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|No assignment to wire data2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|No assignment to wire data2mem

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|No assignment to wire ins2core

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|No assignment to wire mem_Addr

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|No assignment to wire pc

@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|No assignment to wire wr_en

@END

Process took 0h:00m:11s realtime, 0h:00m:11s cputime

# Fri Oct 10 10:26:56 2008

###########################################################[

Version 8.1

Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005

Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

Running FSM Explorer ...

Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_din_ctl(mem_din_ctl)

Automatic dissolve at startup in view:work.mem_module(verilog) of i_mem_addr_ctl(mem_addr_ctl)

Automatic dissolve at startup in view:work.mem_module(verilog) of dmem_ctl_post(infile_dmem_ctl_reg)

Automatic dissolve at startup in view:work.rf_stage(verilog) of rs_fwd_rs(fwd_mux)

Automatic dissolve at startup in view:work.rf_stage(verilog) of rf_fwd_rt(fwd_mux)

Automatic dissolve at startup in view:work.rf_stage(verilog) of jack2(jack)

Automatic dissolve at startup in view:work.rf_stage(verilog) of jack1(jack)

Automatic dissolve at startup in view:work.rf_stage(verilog) of ins_reg(r32_reg_clr_cls)

Automatic dissolve at startup in view:work.rf_stage(verilog) of i_pc_gen(pc_gen)

Automatic dissolve at startup in view:work.exec_stage(verilog) of spc(r32_reg_cls)

Automatic dissolve at startup in view:work.exec_stage(verilog) of pc_nxt(r32_reg)

Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxb(alu_muxb)

Automatic dissolve at startup in view:work.exec_stage(verilog) of i_alu_muxa(alu_muxa)

Automatic dissolve at startup in view:work.exec_stage(verilog) of dmem_fw_mux(fwd_mux)

Automatic dissolve at startup in view:work.exec_stage(verilog) of add4(add32)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U9(dmem_ctl_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U8(pc_gen_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U7(muxa_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U6(alu_we_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U5(rd_sel_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U4(ext_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U3(dmem_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U26(alu_func_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U24(alu_we_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U22(wb_we_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U21(wb_mux_ctl_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U20(wb_we_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U2(cmp_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U19(wb_we_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U18(wb_mux_ctl_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U17(muxa_ctl_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U16(alu_func_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U15(dmem_ctl_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U14(muxb_ctl_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U13(wb_mux_ctl_reg_clr)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U12(wb_we_reg)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U11(wb_we_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U10(wb_mux_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.pipelinedregs(verilog) of U1(muxb_ctl_reg_clr_cls)

Automatic dissolve at startup in view:work.decode_pipe(verilog) of pipereg(pipelinedregs)

Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rnt(fw_latch5)

Automatic dissolve at startup in view:work.forward(verilog) of fw_reg_rns(fw_latch5)

Automatic dissolve at startup in view:work.mips_core(verilog) of wb_mux(wb_mux)

Automatic dissolve at startup in view:work.mips_core(verilog) of rt_reg(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of rs_reg(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass2(r5_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass1(r5_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of rnd_pass0(r5_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of pc(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of ext_reg(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of cop_dout_reg(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_reg(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of cop_data_or(or32)

Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass1(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of alu_pass0(r32_reg)

Automatic dissolve at startup in view:work.mips_core(verilog) of iexec_stage(exec_stage)

Automatic dissolve at startup in view:work.mips_core(verilog) of iRF_stage(rf_stage)

Automatic dissolve at startup in view:work.mips_core(verilog) of MEM_CTL(mem_module)

Automatic dissolve at startup in view:work.uart_write(verilog) of fifo(fifo512_cyclone)

Automatic dissolve at startup in view:work.uart0(verilog) of rxd_rdy_hold_lw(rxd_d)

Automatic dissolve at startup in view:work.tmr0(verilog) of itmr_d(tmr_d)

Warning: Found 30 combinational loops!

         Each loop is reported with an instance in the loop

         and nets connected to that instance.

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]

1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]

2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[1]" in work.decoder(verilog)

        net "fsm_dly_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]

3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[1]" in work.decoder(verilog)

        net "fsm_dly_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[0]

4) instance work.decoder(verilog)-ext_ctl_1[0], output net "ext_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "ext_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[1]

5) instance work.decoder(verilog)-ext_ctl_1[1], output net "ext_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "ext_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net ext_ctl_1[2]

6) instance work.decoder(verilog)-ext_ctl_1[2], output net "ext_ctl_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "ext_ctl_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[0]

7) instance work.decoder(verilog)-rd_sel_1[0], output net "rd_sel_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "rd_sel_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net rd_sel_1[1]

8) instance work.decoder(verilog)-rd_sel_1[1], output net "rd_sel_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "rd_sel_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_22" in work.decoder(verilog)

        net "fsm_dly373" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[0]

9) instance work.decoder(verilog)-cmp_ctl_1[0], output net "cmp_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "cmp_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[1]

10) instance work.decoder(verilog)-cmp_ctl_1[1], output net "cmp_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "cmp_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net cmp_ctl_1[2]

11) instance work.decoder(verilog)-cmp_ctl_1[2], output net "cmp_ctl_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "cmp_ctl_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[0]

12) instance work.decoder(verilog)-pc_gen_ctl_1[0], output net "pc_gen_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "pc_gen_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[1]

13) instance work.decoder(verilog)-pc_gen_ctl_1[1], output net "pc_gen_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "pc_gen_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net pc_gen_ctl_1[2]

14) instance work.decoder(verilog)-pc_gen_ctl_1[2], output net "pc_gen_ctl_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "pc_gen_ctl_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[0]

15) instance work.decoder(verilog)-muxa_ctl_1[0], output net "muxa_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "muxa_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxa_ctl_1[1]

16) instance work.decoder(verilog)-muxa_ctl_1[1], output net "muxa_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "muxa_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[0]

17) instance work.decoder(verilog)-muxb_ctl_1[0], output net "muxb_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "muxb_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net muxb_ctl_1[1]

18) instance work.decoder(verilog)-muxb_ctl_1[1], output net "muxb_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "muxb_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[0]

19) instance work.decoder(verilog)-alu_func_1[0], output net "alu_func_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[1]

20) instance work.decoder(verilog)-alu_func_1[1], output net "alu_func_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[2]

21) instance work.decoder(verilog)-alu_func_1[2], output net "alu_func_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[3]

22) instance work.decoder(verilog)-alu_func_1[3], output net "alu_func_1[3]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_2[3]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_1[4]

23) instance work.decoder(verilog)-alu_func_1[4], output net "alu_func_1[4]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_2[4]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[0]

24) instance work.decoder(verilog)-dmem_ctl_1[0], output net "dmem_ctl_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "dmem_ctl_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_23" in work.decoder(verilog)

        net "un1_ins_i_20" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[1]

25) instance work.decoder(verilog)-dmem_ctl_1[1], output net "dmem_ctl_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "dmem_ctl_2[1]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_22" in work.decoder(verilog)

        net "fsm_dly373" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[2]

26) instance work.decoder(verilog)-dmem_ctl_1[2], output net "dmem_ctl_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "dmem_ctl_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_24" in work.decoder(verilog)

        net "un1_ins_i_15" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net dmem_ctl_1[3]

27) instance work.decoder(verilog)-dmem_ctl_1[3], output net "dmem_ctl_1[3]" in work.decoder(verilog)

    input nets to instance:

        net "dmem_ctl_2[3]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_we[0]

28) instance work.decoder(verilog)-alu_we[0], output net "alu_we[0]" in work.decoder(verilog)

    input nets to instance:

        net "alu_we_1[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux[0]

29) instance work.decoder(verilog)-wb_mux[0], output net "wb_mux[0]" in work.decoder(verilog)

    input nets to instance:

        net "wb_mux_1[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we[0]

30) instance work.decoder(verilog)-wb_we[0], output net "wb_we[0]" in work.decoder(verilog)

    input nets to instance:

        net "wb_we_1[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

End of loops

RTL optimization done.

Warning: Found 30 combinational loops!

         Each loop is reported with an instance in the loop

         and nets connected to that instance.

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[0]

1) instance work.decoder(verilog)-fsm_dly_1[0], output net "fsm_dly_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[0]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[1]

2) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[1]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[1]" in work.decoder(verilog)

        net "fsm_dly_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net fsm_dly_1[2]

3) instance work.decoder(verilog)-fsm_dly_1[2:1], output net "fsm_dly_1[2]" in work.decoder(verilog)

    input nets to instance:

        net "fsm_dly_2[1]" in work.decoder(verilog)

        net "fsm_dly_2[2]" in work.decoder(verilog)

        net "un1_fsm_dly370" in work.decoder(verilog)

        net "un1_ins_i_21" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_mux_1[0]

4) instance work.decoder(verilog)-wb_mux_1[0], output net "wb_mux_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "un1_alu_we_3_sqmuxa_4" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)

        net "wb_mux[0]" in work.decoder(verilog)

        net "un1_fsm_dly365" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net wb_we_1[0]

5) instance work.decoder(verilog)-wb_we_1[0], output net "wb_we_1[0]" in work.decoder(verilog)

    input nets to instance:

        net "un1_alu_we_3_sqmuxa_3" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "un1_alu_we_3_sqmuxa" in work.decoder(verilog)

        net "wb_we[0]" in work.decoder(verilog)

        net "un1_fsm_dly362" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Found combinational loop during mapping at net alu_func_2[0]

6) instance work.decoder(verilog)-alu_func_2[4:0], output net "alu_func_2[0]" in work.decoder(verilog)

    input nets to instance:

        net "alu_func_0_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_1_sqmuxa" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_2_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_3_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_4_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_5_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_6_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_7_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_8_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_9_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_10_sqmuxa" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "GND" in work.decoder(verilog)

        net "alu_func_11_sqmuxa" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)

        net "VCC" in work.decoder(verilog)