OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [fifo512_cyclone.tlg] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mcupro 
Selecting top level module mips_sys
2 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg
3 
 
4 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <30> of dmem_addr_i[31:0] is unused
5 
 
6 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <29> of dmem_addr_i[31:0] is unused
7 
 
8 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <28> of dmem_addr_i[31:0] is unused
9 
 
10 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <27> of dmem_addr_i[31:0] is unused
11 
 
12 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <26> of dmem_addr_i[31:0] is unused
13 
 
14 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <25> of dmem_addr_i[31:0] is unused
15 
 
16 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <24> of dmem_addr_i[31:0] is unused
17 
 
18 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <23> of dmem_addr_i[31:0] is unused
19 
 
20 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <22> of dmem_addr_i[31:0] is unused
21 
 
22 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <21> of dmem_addr_i[31:0] is unused
23 
 
24 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <20> of dmem_addr_i[31:0] is unused
25 
 
26 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <19> of dmem_addr_i[31:0] is unused
27 
 
28 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <18> of dmem_addr_i[31:0] is unused
29 
 
30 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <17> of dmem_addr_i[31:0] is unused
31 
 
32 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <16> of dmem_addr_i[31:0] is unused
33 
 
34 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <15> of dmem_addr_i[31:0] is unused
35 
 
36 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <14> of dmem_addr_i[31:0] is unused
37 
 
38 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <13> of dmem_addr_i[31:0] is unused
39 
 
40 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <12> of dmem_addr_i[31:0] is unused
41 
 
42 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <11> of dmem_addr_i[31:0] is unused
43 
 
44 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <10> of dmem_addr_i[31:0] is unused
45 
 
46 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <9> of dmem_addr_i[31:0] is unused
47 
 
48 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <8> of dmem_addr_i[31:0] is unused
49 
 
50 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <7> of dmem_addr_i[31:0] is unused
51 
 
52 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <6> of dmem_addr_i[31:0] is unused
53 
 
54 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <5> of dmem_addr_i[31:0] is unused
55 
 
56 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <4> of dmem_addr_i[31:0] is unused
57 
 
58 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <3> of dmem_addr_i[31:0] is unused
59 
 
60 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|Input port bit <2> of dmem_addr_i[31:0] is unused
61 
 
62 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl
63 
 
64 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|Latch generated from always block for signal wr_en[3:0], probably caused by a missing assignment in an if or case stmt
65 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <31> of addr_i[31:0] is unused
66 
 
67 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <30> of addr_i[31:0] is unused
68 
 
69 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <29> of addr_i[31:0] is unused
70 
 
71 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <28> of addr_i[31:0] is unused
72 
 
73 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <27> of addr_i[31:0] is unused
74 
 
75 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <26> of addr_i[31:0] is unused
76 
 
77 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <25> of addr_i[31:0] is unused
78 
 
79 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <24> of addr_i[31:0] is unused
80 
 
81 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <23> of addr_i[31:0] is unused
82 
 
83 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <22> of addr_i[31:0] is unused
84 
 
85 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <21> of addr_i[31:0] is unused
86 
 
87 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <20> of addr_i[31:0] is unused
88 
 
89 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <19> of addr_i[31:0] is unused
90 
 
91 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <18> of addr_i[31:0] is unused
92 
 
93 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <17> of addr_i[31:0] is unused
94 
 
95 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <16> of addr_i[31:0] is unused
96 
 
97 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <15> of addr_i[31:0] is unused
98 
 
99 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <14> of addr_i[31:0] is unused
100 
 
101 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <13> of addr_i[31:0] is unused
102 
 
103 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <12> of addr_i[31:0] is unused
104 
 
105 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <11> of addr_i[31:0] is unused
106 
 
107 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <10> of addr_i[31:0] is unused
108 
 
109 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <9> of addr_i[31:0] is unused
110 
 
111 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <8> of addr_i[31:0] is unused
112 
 
113 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <7> of addr_i[31:0] is unused
114 
 
115 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <6> of addr_i[31:0] is unused
116 
 
117 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <5> of addr_i[31:0] is unused
118 
 
119 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <4> of addr_i[31:0] is unused
120 
 
121 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <3> of addr_i[31:0] is unused
122 
 
123 
@W:"E:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|Input port bit <2> of addr_i[31:0] is unused
124 
 
125 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl
126 
 
127 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl
128 
 
129 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|Latch generated from always block for signal dout[31:0], probably caused by a missing assignment in an if or case stmt
130 
@N:"E:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module
131 
 
132 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi
133 
 
134 
@N:"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM
135 
 
136 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal zz_is_nop, probably caused by a missing assignment in an if or case stmt
137 
@W: CL113 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Feedback mux created for signal iack.
138 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal iack, probably caused by a missing assignment in an if or case stmt
139 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|Latch generated from always block for signal next_delay_counter_Sreg0[5:0], probably caused by a missing assignment in an if or case stmt
140 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\ctl_fsm.v":224:4:224:9|Trying to extract state machine for register CurrState_Sreg0
141 
Extracted state machine for register CurrState_Sreg0
142 
State machine has 9 reachable states with original encodings of:
143 
   0000
144 
   0001
145 
   0010
146 
   0011
147 
   0100
148 
   0101
149 
   0110
150 
   0111
151 
   1000
152 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":50:7:50:12|Synthesizing module pc_gen
153 
 
154 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":30:7:30:13|Synthesizing module compare
155 
 
156 
@W: CG133 :"E:\mips789\mips789\rtl\verilog\RF_components.v":36:14:36:16|No assignment to sum
157 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":2:7:2:9|Synthesizing module ext
158 
 
159 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <31> of ins_i[31:0] is unused
160 
 
161 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <30> of ins_i[31:0] is unused
162 
 
163 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <29> of ins_i[31:0] is unused
164 
 
165 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <28> of ins_i[31:0] is unused
166 
 
167 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <27> of ins_i[31:0] is unused
168 
 
169 
@W:"E:\mips789\mips789\rtl\verilog\RF_components.v":3:21:3:25|Input port bit <26> of ins_i[31:0] is unused
170 
 
171 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":104:7:104:21|Synthesizing module r32_reg_clr_cls
172 
 
173 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":104:167:104:171|Removing redundant assignment
174 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack
175 
 
176 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <31> of ins_i[31:0] is unused
177 
 
178 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <30> of ins_i[31:0] is unused
179 
 
180 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <29> of ins_i[31:0] is unused
181 
 
182 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <28> of ins_i[31:0] is unused
183 
 
184 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <27> of ins_i[31:0] is unused
185 
 
186 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <26> of ins_i[31:0] is unused
187 
 
188 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <10> of ins_i[31:0] is unused
189 
 
190 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <9> of ins_i[31:0] is unused
191 
 
192 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <8> of ins_i[31:0] is unused
193 
 
194 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <7> of ins_i[31:0] is unused
195 
 
196 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <6> of ins_i[31:0] is unused
197 
 
198 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <5> of ins_i[31:0] is unused
199 
 
200 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <4> of ins_i[31:0] is unused
201 
 
202 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <3> of ins_i[31:0] is unused
203 
 
204 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <2> of ins_i[31:0] is unused
205 
 
206 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <1> of ins_i[31:0] is unused
207 
 
208 
@W:"E:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|Input port bit <0> of ins_i[31:0] is unused
209 
 
210 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel
211 
 
212 
@N:"E:\mips789\mips789\rtl\verilog\RF_components.v":90:7:90:15|Synthesizing module reg_array
213 
 
214 
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32
215 
@N: CL134 :"E:\mips789\mips789\rtl\verilog\RF_components.v":140:4:140:9|Found RAM reg_bank, depth=32, width=32
216 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux
217 
 
218 
@N:"E:\mips789\mips789\rtl\verilog\RF_stage.v":3:7:3:14|Synthesizing module rf_stage
219 
 
220 
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":91:24:91:29|Port width mismatch for port ins_no.  Formal has width 101, Actual 1
221 
@W: CS149 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":90:24:90:29|Port width mismatch for port clk_no.  Formal has width 101, Actual 1
222 
@W: CL168 :"E:\mips789\mips789\rtl\verilog\RF_stage.v":87:12:87:18|Pruning instance CAL_CPI - not in use ...
223 
 
224 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":521:7:521:15|Synthesizing module muldiv_ff
225 
 
226 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqz
227 
 
228 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_h64
229 
 
230 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqop2
231 
 
232 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.eqnop2
233 
 
234 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register LAST_CYCLE_DEAL_SECTION.LAST_CYCLE_DEAL_SECTION_DEFAULT.op1s_eq_op2s
235 
 
236 
@W: CL169 :"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":572:4:572:9|Pruning Register START_SECTION.over[32:0]
237 
 
238 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":233:7:233:9|Synthesizing module alu
239 
 
240 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":238:16:238:16|No assignment to wire c
241 
 
242 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":266:4:266:14|Synthesizing module shifter_tak
243 
 
244 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <31> of shift_amount[31:0] is unused
245 
 
246 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <30> of shift_amount[31:0] is unused
247 
 
248 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <29> of shift_amount[31:0] is unused
249 
 
250 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <28> of shift_amount[31:0] is unused
251 
 
252 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <27> of shift_amount[31:0] is unused
253 
 
254 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <26> of shift_amount[31:0] is unused
255 
 
256 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <25> of shift_amount[31:0] is unused
257 
 
258 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <24> of shift_amount[31:0] is unused
259 
 
260 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <23> of shift_amount[31:0] is unused
261 
 
262 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <22> of shift_amount[31:0] is unused
263 
 
264 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <21> of shift_amount[31:0] is unused
265 
 
266 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <20> of shift_amount[31:0] is unused
267 
 
268 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <19> of shift_amount[31:0] is unused
269 
 
270 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <18> of shift_amount[31:0] is unused
271 
 
272 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <17> of shift_amount[31:0] is unused
273 
 
274 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <16> of shift_amount[31:0] is unused
275 
 
276 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <15> of shift_amount[31:0] is unused
277 
 
278 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <14> of shift_amount[31:0] is unused
279 
 
280 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <13> of shift_amount[31:0] is unused
281 
 
282 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <12> of shift_amount[31:0] is unused
283 
 
284 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <11> of shift_amount[31:0] is unused
285 
 
286 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <10> of shift_amount[31:0] is unused
287 
 
288 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <9> of shift_amount[31:0] is unused
289 
 
290 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <8> of shift_amount[31:0] is unused
291 
 
292 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <7> of shift_amount[31:0] is unused
293 
 
294 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <6> of shift_amount[31:0] is unused
295 
 
296 
@W:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":270:25:270:50|Input port bit <5> of shift_amount[31:0] is unused
297 
 
298 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":138:7:138:13|Synthesizing module big_alu
299 
 
300 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32
301 
 
302 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":188:7:188:14|Synthesizing module alu_muxa
303 
 
304 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":212:7:212:14|Synthesizing module alu_muxb
305 
 
306 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":150:7:150:13|Synthesizing module r32_reg
307 
 
308 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":173:7:173:17|Synthesizing module r32_reg_cls
309 
 
310 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":173:132:173:136|Removing redundant assignment
311 
@N:"E:\mips789\mips789\rtl\verilog\EXEC_stage.v":3:7:3:16|Synthesizing module exec_stage
312 
 
313 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32
314 
 
315 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder
316 
 
317 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_func[4:0], probably caused by a missing assignment in an if or case stmt
318 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal pc_gen_ctl[2:0], probably caused by a missing assignment in an if or case stmt
319 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal fsm_dly[2:0], probably caused by a missing assignment in an if or case stmt
320 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal ext_ctl[2:0], probably caused by a missing assignment in an if or case stmt
321 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal rd_sel[1:0], probably caused by a missing assignment in an if or case stmt
322 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxb_ctl[1:0], probably caused by a missing assignment in an if or case stmt
323 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal muxa_ctl[1:0], probably caused by a missing assignment in an if or case stmt
324 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal alu_we[0], probably caused by a missing assignment in an if or case stmt
325 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal dmem_ctl[3:0], probably caused by a missing assignment in an if or case stmt
326 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal cmp_ctl[2:0], probably caused by a missing assignment in an if or case stmt
327 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_we[0], probably caused by a missing assignment in an if or case stmt
328 
@W: CL118 :"E:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|Latch generated from always block for signal wb_mux[0], probably caused by a missing assignment in an if or case stmt
329 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <15> of ins_i[31:0] is unused
330 
 
331 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <14> of ins_i[31:0] is unused
332 
 
333 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <13> of ins_i[31:0] is unused
334 
 
335 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <12> of ins_i[31:0] is unused
336 
 
337 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <11> of ins_i[31:0] is unused
338 
 
339 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <10> of ins_i[31:0] is unused
340 
 
341 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <9> of ins_i[31:0] is unused
342 
 
343 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <8> of ins_i[31:0] is unused
344 
 
345 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <7> of ins_i[31:0] is unused
346 
 
347 
@W:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|Input port bit <6> of ins_i[31:0] is unused
348 
 
349 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module muxb_ctl_reg_clr_cls
350 
 
351 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|Removing redundant assignment
352 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:28|Synthesizing module wb_mux_ctl_reg_clr_cls
353 
 
354 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":94:216:94:227|Removing redundant assignment
355 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":95:7:95:23|Synthesizing module wb_we_reg_clr_cls
356 
 
357 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":95:181:95:187|Removing redundant assignment
358 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":141:7:141:15|Synthesizing module wb_we_reg
359 
 
360 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:24|Synthesizing module wb_mux_ctl_reg_clr
361 
 
362 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module muxb_ctl_reg_clr
363 
 
364 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:22|Synthesizing module dmem_ctl_reg_clr
365 
 
366 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:22|Synthesizing module alu_func_reg_clr
367 
 
368 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxa_ctl_reg_clr
369 
 
370 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:20|Synthesizing module wb_mux_ctl_reg
371 
 
372 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":118:7:118:19|Synthesizing module wb_we_reg_clr
373 
 
374 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:25|Synthesizing module cmp_ctl_reg_clr_cls
375 
 
376 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":86:195:86:203|Removing redundant assignment
377 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:20|Synthesizing module alu_we_reg_clr
378 
 
379 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:26|Synthesizing module alu_func_reg_clr_cls
380 
 
381 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":91:202:91:211|Removing redundant assignment
382 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:26|Synthesizing module dmem_ctl_reg_clr_cls
383 
 
384 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":93:202:93:211|Removing redundant assignment
385 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:25|Synthesizing module ext_ctl_reg_clr_cls
386 
 
387 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":84:195:84:203|Removing redundant assignment
388 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:24|Synthesizing module rd_sel_reg_clr_cls
389 
 
390 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":85:188:85:195|Removing redundant assignment
391 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:24|Synthesizing module alu_we_reg_clr_cls
392 
 
393 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":92:188:92:195|Removing redundant assignment
394 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxa_ctl_reg_clr_cls
395 
 
396 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|Removing redundant assignment
397 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":87:7:87:28|Synthesizing module pc_gen_ctl_reg_clr_cls
398 
 
399 
@N: CG179 :"E:\mips789\mips789\rtl\verilog\ulit.v":87:216:87:227|Removing redundant assignment
400 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:18|Synthesizing module dmem_ctl_reg
401 
 
402 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs
403 
 
404 
@N:"E:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe
405 
 
406 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node
407 
 
408 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5
409 
 
410 
@N:"E:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward
411 
 
412 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:12|Synthesizing module r5_reg
413 
 
414 
@N:"E:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux
415 
 
416 
@N:"E:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core
417 
 
418 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read
419 
 
420 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|Trying to extract state machine for register ua_state
421 
Extracted state machine for register ua_state
422 
State machine has 5 reachable states with original encodings of:
423 
   000
424 
   001
425 
   010
426 
   011
427 
   100
428 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d
429 
 
430 
@N:"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo
431 
 
432 
        lpm_width=32'b00000000000000000000000000001000
433 
        lpm_widthu=32'b00000000000000000000000000001001
434 
        lpm_numwords=32'b00000000000000000000001000000000
435 
        lpm_showahead=24'b010011110100011001000110
436 
        intended_device_family=56'b01000011011110010110001101101100011011110110111001100101
437 
        almost_full_value=32'b00000000000000000000000000000000
438 
        almost_empty_value=32'b00000000000000000000000000000000
439 
        underflow_checking=16'b0100111101001110
440 
        overflow_checking=16'b0100111101001110
441 
        allow_rwcycle_when_full=24'b010011110100011001000110
442 
        lpm_hint=152'b01010010010000010100110101011111010000100100110001001111010000110100101101011111010101000101100101010000010001010011110101000001010101010101010001001111
443 
        use_eab=16'b0100111101001110
444 
        add_ram_output_register=24'b010011110100011001000110
445 
        maximum_depth=32'b00000000000000000000000000000000
446 
        lpm_type=48'b011100110110001101100110011010010110011001101111
447 
   Generated name = scfifo_Z1
448 
@N:"E:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone
449 
 
450 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write
451 
 
452 
@W: CG133 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|No assignment to write_done_n
453 
@N: CL201 :"E:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|Trying to extract state machine for register ua_state
454 
Extracted state machine for register ua_state
455 
State machine has 8 reachable states with original encodings of:
456 
   000
457 
   001
458 
   010
459 
   011
460 
   100
461 
   101
462 
   110
463 
   111
464 
@N:"E:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0
465 
 
466 
@W:"E:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|No assignment to wire w_rxd_clr
467 
 
468 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv
469 
 
470 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d
471 
 
472 
@N:"E:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0
473 
 
474 
@N:"E:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc
475 
 
476 
@N:"E:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys
477 
 
478 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|No assignment to wire data2core
479 
 
480 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|No assignment to wire data2mem
481 
 
482 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|No assignment to wire ins2core
483 
 
484 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|No assignment to wire mem_Addr
485 
 
486 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|No assignment to wire pc
487 
 
488 
@W:"E:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|No assignment to wire wr_en
489 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.