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URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [avendor/] [synplify_prj/] [rev_1/] [syntmp/] [mips_sys.msg] - Blame information for rev 51

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Line No. Rev Author Line
1 15 mcupro 
@TM:1223821882
2 
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
3 
@N: MF197 :"":0:0:0:-1|Retiming summary : 0 registers retimed to 0
4 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
5 
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
6 
@N:  :"c:\program files\synplicity\fpga_81\lib\altera\altera_mf.v":3709:7:3709:12|Synthesizing module scfifo
7 
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":39:12:39:24|M
8 
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":41:12:41:23|M
9 
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":42:7:42:21|Synthesizing module fifo512_cyclone
10 
@W: MT253 :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":66:8:66:23|M
11 
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":74:16:74:28|M
12 
@N:  :"e:\mips789\mips789\rtl\verilog\altera\fifo512_cyclone.v":81:16:81:27|M
13 
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":2:7:2:13|Synthesizing module ctl_FSM
14 
@W:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
15 
@W: CG286 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
16 
@W: CL113 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
17 
@W: CL118 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
18 
@W: CL118 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
19 
@W: MO127 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:8:58:11|M
20 
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:43:58:55|M
21 
@N:  :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":58:57:58:65|M
22 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":138:16:138:16|M
23 
@W: FA140 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":138:16:138:16|M
24 
@N: CL201 :"e:\mips789\mips789\rtl\verilog\ctl_fsm.v":255:4:255:9|M
25 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1:1:961:15|M
26 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":2:7:2:13|Synthesizing module decoder
27 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
28 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
29 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
30 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
31 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
32 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
33 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
34 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
35 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
36 
@W:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":3:20:3:24|M
37 
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
38 
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
39 
@W: BN134 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
40 
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
41 
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
42 
@W: BN137 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
43 
@W: CL118 :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:8:31:11|M
44 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":31:34:31:46|M
45 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":34:45:34:57|M
46 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":533:47:533:59|M
47 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":835:49:835:61|M
48 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1090:7:1090:19|Synthesizing module pipelinedregs
49 
@N:  :"e:\mips789\mips789\rtl\verilog\decode_pipe.v":1419:7:1419:17|Synthesizing module decode_pipe
50 
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":3:7:3:10|Synthesizing module tmr0
51 
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":23:4:23:9|M
52 
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":43:7:43:11|Synthesizing module tmr_d
53 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\dvc.v":45:4:45:9|M
54 
@N:  :"e:\mips789\mips789\rtl\verilog\dvc.v":52:7:52:16|Synthesizing module seg7led_cv
55 
@N: MO106 :"e:\mips789\mips789\rtl\verilog\dvc.v":67:12:67:15|M
56 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":3:7:3:16|Synthesizing module exec_stage
57 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":132:7:132:13|Synthesizing module big_alu
58 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":182:7:182:14|Synthesizing module alu_muxa
59 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":206:7:206:14|Synthesizing module alu_muxb
60 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":227:7:227:9|Synthesizing module alu
61 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":259:4:259:14|Synthesizing module shifter_tak
62 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
63 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
64 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
65 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
66 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
67 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
68 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
69 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
70 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
71 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
72 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
73 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
74 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
75 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
76 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
77 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
78 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
79 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
80 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
81 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
82 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
83 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
84 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
85 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
86 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
87 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
88 
@W:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":263:25:263:50|M
89 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":512:7:512:15|Synthesizing module muldiv_ff
90 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":563:4:563:9|M
91 
@W: CL169 :"e:\mips789\mips789\rtl\verilog\exec_stage.v":563:4:563:9|M
92 
@N:  :"e:\mips789\mips789\rtl\verilog\exec_stage.v":685:80:685:92|M
93 
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":4:7:4:15|Synthesizing module fw_latch5
94 
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":12:7:12:18|Synthesizing module forward_node
95 
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":25:7:25:13|Synthesizing module fwd_mux
96 
@N:  :"e:\mips789\mips789\rtl\verilog\forward.v":41:7:41:13|Synthesizing module forward
97 
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":4:7:4:16|Synthesizing module mem_module
98 
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":78:7:78:25|Synthesizing module infile_dmem_ctl_reg
99 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
100 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
101 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
102 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
103 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
104 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
105 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
106 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
107 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
108 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
109 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
110 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
111 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
112 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
113 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
114 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
115 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
116 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
117 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
118 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
119 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
120 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
121 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
122 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
123 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
124 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
125 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
126 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
127 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":81:20:81:30|M
128 
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":96:7:96:18|Synthesizing module mem_addr_ctl
129 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
130 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
131 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
132 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
133 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
134 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
135 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
136 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
137 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
138 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
139 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
140 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
141 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
142 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
143 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
144 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
145 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
146 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
147 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
148 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
149 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
150 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
151 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
152 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
153 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
154 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
155 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
156 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
157 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
158 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":98:20:98:25|M
159 
@W: CL118 :"e:\mips789\mips789\rtl\verilog\mem_module.v":102:4:102:7|M
160 
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":130:7:130:18|Synthesizing module mem_dout_ctl
161 
@W:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|M
162 
@W: CL118 :"e:\mips789\mips789\rtl\verilog\mem_module.v":161:4:161:7|M
163 
@N:  :"e:\mips789\mips789\rtl\verilog\mem_module.v":199:7:199:17|Synthesizing module mem_din_ctl
164 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_core.v":3:7:3:15|Synthesizing module mips_core
165 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":3:7:3:14|Synthesizing module mips_dvc
166 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\mips_dvc.v":113:4:113:9|M
167 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":4:7:4:14|Synthesizing module mips_sys
168 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":78:16:78:24|M
169 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":79:16:79:23|M
170 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":80:16:80:23|M
171 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":81:16:81:23|M
172 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":82:16:82:17|M
173 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_sys.v":83:15:83:19|M
174 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":3:7:3:11|Synthesizing module rxd_d
175 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":12:7:12:11|Synthesizing module uart0
176 
@W:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":38:9:38:17|M
177 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":70:7:70:16|Synthesizing module uart_write
178 
@W: CG133 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":94:9:94:20|M
179 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":138:4:138:9|M
180 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":151:4:151:9|M
181 
@N: CL201 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":168:4:168:9|M
182 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":210:7:210:15|Synthesizing module uart_read
183 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":243:4:243:9|M
184 
@N:  :"e:\mips789\mips789\rtl\verilog\mips_uart.v":256:4:256:9|M
185 
@N: CL201 :"e:\mips789\mips789\rtl\verilog\mips_uart.v":274:4:274:9|M
186 
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":2:7:2:9|Synthesizing module ext
187 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
188 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
189 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
190 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
191 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
192 
@W:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":3:21:3:25|M
193 
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":30:7:30:13|Synthesizing module compare
194 
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":49:7:49:12|Synthesizing module pc_gen
195 
@N:  :"e:\mips789\mips789\rtl\verilog\rf_components.v":89:7:89:15|Synthesizing module reg_array
196 
@N: CL134 :"e:\mips789\mips789\rtl\verilog\rf_components.v":139:4:139:9|M
197 
@N:  :"e:\mips789\mips789\rtl\verilog\rf_stage.v":3:7:3:14|Synthesizing module rf_stage
198 
@W: CL168 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":87:12:87:18|M
199 
@W: CS149 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":90:24:90:29|M
200 
@W: CS149 :"e:\mips789\mips789\rtl\verilog\rf_stage.v":91:24:91:29|M
201 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":3:7:3:13|Synthesizing module cal_cpi
202 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":22:7:22:11|Synthesizing module add32
203 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":30:7:30:10|Synthesizing module jack
204 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
205 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
206 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
207 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
208 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
209 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
210 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
211 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
212 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
213 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
214 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
215 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
216 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
217 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
218 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
219 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
220 
@W:  :"e:\mips789\mips789\rtl\verilog\ulit.v":31:21:31:25|M
221 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":43:7:43:12|Synthesizing module wb_mux
222 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":54:7:54:10|Synthesizing module or32
223 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":64:7:64:12|Synthesizing module rd_sel
224 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":83:7:83:25|Synthesizing module ext_ctl_reg_clr_cls
225 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":83:195:83:203|M
226 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":84:7:84:24|Synthesizing module rd_sel_reg_clr_cls
227 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":84:188:84:195|M
228 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":85:7:85:25|Synthesizing module cmp_ctl_reg_clr_cls
229 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":85:195:85:203|M
230 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":86:7:86:28|Synthesizing module pc_gen_ctl_reg_clr_cls
231 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":86:216:86:227|M
232 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":88:7:88:26|Synthesizing module muxa_ctl_reg_clr_cls
233 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":88:202:88:211|M
234 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":89:7:89:26|Synthesizing module muxb_ctl_reg_clr_cls
235 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":89:202:89:211|M
236 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":90:7:90:26|Synthesizing module alu_func_reg_clr_cls
237 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":90:202:90:211|M
238 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":91:7:91:24|Synthesizing module alu_we_reg_clr_cls
239 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":91:188:91:195|M
240 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":92:7:92:26|Synthesizing module dmem_ctl_reg_clr_cls
241 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":92:202:92:211|M
242 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":93:7:93:28|Synthesizing module wb_mux_ctl_reg_clr_cls
243 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":93:216:93:227|M
244 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":94:7:94:23|Synthesizing module wb_we_reg_clr_cls
245 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":94:181:94:187|M
246 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":103:7:103:21|Synthesizing module r32_reg_clr_cls
247 
@W: BN116 :"e:\mips789\mips789\rtl\verilog\ulit.v":103:111:103:116|M
248 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":103:167:103:171|M
249 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":111:7:111:22|Synthesizing module muxa_ctl_reg_clr
250 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":112:7:112:22|Synthesizing module muxb_ctl_reg_clr
251 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":113:7:113:22|Synthesizing module alu_func_reg_clr
252 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":114:7:114:20|Synthesizing module alu_we_reg_clr
253 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":115:7:115:22|Synthesizing module dmem_ctl_reg_clr
254 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":116:7:116:24|Synthesizing module wb_mux_ctl_reg_clr
255 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":117:7:117:19|Synthesizing module wb_we_reg_clr
256 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":138:7:138:18|Synthesizing module dmem_ctl_reg
257 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":139:7:139:20|Synthesizing module wb_mux_ctl_reg
258 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":140:7:140:15|Synthesizing module wb_we_reg
259 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":148:7:148:12|Synthesizing module r5_reg
260 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":149:7:149:13|Synthesizing module r32_reg
261 
@W: BN132 :"e:\mips789\mips789\rtl\verilog\ulit.v":149:83:149:88|M
262 
@N:  :"e:\mips789\mips789\rtl\verilog\ulit.v":172:7:172:17|Synthesizing module r32_reg_cls
263 
@N: CG179 :"e:\mips789\mips789\rtl\verilog\ulit.v":172:132:172:136|M

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