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[/] [mips789/] [branches/] [avendor/] [tools/] [gensim.c] - Blame information for rev 59

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Line No. Rev Author Line
1 2 mcupro 
#include "stdio.h"
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main(int file_no,char*file_name[])
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{
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    int j=4,i=0 ;
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    int cntr=0 ;
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    char str1[100],str2[111];
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    FILE*ff=fopen(file_name[1],"r");
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    FILE*ft=fopen(file_name[2],"w");
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    for(j=0;j<4;++j)
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    {
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        fprintf(ft,"module sim_syn_ram%d(\n",j);
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        fprintf(ft,"        data,\n");
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        fprintf(ft,"        wraddress,\n");
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        fprintf(ft,"        rdaddress_a,\n");
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        fprintf(ft,"        rdaddress_b,\n");
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        fprintf(ft,"        wren,\n");
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        fprintf(ft,"        clock,\n");
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        fprintf(ft,"        qa,\n");
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        fprintf(ft,"        qb);\n\n");
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        fprintf(ft,"    input   [7:0]  data;\n");
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        fprintf(ft,"    input   [10:0]  wraddress;\n");
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        fprintf(ft,"    input   [10:0]  rdaddress_a;\n");
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        fprintf(ft,"    input   [10:0]  rdaddress_b;\n");
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        fprintf(ft,"    input     wren;\n");
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        fprintf(ft,"    reg [7:0]  r_data;\n");
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        fprintf(ft,"    reg [10:0]  r_wraddress;\n");
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        fprintf(ft,"    reg [10:0]  r_rdaddress_a;\n");
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        fprintf(ft,"    reg [10:0]  r_rdaddress_b;\n");
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        fprintf(ft,"    reg   r_wren;\n");
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        fprintf(ft,"    input     clock;\n");
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        fprintf(ft,"    output  [7:0]  qa;\n");
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        fprintf(ft,"    output  [7:0]  qb;\n");
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        fprintf(ft,"    reg [7:0] mem_bank  [0:2047]  ;\n");
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        fprintf(ft,"    always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;\n");
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        fprintf(ft,"     initial begin   \n");
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        rewind(ff);
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        i=-1 ;
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        while(fgets(str2,100,ff))
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        {
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            ++i ;
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            if(3==j)
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            {
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                str2[2]=0 ;
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                fprintf(ft," mem_bank[%d] = 'h%s ;",i,&str2[0]);
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                ++cntr ;
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                if(!(cntr%10))
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                {
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                    cntr==0 ;
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                    fprintf(ft,"\n ");
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                }
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            }
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            else
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            if(2==j)
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            {
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                str2[4]=0 ;
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                fprintf(ft," mem_bank[%d] = 'h%s ;",i,&str2[2]);
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                ++cntr ;
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                if(!(cntr%10))
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                {
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                    cntr==0 ;
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                    fprintf(ft,"\n ");
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                }
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            }
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            else
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            if(1==j)
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            {
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                str2[6]=0 ;
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                fprintf(ft," mem_bank[%d] = 'h%s ;",i,&str2[4]);
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                ++cntr ;
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                if(!(cntr%10))
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                {
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                    cntr==0 ;
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                    fprintf(ft,"\n ");
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                }
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            }
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            else
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            if(0==j)
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            {
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                str2[8]=0 ;
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                fprintf(ft," mem_bank[%d] = 'h%s ;",i,&str2[6]);
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                ++cntr ;
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                if(!(cntr%10))
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                {
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                    cntr==0 ;
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                    fprintf(ft,"\n ");
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                }
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            }
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        }
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        fprintf(ft,"    \nend\n always @ (posedge clock)\n");
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        fprintf(ft,"    begin\n");
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        fprintf(ft,"        r_data<=data;\n");
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        fprintf(ft,"        r_wraddress<=wraddress;\n");
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        fprintf(ft,"        r_rdaddress_a<=rdaddress_a;\n");
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        fprintf(ft,"        r_rdaddress_b<=rdaddress_b;\n");
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        fprintf(ft,"        r_wren<=wren;\n");
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        fprintf(ft,"    end\n");
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        fprintf(ft,"    assign qa =mem_bank[r_rdaddress_a];\n");
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        fprintf(ft,"    assign qb =mem_bank[r_rdaddress_b];\n");
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        fprintf(ft,"endmodule\n\n\n\n");
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    }
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}

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