OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [dbe/] [MIPS_MEM.BDE] - Blame information for rev 59

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Line No. Rev Author Line
1 2 mcupro
SCHM0103
2
 
3
HEADER
4
{
5
 FREEID 29883
6
 VARIABLES
7
 {
8
  #BLOCKTABLE_FILE="#table.bde"
9
  #BLOCKTABLE_INCLUDED="1"
10
  #LANGUAGE="VERILOG"
11
  #MODULE="mips_core1"
12
  AUTHOR="YlmF"
13
  COMPANY="WwW.YlmF.CoM"
14
  CREATIONDATE="2007-11-7"
15
  TITLE="No Title"
16
 }
17
 SYMBOL "#default" "wb_mux" "wb_mux"
18
 {
19
  HEADER
20
  {
21
   VARIABLES
22
   {
23
    #DESCRIPTION=""
24
    #LANGUAGE="VERILOG"
25
    #MODIFIED="1194410605"
26
   }
27
  }
28
  PAGE ""
29
  {
30
   PAGEHEADER
31
   {
32
    RECT (0,0,300,160)
33
    FREEID 11
34
   }
35
 
36
   BODY
37
   {
38
    RECT  1, -1, 0
39
    {
40
     VARIABLES
41
     {
42
      #OUTLINE_FILLING="1"
43
     }
44
     AREA (20,0,280,160)
45
    }
46
    TEXT  3, 0, 0
47
    {
48
     TEXT "$#NAME"
49
     RECT (25,30,148,54)
50
     ALIGN 4
51
     MARGINS (1,1)
52
     PARENT 2
53
    }
54
    TEXT  5, 0, 0
55
    {
56
     TEXT "$#NAME"
57
     RECT (163,30,275,54)
58
     ALIGN 6
59
     MARGINS (1,1)
60
     PARENT 4
61
    }
62
    TEXT  7, 0, 0
63
    {
64
     TEXT "$#NAME"
65
     RECT (25,70,159,94)
66
     ALIGN 4
67
     MARGINS (1,1)
68
     PARENT 6
69
    }
70
    TEXT  9, 0, 0
71
    {
72
     TEXT "$#NAME"
73
     RECT (25,110,60,134)
74
     ALIGN 4
75
     MARGINS (1,1)
76
     PARENT 8
77
    }
78
    PIN  2, 0, 0
79
    {
80
     COORD (0,40)
81
     VARIABLES
82
     {
83
      #DIRECTION="IN"
84
      #DOWNTO="1"
85
      #LENGTH="20"
86
      #MDA_RECORD_TOKEN="OTHER"
87
      #NAME="alu_i(31:0)"
88
      #NUMBER="0"
89
      #VERILOG_TYPE="wire"
90
     }
91
     LINE  2, 0, 0
92
     {
93
      POINTS ( (0,0), (20,0) )
94
     }
95
    }
96
    PIN  4, 0, 0
97
    {
98
     COORD (300,40)
99
     VARIABLES
100
     {
101
      #DIRECTION="OUT"
102
      #DOWNTO="1"
103
      #LENGTH="20"
104
      #MDA_RECORD_TOKEN="OTHER"
105
      #NAME="wb_o(31:0)"
106
      #NUMBER="0"
107
      #VERILOG_TYPE="wire"
108
     }
109
     LINE  2, 0, 0
110
     {
111
      POINTS ( (-20,0), (0,0) )
112
     }
113
    }
114
    PIN  6, 0, 0
115
    {
116
     COORD (0,80)
117
     VARIABLES
118
     {
119
      #DIRECTION="IN"
120
      #DOWNTO="1"
121
      #LENGTH="20"
122
      #MDA_RECORD_TOKEN="OTHER"
123
      #NAME="dmem_i(31:0)"
124
      #NUMBER="0"
125
      #VERILOG_TYPE="wire"
126
     }
127
     LINE  2, 0, 0
128
     {
129
      POINTS ( (0,0), (20,0) )
130
     }
131
    }
132
    PIN  8, 0, 0
133
    {
134
     COORD (0,120)
135
     VARIABLES
136
     {
137
      #DIRECTION="IN"
138
      #LENGTH="20"
139
      #MDA_RECORD_TOKEN="OTHER"
140
      #NAME="sel"
141
      #NUMBER="0"
142
      #VERILOG_TYPE="wire"
143
     }
144
     LINE  2, 0, 0
145
     {
146
      POINTS ( (0,0), (20,0) )
147
     }
148
    }
149
   }
150
  }
151
 }
152
 SYMBOL "#default" "r32_reg" "r32_reg"
153
 {
154
  HEADER
155
  {
156
   VARIABLES
157
   {
158
    #DESCRIPTION=""
159
    #LANGUAGE="VERILOG"
160
    #MODIFIED="1194410420"
161
   }
162
  }
163
  PAGE ""
164
  {
165
   PAGEHEADER
166
   {
167
    RECT (0,0,200,120)
168
    FREEID 8
169
   }
170
 
171
   BODY
172
   {
173
    RECT  1, -1, 0
174
    {
175
     VARIABLES
176
     {
177
      #OUTLINE_FILLING="1"
178
     }
179
     AREA (20,0,180,120)
180
    }
181
    TEXT  3, 0, 0
182
    {
183
     TEXT "$#NAME"
184
     RECT (25,30,60,54)
185
     ALIGN 4
186
     MARGINS (1,1)
187
     PARENT 2
188
    }
189
    TEXT  5, 0, 0
190
    {
191
     TEXT "$#NAME"
192
     RECT (52,30,175,54)
193
     ALIGN 6
194
     MARGINS (1,1)
195
     PARENT 4
196
    }
197
    TEXT  7, 0, 0
198
    {
199
     TEXT "$#NAME"
200
     RECT (25,70,148,94)
201
     ALIGN 4
202
     MARGINS (1,1)
203
     PARENT 6
204
    }
205
    PIN  2, 0, 0
206
    {
207
     COORD (0,40)
208
     VARIABLES
209
     {
210
      #DIRECTION="IN"
211
      #LENGTH="20"
212
      #MDA_RECORD_TOKEN="OTHER"
213
      #NAME="clk"
214
      #NUMBER="0"
215
      #VERILOG_TYPE="wire"
216
     }
217
     LINE  2, 0, 0
218
     {
219
      POINTS ( (0,0), (20,0) )
220
     }
221
    }
222
    PIN  4, 0, 0
223
    {
224
     COORD (200,40)
225
     VARIABLES
226
     {
227
      #DIRECTION="OUT"
228
      #DOWNTO="1"
229
      #LENGTH="20"
230
      #MDA_RECORD_TOKEN="OTHER"
231
      #NAME="r32_o(31:0)"
232
      #NUMBER="0"
233
      #VERILOG_TYPE="reg"
234
     }
235
     LINE  2, 0, 0
236
     {
237
      POINTS ( (-20,0), (0,0) )
238
     }
239
    }
240
    PIN  6, 0, 0
241
    {
242
     COORD (0,80)
243
     VARIABLES
244
     {
245
      #DIRECTION="IN"
246
      #DOWNTO="1"
247
      #LENGTH="20"
248
      #MDA_RECORD_TOKEN="OTHER"
249
      #NAME="r32_i(31:0)"
250
      #NUMBER="0"
251
      #VERILOG_TYPE="wire"
252
     }
253
     LINE  2, 0, 0
254
     {
255
      POINTS ( (0,0), (20,0) )
256
     }
257
    }
258
   }
259
  }
260
 }
261
 SYMBOL "#default" "r5_reg" "r5_reg"
262
 {
263
  HEADER
264
  {
265
   VARIABLES
266
   {
267
    #DESCRIPTION=""
268
    #LANGUAGE="VERILOG"
269
    #MODIFIED="1194410832"
270
   }
271
  }
272
  PAGE ""
273
  {
274
   PAGEHEADER
275
   {
276
    RECT (0,0,180,120)
277
    FREEID 8
278
   }
279
 
280
   BODY
281
   {
282
    RECT  1, -1, 0
283
    {
284
     VARIABLES
285
     {
286
      #OUTLINE_FILLING="1"
287
     }
288
     AREA (20,0,160,120)
289
    }
290
    TEXT  3, 0, 0
291
    {
292
     TEXT "$#NAME"
293
     RECT (25,30,60,54)
294
     ALIGN 4
295
     MARGINS (1,1)
296
     PARENT 2
297
    }
298
    TEXT  5, 0, 0
299
    {
300
     TEXT "$#NAME"
301
     RECT (54,30,155,54)
302
     ALIGN 6
303
     MARGINS (1,1)
304
     PARENT 4
305
    }
306
    TEXT  7, 0, 0
307
    {
308
     TEXT "$#NAME"
309
     RECT (25,70,126,94)
310
     ALIGN 4
311
     MARGINS (1,1)
312
     PARENT 6
313
    }
314
    PIN  2, 0, 0
315
    {
316
     COORD (0,40)
317
     VARIABLES
318
     {
319
      #DIRECTION="IN"
320
      #LENGTH="20"
321
      #MDA_RECORD_TOKEN="OTHER"
322
      #NAME="clk"
323
      #NUMBER="0"
324
      #VERILOG_TYPE="wire"
325
     }
326
     LINE  2, 0, 0
327
     {
328
      POINTS ( (0,0), (20,0) )
329
     }
330
    }
331
    PIN  4, 0, 0
332
    {
333
     COORD (180,40)
334
     VARIABLES
335
     {
336
      #DIRECTION="OUT"
337
      #DOWNTO="1"
338
      #LENGTH="20"
339
      #MDA_RECORD_TOKEN="OTHER"
340
      #NAME="r5_o(4:0)"
341
      #NUMBER="0"
342
      #VERILOG_TYPE="reg"
343
     }
344
     LINE  2, 0, 0
345
     {
346
      POINTS ( (-20,0), (0,0) )
347
     }
348
    }
349
    PIN  6, 0, 0
350
    {
351
     COORD (0,80)
352
     VARIABLES
353
     {
354
      #DIRECTION="IN"
355
      #DOWNTO="1"
356
      #LENGTH="20"
357
      #MDA_RECORD_TOKEN="OTHER"
358
      #NAME="r5_i(4:0)"
359
      #NUMBER="0"
360
      #VERILOG_TYPE="wire"
361
     }
362
     LINE  2, 0, 0
363
     {
364
      POINTS ( (0,0), (20,0) )
365
     }
366
    }
367
   }
368
  }
369
 }
370
 SYMBOL "#default" "or32" "or32"
371
 {
372
  HEADER
373
  {
374
   VARIABLES
375
   {
376
    #DESCRIPTION=""
377
    #LANGUAGE="VERILOG"
378
    #MODIFIED="1186304818"
379
   }
380
  }
381
  PAGE ""
382
  {
383
   PAGEHEADER
384
   {
385
    RECT (0,0,200,120)
386
    FREEID 8
387
   }
388
 
389
   BODY
390
   {
391
    RECT  1, -1, 0
392
    {
393
     VARIABLES
394
     {
395
      #OUTLINE_FILLING="1"
396
     }
397
     AREA (20,0,180,120)
398
    }
399
    TEXT  3, 0, 0
400
    {
401
     TEXT "$#NAME"
402
     RECT (25,30,104,54)
403
     ALIGN 4
404
     MARGINS (1,1)
405
     PARENT 2
406
    }
407
    TEXT  5, 0, 0
408
    {
409
     TEXT "$#NAME"
410
     RECT (96,30,175,54)
411
     ALIGN 6
412
     MARGINS (1,1)
413
     PARENT 4
414
    }
415
    TEXT  7, 0, 0
416
    {
417
     TEXT "$#NAME"
418
     RECT (25,70,104,94)
419
     ALIGN 4
420
     MARGINS (1,1)
421
     PARENT 6
422
    }
423
    PIN  2, 0, 0
424
    {
425
     COORD (0,40)
426
     VARIABLES
427
     {
428
      #DIRECTION="IN"
429
      #DOWNTO="1"
430
      #LENGTH="20"
431
      #MDA_RECORD_TOKEN="OTHER"
432
      #NAME="a(31:0)"
433
      #NUMBER="0"
434
      #VERILOG_TYPE="wire"
435
     }
436
     LINE  2, 0, 0
437
     {
438
      POINTS ( (0,0), (20,0) )
439
     }
440
    }
441
    PIN  4, 0, 0
442
    {
443
     COORD (200,40)
444
     VARIABLES
445
     {
446
      #DIRECTION="OUT"
447
      #DOWNTO="1"
448
      #LENGTH="20"
449
      #MDA_RECORD_TOKEN="OTHER"
450
      #NAME="c(31:0)"
451
      #NUMBER="0"
452
      #VERILOG_TYPE="wire"
453
     }
454
     LINE  2, 0, 0
455
     {
456
      POINTS ( (-20,0), (0,0) )
457
     }
458
    }
459
    PIN  6, 0, 0
460
    {
461
     COORD (0,80)
462
     VARIABLES
463
     {
464
      #DIRECTION="IN"
465
      #DOWNTO="1"
466
      #LENGTH="20"
467
      #MDA_RECORD_TOKEN="OTHER"
468
      #NAME="b(31:0)"
469
      #NUMBER="0"
470
      #VERILOG_TYPE="wire"
471
     }
472
     LINE  2, 0, 0
473
     {
474
      POINTS ( (0,0), (20,0) )
475
     }
476
    }
477
   }
478
  }
479
 }
480
 SYMBOL "#default" "decode_pipe3" "decode_pipe3"
481
 {
482
  HEADER
483
  {
484
   VARIABLES
485
   {
486
    #DESCRIPTION=""
487
    #LANGUAGE="VERILOG"
488
    #MODIFIED="1218351593"
489
   }
490
  }
491
  PAGE ""
492
  {
493
   PAGEHEADER
494
   {
495
    RECT (0,0,360,560)
496
    FREEID 38
497
   }
498
 
499
   BODY
500
   {
501
    RECT  1, -1, 0
502
    {
503
     VARIABLES
504
     {
505
      #OUTLINE_FILLING="1"
506
     }
507
     AREA (20,0,340,560)
508
    }
509
    TEXT  3, 0, 0
510
    {
511
     TEXT "$#NAME"
512
     RECT (25,30,60,54)
513
     ALIGN 4
514
     MARGINS (1,1)
515
     PARENT 2
516
    }
517
    TEXT  5, 0, 0
518
    {
519
     TEXT "$#NAME"
520
     RECT (168,30,335,54)
521
     ALIGN 6
522
     MARGINS (1,1)
523
     PARENT 4
524
    }
525
    TEXT  7, 0, 0
526
    {
527
     TEXT "$#NAME"
528
     RECT (25,70,170,94)
529
     ALIGN 4
530
     MARGINS (1,1)
531
     PARENT 6
532
    }
533
    TEXT  9, 0, 0
534
    {
535
     TEXT "$#NAME"
536
     RECT (190,70,335,94)
537
     ALIGN 6
538
     MARGINS (1,1)
539
     PARENT 8
540
    }
541
    TEXT  11, 0, 0
542
    {
543
     TEXT "$#NAME"
544
     RECT (25,110,170,134)
545
     ALIGN 4
546
     MARGINS (1,1)
547
     PARENT 10
548
    }
549
    TEXT  13, 0, 0
550
    {
551
     TEXT "$#NAME"
552
     RECT (179,110,335,134)
553
     ALIGN 6
554
     MARGINS (1,1)
555
     PARENT 12
556
    }
557
    TEXT  15, 0, 0
558
    {
559
     TEXT "$#NAME"
560
     RECT (25,150,148,174)
561
     ALIGN 4
562
     MARGINS (1,1)
563
     PARENT 14
564
    }
565
    TEXT  17, 0, 0
566
    {
567
     TEXT "$#NAME"
568
     RECT (168,150,335,174)
569
     ALIGN 6
570
     MARGINS (1,1)
571
     PARENT 16
572
    }
573
    TEXT  19, 0, 0
574
    {
575
     TEXT "$#NAME"
576
     RECT (25,190,170,214)
577
     ALIGN 4
578
     MARGINS (1,1)
579
     PARENT 18
580
    }
581
    TEXT  21, 0, 0
582
    {
583
     TEXT "$#NAME"
584
     RECT (135,190,335,214)
585
     ALIGN 6
586
     MARGINS (1,1)
587
     PARENT 20
588
    }
589
    TEXT  23, 0, 0
590
    {
591
     TEXT "$#NAME"
592
     RECT (179,230,335,254)
593
     ALIGN 6
594
     MARGINS (1,1)
595
     PARENT 22
596
    }
597
    TEXT  25, 0, 0
598
    {
599
     TEXT "$#NAME"
600
     RECT (201,270,335,294)
601
     ALIGN 6
602
     MARGINS (1,1)
603
     PARENT 24
604
    }
605
    TEXT  27, 0, 0
606
    {
607
     TEXT "$#NAME"
608
     RECT (168,310,335,334)
609
     ALIGN 6
610
     MARGINS (1,1)
611
     PARENT 26
612
    }
613
    TEXT  29, 0, 0
614
    {
615
     TEXT "$#NAME"
616
     RECT (168,350,335,374)
617
     ALIGN 6
618
     MARGINS (1,1)
619
     PARENT 28
620
    }
621
    TEXT  31, 0, 0
622
    {
623
     TEXT "$#NAME"
624
     RECT (146,390,335,414)
625
     ALIGN 6
626
     MARGINS (1,1)
627
     PARENT 30
628
    }
629
    TEXT  33, 0, 0
630
    {
631
     TEXT "$#NAME"
632
     RECT (190,430,335,454)
633
     ALIGN 6
634
     MARGINS (1,1)
635
     PARENT 32
636
    }
637
    TEXT  35, 0, 0
638
    {
639
     TEXT "$#NAME"
640
     RECT (146,470,335,494)
641
     ALIGN 6
642
     MARGINS (1,1)
643
     PARENT 34
644
    }
645
    TEXT  37, 0, 0
646
    {
647
     TEXT "$#NAME"
648
     RECT (201,510,335,534)
649
     ALIGN 6
650
     MARGINS (1,1)
651
     PARENT 36
652
    }
653
    PIN  2, 0, 0
654
    {
655
     COORD (0,40)
656
     VARIABLES
657
     {
658
      #DIRECTION="IN"
659
      #LENGTH="20"
660
      #MDA_RECORD_TOKEN="OTHER"
661
      #NAME="clk"
662
      #NUMBER="0"
663
      #VERILOG_TYPE="wire"
664
     }
665
     LINE  2, 0, 0
666
     {
667
      POINTS ( (0,0), (20,0) )
668
     }
669
    }
670
    PIN  4, 0, 0
671
    {
672
     COORD (360,40)
673
     VARIABLES
674
     {
675
      #DIRECTION="OUT"
676
      #DOWNTO="1"
677
      #LENGTH="20"
678
      #MDA_RECORD_TOKEN="OTHER"
679
      #NAME="alu_func_o(4:0)"
680
      #NUMBER="0"
681
      #VERILOG_TYPE="wire"
682
     }
683
     LINE  2, 0, 0
684
     {
685
      POINTS ( (-20,0), (0,0) )
686
     }
687
    }
688
    PIN  6, 0, 0
689
    {
690
     COORD (0,80)
691
     VARIABLES
692
     {
693
      #DIRECTION="IN"
694
      #LENGTH="20"
695
      #MDA_RECORD_TOKEN="OTHER"
696
      #NAME="id2ra_ctl_clr"
697
      #NUMBER="0"
698
      #VERILOG_TYPE="wire"
699
     }
700
     LINE  2, 0, 0
701
     {
702
      POINTS ( (0,0), (20,0) )
703
     }
704
    }
705
    PIN  8, 0, 0
706
    {
707
     COORD (360,80)
708
     VARIABLES
709
     {
710
      #DIRECTION="OUT"
711
      #DOWNTO="1"
712
      #LENGTH="20"
713
      #MDA_RECORD_TOKEN="OTHER"
714
      #NAME="alu_we_o(0:0)"
715
      #NUMBER="0"
716
      #VERILOG_TYPE="wire"
717
     }
718
     LINE  2, 0, 0
719
     {
720
      POINTS ( (-20,0), (0,0) )
721
     }
722
    }
723
    PIN  10, 0, 0
724
    {
725
     COORD (0,120)
726
     VARIABLES
727
     {
728
      #DIRECTION="IN"
729
      #LENGTH="20"
730
      #MDA_RECORD_TOKEN="OTHER"
731
      #NAME="id2ra_ctl_cls"
732
      #NUMBER="0"
733
      #VERILOG_TYPE="wire"
734
     }
735
     LINE  2, 0, 0
736
     {
737
      POINTS ( (0,0), (20,0) )
738
     }
739
    }
740
    PIN  12, 0, 0
741
    {
742
     COORD (360,120)
743
     VARIABLES
744
     {
745
      #DIRECTION="OUT"
746
      #DOWNTO="1"
747
      #LENGTH="20"
748
      #MDA_RECORD_TOKEN="OTHER"
749
      #NAME="cmp_ctl_o(2:0)"
750
      #NUMBER="0"
751
      #VERILOG_TYPE="wire"
752
     }
753
     LINE  2, 0, 0
754
     {
755
      POINTS ( (-20,0), (0,0) )
756
     }
757
    }
758
    PIN  14, 0, 0
759
    {
760
     COORD (0,160)
761
     VARIABLES
762
     {
763
      #DIRECTION="IN"
764
      #DOWNTO="1"
765
      #LENGTH="20"
766
      #MDA_RECORD_TOKEN="OTHER"
767
      #NAME="ins_i(31:0)"
768
      #NUMBER="0"
769
      #VERILOG_TYPE="wire"
770
     }
771
     LINE  2, 0, 0
772
     {
773
      POINTS ( (0,0), (20,0) )
774
     }
775
    }
776
    PIN  16, 0, 0
777
    {
778
     COORD (360,160)
779
     VARIABLES
780
     {
781
      #DIRECTION="OUT"
782
      #DOWNTO="1"
783
      #LENGTH="20"
784
      #MDA_RECORD_TOKEN="OTHER"
785
      #NAME="dmem_ctl_o(3:0)"
786
      #NUMBER="0"
787
      #VERILOG_TYPE="wire"
788
     }
789
     LINE  2, 0, 0
790
     {
791
      POINTS ( (-20,0), (0,0) )
792
     }
793
    }
794
    PIN  18, 0, 0
795
    {
796
     COORD (0,200)
797
     VARIABLES
798
     {
799
      #DIRECTION="IN"
800
      #LENGTH="20"
801
      #MDA_RECORD_TOKEN="OTHER"
802
      #NAME="ra2ex_ctl_clr"
803
      #NUMBER="0"
804
      #VERILOG_TYPE="wire"
805
     }
806
     LINE  2, 0, 0
807
     {
808
      POINTS ( (0,0), (20,0) )
809
     }
810
    }
811
    PIN  20, 0, 0
812
    {
813
     COORD (360,200)
814
     VARIABLES
815
     {
816
      #DIRECTION="OUT"
817
      #DOWNTO="1"
818
      #LENGTH="20"
819
      #MDA_RECORD_TOKEN="OTHER"
820
      #NAME="dmem_ctl_ur_o(3:0)"
821
      #NUMBER="0"
822
      #VERILOG_TYPE="wire"
823
     }
824
     LINE  2, 0, 0
825
     {
826
      POINTS ( (-20,0), (0,0) )
827
     }
828
    }
829
    PIN  22, 0, 0
830
    {
831
     COORD (360,240)
832
     VARIABLES
833
     {
834
      #DIRECTION="OUT"
835
      #DOWNTO="1"
836
      #LENGTH="20"
837
      #MDA_RECORD_TOKEN="OTHER"
838
      #NAME="ext_ctl_o(2:0)"
839
      #NUMBER="0"
840
      #VERILOG_TYPE="wire"
841
     }
842
     LINE  2, 0, 0
843
     {
844
      POINTS ( (-20,0), (0,0) )
845
     }
846
    }
847
    PIN  24, 0, 0
848
    {
849
     COORD (360,280)
850
     VARIABLES
851
     {
852
      #DIRECTION="OUT"
853
      #DOWNTO="1"
854
      #LENGTH="20"
855
      #MDA_RECORD_TOKEN="OTHER"
856
      #NAME="fsm_dly(2:0)"
857
      #NUMBER="0"
858
      #VERILOG_TYPE="wire"
859
     }
860
     LINE  2, 0, 0
861
     {
862
      POINTS ( (-20,0), (0,0) )
863
     }
864
    }
865
    PIN  26, 0, 0
866
    {
867
     COORD (360,320)
868
     VARIABLES
869
     {
870
      #DIRECTION="OUT"
871
      #DOWNTO="1"
872
      #LENGTH="20"
873
      #MDA_RECORD_TOKEN="OTHER"
874
      #NAME="muxa_ctl_o(1:0)"
875
      #NUMBER="0"
876
      #VERILOG_TYPE="wire"
877
     }
878
     LINE  2, 0, 0
879
     {
880
      POINTS ( (-20,0), (0,0) )
881
     }
882
    }
883
    PIN  28, 0, 0
884
    {
885
     COORD (360,360)
886
     VARIABLES
887
     {
888
      #DIRECTION="OUT"
889
      #DOWNTO="1"
890
      #LENGTH="20"
891
      #MDA_RECORD_TOKEN="OTHER"
892
      #NAME="muxb_ctl_o(1:0)"
893
      #NUMBER="0"
894
      #VERILOG_TYPE="wire"
895
     }
896
     LINE  2, 0, 0
897
     {
898
      POINTS ( (-20,0), (0,0) )
899
     }
900
    }
901
    PIN  30, 0, 0
902
    {
903
     COORD (360,400)
904
     VARIABLES
905
     {
906
      #DIRECTION="OUT"
907
      #DOWNTO="1"
908
      #LENGTH="20"
909
      #MDA_RECORD_TOKEN="OTHER"
910
      #NAME="pc_gen_ctl_o(2:0)"
911
      #NUMBER="0"
912
      #VERILOG_TYPE="wire"
913
     }
914
     LINE  2, 0, 0
915
     {
916
      POINTS ( (-20,0), (0,0) )
917
     }
918
    }
919
    PIN  32, 0, 0
920
    {
921
     COORD (360,440)
922
     VARIABLES
923
     {
924
      #DIRECTION="OUT"
925
      #DOWNTO="1"
926
      #LENGTH="20"
927
      #MDA_RECORD_TOKEN="OTHER"
928
      #NAME="rd_sel_o(1:0)"
929
      #NUMBER="0"
930
      #VERILOG_TYPE="wire"
931
     }
932
     LINE  2, 0, 0
933
     {
934
      POINTS ( (-20,0), (0,0) )
935
     }
936
    }
937
    PIN  34, 0, 0
938
    {
939
     COORD (360,480)
940
     VARIABLES
941
     {
942
      #DIRECTION="OUT"
943
      #DOWNTO="1"
944
      #LENGTH="20"
945
      #MDA_RECORD_TOKEN="OTHER"
946
      #NAME="wb_mux_ctl_o(0:0)"
947
      #NUMBER="0"
948
      #VERILOG_TYPE="wire"
949
     }
950
     LINE  2, 0, 0
951
     {
952
      POINTS ( (-20,0), (0,0) )
953
     }
954
    }
955
    PIN  36, 0, 0
956
    {
957
     COORD (360,520)
958
     VARIABLES
959
     {
960
      #DIRECTION="OUT"
961
      #DOWNTO="1"
962
      #LENGTH="20"
963
      #MDA_RECORD_TOKEN="OTHER"
964
      #NAME="wb_we_o(0:0)"
965
      #NUMBER="0"
966
      #VERILOG_TYPE="wire"
967
     }
968
     LINE  2, 0, 0
969
     {
970
      POINTS ( (-20,0), (0,0) )
971
     }
972
    }
973
   }
974
  }
975
 }
976
 SYMBOL "#default" "forward2" "forward2"
977
 {
978
  HEADER
979
  {
980
   VARIABLES
981
   {
982
    #DESCRIPTION=""
983
    #LANGUAGE="VERILOG"
984
    #MODIFIED="1218651422"
985
   }
986
  }
987
  PAGE ""
988
  {
989
   PAGEHEADER
990
   {
991
    RECT (-40,0,340,320)
992
    FREEID 27
993
   }
994
 
995
   BODY
996
   {
997
    RECT  1, -1, 0
998
    {
999
     VARIABLES
1000
     {
1001
      #OUTLINE_FILLING="1"
1002
     }
1003
     AREA (-20,0,320,320)
1004
    }
1005
    TEXT  3, 0, 0
1006
    {
1007
     TEXT "$#NAME"
1008
     RECT (-15,30,53,54)
1009
     ALIGN 4
1010
     MARGINS (1,1)
1011
     PARENT 2
1012
    }
1013
    TEXT  5, 0, 0
1014
    {
1015
     TEXT "$#NAME"
1016
     RECT (159,30,315,54)
1017
     ALIGN 6
1018
     MARGINS (1,1)
1019
     PARENT 4
1020
    }
1021
    TEXT  7, 0, 0
1022
    {
1023
     TEXT "$#NAME"
1024
     RECT (-15,70,20,94)
1025
     ALIGN 4
1026
     MARGINS (1,1)
1027
     PARENT 6
1028
    }
1029
    TEXT  9, 0, 0
1030
    {
1031
     TEXT "$#NAME"
1032
     RECT (159,70,315,94)
1033
     ALIGN 6
1034
     MARGINS (1,1)
1035
     PARENT 8
1036
    }
1037
    TEXT  11, 0, 0
1038
    {
1039
     TEXT "$#NAME"
1040
     RECT (-15,110,141,134)
1041
     ALIGN 4
1042
     MARGINS (1,1)
1043
     PARENT 10
1044
    }
1045
    TEXT  13, 0, 0
1046
    {
1047
     TEXT "$#NAME"
1048
     RECT (159,110,315,134)
1049
     ALIGN 6
1050
     MARGINS (1,1)
1051
     PARENT 12
1052
    }
1053
    TEXT  15, 0, 0
1054
    {
1055
     TEXT "$#NAME"
1056
     RECT (-15,150,141,174)
1057
     ALIGN 4
1058
     MARGINS (1,1)
1059
     PARENT 14
1060
    }
1061
    TEXT  17, 0, 0
1062
    {
1063
     TEXT "$#NAME"
1064
     RECT (159,150,315,174)
1065
     ALIGN 6
1066
     MARGINS (1,1)
1067
     PARENT 16
1068
    }
1069
    TEXT  19, 0, 0
1070
    {
1071
     TEXT "$#NAME"
1072
     RECT (-15,190,53,214)
1073
     ALIGN 4
1074
     MARGINS (1,1)
1075
     PARENT 18
1076
    }
1077
    TEXT  21, 0, 0
1078
    {
1079
     TEXT "$#NAME"
1080
     RECT (181,190,315,214)
1081
     ALIGN 6
1082
     MARGINS (1,1)
1083
     PARENT 20
1084
    }
1085
    TEXT  23, 0, 0
1086
    {
1087
     TEXT "$#NAME"
1088
     RECT (-15,230,97,254)
1089
     ALIGN 4
1090
     MARGINS (1,1)
1091
     PARENT 22
1092
    }
1093
    TEXT  25, 0, 0
1094
    {
1095
     TEXT "$#NAME"
1096
     RECT (-15,270,97,294)
1097
     ALIGN 4
1098
     MARGINS (1,1)
1099
     PARENT 24
1100
    }
1101
    PIN  2, 0, 0
1102
    {
1103
     COORD (-40,40)
1104
     VARIABLES
1105
     {
1106
      #DIRECTION="IN"
1107
      #LENGTH="20"
1108
      #MDA_RECORD_TOKEN="OTHER"
1109
      #NAME="alu_we"
1110
      #NUMBER="0"
1111
      #VERILOG_TYPE="wire"
1112
     }
1113
     LINE  2, 0, 0
1114
     {
1115
      POINTS ( (0,0), (20,0) )
1116
     }
1117
    }
1118
    PIN  4, 0, 0
1119
    {
1120
     COORD (340,40)
1121
     VARIABLES
1122
     {
1123
      #DIRECTION="OUT"
1124
      #DOWNTO="1"
1125
      #LENGTH="20"
1126
      #MDA_RECORD_TOKEN="OTHER"
1127
      #NAME="alu_rs_fw(2:0)"
1128
      #NUMBER="0"
1129
      #VERILOG_TYPE="wire"
1130
     }
1131
     LINE  2, 0, 0
1132
     {
1133
      POINTS ( (-20,0), (0,0) )
1134
     }
1135
    }
1136
    PIN  6, 0, 0
1137
    {
1138
     COORD (-40,80)
1139
     VARIABLES
1140
     {
1141
      #DIRECTION="IN"
1142
      #LENGTH="20"
1143
      #MDA_RECORD_TOKEN="OTHER"
1144
      #NAME="clk"
1145
      #NUMBER="0"
1146
      #VERILOG_TYPE="wire"
1147
     }
1148
     LINE  2, 0, 0
1149
     {
1150
      POINTS ( (0,0), (20,0) )
1151
     }
1152
    }
1153
    PIN  8, 0, 0
1154
    {
1155
     COORD (340,80)
1156
     VARIABLES
1157
     {
1158
      #DIRECTION="OUT"
1159
      #DOWNTO="1"
1160
      #LENGTH="20"
1161
      #MDA_RECORD_TOKEN="OTHER"
1162
      #NAME="alu_rt_fw(2:0)"
1163
      #NUMBER="0"
1164
      #VERILOG_TYPE="wire"
1165
     }
1166
     LINE  2, 0, 0
1167
     {
1168
      POINTS ( (-20,0), (0,0) )
1169
     }
1170
    }
1171
    PIN  10, 0, 0
1172
    {
1173
     COORD (-40,120)
1174
     VARIABLES
1175
     {
1176
      #DIRECTION="IN"
1177
      #DOWNTO="1"
1178
      #LENGTH="20"
1179
      #MDA_RECORD_TOKEN="OTHER"
1180
      #NAME="fw_alu_rn(4:0)"
1181
      #NUMBER="0"
1182
      #VERILOG_TYPE="wire"
1183
     }
1184
     LINE  2, 0, 0
1185
     {
1186
      POINTS ( (0,0), (20,0) )
1187
     }
1188
    }
1189
    PIN  12, 0, 0
1190
    {
1191
     COORD (340,120)
1192
     VARIABLES
1193
     {
1194
      #DIRECTION="OUT"
1195
      #DOWNTO="1"
1196
      #LENGTH="20"
1197
      #MDA_RECORD_TOKEN="OTHER"
1198
      #NAME="cmp_rs_fw(2:0)"
1199
      #NUMBER="0"
1200
      #VERILOG_TYPE="wire"
1201
     }
1202
     LINE  2, 0, 0
1203
     {
1204
      POINTS ( (-20,0), (0,0) )
1205
     }
1206
    }
1207
    PIN  14, 0, 0
1208
    {
1209
     COORD (-40,160)
1210
     VARIABLES
1211
     {
1212
      #DIRECTION="IN"
1213
      #DOWNTO="1"
1214
      #LENGTH="20"
1215
      #MDA_RECORD_TOKEN="OTHER"
1216
      #NAME="fw_mem_rn(4:0)"
1217
      #NUMBER="0"
1218
      #VERILOG_TYPE="wire"
1219
     }
1220
     LINE  2, 0, 0
1221
     {
1222
      POINTS ( (0,0), (20,0) )
1223
     }
1224
    }
1225
    PIN  16, 0, 0
1226
    {
1227
     COORD (340,160)
1228
     VARIABLES
1229
     {
1230
      #DIRECTION="OUT"
1231
      #DOWNTO="1"
1232
      #LENGTH="20"
1233
      #MDA_RECORD_TOKEN="OTHER"
1234
      #NAME="cmp_rt_fw(2:0)"
1235
      #NUMBER="0"
1236
      #VERILOG_TYPE="wire"
1237
     }
1238
     LINE  2, 0, 0
1239
     {
1240
      POINTS ( (-20,0), (0,0) )
1241
     }
1242
    }
1243
    PIN  18, 0, 0
1244
    {
1245
     COORD (-40,200)
1246
     VARIABLES
1247
     {
1248
      #DIRECTION="IN"
1249
      #LENGTH="20"
1250
      #MDA_RECORD_TOKEN="OTHER"
1251
      #NAME="mem_We"
1252
      #NUMBER="0"
1253
      #VERILOG_TYPE="wire"
1254
     }
1255
     LINE  2, 0, 0
1256
     {
1257
      POINTS ( (0,0), (20,0) )
1258
     }
1259
    }
1260
    PIN  20, 0, 0
1261
    {
1262
     COORD (340,200)
1263
     VARIABLES
1264
     {
1265
      #DIRECTION="OUT"
1266
      #DOWNTO="1"
1267
      #LENGTH="20"
1268
      #MDA_RECORD_TOKEN="OTHER"
1269
      #NAME="dmem_fw(2:0)"
1270
      #NUMBER="0"
1271
      #VERILOG_TYPE="wire"
1272
     }
1273
     LINE  2, 0, 0
1274
     {
1275
      POINTS ( (-20,0), (0,0) )
1276
     }
1277
    }
1278
    PIN  22, 0, 0
1279
    {
1280
     COORD (-40,240)
1281
     VARIABLES
1282
     {
1283
      #DIRECTION="IN"
1284
      #DOWNTO="1"
1285
      #LENGTH="20"
1286
      #MDA_RECORD_TOKEN="OTHER"
1287
      #NAME="rns_i(4:0)"
1288
      #NUMBER="0"
1289
      #VERILOG_TYPE="wire"
1290
     }
1291
     LINE  2, 0, 0
1292
     {
1293
      POINTS ( (0,0), (20,0) )
1294
     }
1295
    }
1296
    PIN  24, 0, 0
1297
    {
1298
     COORD (-40,280)
1299
     VARIABLES
1300
     {
1301
      #DIRECTION="IN"
1302
      #DOWNTO="1"
1303
      #LENGTH="20"
1304
      #MDA_RECORD_TOKEN="OTHER"
1305
      #NAME="rnt_i(4:0)"
1306
      #NUMBER="0"
1307
      #VERILOG_TYPE="wire"
1308
     }
1309
     LINE  2, 0, 0
1310
     {
1311
      POINTS ( (0,0), (20,0) )
1312
     }
1313
    }
1314
   }
1315
  }
1316
 }
1317
 SYMBOL "#default" "mem_module1" "mem_module1"
1318
 {
1319
  HEADER
1320
  {
1321
   VARIABLES
1322
   {
1323
    #DESCRIPTION=""
1324
    #LANGUAGE="VERILOG"
1325
    #MODIFIED="1218620775"
1326
   }
1327
  }
1328
  PAGE ""
1329
  {
1330
   PAGEHEADER
1331
   {
1332
    RECT (0,0,400,240)
1333
    FREEID 21
1334
   }
1335
 
1336
   BODY
1337
   {
1338
    RECT  1, -1, 0
1339
    {
1340
     VARIABLES
1341
     {
1342
      #OUTLINE_FILLING="1"
1343
     }
1344
     AREA (20,0,380,240)
1345
    }
1346
    TEXT  3, 0, 0
1347
    {
1348
     TEXT "$#NAME"
1349
     RECT (25,30,60,54)
1350
     ALIGN 4
1351
     MARGINS (1,1)
1352
     PARENT 2
1353
    }
1354
    TEXT  5, 0, 0
1355
    {
1356
     TEXT "$#NAME"
1357
     RECT (230,30,375,54)
1358
     ALIGN 6
1359
     MARGINS (1,1)
1360
     PARENT 4
1361
    }
1362
    TEXT  7, 0, 0
1363
    {
1364
     TEXT "$#NAME"
1365
     RECT (25,70,126,94)
1366
     ALIGN 4
1367
     MARGINS (1,1)
1368
     PARENT 6
1369
    }
1370
    TEXT  9, 0, 0
1371
    {
1372
     TEXT "$#NAME"
1373
     RECT (230,70,375,94)
1374
     ALIGN 6
1375
     MARGINS (1,1)
1376
     PARENT 8
1377
    }
1378
    TEXT  11, 0, 0
1379
    {
1380
     TEXT "$#NAME"
1381
     RECT (25,110,214,134)
1382
     ALIGN 4
1383
     MARGINS (1,1)
1384
     PARENT 10
1385
    }
1386
    TEXT  13, 0, 0
1387
    {
1388
     TEXT "$#NAME"
1389
     RECT (230,110,375,134)
1390
     ALIGN 6
1391
     MARGINS (1,1)
1392
     PARENT 12
1393
    }
1394
    TEXT  15, 0, 0
1395
    {
1396
     TEXT "$#NAME"
1397
     RECT (25,150,170,174)
1398
     ALIGN 4
1399
     MARGINS (1,1)
1400
     PARENT 14
1401
    }
1402
    TEXT  17, 0, 0
1403
    {
1404
     TEXT "$#NAME"
1405
     RECT (263,150,375,174)
1406
     ALIGN 6
1407
     MARGINS (1,1)
1408
     PARENT 16
1409
    }
1410
    TEXT  19, 0, 0
1411
    {
1412
     TEXT "$#NAME"
1413
     RECT (25,190,159,214)
1414
     ALIGN 4
1415
     MARGINS (1,1)
1416
     PARENT 18
1417
    }
1418
    PIN  2, 0, 0
1419
    {
1420
     COORD (0,40)
1421
     VARIABLES
1422
     {
1423
      #DIRECTION="IN"
1424
      #LENGTH="20"
1425
      #MDA_RECORD_TOKEN="OTHER"
1426
      #NAME="clk"
1427
      #NUMBER="0"
1428
      #VERILOG_TYPE="wire"
1429
     }
1430
     LINE  2, 0, 0
1431
     {
1432
      POINTS ( (0,0), (20,0) )
1433
     }
1434
    }
1435
    PIN  4, 0, 0
1436
    {
1437
     COORD (400,40)
1438
     VARIABLES
1439
     {
1440
      #DIRECTION="OUT"
1441
      #DOWNTO="1"
1442
      #LENGTH="20"
1443
      #MDA_RECORD_TOKEN="OTHER"
1444
      #NAME="Zz_addr(31:0)"
1445
      #NUMBER="0"
1446
      #VERILOG_TYPE="wire"
1447
     }
1448
     LINE  2, 0, 0
1449
     {
1450
      POINTS ( (-20,0), (0,0) )
1451
     }
1452
    }
1453
    PIN  6, 0, 0
1454
    {
1455
     COORD (0,80)
1456
     VARIABLES
1457
     {
1458
      #DIRECTION="IN"
1459
      #DOWNTO="1"
1460
      #LENGTH="20"
1461
      #MDA_RECORD_TOKEN="OTHER"
1462
      #NAME="din(31:0)"
1463
      #NUMBER="0"
1464
      #VERILOG_TYPE="wire"
1465
     }
1466
     LINE  2, 0, 0
1467
     {
1468
      POINTS ( (0,0), (20,0) )
1469
     }
1470
    }
1471
    PIN  8, 0, 0
1472
    {
1473
     COORD (400,80)
1474
     VARIABLES
1475
     {
1476
      #DIRECTION="OUT"
1477
      #DOWNTO="1"
1478
      #LENGTH="20"
1479
      #MDA_RECORD_TOKEN="OTHER"
1480
      #NAME="Zz_dout(31:0)"
1481
      #NUMBER="0"
1482
      #VERILOG_TYPE="wire"
1483
     }
1484
     LINE  2, 0, 0
1485
     {
1486
      POINTS ( (-20,0), (0,0) )
1487
     }
1488
    }
1489
    PIN  10, 0, 0
1490
    {
1491
     COORD (0,120)
1492
     VARIABLES
1493
     {
1494
      #DIRECTION="IN"
1495
      #DOWNTO="1"
1496
      #LENGTH="20"
1497
      #MDA_RECORD_TOKEN="OTHER"
1498
      #NAME="dmem_addr_i(31:0)"
1499
      #NUMBER="0"
1500
      #VERILOG_TYPE="wire"
1501
     }
1502
     LINE  2, 0, 0
1503
     {
1504
      POINTS ( (0,0), (20,0) )
1505
     }
1506
    }
1507
    PIN  12, 0, 0
1508
    {
1509
     COORD (400,120)
1510
     VARIABLES
1511
     {
1512
      #DIRECTION="OUT"
1513
      #DOWNTO="1"
1514
      #LENGTH="20"
1515
      #MDA_RECORD_TOKEN="OTHER"
1516
      #NAME="Zz_wr_en(3:0)"
1517
      #NUMBER="0"
1518
      #VERILOG_TYPE="wire"
1519
     }
1520
     LINE  2, 0, 0
1521
     {
1522
      POINTS ( (-20,0), (0,0) )
1523
     }
1524
    }
1525
    PIN  14, 0, 0
1526
    {
1527
     COORD (0,160)
1528
     VARIABLES
1529
     {
1530
      #DIRECTION="IN"
1531
      #DOWNTO="1"
1532
      #LENGTH="20"
1533
      #MDA_RECORD_TOKEN="OTHER"
1534
      #NAME="dmem_ctl(3:0)"
1535
      #NUMBER="0"
1536
      #VERILOG_TYPE="wire"
1537
     }
1538
     LINE  2, 0, 0
1539
     {
1540
      POINTS ( (0,0), (20,0) )
1541
     }
1542
    }
1543
    PIN  16, 0, 0
1544
    {
1545
     COORD (400,160)
1546
     VARIABLES
1547
     {
1548
      #DIRECTION="OUT"
1549
      #DOWNTO="1"
1550
      #LENGTH="20"
1551
      #MDA_RECORD_TOKEN="OTHER"
1552
      #NAME="dout(31:0)"
1553
      #NUMBER="0"
1554
      #VERILOG_TYPE="wire"
1555
     }
1556
     LINE  2, 0, 0
1557
     {
1558
      POINTS ( (-20,0), (0,0) )
1559
     }
1560
    }
1561
    PIN  18, 0, 0
1562
    {
1563
     COORD (0,200)
1564
     VARIABLES
1565
     {
1566
      #DIRECTION="IN"
1567
      #DOWNTO="1"
1568
      #LENGTH="20"
1569
      #MDA_RECORD_TOKEN="OTHER"
1570
      #NAME="zZ_din(31:0)"
1571
      #NUMBER="0"
1572
      #VERILOG_TYPE="wire"
1573
     }
1574
     LINE  2, 0, 0
1575
     {
1576
      POINTS ( (0,0), (20,0) )
1577
     }
1578
    }
1579
   }
1580
  }
1581
 }
1582
 SYMBOL "#default" "rf_stage8" "rf_stage8"
1583
 {
1584
  HEADER
1585
  {
1586
   VARIABLES
1587
   {
1588
    #DESCRIPTION=""
1589
    #LANGUAGE="VERILOG"
1590
    #MODIFIED="1218999515"
1591
   }
1592
  }
1593
  PAGE ""
1594
  {
1595
   PAGEHEADER
1596
   {
1597
    RECT (-60,0,340,800)
1598
    FREEID 63
1599
   }
1600
 
1601
   BODY
1602
   {
1603
    RECT  1, -1, 0
1604
    {
1605
     VARIABLES
1606
     {
1607
      #OUTLINE_FILLING="1"
1608
     }
1609
     AREA (-40,0,320,800)
1610
    }
1611
    TEXT  3, 0, 0
1612
    {
1613
     TEXT "$#NAME"
1614
     RECT (-35,30,0,54)
1615
     ALIGN 4
1616
     MARGINS (1,1)
1617
     PARENT 2
1618
    }
1619
    TEXT  5, 0, 0
1620
    {
1621
     TEXT "$#NAME"
1622
     RECT (192,30,315,54)
1623
     ALIGN 6
1624
     MARGINS (1,1)
1625
     PARENT 4
1626
    }
1627
    TEXT  7, 0, 0
1628
    {
1629
     TEXT "$#NAME"
1630
     RECT (-35,70,121,94)
1631
     ALIGN 4
1632
     MARGINS (1,1)
1633
     PARENT 6
1634
    }
1635
    TEXT  9, 0, 0
1636
    {
1637
     TEXT "$#NAME"
1638
     RECT (247,70,315,94)
1639
     ALIGN 6
1640
     MARGINS (1,1)
1641
     PARENT 8
1642
    }
1643
    TEXT  11, 0, 0
1644
    {
1645
     TEXT "$#NAME"
1646
     RECT (-35,110,121,134)
1647
     ALIGN 4
1648
     MARGINS (1,1)
1649
     PARENT 10
1650
    }
1651
    TEXT  13, 0, 0
1652
    {
1653
     TEXT "$#NAME"
1654
     RECT (148,110,315,134)
1655
     ALIGN 6
1656
     MARGINS (1,1)
1657
     PARENT 12
1658
    }
1659
    TEXT  15, 0, 0
1660
    {
1661
     TEXT "$#NAME"
1662
     RECT (-35,150,121,174)
1663
     ALIGN 4
1664
     MARGINS (1,1)
1665
     PARENT 14
1666
    }
1667
    TEXT  17, 0, 0
1668
    {
1669
     TEXT "$#NAME"
1670
     RECT (148,150,315,174)
1671
     ALIGN 6
1672
     MARGINS (1,1)
1673
     PARENT 16
1674
    }
1675
    TEXT  19, 0, 0
1676
    {
1677
     TEXT "$#NAME"
1678
     RECT (-35,190,121,214)
1679
     ALIGN 4
1680
     MARGINS (1,1)
1681
     PARENT 18
1682
    }
1683
    TEXT  21, 0, 0
1684
    {
1685
     TEXT "$#NAME"
1686
     RECT (170,190,315,214)
1687
     ALIGN 6
1688
     MARGINS (1,1)
1689
     PARENT 20
1690
    }
1691
    TEXT  23, 0, 0
1692
    {
1693
     TEXT "$#NAME"
1694
     RECT (-35,230,121,254)
1695
     ALIGN 4
1696
     MARGINS (1,1)
1697
     PARENT 22
1698
    }
1699
    TEXT  25, 0, 0
1700
    {
1701
     TEXT "$#NAME"
1702
     RECT (148,230,315,254)
1703
     ALIGN 6
1704
     MARGINS (1,1)
1705
     PARENT 24
1706
    }
1707
    TEXT  27, 0, 0
1708
    {
1709
     TEXT "$#NAME"
1710
     RECT (-35,270,121,294)
1711
     ALIGN 4
1712
     MARGINS (1,1)
1713
     PARENT 26
1714
    }
1715
    TEXT  29, 0, 0
1716
    {
1717
     TEXT "$#NAME"
1718
     RECT (148,270,315,294)
1719
     ALIGN 6
1720
     MARGINS (1,1)
1721
     PARENT 28
1722
    }
1723
    TEXT  31, 0, 0
1724
    {
1725
     TEXT "$#NAME"
1726
     RECT (-35,310,88,334)
1727
     ALIGN 4
1728
     MARGINS (1,1)
1729
     PARENT 30
1730
    }
1731
    TEXT  33, 0, 0
1732
    {
1733
     TEXT "$#NAME"
1734
     RECT (192,310,315,334)
1735
     ALIGN 6
1736
     MARGINS (1,1)
1737
     PARENT 32
1738
    }
1739
    TEXT  35, 0, 0
1740
    {
1741
     TEXT "$#NAME"
1742
     RECT (-35,350,88,374)
1743
     ALIGN 4
1744
     MARGINS (1,1)
1745
     PARENT 34
1746
    }
1747
    TEXT  37, 0, 0
1748
    {
1749
     TEXT "$#NAME"
1750
     RECT (203,350,315,374)
1751
     ALIGN 6
1752
     MARGINS (1,1)
1753
     PARENT 36
1754
    }
1755
    TEXT  39, 0, 0
1756
    {
1757
     TEXT "$#NAME"
1758
     RECT (-35,390,143,414)
1759
     ALIGN 4
1760
     MARGINS (1,1)
1761
     PARENT 38
1762
    }
1763
    TEXT  41, 0, 0
1764
    {
1765
     TEXT "$#NAME"
1766
     RECT (192,390,315,414)
1767
     ALIGN 6
1768
     MARGINS (1,1)
1769
     PARENT 40
1770
    }
1771
    TEXT  43, 0, 0
1772
    {
1773
     TEXT "$#NAME"
1774
     RECT (-35,430,22,454)
1775
     ALIGN 4
1776
     MARGINS (1,1)
1777
     PARENT 42
1778
    }
1779
    TEXT  45, 0, 0
1780
    {
1781
     TEXT "$#NAME"
1782
     RECT (203,430,315,454)
1783
     ALIGN 6
1784
     MARGINS (1,1)
1785
     PARENT 44
1786
    }
1787
    TEXT  47, 0, 0
1788
    {
1789
     TEXT "$#NAME"
1790
     RECT (-35,470,132,494)
1791
     ALIGN 4
1792
     MARGINS (1,1)
1793
     PARENT 46
1794
    }
1795
    TEXT  49, 0, 0
1796
    {
1797
     TEXT "$#NAME"
1798
     RECT (-35,510,77,534)
1799
     ALIGN 4
1800
     MARGINS (1,1)
1801
     PARENT 48
1802
    }
1803
    TEXT  51, 0, 0
1804
    {
1805
     TEXT "$#NAME"
1806
     RECT (-35,550,110,574)
1807
     ALIGN 4
1808
     MARGINS (1,1)
1809
     PARENT 50
1810
    }
1811
    TEXT  53, 0, 0
1812
    {
1813
     TEXT "$#NAME"
1814
     RECT (-35,590,22,614)
1815
     ALIGN 4
1816
     MARGINS (1,1)
1817
     PARENT 52
1818
    }
1819
    TEXT  55, 0, 0
1820
    {
1821
     TEXT "$#NAME"
1822
     RECT (-35,630,121,654)
1823
     ALIGN 4
1824
     MARGINS (1,1)
1825
     PARENT 54
1826
    }
1827
    TEXT  57, 0, 0
1828
    {
1829
     TEXT "$#NAME"
1830
     RECT (-35,670,121,694)
1831
     ALIGN 4
1832
     MARGINS (1,1)
1833
     PARENT 56
1834
    }
1835
    TEXT  59, 0, 0
1836
    {
1837
     TEXT "$#NAME"
1838
     RECT (-35,710,44,734)
1839
     ALIGN 4
1840
     MARGINS (1,1)
1841
     PARENT 58
1842
    }
1843
    TEXT  61, 0, 0
1844
    {
1845
     TEXT "$#NAME"
1846
     RECT (-35,750,121,774)
1847
     ALIGN 4
1848
     MARGINS (1,1)
1849
     PARENT 60
1850
    }
1851
    PIN  2, 0, 0
1852
    {
1853
     COORD (-60,40)
1854
     VARIABLES
1855
     {
1856
      #DIRECTION="IN"
1857
      #LENGTH="20"
1858
      #MDA_RECORD_TOKEN="OTHER"
1859
      #NAME="clk"
1860
      #NUMBER="0"
1861
      #VERILOG_TYPE="wire"
1862
     }
1863
     LINE  2, 0, 0
1864
     {
1865
      POINTS ( (0,0), (20,0) )
1866
     }
1867
    }
1868
    PIN  4, 0, 0
1869
    {
1870
     COORD (340,40)
1871
     VARIABLES
1872
     {
1873
      #DIRECTION="OUT"
1874
      #DOWNTO="1"
1875
      #LENGTH="20"
1876
      #MDA_RECORD_TOKEN="OTHER"
1877
      #NAME="ext_o(31:0)"
1878
      #NUMBER="0"
1879
      #VERILOG_TYPE="wire"
1880
     }
1881
     LINE  2, 0, 0
1882
     {
1883
      POINTS ( (-20,0), (0,0) )
1884
     }
1885
    }
1886
    PIN  6, 0, 0
1887
    {
1888
     COORD (-60,80)
1889
     VARIABLES
1890
     {
1891
      #DIRECTION="IN"
1892
      #DOWNTO="1"
1893
      #LENGTH="20"
1894
      #MDA_RECORD_TOKEN="OTHER"
1895
      #NAME="cmp_ctl_i(2:0)"
1896
      #NUMBER="0"
1897
      #VERILOG_TYPE="wire"
1898
     }
1899
     LINE  2, 0, 0
1900
     {
1901
      POINTS ( (0,0), (20,0) )
1902
     }
1903
    }
1904
    PIN  8, 0, 0
1905
    {
1906
     COORD (340,80)
1907
     VARIABLES
1908
     {
1909
      #DIRECTION="OUT"
1910
      #LENGTH="20"
1911
      #MDA_RECORD_TOKEN="OTHER"
1912
      #NAME="iack_o"
1913
      #NUMBER="0"
1914
      #VERILOG_TYPE="wire"
1915
     }
1916
     LINE  2, 0, 0
1917
     {
1918
      POINTS ( (-20,0), (0,0) )
1919
     }
1920
    }
1921
    PIN  10, 0, 0
1922
    {
1923
     COORD (-60,120)
1924
     VARIABLES
1925
     {
1926
      #DIRECTION="IN"
1927
      #DOWNTO="1"
1928
      #LENGTH="20"
1929
      #MDA_RECORD_TOKEN="OTHER"
1930
      #NAME="ext_ctl_i(2:0)"
1931
      #NUMBER="0"
1932
      #VERILOG_TYPE="wire"
1933
     }
1934
     LINE  2, 0, 0
1935
     {
1936
      POINTS ( (0,0), (20,0) )
1937
     }
1938
    }
1939
    PIN  12, 0, 0
1940
    {
1941
     COORD (340,120)
1942
     VARIABLES
1943
     {
1944
      #DIRECTION="OUT"
1945
      #LENGTH="20"
1946
      #MDA_RECORD_TOKEN="OTHER"
1947
      #NAME="id2ra_ctl_clr_o"
1948
      #NUMBER="0"
1949
      #VERILOG_TYPE="wire"
1950
     }
1951
     LINE  2, 0, 0
1952
     {
1953
      POINTS ( (-20,0), (0,0) )
1954
     }
1955
    }
1956
    PIN  14, 0, 0
1957
    {
1958
     COORD (-60,160)
1959
     VARIABLES
1960
     {
1961
      #DIRECTION="IN"
1962
      #DOWNTO="1"
1963
      #LENGTH="20"
1964
      #MDA_RECORD_TOKEN="OTHER"
1965
      #NAME="fw_alu_i(31:0)"
1966
      #NUMBER="0"
1967
      #VERILOG_TYPE="wire"
1968
     }
1969
     LINE  2, 0, 0
1970
     {
1971
      POINTS ( (0,0), (20,0) )
1972
     }
1973
    }
1974
    PIN  16, 0, 0
1975
    {
1976
     COORD (340,160)
1977
     VARIABLES
1978
     {
1979
      #DIRECTION="OUT"
1980
      #LENGTH="20"
1981
      #MDA_RECORD_TOKEN="OTHER"
1982
      #NAME="id2ra_ctl_cls_o"
1983
      #NUMBER="0"
1984
      #VERILOG_TYPE="wire"
1985
     }
1986
     LINE  2, 0, 0
1987
     {
1988
      POINTS ( (-20,0), (0,0) )
1989
     }
1990
    }
1991
    PIN  18, 0, 0
1992
    {
1993
     COORD (-60,200)
1994
     VARIABLES
1995
     {
1996
      #DIRECTION="IN"
1997
      #DOWNTO="1"
1998
      #LENGTH="20"
1999
      #MDA_RECORD_TOKEN="OTHER"
2000
      #NAME="fw_cmp_rs(2:0)"
2001
      #NUMBER="0"
2002
      #VERILOG_TYPE="wire"
2003
     }
2004
     LINE  2, 0, 0
2005
     {
2006
      POINTS ( (0,0), (20,0) )
2007
     }
2008
    }
2009
    PIN  20, 0, 0
2010
    {
2011
     COORD (340,200)
2012
     VARIABLES
2013
     {
2014
      #DIRECTION="OUT"
2015
      #DOWNTO="1"
2016
      #LENGTH="20"
2017
      #MDA_RECORD_TOKEN="OTHER"
2018
      #NAME="pc_next(31:0)"
2019
      #NUMBER="0"
2020
      #VERILOG_TYPE="wire"
2021
     }
2022
     LINE  2, 0, 0
2023
     {
2024
      POINTS ( (-20,0), (0,0) )
2025
     }
2026
    }
2027
    PIN  22, 0, 0
2028
    {
2029
     COORD (-60,240)
2030
     VARIABLES
2031
     {
2032
      #DIRECTION="IN"
2033
      #DOWNTO="1"
2034
      #LENGTH="20"
2035
      #MDA_RECORD_TOKEN="OTHER"
2036
      #NAME="fw_cmp_rt(2:0)"
2037
      #NUMBER="0"
2038
      #VERILOG_TYPE="wire"
2039
     }
2040
     LINE  2, 0, 0
2041
     {
2042
      POINTS ( (0,0), (20,0) )
2043
     }
2044
    }
2045
    PIN  24, 0, 0
2046
    {
2047
     COORD (340,240)
2048
     VARIABLES
2049
     {
2050
      #DIRECTION="OUT"
2051
      #LENGTH="20"
2052
      #MDA_RECORD_TOKEN="OTHER"
2053
      #NAME="ra2ex_ctl_clr_o"
2054
      #NUMBER="0"
2055
      #VERILOG_TYPE="wire"
2056
     }
2057
     LINE  2, 0, 0
2058
     {
2059
      POINTS ( (-20,0), (0,0) )
2060
     }
2061
    }
2062
    PIN  26, 0, 0
2063
    {
2064
     COORD (-60,280)
2065
     VARIABLES
2066
     {
2067
      #DIRECTION="IN"
2068
      #DOWNTO="1"
2069
      #LENGTH="20"
2070
      #MDA_RECORD_TOKEN="OTHER"
2071
      #NAME="fw_mem_i(31:0)"
2072
      #NUMBER="0"
2073
      #VERILOG_TYPE="wire"
2074
     }
2075
     LINE  2, 0, 0
2076
     {
2077
      POINTS ( (0,0), (20,0) )
2078
     }
2079
    }
2080
    PIN  28, 0, 0
2081
    {
2082
     COORD (340,280)
2083
     VARIABLES
2084
     {
2085
      #DIRECTION="OUT"
2086
      #DOWNTO="1"
2087
      #LENGTH="20"
2088
      #MDA_RECORD_TOKEN="OTHER"
2089
      #NAME="rd_index_o(4:0)"
2090
      #NUMBER="0"
2091
      #VERILOG_TYPE="wire"
2092
     }
2093
     LINE  2, 0, 0
2094
     {
2095
      POINTS ( (-20,0), (0,0) )
2096
     }
2097
    }
2098
    PIN  30, 0, 0
2099
    {
2100
     COORD (-60,320)
2101
     VARIABLES
2102
     {
2103
      #DIRECTION="IN"
2104
      #DOWNTO="1"
2105
      #LENGTH="20"
2106
      #MDA_RECORD_TOKEN="OTHER"
2107
      #NAME="id_cmd(2:0)"
2108
      #NUMBER="0"
2109
      #VERILOG_TYPE="wire"
2110
     }
2111
     LINE  2, 0, 0
2112
     {
2113
      POINTS ( (0,0), (20,0) )
2114
     }
2115
    }
2116
    PIN  32, 0, 0
2117
    {
2118
     COORD (340,320)
2119
     VARIABLES
2120
     {
2121
      #DIRECTION="OUT"
2122
      #DOWNTO="1"
2123
      #LENGTH="20"
2124
      #MDA_RECORD_TOKEN="OTHER"
2125
      #NAME="rs_n_o(4:0)"
2126
      #NUMBER="0"
2127
      #VERILOG_TYPE="wire"
2128
     }
2129
     LINE  2, 0, 0
2130
     {
2131
      POINTS ( (-20,0), (0,0) )
2132
     }
2133
    }
2134
    PIN  34, 0, 0
2135
    {
2136
     COORD (-60,360)
2137
     VARIABLES
2138
     {
2139
      #DIRECTION="IN"
2140
      #DOWNTO="1"
2141
      #LENGTH="20"
2142
      #MDA_RECORD_TOKEN="OTHER"
2143
      #NAME="ins_i(31:0)"
2144
      #NUMBER="0"
2145
      #VERILOG_TYPE="wire"
2146
     }
2147
     LINE  2, 0, 0
2148
     {
2149
      POINTS ( (0,0), (20,0) )
2150
     }
2151
    }
2152
    PIN  36, 0, 0
2153
    {
2154
     COORD (340,360)
2155
     VARIABLES
2156
     {
2157
      #DIRECTION="OUT"
2158
      #DOWNTO="1"
2159
      #LENGTH="20"
2160
      #MDA_RECORD_TOKEN="OTHER"
2161
      #NAME="rs_o(31:0)"
2162
      #NUMBER="0"
2163
      #VERILOG_TYPE="wire"
2164
     }
2165
     LINE  2, 0, 0
2166
     {
2167
      POINTS ( (-20,0), (0,0) )
2168
     }
2169
    }
2170
    PIN  38, 0, 0
2171
    {
2172
     COORD (-60,400)
2173
     VARIABLES
2174
     {
2175
      #DIRECTION="IN"
2176
      #DOWNTO="1"
2177
      #LENGTH="20"
2178
      #MDA_RECORD_TOKEN="OTHER"
2179
      #NAME="irq_addr_i(31:0)"
2180
      #NUMBER="0"
2181
      #VERILOG_TYPE="wire"
2182
     }
2183
     LINE  2, 0, 0
2184
     {
2185
      POINTS ( (0,0), (20,0) )
2186
     }
2187
    }
2188
    PIN  40, 0, 0
2189
    {
2190
     COORD (340,400)
2191
     VARIABLES
2192
     {
2193
      #DIRECTION="OUT"
2194
      #DOWNTO="1"
2195
      #LENGTH="20"
2196
      #MDA_RECORD_TOKEN="OTHER"
2197
      #NAME="rt_n_o(4:0)"
2198
      #NUMBER="0"
2199
      #VERILOG_TYPE="wire"
2200
     }
2201
     LINE  2, 0, 0
2202
     {
2203
      POINTS ( (-20,0), (0,0) )
2204
     }
2205
    }
2206
    PIN  42, 0, 0
2207
    {
2208
     COORD (-60,440)
2209
     VARIABLES
2210
     {
2211
      #DIRECTION="IN"
2212
      #LENGTH="20"
2213
      #MDA_RECORD_TOKEN="OTHER"
2214
      #NAME="irq_i"
2215
      #NUMBER="0"
2216
      #VERILOG_TYPE="wire"
2217
     }
2218
     LINE  2, 0, 0
2219
     {
2220
      POINTS ( (0,0), (20,0) )
2221
     }
2222
    }
2223
    PIN  44, 0, 0
2224
    {
2225
     COORD (340,440)
2226
     VARIABLES
2227
     {
2228
      #DIRECTION="OUT"
2229
      #DOWNTO="1"
2230
      #LENGTH="20"
2231
      #MDA_RECORD_TOKEN="OTHER"
2232
      #NAME="rt_o(31:0)"
2233
      #NUMBER="0"
2234
      #VERILOG_TYPE="wire"
2235
     }
2236
     LINE  2, 0, 0
2237
     {
2238
      POINTS ( (-20,0), (0,0) )
2239
     }
2240
    }
2241
    PIN  46, 0, 0
2242
    {
2243
     COORD (-60,480)
2244
     VARIABLES
2245
     {
2246
      #DIRECTION="IN"
2247
      #DOWNTO="1"
2248
      #LENGTH="20"
2249
      #MDA_RECORD_TOKEN="OTHER"
2250
      #NAME="pc_gen_ctl(2:0)"
2251
      #NUMBER="0"
2252
      #VERILOG_TYPE="wire"
2253
     }
2254
     LINE  2, 0, 0
2255
     {
2256
      POINTS ( (0,0), (20,0) )
2257
     }
2258
    }
2259
    PIN  48, 0, 0
2260
    {
2261
     COORD (-60,520)
2262
     VARIABLES
2263
     {
2264
      #DIRECTION="IN"
2265
      #DOWNTO="1"
2266
      #LENGTH="20"
2267
      #MDA_RECORD_TOKEN="OTHER"
2268
      #NAME="pc_i(31:0)"
2269
      #NUMBER="0"
2270
      #VERILOG_TYPE="wire"
2271
     }
2272
     LINE  2, 0, 0
2273
     {
2274
      POINTS ( (0,0), (20,0) )
2275
     }
2276
    }
2277
    PIN  50, 0, 0
2278
    {
2279
     COORD (-60,560)
2280
     VARIABLES
2281
     {
2282
      #DIRECTION="IN"
2283
      #DOWNTO="1"
2284
      #LENGTH="20"
2285
      #MDA_RECORD_TOKEN="OTHER"
2286
      #NAME="rd_sel_i(1:0)"
2287
      #NUMBER="0"
2288
      #VERILOG_TYPE="wire"
2289
     }
2290
     LINE  2, 0, 0
2291
     {
2292
      POINTS ( (0,0), (20,0) )
2293
     }
2294
    }
2295
    PIN  52, 0, 0
2296
    {
2297
     COORD (-60,600)
2298
     VARIABLES
2299
     {
2300
      #DIRECTION="IN"
2301
      #LENGTH="20"
2302
      #MDA_RECORD_TOKEN="OTHER"
2303
      #NAME="rst_i"
2304
      #NUMBER="0"
2305
      #VERILOG_TYPE="wire"
2306
     }
2307
     LINE  2, 0, 0
2308
     {
2309
      POINTS ( (0,0), (20,0) )
2310
     }
2311
    }
2312
    PIN  54, 0, 0
2313
    {
2314
     COORD (-60,640)
2315
     VARIABLES
2316
     {
2317
      #DIRECTION="IN"
2318
      #DOWNTO="1"
2319
      #LENGTH="20"
2320
      #MDA_RECORD_TOKEN="OTHER"
2321
      #NAME="wb_addr_i(4:0)"
2322
      #NUMBER="0"
2323
      #VERILOG_TYPE="wire"
2324
     }
2325
     LINE  2, 0, 0
2326
     {
2327
      POINTS ( (0,0), (20,0) )
2328
     }
2329
    }
2330
    PIN  56, 0, 0
2331
    {
2332
     COORD (-60,680)
2333
     VARIABLES
2334
     {
2335
      #DIRECTION="IN"
2336
      #DOWNTO="1"
2337
      #LENGTH="20"
2338
      #MDA_RECORD_TOKEN="OTHER"
2339
      #NAME="wb_din_i(31:0)"
2340
      #NUMBER="0"
2341
      #VERILOG_TYPE="wire"
2342
     }
2343
     LINE  2, 0, 0
2344
     {
2345
      POINTS ( (0,0), (20,0) )
2346
     }
2347
    }
2348
    PIN  58, 0, 0
2349
    {
2350
     COORD (-60,720)
2351
     VARIABLES
2352
     {
2353
      #DIRECTION="IN"
2354
      #LENGTH="20"
2355
      #MDA_RECORD_TOKEN="OTHER"
2356
      #NAME="wb_we_i"
2357
      #NUMBER="0"
2358
      #VERILOG_TYPE="wire"
2359
     }
2360
     LINE  2, 0, 0
2361
     {
2362
      POINTS ( (0,0), (20,0) )
2363
     }
2364
    }
2365
    PIN  60, 0, 0
2366
    {
2367
     COORD (-60,760)
2368
     VARIABLES
2369
     {
2370
      #DIRECTION="IN"
2371
      #DOWNTO="1"
2372
      #LENGTH="20"
2373
      #MDA_RECORD_TOKEN="OTHER"
2374
      #NAME="zz_spc_i(31:0)"
2375
      #NUMBER="0"
2376
      #VERILOG_TYPE="wire"
2377
     }
2378
     LINE  2, 0, 0
2379
     {
2380
      POINTS ( (0,0), (20,0) )
2381
     }
2382
    }
2383
   }
2384
  }
2385
 }
2386
 SYMBOL "#default" "exec_stage1" "exec_stage1"
2387
 {
2388
  HEADER
2389
  {
2390
   VARIABLES
2391
   {
2392
    #DESCRIPTION=""
2393
    #LANGUAGE="VERILOG"
2394
    #MODIFIED="1218999718"
2395
   }
2396
  }
2397
  PAGE ""
2398
  {
2399
   PAGEHEADER
2400
   {
2401
    RECT (0,0,400,640)
2402
    FREEID 39
2403
   }
2404
 
2405
   BODY
2406
   {
2407
    RECT  1, -1, 0
2408
    {
2409
     VARIABLES
2410
     {
2411
      #OUTLINE_FILLING="1"
2412
     }
2413
     AREA (20,0,380,640)
2414
    }
2415
    TEXT  3, 0, 0
2416
    {
2417
     TEXT "$#NAME"
2418
     RECT (25,30,170,54)
2419
     ALIGN 4
2420
     MARGINS (1,1)
2421
     PARENT 2
2422
    }
2423
    TEXT  5, 0, 0
2424
    {
2425
     TEXT "$#NAME"
2426
     RECT (219,30,375,54)
2427
     ALIGN 6
2428
     MARGINS (1,1)
2429
     PARENT 4
2430
    }
2431
    TEXT  7, 0, 0
2432
    {
2433
     TEXT "$#NAME"
2434
     RECT (25,70,60,94)
2435
     ALIGN 4
2436
     MARGINS (1,1)
2437
     PARENT 6
2438
    }
2439
    TEXT  9, 0, 0
2440
    {
2441
     TEXT "$#NAME"
2442
     RECT (153,70,375,94)
2443
     ALIGN 6
2444
     MARGINS (1,1)
2445
     PARENT 8
2446
    }
2447
    TEXT  11, 0, 0
2448
    {
2449
     TEXT "$#NAME"
2450
     RECT (25,110,203,134)
2451
     ALIGN 4
2452
     MARGINS (1,1)
2453
     PARENT 10
2454
    }
2455
    TEXT  13, 0, 0
2456
    {
2457
     TEXT "$#NAME"
2458
     RECT (219,110,375,134)
2459
     ALIGN 6
2460
     MARGINS (1,1)
2461
     PARENT 12
2462
    }
2463
    TEXT  15, 0, 0
2464
    {
2465
     TEXT "$#NAME"
2466
     RECT (25,150,148,174)
2467
     ALIGN 4
2468
     MARGINS (1,1)
2469
     PARENT 14
2470
    }
2471
    TEXT  17, 0, 0
2472
    {
2473
     TEXT "$#NAME"
2474
     RECT (25,190,159,214)
2475
     ALIGN 4
2476
     MARGINS (1,1)
2477
     PARENT 16
2478
    }
2479
    TEXT  19, 0, 0
2480
    {
2481
     TEXT "$#NAME"
2482
     RECT (25,230,170,254)
2483
     ALIGN 4
2484
     MARGINS (1,1)
2485
     PARENT 18
2486
    }
2487
    TEXT  21, 0, 0
2488
    {
2489
     TEXT "$#NAME"
2490
     RECT (25,270,192,294)
2491
     ALIGN 4
2492
     MARGINS (1,1)
2493
     PARENT 20
2494
    }
2495
    TEXT  23, 0, 0
2496
    {
2497
     TEXT "$#NAME"
2498
     RECT (25,310,203,334)
2499
     ALIGN 4
2500
     MARGINS (1,1)
2501
     PARENT 22
2502
    }
2503
    TEXT  25, 0, 0
2504
    {
2505
     TEXT "$#NAME"
2506
     RECT (25,350,192,374)
2507
     ALIGN 4
2508
     MARGINS (1,1)
2509
     PARENT 24
2510
    }
2511
    TEXT  27, 0, 0
2512
    {
2513
     TEXT "$#NAME"
2514
     RECT (25,390,203,414)
2515
     ALIGN 4
2516
     MARGINS (1,1)
2517
     PARENT 26
2518
    }
2519
    TEXT  29, 0, 0
2520
    {
2521
     TEXT "$#NAME"
2522
     RECT (25,430,137,454)
2523
     ALIGN 4
2524
     MARGINS (1,1)
2525
     PARENT 28
2526
    }
2527
    TEXT  31, 0, 0
2528
    {
2529
     TEXT "$#NAME"
2530
     RECT (25,470,137,494)
2531
     ALIGN 4
2532
     MARGINS (1,1)
2533
     PARENT 30
2534
    }
2535
    TEXT  33, 0, 0
2536
    {
2537
     TEXT "$#NAME"
2538
     RECT (25,510,60,534)
2539
     ALIGN 4
2540
     MARGINS (1,1)
2541
     PARENT 32
2542
    }
2543
    TEXT  35, 0, 0
2544
    {
2545
     TEXT "$#NAME"
2546
     RECT (25,550,137,574)
2547
     ALIGN 4
2548
     MARGINS (1,1)
2549
     PARENT 34
2550
    }
2551
    TEXT  37, 0, 0
2552
    {
2553
     TEXT "$#NAME"
2554
     RECT (25,590,126,614)
2555
     ALIGN 4
2556
     MARGINS (1,1)
2557
     PARENT 36
2558
    }
2559
    PIN  2, 0, 0
2560
    {
2561
     COORD (0,40)
2562
     VARIABLES
2563
     {
2564
      #DIRECTION="IN"
2565
      #DOWNTO="1"
2566
      #LENGTH="20"
2567
      #MDA_RECORD_TOKEN="OTHER"
2568
      #NAME="alu_func(4:0)"
2569
      #NUMBER="0"
2570
      #VERILOG_TYPE="wire"
2571
     }
2572
     LINE  2, 0, 0
2573
     {
2574
      POINTS ( (0,0), (20,0) )
2575
     }
2576
    }
2577
    PIN  4, 0, 0
2578
    {
2579
     COORD (400,40)
2580
     VARIABLES
2581
     {
2582
      #DIRECTION="OUT"
2583
      #DOWNTO="1"
2584
      #LENGTH="20"
2585
      #MDA_RECORD_TOKEN="OTHER"
2586
      #NAME="alu_ur_o(31:0)"
2587
      #NUMBER="0"
2588
      #VERILOG_TYPE="wire"
2589
     }
2590
     LINE  2, 0, 0
2591
     {
2592
      POINTS ( (-20,0), (0,0) )
2593
     }
2594
    }
2595
    PIN  6, 0, 0
2596
    {
2597
     COORD (0,80)
2598
     VARIABLES
2599
     {
2600
      #DIRECTION="IN"
2601
      #LENGTH="20"
2602
      #MDA_RECORD_TOKEN="OTHER"
2603
      #NAME="clk"
2604
      #NUMBER="0"
2605
      #VERILOG_TYPE="wire"
2606
     }
2607
     LINE  2, 0, 0
2608
     {
2609
      POINTS ( (0,0), (20,0) )
2610
     }
2611
    }
2612
    PIN  8, 0, 0
2613
    {
2614
     COORD (400,80)
2615
     VARIABLES
2616
     {
2617
      #DIRECTION="OUT"
2618
      #DOWNTO="1"
2619
      #LENGTH="20"
2620
      #MDA_RECORD_TOKEN="OTHER"
2621
      #NAME="dmem_data_ur_o(31:0)"
2622
      #NUMBER="0"
2623
      #VERILOG_TYPE="wire"
2624
     }
2625
     LINE  2, 0, 0
2626
     {
2627
      POINTS ( (-20,0), (0,0) )
2628
     }
2629
    }
2630
    PIN  10, 0, 0
2631
    {
2632
     COORD (0,120)
2633
     VARIABLES
2634
     {
2635
      #DIRECTION="IN"
2636
      #DOWNTO="1"
2637
      #LENGTH="20"
2638
      #MDA_RECORD_TOKEN="OTHER"
2639
      #NAME="dmem_fw_ctl(2:0)"
2640
      #NUMBER="0"
2641
      #VERILOG_TYPE="wire"
2642
     }
2643
     LINE  2, 0, 0
2644
     {
2645
      POINTS ( (0,0), (20,0) )
2646
     }
2647
    }
2648
    PIN  12, 0, 0
2649
    {
2650
     COORD (400,120)
2651
     VARIABLES
2652
     {
2653
      #DIRECTION="OUT"
2654
      #DOWNTO="1"
2655
      #LENGTH="20"
2656
      #MDA_RECORD_TOKEN="OTHER"
2657
      #NAME="zz_spc_o(31:0)"
2658
      #NUMBER="0"
2659
      #VERILOG_TYPE="wire"
2660
     }
2661
     LINE  2, 0, 0
2662
     {
2663
      POINTS ( (-20,0), (0,0) )
2664
     }
2665
    }
2666
    PIN  14, 0, 0
2667
    {
2668
     COORD (0,160)
2669
     VARIABLES
2670
     {
2671
      #DIRECTION="IN"
2672
      #DOWNTO="1"
2673
      #LENGTH="20"
2674
      #MDA_RECORD_TOKEN="OTHER"
2675
      #NAME="ext_i(31:0)"
2676
      #NUMBER="0"
2677
      #VERILOG_TYPE="wire"
2678
     }
2679
     LINE  2, 0, 0
2680
     {
2681
      POINTS ( (0,0), (20,0) )
2682
     }
2683
    }
2684
    PIN  16, 0, 0
2685
    {
2686
     COORD (0,200)
2687
     VARIABLES
2688
     {
2689
      #DIRECTION="IN"
2690
      #DOWNTO="1"
2691
      #LENGTH="20"
2692
      #MDA_RECORD_TOKEN="OTHER"
2693
      #NAME="fw_alu(31:0)"
2694
      #NUMBER="0"
2695
      #VERILOG_TYPE="wire"
2696
     }
2697
     LINE  2, 0, 0
2698
     {
2699
      POINTS ( (0,0), (20,0) )
2700
     }
2701
    }
2702
    PIN  18, 0, 0
2703
    {
2704
     COORD (0,240)
2705
     VARIABLES
2706
     {
2707
      #DIRECTION="IN"
2708
      #DOWNTO="1"
2709
      #LENGTH="20"
2710
      #MDA_RECORD_TOKEN="OTHER"
2711
      #NAME="fw_dmem(31:0)"
2712
      #NUMBER="0"
2713
      #VERILOG_TYPE="wire"
2714
     }
2715
     LINE  2, 0, 0
2716
     {
2717
      POINTS ( (0,0), (20,0) )
2718
     }
2719
    }
2720
    PIN  20, 0, 0
2721
    {
2722
     COORD (0,280)
2723
     VARIABLES
2724
     {
2725
      #DIRECTION="IN"
2726
      #DOWNTO="1"
2727
      #LENGTH="20"
2728
      #MDA_RECORD_TOKEN="OTHER"
2729
      #NAME="muxa_ctl_i(1:0)"
2730
      #NUMBER="0"
2731
      #VERILOG_TYPE="wire"
2732
     }
2733
     LINE  2, 0, 0
2734
     {
2735
      POINTS ( (0,0), (20,0) )
2736
     }
2737
    }
2738
    PIN  22, 0, 0
2739
    {
2740
     COORD (0,320)
2741
     VARIABLES
2742
     {
2743
      #DIRECTION="IN"
2744
      #DOWNTO="1"
2745
      #LENGTH="20"
2746
      #MDA_RECORD_TOKEN="OTHER"
2747
      #NAME="muxa_fw_ctl(2:0)"
2748
      #NUMBER="0"
2749
      #VERILOG_TYPE="wire"
2750
     }
2751
     LINE  2, 0, 0
2752
     {
2753
      POINTS ( (0,0), (20,0) )
2754
     }
2755
    }
2756
    PIN  24, 0, 0
2757
    {
2758
     COORD (0,360)
2759
     VARIABLES
2760
     {
2761
      #DIRECTION="IN"
2762
      #DOWNTO="1"
2763
      #LENGTH="20"
2764
      #MDA_RECORD_TOKEN="OTHER"
2765
      #NAME="muxb_ctl_i(1:0)"
2766
      #NUMBER="0"
2767
      #VERILOG_TYPE="wire"
2768
     }
2769
     LINE  2, 0, 0
2770
     {
2771
      POINTS ( (0,0), (20,0) )
2772
     }
2773
    }
2774
    PIN  26, 0, 0
2775
    {
2776
     COORD (0,400)
2777
     VARIABLES
2778
     {
2779
      #DIRECTION="IN"
2780
      #DOWNTO="1"
2781
      #LENGTH="20"
2782
      #MDA_RECORD_TOKEN="OTHER"
2783
      #NAME="muxb_fw_ctl(2:0)"
2784
      #NUMBER="0"
2785
      #VERILOG_TYPE="wire"
2786
     }
2787
     LINE  2, 0, 0
2788
     {
2789
      POINTS ( (0,0), (20,0) )
2790
     }
2791
    }
2792
    PIN  28, 0, 0
2793
    {
2794
     COORD (0,440)
2795
     VARIABLES
2796
     {
2797
      #DIRECTION="IN"
2798
      #DOWNTO="1"
2799
      #LENGTH="20"
2800
      #MDA_RECORD_TOKEN="OTHER"
2801
      #NAME="pc_i(31:0)"
2802
      #NUMBER="0"
2803
      #VERILOG_TYPE="wire"
2804
     }
2805
     LINE  2, 0, 0
2806
     {
2807
      POINTS ( (0,0), (20,0) )
2808
     }
2809
    }
2810
    PIN  30, 0, 0
2811
    {
2812
     COORD (0,480)
2813
     VARIABLES
2814
     {
2815
      #DIRECTION="IN"
2816
      #DOWNTO="1"
2817
      #LENGTH="20"
2818
      #MDA_RECORD_TOKEN="OTHER"
2819
      #NAME="rs_i(31:0)"
2820
      #NUMBER="0"
2821
      #VERILOG_TYPE="wire"
2822
     }
2823
     LINE  2, 0, 0
2824
     {
2825
      POINTS ( (0,0), (20,0) )
2826
     }
2827
    }
2828
    PIN  32, 0, 0
2829
    {
2830
     COORD (0,520)
2831
     VARIABLES
2832
     {
2833
      #DIRECTION="IN"
2834
      #LENGTH="20"
2835
      #MDA_RECORD_TOKEN="OTHER"
2836
      #NAME="rst"
2837
      #NUMBER="0"
2838
      #VERILOG_TYPE="wire"
2839
     }
2840
     LINE  2, 0, 0
2841
     {
2842
      POINTS ( (0,0), (20,0) )
2843
     }
2844
    }
2845
    PIN  34, 0, 0
2846
    {
2847
     COORD (0,560)
2848
     VARIABLES
2849
     {
2850
      #DIRECTION="IN"
2851
      #DOWNTO="1"
2852
      #LENGTH="20"
2853
      #MDA_RECORD_TOKEN="OTHER"
2854
      #NAME="rt_i(31:0)"
2855
      #NUMBER="0"
2856
      #VERILOG_TYPE="wire"
2857
     }
2858
     LINE  2, 0, 0
2859
     {
2860
      POINTS ( (0,0), (20,0) )
2861
     }
2862
    }
2863
    PIN  36, 0, 0
2864
    {
2865
     COORD (0,600)
2866
     VARIABLES
2867
     {
2868
      #DIRECTION="IN"
2869
      #LENGTH="20"
2870
      #MDA_RECORD_TOKEN="OTHER"
2871
      #NAME="spc_cls_i"
2872
      #NUMBER="0"
2873
      #VERILOG_TYPE="wire"
2874
     }
2875
     LINE  2, 0, 0
2876
     {
2877
      POINTS ( (0,0), (20,0) )
2878
     }
2879
    }
2880
   }
2881
  }
2882
 }
2883
}
2884
 
2885
PAGE ""
2886
{
2887
 PAGEHEADER
2888
 {
2889
  PAGESIZE (3307,2338)
2890
  MARGINS (200,200,200,200)
2891
  RECT (0,0,100,200)
2892
 }
2893
 
2894
 BODY
2895
 {
2896
  INSTANCE  83, 0, 0
2897
  {
2898
   VARIABLES
2899
   {
2900
    #COMPONENT="wb_mux"
2901
    #LIBRARY="#default"
2902
    #REFERENCE="wb_mux"
2903
    #SYMBOL="wb_mux"
2904
   }
2905
   COORD (2800,440)
2906
   VERTEXES ( (6,23943), (4,23940), (2,26152), (8,26277) )
2907
  }
2908
  TEXT  84, 0, 0
2909
  {
2910
   TEXT "$#REFERENCE"
2911
   RECT (2820,405,2924,440)
2912
   ALIGN 8
2913
   MARGINS (1,1)
2914
   PARENT 83
2915
  }
2916
  TEXT  88, 0, 0
2917
  {
2918
   TEXT "$#COMPONENT"
2919
   RECT (2800,600,2904,635)
2920
   MARGINS (1,1)
2921
   PARENT 83
2922
  }
2923
  NET BUS  109, 0, 0
2924
  NET BUS  117, 0, 0
2925
  NET BUS  197, 0, 0
2926
  INSTANCE  244, 0, 0
2927
  {
2928
   VARIABLES
2929
   {
2930
    #COMPONENT="Input"
2931
    #LIBRARY="#terminals"
2932
    #REFERENCE="irq_i"
2933
    #SYMBOL="Input"
2934
   }
2935
   COORD (740,1280)
2936
   VERTEXES ( (2,24007) )
2937
  }
2938
  TEXT  245, 0, 0
2939
  {
2940
   TEXT "$#REFERENCE"
2941
   RECT (602,1263,689,1298)
2942
   ALIGN 6
2943
   MARGINS (1,1)
2944
   PARENT 244
2945
  }
2946
  NET BUS  271, 0, 0
2947
  NET BUS  371, 0, 0
2948
  INSTANCE  388, 0, 0
2949
  {
2950
   VARIABLES
2951
   {
2952
    #COMPONENT="r32_reg"
2953
    #LIBRARY="#default"
2954
    #REFERENCE="alu_pass0"
2955
    #SYMBOL="r32_reg"
2956
   }
2957
   COORD (2540,920)
2958
   VERTEXES ( (2,23927), (4,23923), (6,26975) )
2959
  }
2960
  TEXT  389, 0, 0
2961
  {
2962
   TEXT "$#REFERENCE"
2963
   RECT (2540,884,2695,919)
2964
   ALIGN 8
2965
   MARGINS (1,1)
2966
   PARENT 388
2967
  }
2968
  TEXT  393, 0, 0
2969
  {
2970
   TEXT "$#COMPONENT"
2971
   RECT (2540,1040,2661,1075)
2972
   MARGINS (1,1)
2973
   PARENT 388
2974
  }
2975
  INSTANCE  397, 0, 0
2976
  {
2977
   VARIABLES
2978
   {
2979
    #COMPONENT="r32_reg"
2980
    #LIBRARY="#default"
2981
    #REFERENCE="alu_pass1"
2982
    #SYMBOL="r32_reg"
2983
   }
2984
   COORD (2780,880)
2985
   VERTEXES ( (2,23922), (6,23924), (4,26151) )
2986
  }
2987
  TEXT  398, 0, 0
2988
  {
2989
   TEXT "$#REFERENCE"
2990
   RECT (2780,844,2935,879)
2991
   ALIGN 8
2992
   MARGINS (1,1)
2993
   PARENT 397
2994
  }
2995
  TEXT  399, 0, 0
2996
  {
2997
   TEXT "$#COMPONENT"
2998
   RECT (2780,1000,2901,1035)
2999
   MARGINS (1,1)
3000
   PARENT 397
3001
  }
3002
  NET BUS  422, 0, 0
3003
  INSTANCE  432, 0, 0
3004
  {
3005
   VARIABLES
3006
   {
3007
    #COMPONENT="r32_reg"
3008
    #LIBRARY="#default"
3009
    #REFERENCE="cop_dout_reg"
3010
    #SYMBOL="r32_reg"
3011
   }
3012
   COORD (2280,460)
3013
   VERTEXES ( (2,23902), (4,23945), (6,26756) )
3014
  }
3015
  TEXT  433, 0, 0
3016
  {
3017
   TEXT "$#REFERENCE"
3018
   RECT (2280,424,2486,459)
3019
   ALIGN 8
3020
   MARGINS (1,1)
3021
   PARENT 432
3022
  }
3023
  TEXT  434, 0, 0
3024
  {
3025
   TEXT "$#COMPONENT"
3026
   RECT (2280,580,2401,615)
3027
   MARGINS (1,1)
3028
   PARENT 432
3029
  }
3030
  NET WIRE  457, 0, 0
3031
  INSTANCE  708, 0, 0
3032
  {
3033
   VARIABLES
3034
   {
3035
    #COMPONENT="r5_reg"
3036
    #LIBRARY="#default"
3037
    #REFERENCE="rnd_pass0"
3038
    #SYMBOL="r5_reg"
3039
   }
3040
   COORD (1560,1020)
3041
   VERTEXES ( (2,23909), (6,23984), (4,23901) )
3042
  }
3043
  TEXT  709, 0, 0
3044
  {
3045
   TEXT "$#REFERENCE"
3046
   RECT (1580,985,1735,1020)
3047
   ALIGN 8
3048
   MARGINS (1,1)
3049
   PARENT 708
3050
  }
3051
  TEXT  713, 0, 0
3052
  {
3053
   TEXT "$#COMPONENT"
3054
   RECT (1560,1140,1664,1175)
3055
   MARGINS (1,1)
3056
   PARENT 708
3057
  }
3058
  INSTANCE  717, 0, 0
3059
  {
3060
   VARIABLES
3061
   {
3062
    #COMPONENT="r5_reg"
3063
    #LIBRARY="#default"
3064
    #REFERENCE="rnd_pass1"
3065
    #SYMBOL="r5_reg"
3066
   }
3067
   COORD (1520,1200)
3068
   VERTEXES ( (2,23911), (6,23900), (4,23897) )
3069
  }
3070
  TEXT  718, 0, 0
3071
  {
3072
   TEXT "$#REFERENCE"
3073
   RECT (1520,1164,1675,1199)
3074
   ALIGN 8
3075
   MARGINS (1,1)
3076
   PARENT 717
3077
  }
3078
  TEXT  719, 0, 0
3079
  {
3080
   TEXT "$#COMPONENT"
3081
   RECT (1520,1320,1624,1355)
3082
   MARGINS (1,1)
3083
   PARENT 717
3084
  }
3085
  NET BUS  748, 0, 0
3086
  NET BUS  756, 0, 0
3087
  NET WIRE  767, 0, 0
3088
  NET BUS  775, 0, 0
3089
  INSTANCE  789, 0, 0
3090
  {
3091
   VARIABLES
3092
   {
3093
    #COMPONENT="r5_reg"
3094
    #LIBRARY="#default"
3095
    #REFERENCE="rnd_pass2"
3096
    #SYMBOL="r5_reg"
3097
   }
3098
   COORD (1600,1400)
3099
   VERTEXES ( (2,23914), (6,23895), (4,23898) )
3100
  }
3101
  TEXT  790, 0, 0
3102
  {
3103
   TEXT "$#REFERENCE"
3104
   RECT (1600,1364,1755,1399)
3105
   ALIGN 8
3106
   MARGINS (1,1)
3107
   PARENT 789
3108
  }
3109
  TEXT  791, 0, 0
3110
  {
3111
   TEXT "$#COMPONENT"
3112
   RECT (1600,1520,1704,1555)
3113
   MARGINS (1,1)
3114
   PARENT 789
3115
  }
3116
  NET BUS  1158, 0, 0
3117
  NET BUS  1196, 0, 0
3118
  NET WIRE  1375, 0, 0
3119
  NET WIRE  1572, 0, 0
3120
  NET WIRE  1606, 0, 0
3121
  NET WIRE  1640, 0, 0
3122
  NET BUS  1724, 0, 0
3123
  NET BUS  1726, 0, 0
3124
  NET BUS  2140, 0, 0
3125
  NET BUS  2156, 0, 0
3126
  NET BUS  5832, 0, 0
3127
  NET BUS  5840, 0, 0
3128
  NET BUS  5985, 0, 0
3129
  NET BUS  5993, 0, 0
3130
  NET BUS  6275, 0, 0
3131
  NET WIRE  6336, 0, 0
3132
  NET BUS  6364, 0, 0
3133
  INSTANCE  6366, 0, 0
3134
  {
3135
   VARIABLES
3136
   {
3137
    #COMPONENT="BusInput"
3138
    #LIBRARY="#terminals"
3139
    #REFERENCE="irq_addr(31:0)"
3140
    #SYMBOL="BusInput"
3141
   }
3142
   COORD (740,1240)
3143
   VERTEXES ( (2,24011) )
3144
  }
3145
  TEXT  6367, 0, 0
3146
  {
3147
   TEXT "$#REFERENCE"
3148
   RECT (460,1223,700,1258)
3149
   ALIGN 6
3150
   MARGINS (1,1)
3151
   PARENT 6366
3152
  }
3153
  INSTANCE  6890, 0, 0
3154
  {
3155
   VARIABLES
3156
   {
3157
    #COMPONENT="Input"
3158
    #LIBRARY="#terminals"
3159
    #REFERENCE="rst"
3160
    #SYMBOL="Input"
3161
   }
3162
   COORD (660,1660)
3163
   VERTEXES ( (2,23948) )
3164
  }
3165
  TEXT  6891, 0, 0
3166
  {
3167
   TEXT "$#REFERENCE"
3168
   RECT (556,1643,609,1678)
3169
   ALIGN 6
3170
   MARGINS (1,1)
3171
   PARENT 6890
3172
  }
3173
  INSTANCE  7088, 0, 0
3174
  {
3175
   VARIABLES
3176
   {
3177
    #COMPONENT="r32_reg"
3178
    #LIBRARY="#default"
3179
    #REFERENCE="rs_reg"
3180
    #SYMBOL="r32_reg"
3181
   }
3182
   COORD (2540,1260)
3183
   VERTEXES ( (2,23920), (6,24861), (4,29651) )
3184
  }
3185
  TEXT  7089, 0, 0
3186
  {
3187
   TEXT "$#REFERENCE"
3188
   RECT (2740,1245,2844,1280)
3189
   ALIGN 8
3190
   MARGINS (1,1)
3191
   PARENT 7088
3192
  }
3193
  TEXT  7090, 0, 0
3194
  {
3195
   TEXT "$#COMPONENT"
3196
   RECT (2540,1380,2661,1415)
3197
   MARGINS (1,1)
3198
   PARENT 7088
3199
  }
3200
  INSTANCE  7093, 0, 0
3201
  {
3202
   VARIABLES
3203
   {
3204
    #COMPONENT="r32_reg"
3205
    #LIBRARY="#default"
3206
    #REFERENCE="rt_reg"
3207
    #SYMBOL="r32_reg"
3208
   }
3209
   COORD (2540,1440)
3210
   VERTEXES ( (2,23919), (6,23995), (4,29654) )
3211
  }
3212
  TEXT  7094, 0, 0
3213
  {
3214
   TEXT "$#REFERENCE"
3215
   RECT (2720,1425,2824,1460)
3216
   ALIGN 8
3217
   MARGINS (1,1)
3218
   PARENT 7093
3219
  }
3220
  TEXT  7095, 0, 0
3221
  {
3222
   TEXT "$#COMPONENT"
3223
   RECT (2540,1560,2661,1595)
3224
   MARGINS (1,1)
3225
   PARENT 7093
3226
  }
3227
  INSTANCE  7096, 0, 0
3228
  {
3229
   VARIABLES
3230
   {
3231
    #COMPONENT="r32_reg"
3232
    #LIBRARY="#default"
3233
    #REFERENCE="ext_reg"
3234
    #SYMBOL="r32_reg"
3235
   }
3236
   COORD (2540,1660)
3237
   VERTEXES ( (2,23917), (6,27943), (4,29638) )
3238
  }
3239
  TEXT  7097, 0, 0
3240
  {
3241
   TEXT "$#REFERENCE"
3242
   RECT (2720,1645,2841,1680)
3243
   ALIGN 8
3244
   MARGINS (1,1)
3245
   PARENT 7096
3246
  }
3247
  TEXT  7098, 0, 0
3248
  {
3249
   TEXT "$#COMPONENT"
3250
   RECT (2540,1780,2661,1815)
3251
   MARGINS (1,1)
3252
   PARENT 7096
3253
  }
3254
  NET BUS  7101, 0, 0
3255
  NET BUS  7117, 0, 0
3256
  NET BUS  7160, 0, 0
3257
  NET BUS  7219, 0, 0
3258
  NET BUS  7231, 0, 0
3259
  INSTANCE  7417, 0, 0
3260
  {
3261
   VARIABLES
3262
   {
3263
    #COMPONENT="or32"
3264
    #LIBRARY="#default"
3265
    #REFERENCE="cop_data_or"
3266
    #SYMBOL="or32"
3267
   }
3268
   COORD (2840,260)
3269
   VERTEXES ( (2,23942), (6,23946), (4,23944) )
3270
  }
3271
  TEXT  7418, 0, 0
3272
  {
3273
   TEXT "$#REFERENCE"
3274
   RECT (2840,224,3029,259)
3275
   ALIGN 8
3276
   MARGINS (1,1)
3277
   PARENT 7417
3278
  }
3279
  TEXT  7422, 0, 0
3280
  {
3281
   TEXT "$#COMPONENT"
3282
   RECT (3060,340,3130,375)
3283
   MARGINS (1,1)
3284
   PARENT 7417
3285
  }
3286
  INSTANCE  7441, 0, 0
3287
  {
3288
   VARIABLES
3289
   {
3290
    #COMPONENT="BusInput"
3291
    #LIBRARY="#terminals"
3292
    #REFERENCE="cop_dout(31:0)"
3293
    #SYMBOL="BusInput"
3294
   }
3295
   COORD (2800,300)
3296
   VERTEXES ( (2,23941) )
3297
  }
3298
  TEXT  7442, 0, 0
3299
  {
3300
   TEXT "$#REFERENCE"
3301
   RECT (2509,283,2749,318)
3302
   ALIGN 6
3303
   MARGINS (1,1)
3304
   PARENT 7441
3305
  }
3306
  NET BUS  7446, 0, 0
3307
  INSTANCE  7466, 0, 0
3308
  {
3309
   VARIABLES
3310
   {
3311
    #COMPONENT="BusOutput"
3312
    #LIBRARY="#terminals"
3313
    #REFERENCE="cop_mem_ctl_o(3:0)"
3314
    #SYMBOL="BusOutput"
3315
   }
3316
   COORD (980,400)
3317
   VERTEXES ( (2,23952) )
3318
  }
3319
  TEXT  7467, 0, 0
3320
  {
3321
   TEXT "$#REFERENCE"
3322
   RECT (1032,383,1340,418)
3323
   ALIGN 4
3324
   MARGINS (1,1)
3325
   PARENT 7466
3326
  }
3327
  NET BUS  7471, 0, 0
3328
  INSTANCE  7488, 0, 0
3329
  {
3330
   VARIABLES
3331
   {
3332
    #COMPONENT="BusOutput"
3333
    #LIBRARY="#terminals"
3334
    #REFERENCE="cop_addr_o(31:0)"
3335
    #SYMBOL="BusOutput"
3336
   }
3337
   COORD (2560,740)
3338
   VERTEXES ( (2,23934) )
3339
  }
3340
  TEXT  7489, 0, 0
3341
  {
3342
   TEXT "$#REFERENCE"
3343
   RECT (2612,723,2886,758)
3344
   ALIGN 4
3345
   MARGINS (1,1)
3346
   PARENT 7488
3347
  }
3348
  NET WIRE  7555, 0, 0
3349
  NET BUS  7772, 0, 0
3350
  NET BUS  7780, 0, 0
3351
  NET BUS  9589, 0, 0
3352
  INSTANCE  9873, 0, 0
3353
  {
3354
   VARIABLES
3355
   {
3356
    #COMPONENT="r32_reg"
3357
    #LIBRARY="#default"
3358
    #REFERENCE="cop_data_reg"
3359
    #SYMBOL="r32_reg"
3360
   }
3361
   COORD (2280,640)
3362
   VERTEXES ( (2,23933), (4,23935), (6,26137) )
3363
  }
3364
  TEXT  9874, 0, 0
3365
  {
3366
   TEXT "$#REFERENCE"
3367
   RECT (2280,604,2486,639)
3368
   ALIGN 8
3369
   MARGINS (1,1)
3370
   PARENT 9873
3371
  }
3372
  TEXT  9875, 0, 0
3373
  {
3374
   TEXT "$#COMPONENT"
3375
   RECT (2280,760,2401,795)
3376
   MARGINS (1,1)
3377
   PARENT 9873
3378
  }
3379
  NET BUS  9884, 0, 0
3380
  INSTANCE  9897, 0, 0
3381
  {
3382
   VARIABLES
3383
   {
3384
    #COMPONENT="BusOutput"
3385
    #LIBRARY="#terminals"
3386
    #REFERENCE="cop_data_o(31:0)"
3387
    #SYMBOL="BusOutput"
3388
   }
3389
   COORD (2560,680)
3390
   VERTEXES ( (2,23936) )
3391
  }
3392
  TEXT  9898, 0, 0
3393
  {
3394
   TEXT "$#REFERENCE"
3395
   RECT (2612,663,2886,698)
3396
   ALIGN 4
3397
   MARGINS (1,1)
3398
   PARENT 9897
3399
  }
3400
  NET BUS  9899, 0, 0
3401
  NET BUS  15471, 0, 0
3402
  INSTANCE  15974, 0, 0
3403
  {
3404
   VARIABLES
3405
   {
3406
    #COMPONENT="decode_pipe3"
3407
    #LIBRARY="#default"
3408
    #REFERENCE="decoder_pipe"
3409
    #SYMBOL="decode_pipe3"
3410
   }
3411
   COORD (340,240)
3412
   VERTEXES ( (2,23949), (6,23972), (14,23951), (18,23982), (12,23968), (16,23953), (20,24061), (22,23970), (36,23960), (30,25917), (24,25924), (32,25950), (10,26218), (34,26278), (8,27789), (4,29629), (26,29642), (28,29646) )
3413
  }
3414
  TEXT  15975, 0, 0
3415
  {
3416
   TEXT "$#REFERENCE"
3417
   RECT (340,204,546,239)
3418
   ALIGN 8
3419
   MARGINS (1,1)
3420
   PARENT 15974
3421
  }
3422
  TEXT  15979, 0, 0
3423
  {
3424
   TEXT "$#COMPONENT"
3425
   RECT (340,800,546,835)
3426
   MARGINS (1,1)
3427
   PARENT 15974
3428
  }
3429
  INSTANCE  16322, 0, 0
3430
  {
3431
   VARIABLES
3432
   {
3433
    #COMPONENT="r32_reg"
3434
    #LIBRARY="#default"
3435
    #REFERENCE="pc"
3436
    #SYMBOL="r32_reg"
3437
   }
3438
   COORD (320,1340)
3439
   VERTEXES ( (2,23958), (4,24059), (6,25764) )
3440
  }
3441
  TEXT  16323, 0, 0
3442
  {
3443
   TEXT "$#REFERENCE"
3444
   RECT (320,1304,356,1339)
3445
   ALIGN 8
3446
   MARGINS (1,1)
3447
   PARENT 16322
3448
  }
3449
  TEXT  16324, 0, 0
3450
  {
3451
   TEXT "$#COMPONENT"
3452
   RECT (320,1460,441,1495)
3453
   MARGINS (1,1)
3454
   PARENT 16322
3455
  }
3456
  INSTANCE  17706, 0, 0
3457
  {
3458
   VARIABLES
3459
   {
3460
    #COMPONENT="forward2"
3461
    #LIBRARY="#default"
3462
    #REFERENCE="forward"
3463
    #SYMBOL="forward2"
3464
   }
3465
   COORD (1680,1720)
3466
   VERTEXES ( (12,23978), (16,23980), (2,27790), (6,27788), (10,27787), (14,27786), (18,27785), (22,27784), (24,27782), (4,29644), (8,29648), (20,29634) )
3467
  }
3468
  TEXT  17707, 0, 0
3469
  {
3470
   TEXT "$#REFERENCE"
3471
   RECT (1640,1684,1761,1719)
3472
   ALIGN 8
3473
   MARGINS (1,1)
3474
   PARENT 17706
3475
  }
3476
  TEXT  17711, 0, 0
3477
  {
3478
   TEXT "$#COMPONENT"
3479
   RECT (1640,2040,1778,2075)
3480
   MARGINS (1,1)
3481
   PARENT 17706
3482
  }
3483
  NET BUS  18211, 0, 0
3484
  INSTANCE  21044, 0, 0
3485
  {
3486
   VARIABLES
3487
   {
3488
    #COMPONENT="Output"
3489
    #LIBRARY="#terminals"
3490
    #REFERENCE="iack_o"
3491
    #SYMBOL="Output"
3492
   }
3493
   COORD (1280,820)
3494
   ORIENTATION 2
3495
   VERTEXES ( (2,26733) )
3496
  }
3497
  TEXT  21045, 0, 0
3498
  {
3499
   TEXT "$#REFERENCE"
3500
   RECT (1124,803,1228,838)
3501
   ALIGN 6
3502
   MARGINS (1,1)
3503
   PARENT 21044
3504
   ORIENTATION 2
3505
  }
3506
  NET WIRE  21056, 0, 0
3507
  INSTANCE  21057, 0, 0
3508
  {
3509
   VARIABLES
3510
   {
3511
    #COMPONENT="or2"
3512
    #LIBRARY="#builtin"
3513
    #REFERENCE="U1"
3514
    #SYMBOL="or2"
3515
   }
3516
   COORD (2180,1660)
3517
   VERTEXES ( (2,25739), (6,26719), (4,29656) )
3518
  }
3519
  NET WIRE  21531, 0, 0
3520
  INSTANCE  21964, 0, 0
3521
  {
3522
   VARIABLES
3523
   {
3524
    #COMPONENT="mem_module1"
3525
    #LIBRARY="#default"
3526
    #REFERENCE="MEM_CTL"
3527
    #SYMBOL="mem_module1"
3528
   }
3529
   COORD (1780,500)
3530
   VERTEXES ( (6,24042), (14,24062), (8,24049), (12,24047), (18,26737), (2,26744), (16,26757), (4,26068), (10,26994) )
3531
  }
3532
  TEXT  21965, 0, 0
3533
  {
3534
   TEXT "$#REFERENCE"
3535
   RECT (1780,464,1901,499)
3536
   ALIGN 8
3537
   MARGINS (1,1)
3538
   PARENT 21964
3539
  }
3540
  TEXT  21969, 0, 0
3541
  {
3542
   TEXT "$#COMPONENT"
3543
   RECT (1780,740,1969,775)
3544
   MARGINS (1,1)
3545
   PARENT 21964
3546
  }
3547
  INSTANCE  22150, 0, 0
3548
  {
3549
   VARIABLES
3550
   {
3551
    #COMPONENT="BusOutput"
3552
    #LIBRARY="#terminals"
3553
    #REFERENCE="zz_dout(31:0)"
3554
    #SYMBOL="BusOutput"
3555
    #VERILOG_TYPE="wire"
3556
   }
3557
   COORD (2140,320)
3558
   ORIENTATION 2
3559
   VERTEXES ( (2,24048) )
3560
  }
3561
  TEXT  22151, 0, 0
3562
  {
3563
   TEXT "$#REFERENCE"
3564
   RECT (1865,303,2088,338)
3565
   ALIGN 6
3566
   MARGINS (1,1)
3567
   PARENT 22150
3568
   ORIENTATION 2
3569
  }
3570
  NET BUS  22155, 0, 0
3571
  INSTANCE  22159, 0, 0
3572
  {
3573
   VARIABLES
3574
   {
3575
    #COMPONENT="BusOutput"
3576
    #LIBRARY="#terminals"
3577
    #REFERENCE="zz_wr_en_o(3:0)"
3578
    #SYMBOL="BusOutput"
3579
    #VERILOG_TYPE="wire"
3580
   }
3581
   COORD (2140,280)
3582
   ORIENTATION 2
3583
   VERTEXES ( (2,24046) )
3584
  }
3585
  TEXT  22160, 0, 0
3586
  {
3587
   TEXT "$#REFERENCE"
3588
   RECT (1831,263,2088,298)
3589
   ALIGN 6
3590
   MARGINS (1,1)
3591
   PARENT 22159
3592
   ORIENTATION 2
3593
  }
3594
  NET BUS  22164, 0, 0
3595
  NET BUS  22220, 0, 0
3596
  INSTANCE  22226, 0, 0
3597
  {
3598
   VARIABLES
3599
   {
3600
    #COMPONENT="BusInput"
3601
    #LIBRARY="#terminals"
3602
    #REFERENCE="zz_din(31:0)"
3603
    #SYMBOL="BusInput"
3604
   }
3605
   COORD (1720,420)
3606
   ORIENTATION 2
3607
   VERTEXES ( (2,26738) )
3608
  }
3609
  TEXT  22227, 0, 0
3610
  {
3611
   TEXT "$#REFERENCE"
3612
   RECT (1771,403,1977,438)
3613
   ALIGN 4
3614
   MARGINS (1,1)
3615
   PARENT 22226
3616
  }
3617
  NET BUS  22353, 0, 0
3618
  INSTANCE  22394, 0, 0
3619
  {
3620
   VARIABLES
3621
   {
3622
    #COMPONENT="BusInput"
3623
    #LIBRARY="#terminals"
3624
    #REFERENCE="zz_ins_i(31:0)"
3625
    #SYMBOL="BusInput"
3626
   }
3627
   COORD (2140,240)
3628
   VERTEXES ( (2,26143) )
3629
  }
3630
  TEXT  22395, 0, 0
3631
  {
3632
   TEXT "$#REFERENCE"
3633
   RECT (1849,223,2089,258)
3634
   ALIGN 6
3635
   MARGINS (1,1)
3636
   PARENT 22394
3637
  }
3638
  NET BUS  22401, 0, 0
3639
  NET BUS  22426, 0, 0
3640
  INSTANCE  22434, 0, 0
3641
  {
3642
   VARIABLES
3643
   {
3644
    #COMPONENT="BusOutput"
3645
    #LIBRARY="#terminals"
3646
    #REFERENCE="zz_addr_o(31:0)"
3647
    #SYMBOL="BusOutput"
3648
    #VERILOG_TYPE="wire"
3649
   }
3650
   COORD (2140,360)
3651
   ORIENTATION 2
3652
   VERTEXES ( (2,26069) )
3653
  }
3654
  TEXT  22435, 0, 0
3655
  {
3656
   TEXT "$#REFERENCE"
3657
   RECT (1831,343,2088,378)
3658
   ALIGN 6
3659
   MARGINS (1,1)
3660
   PARENT 22434
3661
   ORIENTATION 2
3662
  }
3663
  INSTANCE  22638, 0, 0
3664
  {
3665
   VARIABLES
3666
   {
3667
    #COMPONENT="BusOutput"
3668
    #LIBRARY="#terminals"
3669
    #REFERENCE="zz_pc_o(31:0)"
3670
    #SYMBOL="BusOutput"
3671
   }
3672
   COORD (320,1520)
3673
   VERTEXES ( (2,27049) )
3674
  }
3675
  TEXT  22639, 0, 0
3676
  {
3677
   TEXT "$#REFERENCE"
3678
   RECT (372,1503,595,1538)
3679
   ALIGN 4
3680
   MARGINS (1,1)
3681
   PARENT 22638
3682
   ORIENTATION 2
3683
  }
3684
  INSTANCE  22721, 0, 0
3685
  {
3686
   VARIABLES
3687
   {
3688
    #COMPONENT="Input"
3689
    #LIBRARY="#terminals"
3690
    #REFERENCE="clk"
3691
    #SYMBOL="Input"
3692
    #VERILOG_TYPE="wire"
3693
   }
3694
   COORD (240,160)
3695
   VERTEXES ( (2,25633) )
3696
  }
3697
  TEXT  22722, 0, 0
3698
  {
3699
   TEXT "$#REFERENCE"
3700
   RECT (136,143,189,178)
3701
   ALIGN 6
3702
   MARGINS (1,1)
3703
   PARENT 22721
3704
  }
3705
  VTX  23895, 0, 0
3706
  {
3707
   COORD (1600,1480)
3708
  }
3709
  VTX  23896, 0, 0
3710
  {
3711
   COORD (1560,1480)
3712
  }
3713
  VTX  23897, 0, 0
3714
  {
3715
   COORD (1700,1240)
3716
  }
3717
  VTX  23898, 0, 0
3718
  {
3719
   COORD (1780,1440)
3720
  }
3721
  VTX  23899, 0, 0
3722
  {
3723
   COORD (1580,1660)
3724
  }
3725
  VTX  23900, 0, 0
3726
  {
3727
   COORD (1520,1280)
3728
  }
3729
  VTX  23901, 0, 0
3730
  {
3731
   COORD (1740,1060)
3732
  }
3733
  VTX  23902, 0, 0
3734
  {
3735
   COORD (2280,500)
3736
  }
3737
  VTX  23903, 0, 0
3738
  {
3739
   COORD (2240,120)
3740
  }
3741
  VTX  23905, 0, 0
3742
  {
3743
   COORD (2180,120)
3744
  }
3745
  VTX  23906, 0, 0
3746
  {
3747
   COORD (2500,880)
3748
  }
3749
  VTX  23907, 0, 0
3750
  {
3751
   COORD (2500,960)
3752
  }
3753
  VTX  23908, 0, 0
3754
  {
3755
   COORD (1580,120)
3756
  }
3757
  VTX  23909, 0, 0
3758
  {
3759
   COORD (1560,1060)
3760
  }
3761
  VTX  23910, 0, 0
3762
  {
3763
   COORD (1540,1060)
3764
  }
3765
  VTX  23911, 0, 0
3766
  {
3767
   COORD (1520,1240)
3768
  }
3769
  VTX  23913, 0, 0
3770
  {
3771
   COORD (260,280)
3772
  }
3773
  VTX  23914, 0, 0
3774
  {
3775
   COORD (1600,1440)
3776
  }
3777
  VTX  23915, 0, 0
3778
  {
3779
   COORD (1540,1800)
3780
  }
3781
  VTX  23916, 0, 0
3782
  {
3783
   COORD (2520,1700)
3784
  }
3785
  VTX  23917, 0, 0
3786
  {
3787
   COORD (2540,1700)
3788
  }
3789
  VTX  23918, 0, 0
3790
  {
3791
   COORD (2520,1480)
3792
  }
3793
  VTX  23919, 0, 0
3794
  {
3795
   COORD (2540,1480)
3796
  }
3797
  VTX  23920, 0, 0
3798
  {
3799
   COORD (2540,1300)
3800
  }
3801
  VTX  23921, 0, 0
3802
  {
3803
   COORD (2500,1300)
3804
  }
3805
  VTX  23922, 0, 0
3806
  {
3807
   COORD (2780,920)
3808
  }
3809
  VTX  23923, 0, 0
3810
  {
3811
   COORD (2740,960)
3812
  }
3813
  VTX  23924, 0, 0
3814
  {
3815
   COORD (2780,960)
3816
  }
3817
  VTX  23925, 0, 0
3818
  {
3819
   COORD (2540,780)
3820
  }
3821
  VTX  23927, 0, 0
3822
  {
3823
   COORD (2540,960)
3824
  }
3825
  VTX  23932, 0, 0
3826
  {
3827
   COORD (2180,680)
3828
  }
3829
  VTX  23933, 0, 0
3830
  {
3831
   COORD (2280,680)
3832
  }
3833
  VTX  23934, 0, 0
3834
  {
3835
   COORD (2560,740)
3836
  }
3837
  VTX  23935, 0, 0
3838
  {
3839
   COORD (2480,680)
3840
  }
3841
  VTX  23936, 0, 0
3842
  {
3843
   COORD (2560,680)
3844
  }
3845
  VTX  23939, 0, 0
3846
  {
3847
   COORD (1820,1640)
3848
  }
3849
  VTX  23940, 0, 0
3850
  {
3851
   COORD (3100,480)
3852
  }
3853
  VTX  23941, 0, 0
3854
  {
3855
   COORD (2800,300)
3856
  }
3857
  VTX  23942, 0, 0
3858
  {
3859
   COORD (2840,300)
3860
  }
3861
  VTX  23943, 0, 0
3862
  {
3863
   COORD (2800,520)
3864
  }
3865
  VTX  23944, 0, 0
3866
  {
3867
   COORD (3040,300)
3868
  }
3869
  VTX  23945, 0, 0
3870
  {
3871
   COORD (2480,500)
3872
  }
3873
  VTX  23946, 0, 0
3874
  {
3875
   COORD (2840,340)
3876
  }
3877
  VTX  23947, 0, 0
3878
  {
3879
   COORD (860,1660)
3880
  }
3881
  VTX  23948, 0, 0
3882
  {
3883
   COORD (660,1660)
3884
  }
3885
  VTX  23949, 0, 0
3886
  {
3887
   COORD (340,280)
3888
  }
3889
  VTX  23950, 0, 0
3890
  {
3891
   COORD (1540,760)
3892
  }
3893
  VTX  23951, 0, 0
3894
  {
3895
   COORD (340,400)
3896
  }
3897
  VTX  23952, 0, 0
3898
  {
3899
   COORD (980,400)
3900
  }
3901
  VTX  23953, 0, 0
3902
  {
3903
   COORD (700,400)
3904
  }
3905
  VTX  23958, 0, 0
3906
  {
3907
   COORD (320,1380)
3908
  }
3909
  VTX  23960, 0, 0
3910
  {
3911
   COORD (700,760)
3912
  }
3913
  VTX  23961, 0, 0
3914
  {
3915
   COORD (780,1560)
3916
  }
3917
  VTX  23968, 0, 0
3918
  {
3919
   COORD (700,360)
3920
  }
3921
  VTX  23969, 0, 0
3922
  {
3923
   COORD (920,920)
3924
  }
3925
  VTX  23970, 0, 0
3926
  {
3927
   COORD (700,480)
3928
  }
3929
  VTX  23971, 0, 0
3930
  {
3931
   COORD (920,960)
3932
  }
3933
  VTX  23972, 0, 0
3934
  {
3935
   COORD (340,320)
3936
  }
3937
  VTX  23973, 0, 0
3938
  {
3939
   COORD (1320,960)
3940
  }
3941
  VTX  23974, 0, 0
3942
  {
3943
   COORD (920,1000)
3944
  }
3945
  VTX  23976, 0, 0
3946
  {
3947
   COORD (1440,980)
3948
  }
3949
  VTX  23977, 0, 0
3950
  {
3951
   COORD (1320,1000)
3952
  }
3953
  VTX  23978, 0, 0
3954
  {
3955
   COORD (2020,1840)
3956
  }
3957
  VTX  23979, 0, 0
3958
  {
3959
   COORD (920,1040)
3960
  }
3961
  VTX  23980, 0, 0
3962
  {
3963
   COORD (2020,1880)
3964
  }
3965
  VTX  23981, 0, 0
3966
  {
3967
   COORD (920,1080)
3968
  }
3969
  VTX  23982, 0, 0
3970
  {
3971
   COORD (340,440)
3972
  }
3973
  VTX  23983, 0, 0
3974
  {
3975
   COORD (1320,1080)
3976
  }
3977
  VTX  23984, 0, 0
3978
  {
3979
   COORD (1560,1100)
3980
  }
3981
  VTX  23985, 0, 0
3982
  {
3983
   COORD (1320,1120)
3984
  }
3985
  VTX  23995, 0, 0
3986
  {
3987
   COORD (2540,1520)
3988
  }
3989
  VTX  23996, 0, 0
3990
  {
3991
   COORD (1320,1280)
3992
  }
3993
  VTX  23997, 0, 0
3994
  {
3995
   COORD (680,1380)
3996
  }
3997
  VTX  23998, 0, 0
3998
  {
3999
   COORD (920,1360)
4000
  }
4001
  VTX  24001, 0, 0
4002
  {
4003
   COORD (920,1440)
4004
  }
4005
  VTX  24003, 0, 0
4006
  {
4007
   COORD (920,1560)
4008
  }
4009
  VTX  24006, 0, 0
4010
  {
4011
   COORD (920,1280)
4012
  }
4013
  VTX  24007, 0, 0
4014
  {
4015
   COORD (740,1280)
4016
  }
4017
  VTX  24010, 0, 0
4018
  {
4019
   COORD (920,1240)
4020
  }
4021
  VTX  24011, 0, 0
4022
  {
4023
   COORD (740,1240)
4024
  }
4025
  VTX  24012, 0, 0
4026
  {
4027
   COORD (1340,920)
4028
  }
4029
  VTX  24013, 0, 0
4030
  {
4031
   COORD (1320,920)
4032
  }
4033
  VTX  24042, 0, 0
4034
  {
4035
   COORD (1780,580)
4036
  }
4037
  VTX  24046, 0, 0
4038
  {
4039
   COORD (2140,280)
4040
  }
4041
  VTX  24047, 0, 0
4042
  {
4043
   COORD (2180,620)
4044
  }
4045
  VTX  24048, 0, 0
4046
  {
4047
   COORD (2140,320)
4048
  }
4049
  VTX  24049, 0, 0
4050
  {
4051
   COORD (2180,580)
4052
  }
4053
  VTX  24055, 0, 0
4054
  {
4055
   COORD (840,1520)
4056
  }
4057
  VTX  24056, 0, 0
4058
  {
4059
   COORD (920,1120)
4060
  }
4061
  VTX  24057, 0, 0
4062
  {
4063
   COORD (920,1520)
4064
  }
4065
  VTX  24059, 0, 0
4066
  {
4067
   COORD (520,1380)
4068
  }
4069
  VTX  24061, 0, 0
4070
  {
4071
   COORD (700,440)
4072
  }
4073
  VTX  24062, 0, 0
4074
  {
4075
   COORD (1780,660)
4076
  }
4077
  BUS  24066, 0, 0
4078
  {
4079
   NET 1724
4080
   VTX 23895, 23896
4081
  }
4082
  VTX  24067, 0, 0
4083
  {
4084
   COORD (1720,1240)
4085
  }
4086
  BUS  24068, 0, 0
4087
  {
4088
   NET 1724
4089
   VTX 23897, 24067
4090
  }
4091
  VTX  24069, 0, 0
4092
  {
4093
   COORD (1720,1380)
4094
  }
4095
  BUS  24070, 0, 0
4096
  {
4097
   NET 1724
4098
   VTX 24067, 24069
4099
  }
4100
  VTX  24071, 0, 0
4101
  {
4102
   COORD (1560,1380)
4103
  }
4104
  BUS  24072, 0, 0
4105
  {
4106
   NET 1724
4107
   VTX 24069, 24071
4108
  }
4109
  BUS  24073, 0, 0
4110
  {
4111
   NET 1724
4112
   VTX 24071, 23896
4113
  }
4114
  VTX  24074, 0, 0
4115
  {
4116
   COORD (1800,1440)
4117
  }
4118
  BUS  24075, 0, 0
4119
  {
4120
   NET 18211
4121
   VTX 23898, 24074
4122
  }
4123
  VTX  24076, 0, 0
4124
  {
4125
   COORD (1800,1660)
4126
  }
4127
  BUS  24077, 0, 0
4128
  {
4129
   NET 18211
4130
   VTX 24074, 24076
4131
  }
4132
  BUS  24078, 0, 0
4133
  {
4134
   NET 18211
4135
   VTX 24076, 23899
4136
  }
4137
  VTX  24079, 0, 0
4138
  {
4139
   COORD (1500,1280)
4140
  }
4141
  BUS  24080, 0, 0
4142
  {
4143
   NET 1726
4144
   VTX 23900, 24079
4145
  }
4146
  VTX  24081, 0, 0
4147
  {
4148
   COORD (1500,1180)
4149
  }
4150
  BUS  24082, 0, 0
4151
  {
4152
   NET 1726
4153
   VTX 24079, 24081
4154
  }
4155
  VTX  24083, 0, 0
4156
  {
4157
   COORD (1750,1180)
4158
  }
4159
  BUS  24084, 0, 0
4160
  {
4161
   NET 1726
4162
   VTX 24081, 24083
4163
  }
4164
  VTX  24085, 0, 0
4165
  {
4166
   COORD (1750,1060)
4167
  }
4168
  BUS  24086, 0, 0
4169
  {
4170
   NET 1726
4171
   VTX 24083, 24085
4172
  }
4173
  BUS  24087, 0, 0
4174
  {
4175
   NET 1726
4176
   VTX 24085, 23901
4177
  }
4178
  VTX  24088, 0, 0
4179
  {
4180
   COORD (2240,500)
4181
  }
4182
  WIRE  24089, 0, 0
4183
  {
4184
   NET 26196
4185
   VTX 23902, 24088
4186
  }
4187
  WIRE  24090, 0, 0
4188
  {
4189
   NET 26196
4190
   VTX 24088, 23903
4191
  }
4192
  WIRE  24092, 0, 0
4193
  {
4194
   NET 26196
4195
   VTX 23905, 23903
4196
  }
4197
  VTX  24093, 0, 0
4198
  {
4199
   COORD (2500,120)
4200
  }
4201
  WIRE  24094, 0, 0
4202
  {
4203
   NET 26196
4204
   VTX 23903, 24093
4205
  }
4206
  WIRE  24095, 0, 0
4207
  {
4208
   NET 26196
4209
   VTX 24093, 23906
4210
  }
4211
  WIRE  24096, 0, 0
4212
  {
4213
   NET 26196
4214
   VTX 23907, 23906
4215
  }
4216
  WIRE  24097, 0, 0
4217
  {
4218
   NET 26196
4219
   VTX 23908, 26745
4220
  }
4221
  WIRE  24098, 0, 0
4222
  {
4223
   NET 26196
4224
   VTX 23909, 23910
4225
  }
4226
  VTX  24099, 0, 0
4227
  {
4228
   COORD (1540,840)
4229
  }
4230
  WIRE  24100, 0, 0
4231
  {
4232
   NET 26196
4233
   VTX 23910, 24099
4234
  }
4235
  VTX  24101, 0, 0
4236
  {
4237
   COORD (1580,840)
4238
  }
4239
  WIRE  24102, 0, 0
4240
  {
4241
   NET 26196
4242
   VTX 24099, 24101
4243
  }
4244
  WIRE  24103, 0, 0
4245
  {
4246
   NET 26196
4247
   VTX 24101, 23908
4248
  }
4249
  VTX  24104, 0, 0
4250
  {
4251
   COORD (1540,1120)
4252
  }
4253
  WIRE  24105, 0, 0
4254
  {
4255
   NET 26196
4256
   VTX 23910, 24104
4257
  }
4258
  VTX  24106, 0, 0
4259
  {
4260
   COORD (1460,1120)
4261
  }
4262
  WIRE  24107, 0, 0
4263
  {
4264
   NET 26196
4265
   VTX 24104, 24106
4266
  }
4267
  VTX  24108, 0, 0
4268
  {
4269
   COORD (1460,1240)
4270
  }
4271
  WIRE  24109, 0, 0
4272
  {
4273
   NET 26196
4274
   VTX 24106, 24108
4275
  }
4276
  WIRE  24110, 0, 0
4277
  {
4278
   NET 26196
4279
   VTX 24108, 23911
4280
  }
4281
  VTX  24114, 0, 0
4282
  {
4283
   COORD (1540,1440)
4284
  }
4285
  WIRE  24115, 0, 0
4286
  {
4287
   NET 26196
4288
   VTX 23914, 24114
4289
  }
4290
  WIRE  24116, 0, 0
4291
  {
4292
   NET 26196
4293
   VTX 24114, 23915
4294
  }
4295
  WIRE  24118, 0, 0
4296
  {
4297
   NET 26196
4298
   VTX 23916, 23917
4299
  }
4300
  WIRE  24119, 0, 0
4301
  {
4302
   NET 26196
4303
   VTX 23918, 23916
4304
  }
4305
  WIRE  24120, 0, 0
4306
  {
4307
   NET 26196
4308
   VTX 23919, 23918
4309
  }
4310
  WIRE  24121, 0, 0
4311
  {
4312
   NET 26196
4313
   VTX 23920, 23921
4314
  }
4315
  VTX  24122, 0, 0
4316
  {
4317
   COORD (2500,1400)
4318
  }
4319
  WIRE  24123, 0, 0
4320
  {
4321
   NET 26196
4322
   VTX 23921, 24122
4323
  }
4324
  VTX  24124, 0, 0
4325
  {
4326
   COORD (2520,1400)
4327
  }
4328
  WIRE  24125, 0, 0
4329
  {
4330
   NET 26196
4331
   VTX 24122, 24124
4332
  }
4333
  WIRE  24126, 0, 0
4334
  {
4335
   NET 26196
4336
   VTX 24124, 23918
4337
  }
4338
  VTX  24127, 0, 0
4339
  {
4340
   COORD (2760,880)
4341
  }
4342
  WIRE  24128, 0, 0
4343
  {
4344
   NET 26196
4345
   VTX 23906, 24127
4346
  }
4347
  VTX  24129, 0, 0
4348
  {
4349
   COORD (2760,920)
4350
  }
4351
  WIRE  24130, 0, 0
4352
  {
4353
   NET 26196
4354
   VTX 24127, 24129
4355
  }
4356
  WIRE  24131, 0, 0
4357
  {
4358
   NET 26196
4359
   VTX 24129, 23922
4360
  }
4361
  BUS  24132, 0, 0
4362
  {
4363
   NET 29854
4364
   VTX 23923, 23924
4365
  }
4366
  VTX  24133, 0, 0
4367
  {
4368
   COORD (2740,780)
4369
  }
4370
  BUS  24134, 0, 0
4371
  {
4372
   NET 29854
4373
   VTX 23923, 24133
4374
  }
4375
  BUS  24135, 0, 0
4376
  {
4377
   NET 29854
4378
   VTX 24133, 23925
4379
  }
4380
  BUS  24136, 0, 0
4381
  {
4382
   NET 29854
4383
   VTX 26673, 23925
4384
  }
4385
  VTX  24137, 0, 0
4386
  {
4387
   COORD (1540,2160)
4388
  }
4389
  WIRE  24138, 0, 0
4390
  {
4391
   NET 26196
4392
   VTX 23915, 24137
4393
  }
4394
  VTX  24139, 0, 0
4395
  {
4396
   COORD (2180,2160)
4397
  }
4398
  WIRE  24140, 0, 0
4399
  {
4400
   NET 26196
4401
   VTX 24137, 24139
4402
  }
4403
  VTX  24141, 0, 0
4404
  {
4405
   COORD (2180,1840)
4406
  }
4407
  WIRE  24142, 0, 0
4408
  {
4409
   NET 26196
4410
   VTX 24139, 24141
4411
  }
4412
  VTX  24143, 0, 0
4413
  {
4414
   COORD (2520,1840)
4415
  }
4416
  WIRE  24144, 0, 0
4417
  {
4418
   NET 26196
4419
   VTX 24141, 24143
4420
  }
4421
  WIRE  24145, 0, 0
4422
  {
4423
   NET 26196
4424
   VTX 24143, 23916
4425
  }
4426
  WIRE  24146, 0, 0
4427
  {
4428
   NET 26196
4429
   VTX 23907, 23927
4430
  }
4431
  WIRE  24147, 0, 0
4432
  {
4433
   NET 26196
4434
   VTX 23907, 23921
4435
  }
4436
  WIRE  24152, 0, 0
4437
  {
4438
   NET 26196
4439
   VTX 23905, 28063
4440
  }
4441
  WIRE  24153, 0, 0
4442
  {
4443
   NET 26196
4444
   VTX 23933, 23932
4445
  }
4446
  VTX  24154, 0, 0
4447
  {
4448
   COORD (2540,740)
4449
  }
4450
  BUS  24155, 0, 0
4451
  {
4452
   NET 29854
4453
   VTX 23925, 24154
4454
  }
4455
  BUS  24156, 0, 0
4456
  {
4457
   NET 29854
4458
   VTX 24154, 23934
4459
  }
4460
  BUS  24157, 0, 0
4461
  {
4462
   NET 9899
4463
   VTX 23935, 23936
4464
  }
4465
  VTX  24167, 0, 0
4466
  {
4467
   COORD (3110,1640)
4468
  }
4469
  BUS  24168, 0, 0
4470
  {
4471
   NET 15471
4472
   VTX 23939, 24167
4473
  }
4474
  VTX  24169, 0, 0
4475
  {
4476
   COORD (3110,480)
4477
  }
4478
  BUS  24170, 0, 0
4479
  {
4480
   NET 15471
4481
   VTX 24167, 24169
4482
  }
4483
  BUS  24171, 0, 0
4484
  {
4485
   NET 15471
4486
   VTX 24169, 23940
4487
  }
4488
  BUS  24172, 0, 0
4489
  {
4490
   NET 7446
4491
   VTX 23941, 23942
4492
  }
4493
  VTX  24173, 0, 0
4494
  {
4495
   COORD (2780,520)
4496
  }
4497
  BUS  24174, 0, 0
4498
  {
4499
   NET 7780
4500
   VTX 23943, 24173
4501
  }
4502
  VTX  24175, 0, 0
4503
  {
4504
   COORD (2780,400)
4505
  }
4506
  BUS  24176, 0, 0
4507
  {
4508
   NET 7780
4509
   VTX 24173, 24175
4510
  }
4511
  VTX  24177, 0, 0
4512
  {
4513
   COORD (3050,400)
4514
  }
4515
  BUS  24178, 0, 0
4516
  {
4517
   NET 7780
4518
   VTX 24175, 24177
4519
  }
4520
  VTX  24179, 0, 0
4521
  {
4522
   COORD (3050,300)
4523
  }
4524
  BUS  24180, 0, 0
4525
  {
4526
   NET 7780
4527
   VTX 24177, 24179
4528
  }
4529
  BUS  24181, 0, 0
4530
  {
4531
   NET 7780
4532
   VTX 24179, 23944
4533
  }
4534
  VTX  24182, 0, 0
4535
  {
4536
   COORD (2540,500)
4537
  }
4538
  BUS  24183, 0, 0
4539
  {
4540
   NET 7772
4541
   VTX 23945, 24182
4542
  }
4543
  VTX  24184, 0, 0
4544
  {
4545
   COORD (2540,340)
4546
  }
4547
  BUS  24185, 0, 0
4548
  {
4549
   NET 7772
4550
   VTX 24182, 24184
4551
  }
4552
  BUS  24186, 0, 0
4553
  {
4554
   NET 7772
4555
   VTX 24184, 23946
4556
  }
4557
  WIRE  24187, 0, 0
4558
  {
4559
   NET 7555
4560
   VTX 23947, 23948
4561
  }
4562
  WIRE  24188, 0, 0
4563
  {
4564
   NET 26196
4565
   VTX 23913, 23949
4566
  }
4567
  VTX  24189, 0, 0
4568
  {
4569
   COORD (1540,180)
4570
  }
4571
  BUS  24190, 0, 0
4572
  {
4573
   NET 22353
4574
   VTX 23950, 24189
4575
  }
4576
  VTX  24191, 0, 0
4577
  {
4578
   COORD (320,180)
4579
  }
4580
  BUS  24192, 0, 0
4581
  {
4582
   NET 22353
4583
   VTX 24189, 24191
4584
  }
4585
  VTX  24193, 0, 0
4586
  {
4587
   COORD (320,400)
4588
  }
4589
  BUS  24194, 0, 0
4590
  {
4591
   NET 22353
4592
   VTX 24191, 24193
4593
  }
4594
  BUS  24195, 0, 0
4595
  {
4596
   NET 22353
4597
   VTX 24193, 23951
4598
  }
4599
  BUS  24196, 0, 0
4600
  {
4601
   NET 7471
4602
   VTX 23952, 23953
4603
  }
4604
  VTX  24215, 0, 0
4605
  {
4606
   COORD (260,1380)
4607
  }
4608
  WIRE  24216, 0, 0
4609
  {
4610
   NET 26196
4611
   VTX 23913, 24215
4612
  }
4613
  WIRE  24217, 0, 0
4614
  {
4615
   NET 26196
4616
   VTX 24215, 23958
4617
  }
4618
  VTX  24221, 0, 0
4619
  {
4620
   COORD (820,760)
4621
  }
4622
  WIRE  24222, 0, 0
4623
  {
4624
   NET 1375
4625
   VTX 23960, 24221
4626
  }
4627
  VTX  24223, 0, 0
4628
  {
4629
   COORD (820,1340)
4630
  }
4631
  WIRE  24224, 0, 0
4632
  {
4633
   NET 1375
4634
   VTX 24221, 24223
4635
  }
4636
  VTX  24225, 0, 0
4637
  {
4638
   COORD (780,1340)
4639
  }
4640
  WIRE  24226, 0, 0
4641
  {
4642
   NET 1375
4643
   VTX 24223, 24225
4644
  }
4645
  WIRE  24227, 0, 0
4646
  {
4647
   NET 1375
4648
   VTX 24225, 23961
4649
  }
4650
  VTX  24263, 0, 0
4651
  {
4652
   COORD (720,360)
4653
  }
4654
  BUS  24264, 0, 0
4655
  {
4656
   NET 109
4657
   VTX 23968, 24263
4658
  }
4659
  VTX  24265, 0, 0
4660
  {
4661
   COORD (720,220)
4662
  }
4663
  BUS  24266, 0, 0
4664
  {
4665
   NET 109
4666
   VTX 24263, 24265
4667
  }
4668
  VTX  24267, 0, 0
4669
  {
4670
   COORD (180,220)
4671
  }
4672
  BUS  24268, 0, 0
4673
  {
4674
   NET 109
4675
   VTX 24265, 24267
4676
  }
4677
  VTX  24269, 0, 0
4678
  {
4679
   COORD (180,900)
4680
  }
4681
  BUS  24270, 0, 0
4682
  {
4683
   NET 109
4684
   VTX 24267, 24269
4685
  }
4686
  VTX  24271, 0, 0
4687
  {
4688
   COORD (900,900)
4689
  }
4690
  BUS  24272, 0, 0
4691
  {
4692
   NET 109
4693
   VTX 24269, 24271
4694
  }
4695
  VTX  24273, 0, 0
4696
  {
4697
   COORD (900,920)
4698
  }
4699
  BUS  24274, 0, 0
4700
  {
4701
   NET 109
4702
   VTX 24271, 24273
4703
  }
4704
  BUS  24275, 0, 0
4705
  {
4706
   NET 109
4707
   VTX 24273, 23969
4708
  }
4709
  VTX  24276, 0, 0
4710
  {
4711
   COORD (840,480)
4712
  }
4713
  BUS  24277, 0, 0
4714
  {
4715
   NET 117
4716
   VTX 23970, 24276
4717
  }
4718
  VTX  24278, 0, 0
4719
  {
4720
   COORD (840,940)
4721
  }
4722
  BUS  24279, 0, 0
4723
  {
4724
   NET 117
4725
   VTX 24276, 24278
4726
  }
4727
  VTX  24280, 0, 0
4728
  {
4729
   COORD (900,940)
4730
  }
4731
  BUS  24281, 0, 0
4732
  {
4733
   NET 117
4734
   VTX 24278, 24280
4735
  }
4736
  VTX  24282, 0, 0
4737
  {
4738
   COORD (900,960)
4739
  }
4740
  BUS  24283, 0, 0
4741
  {
4742
   NET 117
4743
   VTX 24280, 24282
4744
  }
4745
  BUS  24284, 0, 0
4746
  {
4747
   NET 117
4748
   VTX 24282, 23971
4749
  }
4750
  VTX  24285, 0, 0
4751
  {
4752
   COORD (280,320)
4753
  }
4754
  WIRE  24286, 0, 0
4755
  {
4756
   NET 1606
4757
   VTX 23972, 24285
4758
  }
4759
  VTX  24287, 0, 0
4760
  {
4761
   COORD (280,200)
4762
  }
4763
  WIRE  24288, 0, 0
4764
  {
4765
   NET 1606
4766
   VTX 24285, 24287
4767
  }
4768
  VTX  24289, 0, 0
4769
  {
4770
   COORD (1460,200)
4771
  }
4772
  WIRE  24290, 0, 0
4773
  {
4774
   NET 1606
4775
   VTX 24287, 24289
4776
  }
4777
  VTX  24291, 0, 0
4778
  {
4779
   COORD (1460,940)
4780
  }
4781
  WIRE  24292, 0, 0
4782
  {
4783
   NET 1606
4784
   VTX 24289, 24291
4785
  }
4786
  VTX  24293, 0, 0
4787
  {
4788
   COORD (1340,940)
4789
  }
4790
  WIRE  24294, 0, 0
4791
  {
4792
   NET 1606
4793
   VTX 24291, 24293
4794
  }
4795
  VTX  24295, 0, 0
4796
  {
4797
   COORD (1340,960)
4798
  }
4799
  WIRE  24296, 0, 0
4800
  {
4801
   NET 1606
4802
   VTX 24293, 24295
4803
  }
4804
  WIRE  24297, 0, 0
4805
  {
4806
   NET 1606
4807
   VTX 24295, 23973
4808
  }
4809
  VTX  24298, 0, 0
4810
  {
4811
   COORD (880,780)
4812
  }
4813
  VTX  24300, 0, 0
4814
  {
4815
   COORD (880,1000)
4816
  }
4817
  BUS  24301, 0, 0
4818
  {
4819
   NET 29854
4820
   VTX 24298, 24300
4821
  }
4822
  BUS  24302, 0, 0
4823
  {
4824
   NET 29854
4825
   VTX 24300, 23974
4826
  }
4827
  VTX  24310, 0, 0
4828
  {
4829
   COORD (1340,980)
4830
  }
4831
  WIRE  24311, 0, 0
4832
  {
4833
   NET 1572
4834
   VTX 23976, 24310
4835
  }
4836
  VTX  24312, 0, 0
4837
  {
4838
   COORD (1340,1000)
4839
  }
4840
  WIRE  24313, 0, 0
4841
  {
4842
   NET 1572
4843
   VTX 24310, 24312
4844
  }
4845
  WIRE  24314, 0, 0
4846
  {
4847
   NET 1572
4848
   VTX 24312, 23977
4849
  }
4850
  VTX  24315, 0, 0
4851
  {
4852
   COORD (2060,1840)
4853
  }
4854
  BUS  24316, 0, 0
4855
  {
4856
   NET 2140
4857
   VTX 23978, 24315
4858
  }
4859
  VTX  24317, 0, 0
4860
  {
4861
   COORD (2060,1620)
4862
  }
4863
  BUS  24318, 0, 0
4864
  {
4865
   NET 2140
4866
   VTX 24315, 24317
4867
  }
4868
  VTX  24319, 0, 0
4869
  {
4870
   COORD (1520,1620)
4871
  }
4872
  BUS  24320, 0, 0
4873
  {
4874
   NET 2140
4875
   VTX 24317, 24319
4876
  }
4877
  VTX  24321, 0, 0
4878
  {
4879
   COORD (1520,1720)
4880
  }
4881
  BUS  24322, 0, 0
4882
  {
4883
   NET 2140
4884
   VTX 24319, 24321
4885
  }
4886
  VTX  24323, 0, 0
4887
  {
4888
   COORD (760,1720)
4889
  }
4890
  BUS  24324, 0, 0
4891
  {
4892
   NET 2140
4893
   VTX 24321, 24323
4894
  }
4895
  VTX  24325, 0, 0
4896
  {
4897
   COORD (760,1040)
4898
  }
4899
  BUS  24326, 0, 0
4900
  {
4901
   NET 2140
4902
   VTX 24323, 24325
4903
  }
4904
  BUS  24327, 0, 0
4905
  {
4906
   NET 2140
4907
   VTX 24325, 23979
4908
  }
4909
  VTX  24328, 0, 0
4910
  {
4911
   COORD (2080,1880)
4912
  }
4913
  BUS  24329, 0, 0
4914
  {
4915
   NET 2156
4916
   VTX 23980, 24328
4917
  }
4918
  VTX  24330, 0, 0
4919
  {
4920
   COORD (2080,2200)
4921
  }
4922
  BUS  24331, 0, 0
4923
  {
4924
   NET 2156
4925
   VTX 24328, 24330
4926
  }
4927
  VTX  24332, 0, 0
4928
  {
4929
   COORD (800,2200)
4930
  }
4931
  BUS  24333, 0, 0
4932
  {
4933
   NET 2156
4934
   VTX 24330, 24332
4935
  }
4936
  VTX  24334, 0, 0
4937
  {
4938
   COORD (800,1400)
4939
  }
4940
  BUS  24335, 0, 0
4941
  {
4942
   NET 2156
4943
   VTX 24332, 24334
4944
  }
4945
  VTX  24336, 0, 0
4946
  {
4947
   COORD (860,1400)
4948
  }
4949
  BUS  24337, 0, 0
4950
  {
4951
   NET 2156
4952
   VTX 24334, 24336
4953
  }
4954
  VTX  24338, 0, 0
4955
  {
4956
   COORD (860,1080)
4957
  }
4958
  BUS  24339, 0, 0
4959
  {
4960
   NET 2156
4961
   VTX 24336, 24338
4962
  }
4963
  BUS  24340, 0, 0
4964
  {
4965
   NET 2156
4966
   VTX 24338, 23981
4967
  }
4968
  VTX  24341, 0, 0
4969
  {
4970
   COORD (320,440)
4971
  }
4972
  WIRE  24342, 0, 0
4973
  {
4974
   NET 1640
4975
   VTX 23982, 24341
4976
  }
4977
  VTX  24343, 0, 0
4978
  {
4979
   COORD (320,820)
4980
  }
4981
  WIRE  24344, 0, 0
4982
  {
4983
   NET 1640
4984
   VTX 24341, 24343
4985
  }
4986
  VTX  24345, 0, 0
4987
  {
4988
   COORD (900,820)
4989
  }
4990
  WIRE  24346, 0, 0
4991
  {
4992
   NET 1640
4993
   VTX 24343, 24345
4994
  }
4995
  VTX  24347, 0, 0
4996
  {
4997
   COORD (900,800)
4998
  }
4999
  WIRE  24348, 0, 0
5000
  {
5001
   NET 1640
5002
   VTX 24345, 24347
5003
  }
5004
  VTX  24349, 0, 0
5005
  {
5006
   COORD (1360,800)
5007
  }
5008
  WIRE  24350, 0, 0
5009
  {
5010
   NET 1640
5011
   VTX 24347, 24349
5012
  }
5013
  VTX  24351, 0, 0
5014
  {
5015
   COORD (1360,1020)
5016
  }
5017
  WIRE  24352, 0, 0
5018
  {
5019
   NET 1640
5020
   VTX 24349, 24351
5021
  }
5022
  VTX  24353, 0, 0
5023
  {
5024
   COORD (1340,1020)
5025
  }
5026
  WIRE  24354, 0, 0
5027
  {
5028
   NET 1640
5029
   VTX 24351, 24353
5030
  }
5031
  VTX  24355, 0, 0
5032
  {
5033
   COORD (1340,1080)
5034
  }
5035
  WIRE  24356, 0, 0
5036
  {
5037
   NET 1640
5038
   VTX 24353, 24355
5039
  }
5040
  WIRE  24357, 0, 0
5041
  {
5042
   NET 1640
5043
   VTX 24355, 23983
5044
  }
5045
  VTX  24358, 0, 0
5046
  {
5047
   COORD (1340,1100)
5048
  }
5049
  BUS  24359, 0, 0
5050
  {
5051
   NET 775
5052
   VTX 23984, 24358
5053
  }
5054
  VTX  24360, 0, 0
5055
  {
5056
   COORD (1340,1120)
5057
  }
5058
  BUS  24361, 0, 0
5059
  {
5060
   NET 775
5061
   VTX 24358, 24360
5062
  }
5063
  BUS  24362, 0, 0
5064
  {
5065
   NET 775
5066
   VTX 24360, 23985
5067
  }
5068
  VTX  24416, 0, 0
5069
  {
5070
   COORD (2500,1520)
5071
  }
5072
  BUS  24417, 0, 0
5073
  {
5074
   NET 7160
5075
   VTX 23995, 24416
5076
  }
5077
  VTX  24418, 0, 0
5078
  {
5079
   COORD (2500,1820)
5080
  }
5081
  BUS  24419, 0, 0
5082
  {
5083
   NET 7160
5084
   VTX 24416, 24418
5085
  }
5086
  VTX  24420, 0, 0
5087
  {
5088
   COORD (2140,1820)
5089
  }
5090
  BUS  24421, 0, 0
5091
  {
5092
   NET 7160
5093
   VTX 24418, 24420
5094
  }
5095
  VTX  24422, 0, 0
5096
  {
5097
   COORD (2140,2140)
5098
  }
5099
  BUS  24423, 0, 0
5100
  {
5101
   NET 7160
5102
   VTX 24420, 24422
5103
  }
5104
  VTX  24424, 0, 0
5105
  {
5106
   COORD (1380,2140)
5107
  }
5108
  BUS  24425, 0, 0
5109
  {
5110
   NET 7160
5111
   VTX 24422, 24424
5112
  }
5113
  VTX  24426, 0, 0
5114
  {
5115
   COORD (1380,1280)
5116
  }
5117
  BUS  24427, 0, 0
5118
  {
5119
   NET 7160
5120
   VTX 24424, 24426
5121
  }
5122
  BUS  24428, 0, 0
5123
  {
5124
   NET 7160
5125
   VTX 24426, 23996
5126
  }
5127
  VTX  24429, 0, 0
5128
  {
5129
   COORD (720,1380)
5130
  }
5131
  BUS  24430, 0, 0
5132
  {
5133
   NET 27031
5134
   VTX 23997, 24429
5135
  }
5136
  VTX  24431, 0, 0
5137
  {
5138
   COORD (720,1360)
5139
  }
5140
  BUS  24432, 0, 0
5141
  {
5142
   NET 27031
5143
   VTX 24429, 24431
5144
  }
5145
  BUS  24433, 0, 0
5146
  {
5147
   NET 27031
5148
   VTX 24431, 23998
5149
  }
5150
  VTX  24447, 0, 0
5151
  {
5152
   COORD (860,1440)
5153
  }
5154
  WIRE  24448, 0, 0
5155
  {
5156
   NET 7555
5157
   VTX 24001, 24447
5158
  }
5159
  WIRE  24449, 0, 0
5160
  {
5161
   NET 7555
5162
   VTX 24447, 23947
5163
  }
5164
  WIRE  24459, 0, 0
5165
  {
5166
   NET 1375
5167
   VTX 23961, 24003
5168
  }
5169
  WIRE  24485, 0, 0
5170
  {
5171
   NET 6336
5172
   VTX 24006, 24007
5173
  }
5174
  BUS  24495, 0, 0
5175
  {
5176
   NET 6364
5177
   VTX 24010, 24011
5178
  }
5179
  WIRE  24496, 0, 0
5180
  {
5181
   NET 21056
5182
   VTX 24012, 24013
5183
  }
5184
  VTX  24696, 0, 0
5185
  {
5186
   COORD (1740,840)
5187
  }
5188
  VTX  24698, 0, 0
5189
  {
5190
   COORD (1740,580)
5191
  }
5192
  BUS  24699, 0, 0
5193
  {
5194
   NET 9884
5195
   VTX 24696, 24698
5196
  }
5197
  BUS  24700, 0, 0
5198
  {
5199
   NET 9884
5200
   VTX 24698, 24042
5201
  }
5202
  VTX  24715, 0, 0
5203
  {
5204
   COORD (2220,280)
5205
  }
5206
  BUS  24716, 0, 0
5207
  {
5208
   NET 22164
5209
   VTX 24046, 24715
5210
  }
5211
  VTX  24717, 0, 0
5212
  {
5213
   COORD (2220,620)
5214
  }
5215
  BUS  24718, 0, 0
5216
  {
5217
   NET 22164
5218
   VTX 24715, 24717
5219
  }
5220
  BUS  24719, 0, 0
5221
  {
5222
   NET 22164
5223
   VTX 24717, 24047
5224
  }
5225
  VTX  24720, 0, 0
5226
  {
5227
   COORD (2200,320)
5228
  }
5229
  BUS  24721, 0, 0
5230
  {
5231
   NET 22155
5232
   VTX 24048, 24720
5233
  }
5234
  VTX  24722, 0, 0
5235
  {
5236
   COORD (2200,580)
5237
  }
5238
  BUS  24723, 0, 0
5239
  {
5240
   NET 22155
5241
   VTX 24720, 24722
5242
  }
5243
  BUS  24724, 0, 0
5244
  {
5245
   NET 22155
5246
   VTX 24722, 24049
5247
  }
5248
  VTX  24750, 0, 0
5249
  {
5250
   COORD (840,1120)
5251
  }
5252
  BUS  24751, 0, 0
5253
  {
5254
   NET 15471
5255
   VTX 24055, 24750
5256
  }
5257
  BUS  24752, 0, 0
5258
  {
5259
   NET 15471
5260
   VTX 24750, 24056
5261
  }
5262
  BUS  24753, 0, 0
5263
  {
5264
   NET 15471
5265
   VTX 24055, 24057
5266
  }
5267
  VTX  24754, 0, 0
5268
  {
5269
   COORD (840,1800)
5270
  }
5271
  BUS  24755, 0, 0
5272
  {
5273
   NET 15471
5274
   VTX 24055, 24754
5275
  }
5276
  VTX  24756, 0, 0
5277
  {
5278
   COORD (1500,1800)
5279
  }
5280
  BUS  24757, 0, 0
5281
  {
5282
   NET 15471
5283
   VTX 24754, 24756
5284
  }
5285
  VTX  24758, 0, 0
5286
  {
5287
   COORD (1500,1680)
5288
  }
5289
  BUS  24759, 0, 0
5290
  {
5291
   NET 15471
5292
   VTX 24756, 24758
5293
  }
5294
  VTX  24760, 0, 0
5295
  {
5296
   COORD (1820,1680)
5297
  }
5298
  BUS  24761, 0, 0
5299
  {
5300
   NET 15471
5301
   VTX 24758, 24760
5302
  }
5303
  BUS  24762, 0, 0
5304
  {
5305
   NET 15471
5306
   VTX 24760, 23939
5307
  }
5308
  VTX  24768, 0, 0
5309
  {
5310
   COORD (1660,440)
5311
  }
5312
  BUS  24769, 0, 0
5313
  {
5314
   NET 5985
5315
   VTX 24061, 24768
5316
  }
5317
  VTX  24770, 0, 0
5318
  {
5319
   COORD (1660,660)
5320
  }
5321
  BUS  24771, 0, 0
5322
  {
5323
   NET 5985
5324
   VTX 24768, 24770
5325
  }
5326
  BUS  24772, 0, 0
5327
  {
5328
   NET 5985
5329
   VTX 24770, 24062
5330
  }
5331
  NET BUS  24839, 0, 0
5332
  VTX  24861, 0, 0
5333
  {
5334
   COORD (2540,1340)
5335
  }
5336
  VTX  24862, 0, 0
5337
  {
5338
   COORD (1320,1200)
5339
  }
5340
  VTX  24863, 0, 0
5341
  {
5342
   COORD (2440,1340)
5343
  }
5344
  BUS  24864, 0, 0
5345
  {
5346
   NET 24839
5347
   VTX 24861, 24863
5348
  }
5349
  VTX  24865, 0, 0
5350
  {
5351
   COORD (2440,1560)
5352
  }
5353
  BUS  24866, 0, 0
5354
  {
5355
   NET 24839
5356
   VTX 24863, 24865
5357
  }
5358
  VTX  24867, 0, 0
5359
  {
5360
   COORD (2160,1560)
5361
  }
5362
  BUS  24868, 0, 0
5363
  {
5364
   NET 24839
5365
   VTX 24865, 24867
5366
  }
5367
  VTX  24869, 0, 0
5368
  {
5369
   COORD (2160,2220)
5370
  }
5371
  BUS  24870, 0, 0
5372
  {
5373
   NET 24839
5374
   VTX 24867, 24869
5375
  }
5376
  VTX  24871, 0, 0
5377
  {
5378
   COORD (1400,2220)
5379
  }
5380
  BUS  24872, 0, 0
5381
  {
5382
   NET 24839
5383
   VTX 24869, 24871
5384
  }
5385
  VTX  24873, 0, 0
5386
  {
5387
   COORD (1400,1200)
5388
  }
5389
  BUS  24874, 0, 0
5390
  {
5391
   NET 24839
5392
   VTX 24871, 24873
5393
  }
5394
  BUS  24875, 0, 0
5395
  {
5396
   NET 24839
5397
   VTX 24873, 24862
5398
  }
5399
  VTX  25632, 0, 0
5400
  {
5401
   COORD (260,160)
5402
  }
5403
  VTX  25633, 0, 0
5404
  {
5405
   COORD (240,160)
5406
  }
5407
  WIRE  25635, 0, 0
5408
  {
5409
   NET 26196
5410
   VTX 25632, 23913
5411
  }
5412
  WIRE  25637, 0, 0
5413
  {
5414
   NET 26196
5415
   VTX 25632, 25633
5416
  }
5417
  VTX  25739, 0, 0
5418
  {
5419
   COORD (2180,1720)
5420
  }
5421
  VTX  25740, 0, 0
5422
  {
5423
   COORD (1440,1060)
5424
  }
5425
  WIRE  25741, 0, 0
5426
  {
5427
   NET 1572
5428
   VTX 23976, 25740
5429
  }
5430
  VTX  25742, 0, 0
5431
  {
5432
   COORD (1380,1060)
5433
  }
5434
  WIRE  25743, 0, 0
5435
  {
5436
   NET 1572
5437
   VTX 25740, 25742
5438
  }
5439
  VTX  25744, 0, 0
5440
  {
5441
   COORD (1380,1260)
5442
  }
5443
  WIRE  25745, 0, 0
5444
  {
5445
   NET 1572
5446
   VTX 25742, 25744
5447
  }
5448
  VTX  25746, 0, 0
5449
  {
5450
   COORD (1460,1260)
5451
  }
5452
  WIRE  25747, 0, 0
5453
  {
5454
   NET 1572
5455
   VTX 25744, 25746
5456
  }
5457
  VTX  25748, 0, 0
5458
  {
5459
   COORD (1460,1300)
5460
  }
5461
  WIRE  25749, 0, 0
5462
  {
5463
   NET 1572
5464
   VTX 25746, 25748
5465
  }
5466
  VTX  25750, 0, 0
5467
  {
5468
   COORD (1500,1300)
5469
  }
5470
  WIRE  25751, 0, 0
5471
  {
5472
   NET 1572
5473
   VTX 25748, 25750
5474
  }
5475
  VTX  25752, 0, 0
5476
  {
5477
   COORD (1500,1560)
5478
  }
5479
  WIRE  25753, 0, 0
5480
  {
5481
   NET 1572
5482
   VTX 25750, 25752
5483
  }
5484
  VTX  25754, 0, 0
5485
  {
5486
   COORD (1620,1560)
5487
  }
5488
  WIRE  25755, 0, 0
5489
  {
5490
   NET 1572
5491
   VTX 25752, 25754
5492
  }
5493
  VTX  25756, 0, 0
5494
  {
5495
   COORD (1620,2080)
5496
  }
5497
  WIRE  25757, 0, 0
5498
  {
5499
   NET 1572
5500
   VTX 25754, 25756
5501
  }
5502
  VTX  25758, 0, 0
5503
  {
5504
   COORD (2120,2080)
5505
  }
5506
  WIRE  25759, 0, 0
5507
  {
5508
   NET 1572
5509
   VTX 25756, 25758
5510
  }
5511
  VTX  25760, 0, 0
5512
  {
5513
   COORD (2120,1720)
5514
  }
5515
  WIRE  25761, 0, 0
5516
  {
5517
   NET 1572
5518
   VTX 25758, 25760
5519
  }
5520
  WIRE  25762, 0, 0
5521
  {
5522
   NET 1572
5523
   VTX 25760, 25739
5524
  }
5525
  VTX  25763, 0, 0
5526
  {
5527
   COORD (1320,1040)
5528
  }
5529
  VTX  25764, 0, 0
5530
  {
5531
   COORD (320,1420)
5532
  }
5533
  VTX  25765, 0, 0
5534
  {
5535
   COORD (1400,1040)
5536
  }
5537
  BUS  25766, 0, 0
5538
  {
5539
   NET 27044
5540
   VTX 25763, 25765
5541
  }
5542
  VTX  25767, 0, 0
5543
  {
5544
   COORD (1400,680)
5545
  }
5546
  BUS  25768, 0, 0
5547
  {
5548
   NET 27044
5549
   VTX 25765, 25767
5550
  }
5551
  VTX  25769, 0, 0
5552
  {
5553
   COORD (780,680)
5554
  }
5555
  BUS  25770, 0, 0
5556
  {
5557
   NET 27044
5558
   VTX 25767, 25769
5559
  }
5560
  VTX  25771, 0, 0
5561
  {
5562
   COORD (780,780)
5563
  }
5564
  BUS  25772, 0, 0
5565
  {
5566
   NET 27044
5567
   VTX 25769, 25771
5568
  }
5569
  VTX  25773, 0, 0
5570
  {
5571
   COORD (720,780)
5572
  }
5573
  BUS  25774, 0, 0
5574
  {
5575
   NET 27044
5576
   VTX 25771, 25773
5577
  }
5578
  VTX  25775, 0, 0
5579
  {
5580
   COORD (720,1220)
5581
  }
5582
  BUS  25776, 0, 0
5583
  {
5584
   NET 27044
5585
   VTX 25773, 25775
5586
  }
5587
  VTX  25777, 0, 0
5588
  {
5589
   COORD (300,1220)
5590
  }
5591
  BUS  25778, 0, 0
5592
  {
5593
   NET 27044
5594
   VTX 25775, 25777
5595
  }
5596
  VTX  25779, 0, 0
5597
  {
5598
   COORD (300,1420)
5599
  }
5600
  BUS  25780, 0, 0
5601
  {
5602
   NET 27044
5603
   VTX 25777, 25779
5604
  }
5605
  BUS  25781, 0, 0
5606
  {
5607
   NET 27044
5608
   VTX 25779, 25764
5609
  }
5610
  VTX  25826, 0, 0
5611
  {
5612
   COORD (920,1480)
5613
  }
5614
  VTX  25827, 0, 0
5615
  {
5616
   COORD (1420,1660)
5617
  }
5618
  BUS  25828, 0, 0
5619
  {
5620
   NET 18211
5621
   VTX 23899, 25827
5622
  }
5623
  VTX  25829, 0, 0
5624
  {
5625
   COORD (1420,1980)
5626
  }
5627
  BUS  25830, 0, 0
5628
  {
5629
   NET 18211
5630
   VTX 25827, 25829
5631
  }
5632
  VTX  25831, 0, 0
5633
  {
5634
   COORD (880,1980)
5635
  }
5636
  BUS  25832, 0, 0
5637
  {
5638
   NET 18211
5639
   VTX 25829, 25831
5640
  }
5641
  VTX  25833, 0, 0
5642
  {
5643
   COORD (880,1480)
5644
  }
5645
  BUS  25834, 0, 0
5646
  {
5647
   NET 18211
5648
   VTX 25831, 25833
5649
  }
5650
  BUS  25835, 0, 0
5651
  {
5652
   NET 18211
5653
   VTX 25833, 25826
5654
  }
5655
  VTX  25917, 0, 0
5656
  {
5657
   COORD (700,640)
5658
  }
5659
  VTX  25918, 0, 0
5660
  {
5661
   COORD (920,1320)
5662
  }
5663
  VTX  25919, 0, 0
5664
  {
5665
   COORD (800,640)
5666
  }
5667
  BUS  25920, 0, 0
5668
  {
5669
   NET 271
5670
   VTX 25917, 25919
5671
  }
5672
  VTX  25921, 0, 0
5673
  {
5674
   COORD (800,1320)
5675
  }
5676
  BUS  25922, 0, 0
5677
  {
5678
   NET 271
5679
   VTX 25919, 25921
5680
  }
5681
  BUS  25923, 0, 0
5682
  {
5683
   NET 271
5684
   VTX 25921, 25918
5685
  }
5686
  VTX  25924, 0, 0
5687
  {
5688
   COORD (700,520)
5689
  }
5690
  VTX  25925, 0, 0
5691
  {
5692
   COORD (920,1160)
5693
  }
5694
  VTX  25926, 0, 0
5695
  {
5696
   COORD (760,520)
5697
  }
5698
  BUS  25927, 0, 0
5699
  {
5700
   NET 197
5701
   VTX 25924, 25926
5702
  }
5703
  VTX  25928, 0, 0
5704
  {
5705
   COORD (760,800)
5706
  }
5707
  BUS  25929, 0, 0
5708
  {
5709
   NET 197
5710
   VTX 25926, 25928
5711
  }
5712
  VTX  25930, 0, 0
5713
  {
5714
   COORD (740,800)
5715
  }
5716
  BUS  25931, 0, 0
5717
  {
5718
   NET 197
5719
   VTX 25928, 25930
5720
  }
5721
  VTX  25932, 0, 0
5722
  {
5723
   COORD (740,1160)
5724
  }
5725
  BUS  25933, 0, 0
5726
  {
5727
   NET 197
5728
   VTX 25930, 25932
5729
  }
5730
  BUS  25934, 0, 0
5731
  {
5732
   NET 197
5733
   VTX 25932, 25925
5734
  }
5735
  VTX  25950, 0, 0
5736
  {
5737
   COORD (700,680)
5738
  }
5739
  VTX  25951, 0, 0
5740
  {
5741
   COORD (920,1400)
5742
  }
5743
  VTX  25952, 0, 0
5744
  {
5745
   COORD (775,680)
5746
  }
5747
  BUS  25953, 0, 0
5748
  {
5749
   NET 371
5750
   VTX 25950, 25952
5751
  }
5752
  VTX  25954, 0, 0
5753
  {
5754
   COORD (775,1320)
5755
  }
5756
  BUS  25955, 0, 0
5757
  {
5758
   NET 371
5759
   VTX 25952, 25954
5760
  }
5761
  VTX  25956, 0, 0
5762
  {
5763
   COORD (780,1320)
5764
  }
5765
  BUS  25957, 0, 0
5766
  {
5767
   NET 371
5768
   VTX 25954, 25956
5769
  }
5770
  VTX  25958, 0, 0
5771
  {
5772
   COORD (780,1380)
5773
  }
5774
  BUS  25959, 0, 0
5775
  {
5776
   NET 371
5777
   VTX 25956, 25958
5778
  }
5779
  VTX  25960, 0, 0
5780
  {
5781
   COORD (880,1380)
5782
  }
5783
  BUS  25961, 0, 0
5784
  {
5785
   NET 371
5786
   VTX 25958, 25960
5787
  }
5788
  VTX  25962, 0, 0
5789
  {
5790
   COORD (880,1400)
5791
  }
5792
  BUS  25963, 0, 0
5793
  {
5794
   NET 371
5795
   VTX 25960, 25962
5796
  }
5797
  BUS  25964, 0, 0
5798
  {
5799
   NET 371
5800
   VTX 25962, 25951
5801
  }
5802
  VTX  26068, 0, 0
5803
  {
5804
   COORD (2180,540)
5805
  }
5806
  VTX  26069, 0, 0
5807
  {
5808
   COORD (2140,360)
5809
  }
5810
  VTX  26070, 0, 0
5811
  {
5812
   COORD (2190,540)
5813
  }
5814
  BUS  26071, 0, 0
5815
  {
5816
   NET 22426
5817
   VTX 26068, 26070
5818
  }
5819
  VTX  26072, 0, 0
5820
  {
5821
   COORD (2190,490)
5822
  }
5823
  BUS  26073, 0, 0
5824
  {
5825
   NET 22426
5826
   VTX 26070, 26072
5827
  }
5828
  VTX  26074, 0, 0
5829
  {
5830
   COORD (2150,490)
5831
  }
5832
  BUS  26075, 0, 0
5833
  {
5834
   NET 22426
5835
   VTX 26072, 26074
5836
  }
5837
  VTX  26076, 0, 0
5838
  {
5839
   COORD (2150,360)
5840
  }
5841
  BUS  26077, 0, 0
5842
  {
5843
   NET 22426
5844
   VTX 26074, 26076
5845
  }
5846
  BUS  26078, 0, 0
5847
  {
5848
   NET 22426
5849
   VTX 26076, 26069
5850
  }
5851
  VTX  26137, 0, 0
5852
  {
5853
   COORD (2280,720)
5854
  }
5855
  VTX  26138, 0, 0
5856
  {
5857
   COORD (2280,840)
5858
  }
5859
  BUS  26139, 0, 0
5860
  {
5861
   NET 9884
5862
   VTX 26137, 26138
5863
  }
5864
  BUS  26141, 0, 0
5865
  {
5866
   NET 9884
5867
   VTX 24696, 26138
5868
  }
5869
  VTX  26143, 0, 0
5870
  {
5871
   COORD (2140,240)
5872
  }
5873
  VTX  26144, 0, 0
5874
  {
5875
   COORD (2260,760)
5876
  }
5877
  BUS  26145, 0, 0
5878
  {
5879
   NET 22353
5880
   VTX 23950, 26144
5881
  }
5882
  VTX  26147, 0, 0
5883
  {
5884
   COORD (2260,240)
5885
  }
5886
  BUS  26148, 0, 0
5887
  {
5888
   NET 22353
5889
   VTX 26143, 26147
5890
  }
5891
  BUS  26150, 0, 0
5892
  {
5893
   NET 22353
5894
   VTX 26144, 26147
5895
  }
5896
  VTX  26151, 0, 0
5897
  {
5898
   COORD (2980,920)
5899
  }
5900
  VTX  26152, 0, 0
5901
  {
5902
   COORD (2800,480)
5903
  }
5904
  VTX  26153, 0, 0
5905
  {
5906
   COORD (2980,640)
5907
  }
5908
  BUS  26154, 0, 0
5909
  {
5910
   NET 422
5911
   VTX 26151, 26153
5912
  }
5913
  VTX  26155, 0, 0
5914
  {
5915
   COORD (2760,640)
5916
  }
5917
  BUS  26156, 0, 0
5918
  {
5919
   NET 422
5920
   VTX 26153, 26155
5921
  }
5922
  VTX  26157, 0, 0
5923
  {
5924
   COORD (2760,480)
5925
  }
5926
  BUS  26158, 0, 0
5927
  {
5928
   NET 422
5929
   VTX 26155, 26157
5930
  }
5931
  BUS  26159, 0, 0
5932
  {
5933
   NET 422
5934
   VTX 26157, 26152
5935
  }
5936
  NET WIRE  26196, 0, 0
5937
  VTX  26197, 0, 0
5938
  {
5939
   COORD (860,120)
5940
  }
5941
  VTX  26198, 0, 0
5942
  {
5943
   COORD (920,880)
5944
  }
5945
  WIRE  26199, 0, 0
5946
  {
5947
   NET 26196
5948
   VTX 23908, 26197
5949
  }
5950
  VTX  26200, 0, 0
5951
  {
5952
   COORD (860,880)
5953
  }
5954
  WIRE  26201, 0, 0
5955
  {
5956
   NET 26196
5957
   VTX 26198, 26200
5958
  }
5959
  WIRE  26202, 0, 0
5960
  {
5961
   NET 26196
5962
   VTX 26200, 26197
5963
  }
5964
  VTX  26203, 0, 0
5965
  {
5966
   COORD (260,120)
5967
  }
5968
  WIRE  26204, 0, 0
5969
  {
5970
   NET 26196
5971
   VTX 25632, 26203
5972
  }
5973
  WIRE  26205, 0, 0
5974
  {
5975
   NET 26196
5976
   VTX 26203, 26197
5977
  }
5978
  VTX  26218, 0, 0
5979
  {
5980
   COORD (340,360)
5981
  }
5982
  VTX  26219, 0, 0
5983
  {
5984
   COORD (300,360)
5985
  }
5986
  WIRE  26220, 0, 0
5987
  {
5988
   NET 1572
5989
   VTX 26218, 26219
5990
  }
5991
  VTX  26221, 0, 0
5992
  {
5993
   COORD (300,140)
5994
  }
5995
  WIRE  26222, 0, 0
5996
  {
5997
   NET 1572
5998
   VTX 26219, 26221
5999
  }
6000
  VTX  26223, 0, 0
6001
  {
6002
   COORD (1440,140)
6003
  }
6004
  WIRE  26224, 0, 0
6005
  {
6006
   NET 1572
6007
   VTX 26221, 26223
6008
  }
6009
  WIRE  26225, 0, 0
6010
  {
6011
   NET 1572
6012
   VTX 26223, 23976
6013
  }
6014
  VTX  26277, 0, 0
6015
  {
6016
   COORD (2800,560)
6017
  }
6018
  VTX  26278, 0, 0
6019
  {
6020
   COORD (700,720)
6021
  }
6022
  VTX  26279, 0, 0
6023
  {
6024
   COORD (2740,560)
6025
  }
6026
  WIRE  26280, 0, 0
6027
  {
6028
   NET 457
6029
   VTX 26277, 26279
6030
  }
6031
  VTX  26281, 0, 0
6032
  {
6033
   COORD (2740,420)
6034
  }
6035
  WIRE  26282, 0, 0
6036
  {
6037
   NET 457
6038
   VTX 26279, 26281
6039
  }
6040
  VTX  26283, 0, 0
6041
  {
6042
   COORD (2160,420)
6043
  }
6044
  WIRE  26284, 0, 0
6045
  {
6046
   NET 457
6047
   VTX 26281, 26283
6048
  }
6049
  VTX  26285, 0, 0
6050
  {
6051
   COORD (2160,460)
6052
  }
6053
  WIRE  26286, 0, 0
6054
  {
6055
   NET 457
6056
   VTX 26283, 26285
6057
  }
6058
  VTX  26287, 0, 0
6059
  {
6060
   COORD (740,460)
6061
  }
6062
  WIRE  26288, 0, 0
6063
  {
6064
   NET 457
6065
   VTX 26285, 26287
6066
  }
6067
  VTX  26289, 0, 0
6068
  {
6069
   COORD (740,720)
6070
  }
6071
  WIRE  26290, 0, 0
6072
  {
6073
   NET 457
6074
   VTX 26287, 26289
6075
  }
6076
  WIRE  26291, 0, 0
6077
  {
6078
   NET 457
6079
   VTX 26289, 26278
6080
  }
6081
  VTX  26673, 0, 0
6082
  {
6083
   COORD (1920,780)
6084
  }
6085
  BUS  26679, 0, 0
6086
  {
6087
   NET 29854
6088
   VTX 26673, 24298
6089
  }
6090
  VTX  26719, 0, 0
6091
  {
6092
   COORD (2180,1680)
6093
  }
6094
  VTX  26720, 0, 0
6095
  {
6096
   COORD (1800,920)
6097
  }
6098
  WIRE  26721, 0, 0
6099
  {
6100
   NET 21056
6101
   VTX 24012, 26720
6102
  }
6103
  VTX  26722, 0, 0
6104
  {
6105
   COORD (1800,1120)
6106
  }
6107
  WIRE  26723, 0, 0
6108
  {
6109
   NET 21056
6110
   VTX 26720, 26722
6111
  }
6112
  VTX  26724, 0, 0
6113
  {
6114
   COORD (1960,1120)
6115
  }
6116
  WIRE  26725, 0, 0
6117
  {
6118
   NET 21056
6119
   VTX 26722, 26724
6120
  }
6121
  VTX  26726, 0, 0
6122
  {
6123
   COORD (1960,1700)
6124
  }
6125
  WIRE  26727, 0, 0
6126
  {
6127
   NET 21056
6128
   VTX 26724, 26726
6129
  }
6130
  VTX  26728, 0, 0
6131
  {
6132
   COORD (2120,1700)
6133
  }
6134
  WIRE  26729, 0, 0
6135
  {
6136
   NET 21056
6137
   VTX 26726, 26728
6138
  }
6139
  VTX  26730, 0, 0
6140
  {
6141
   COORD (2120,1680)
6142
  }
6143
  WIRE  26731, 0, 0
6144
  {
6145
   NET 21056
6146
   VTX 26728, 26730
6147
  }
6148
  WIRE  26732, 0, 0
6149
  {
6150
   NET 21056
6151
   VTX 26730, 26719
6152
  }
6153
  VTX  26733, 0, 0
6154
  {
6155
   COORD (1280,820)
6156
  }
6157
  VTX  26734, 0, 0
6158
  {
6159
   COORD (1340,820)
6160
  }
6161
  WIRE  26735, 0, 0
6162
  {
6163
   NET 21056
6164
   VTX 24012, 26734
6165
  }
6166
  WIRE  26736, 0, 0
6167
  {
6168
   NET 21056
6169
   VTX 26734, 26733
6170
  }
6171
  VTX  26737, 0, 0
6172
  {
6173
   COORD (1780,700)
6174
  }
6175
  VTX  26738, 0, 0
6176
  {
6177
   COORD (1720,420)
6178
  }
6179
  VTX  26739, 0, 0
6180
  {
6181
   COORD (1700,700)
6182
  }
6183
  BUS  26740, 0, 0
6184
  {
6185
   NET 22220
6186
   VTX 26737, 26739
6187
  }
6188
  VTX  26741, 0, 0
6189
  {
6190
   COORD (1700,420)
6191
  }
6192
  BUS  26742, 0, 0
6193
  {
6194
   NET 22220
6195
   VTX 26739, 26741
6196
  }
6197
  BUS  26743, 0, 0
6198
  {
6199
   NET 22220
6200
   VTX 26741, 26738
6201
  }
6202
  VTX  26744, 0, 0
6203
  {
6204
   COORD (1780,540)
6205
  }
6206
  VTX  26745, 0, 0
6207
  {
6208
   COORD (1680,120)
6209
  }
6210
  VTX  26747, 0, 0
6211
  {
6212
   COORD (1680,540)
6213
  }
6214
  WIRE  26748, 0, 0
6215
  {
6216
   NET 26196
6217
   VTX 26745, 26747
6218
  }
6219
  WIRE  26749, 0, 0
6220
  {
6221
   NET 26196
6222
   VTX 26747, 26744
6223
  }
6224
  WIRE  26750, 0, 0
6225
  {
6226
   NET 26196
6227
   VTX 23905, 26745
6228
  }
6229
  VTX  26756, 0, 0
6230
  {
6231
   COORD (2280,540)
6232
  }
6233
  VTX  26757, 0, 0
6234
  {
6235
   COORD (2180,660)
6236
  }
6237
  VTX  26758, 0, 0
6238
  {
6239
   COORD (2240,540)
6240
  }
6241
  BUS  26759, 0, 0
6242
  {
6243
   NET 22401
6244
   VTX 26756, 26758
6245
  }
6246
  VTX  26760, 0, 0
6247
  {
6248
   COORD (2240,660)
6249
  }
6250
  BUS  26761, 0, 0
6251
  {
6252
   NET 22401
6253
   VTX 26758, 26760
6254
  }
6255
  BUS  26762, 0, 0
6256
  {
6257
   NET 22401
6258
   VTX 26760, 26757
6259
  }
6260
  VTX  26975, 0, 0
6261
  {
6262
   COORD (2540,1000)
6263
  }
6264
  VTX  26979, 0, 0
6265
  {
6266
   COORD (2480,1000)
6267
  }
6268
  BUS  26980, 0, 0
6269
  {
6270
   NET 9589
6271
   VTX 26975, 26979
6272
  }
6273
  VTX  26982, 0, 0
6274
  {
6275
   COORD (2480,920)
6276
  }
6277
  VTX  26994, 0, 0
6278
  {
6279
   COORD (1780,620)
6280
  }
6281
  VTX  26995, 0, 0
6282
  {
6283
   COORD (1720,620)
6284
  }
6285
  BUS  26996, 0, 0
6286
  {
6287
   NET 9589
6288
   VTX 26994, 26995
6289
  }
6290
  VTX  26997, 0, 0
6291
  {
6292
   COORD (1720,860)
6293
  }
6294
  BUS  26998, 0, 0
6295
  {
6296
   NET 9589
6297
   VTX 26995, 26997
6298
  }
6299
  VTX  26999, 0, 0
6300
  {
6301
   COORD (2480,860)
6302
  }
6303
  BUS  27000, 0, 0
6304
  {
6305
   NET 9589
6306
   VTX 26997, 26999
6307
  }
6308
  BUS  27001, 0, 0
6309
  {
6310
   NET 9589
6311
   VTX 26999, 26982
6312
  }
6313
  BUS  27002, 0, 0
6314
  {
6315
   NET 9589
6316
   VTX 26979, 26982
6317
  }
6318
  NET BUS  27031, 0, 0
6319
  BUS  27033, 0, 0
6320
  {
6321
   NET 27031
6322
   VTX 23997, 24059
6323
  }
6324
  NET BUS  27044, 0, 0
6325
  VTX  27049, 0, 0
6326
  {
6327
   COORD (320,1520)
6328
  }
6329
  VTX  27050, 0, 0
6330
  {
6331
   COORD (300,1520)
6332
  }
6333
  BUS  27051, 0, 0
6334
  {
6335
   NET 27044
6336
   VTX 25779, 27050
6337
  }
6338
  BUS  27052, 0, 0
6339
  {
6340
   NET 27044
6341
   VTX 27050, 27049
6342
  }
6343
  VTX  27781, 0, 0
6344
  {
6345
   COORD (1320,1240)
6346
  }
6347
  VTX  27782, 0, 0
6348
  {
6349
   COORD (1640,2000)
6350
  }
6351
  VTX  27783, 0, 0
6352
  {
6353
   COORD (1320,1160)
6354
  }
6355
  VTX  27784, 0, 0
6356
  {
6357
   COORD (1640,1960)
6358
  }
6359
  VTX  27785, 0, 0
6360
  {
6361
   COORD (1640,1920)
6362
  }
6363
  VTX  27786, 0, 0
6364
  {
6365
   COORD (1640,1880)
6366
  }
6367
  VTX  27787, 0, 0
6368
  {
6369
   COORD (1640,1840)
6370
  }
6371
  VTX  27788, 0, 0
6372
  {
6373
   COORD (1640,1800)
6374
  }
6375
  VTX  27789, 0, 0
6376
  {
6377
   COORD (700,320)
6378
  }
6379
  VTX  27790, 0, 0
6380
  {
6381
   COORD (1640,1760)
6382
  }
6383
  VTX  27791, 0, 0
6384
  {
6385
   COORD (1440,1240)
6386
  }
6387
  BUS  27792, 0, 0
6388
  {
6389
   NET 756
6390
   VTX 27781, 27791
6391
  }
6392
  VTX  27793, 0, 0
6393
  {
6394
   COORD (1440,2000)
6395
  }
6396
  BUS  27794, 0, 0
6397
  {
6398
   NET 756
6399
   VTX 27791, 27793
6400
  }
6401
  BUS  27795, 0, 0
6402
  {
6403
   NET 756
6404
   VTX 27793, 27782
6405
  }
6406
  VTX  27796, 0, 0
6407
  {
6408
   COORD (1420,1160)
6409
  }
6410
  BUS  27797, 0, 0
6411
  {
6412
   NET 748
6413
   VTX 27783, 27796
6414
  }
6415
  VTX  27798, 0, 0
6416
  {
6417
   COORD (1420,1540)
6418
  }
6419
  BUS  27799, 0, 0
6420
  {
6421
   NET 748
6422
   VTX 27796, 27798
6423
  }
6424
  VTX  27800, 0, 0
6425
  {
6426
   COORD (1600,1540)
6427
  }
6428
  BUS  27801, 0, 0
6429
  {
6430
   NET 748
6431
   VTX 27798, 27800
6432
  }
6433
  VTX  27802, 0, 0
6434
  {
6435
   COORD (1600,1960)
6436
  }
6437
  BUS  27803, 0, 0
6438
  {
6439
   NET 748
6440
   VTX 27800, 27802
6441
  }
6442
  BUS  27804, 0, 0
6443
  {
6444
   NET 748
6445
   VTX 27802, 27784
6446
  }
6447
  VTX  27805, 0, 0
6448
  {
6449
   COORD (780,1920)
6450
  }
6451
  WIRE  27806, 0, 0
6452
  {
6453
   NET 1375
6454
   VTX 23961, 27805
6455
  }
6456
  WIRE  27807, 0, 0
6457
  {
6458
   NET 1375
6459
   VTX 27805, 27785
6460
  }
6461
  VTX  27808, 0, 0
6462
  {
6463
   COORD (1580,1880)
6464
  }
6465
  BUS  27809, 0, 0
6466
  {
6467
   NET 18211
6468
   VTX 23899, 27808
6469
  }
6470
  BUS  27810, 0, 0
6471
  {
6472
   NET 18211
6473
   VTX 27808, 27786
6474
  }
6475
  VTX  27811, 0, 0
6476
  {
6477
   COORD (1560,1840)
6478
  }
6479
  BUS  27812, 0, 0
6480
  {
6481
   NET 1724
6482
   VTX 23896, 27811
6483
  }
6484
  BUS  27813, 0, 0
6485
  {
6486
   NET 1724
6487
   VTX 27811, 27787
6488
  }
6489
  WIRE  27814, 0, 0
6490
  {
6491
   NET 26196
6492
   VTX 23915, 27788
6493
  }
6494
  VTX  27815, 0, 0
6495
  {
6496
   COORD (1480,320)
6497
  }
6498
  WIRE  27816, 0, 0
6499
  {
6500
   NET 767
6501
   VTX 27789, 27815
6502
  }
6503
  VTX  27817, 0, 0
6504
  {
6505
   COORD (1480,1760)
6506
  }
6507
  WIRE  27818, 0, 0
6508
  {
6509
   NET 767
6510
   VTX 27815, 27817
6511
  }
6512
  WIRE  27819, 0, 0
6513
  {
6514
   NET 767
6515
   VTX 27817, 27790
6516
  }
6517
  INSTANCE  27919, 0, 0
6518
  {
6519
   VARIABLES
6520
   {
6521
    #COMPONENT="rf_stage8"
6522
    #LIBRARY="#default"
6523
    #REFERENCE="U2"
6524
    #SYMBOL="rf_stage8"
6525
   }
6526
   COORD (980,840)
6527
   VERTEXES ( (2,26198), (6,23969), (8,24013), (10,23971), (12,23973), (14,23974), (16,23977), (18,23979), (20,25763), (22,23981), (24,23983), (26,24056), (28,23985), (30,25925), (32,27783), (36,24862), (38,24010), (40,27781), (42,24006), (44,23996), (46,25918), (48,23998), (50,25951), (52,24001), (54,25826), (56,24057), (58,24003), (4,27944), (34,27959), (60,29636) )
6528
  }
6529
  TEXT  27920, 0, 0
6530
  {
6531
   TEXT "$#REFERENCE"
6532
   RECT (920,804,956,839)
6533
   ALIGN 8
6534
   MARGINS (1,1)
6535
   PARENT 27919
6536
  }
6537
  TEXT  27924, 0, 0
6538
  {
6539
   TEXT "$#COMPONENT"
6540
   RECT (920,1640,1075,1675)
6541
   MARGINS (1,1)
6542
   PARENT 27919
6543
  }
6544
  VTX  27943, 0, 0
6545
  {
6546
   COORD (2540,1740)
6547
  }
6548
  VTX  27944, 0, 0
6549
  {
6550
   COORD (1320,880)
6551
  }
6552
  VTX  27945, 0, 0
6553
  {
6554
   COORD (2340,1740)
6555
  }
6556
  BUS  27946, 0, 0
6557
  {
6558
   NET 7219
6559
   VTX 27943, 27945
6560
  }
6561
  VTX  27947, 0, 0
6562
  {
6563
   COORD (2340,1760)
6564
  }
6565
  BUS  27948, 0, 0
6566
  {
6567
   NET 7219
6568
   VTX 27945, 27947
6569
  }
6570
  VTX  27949, 0, 0
6571
  {
6572
   COORD (2080,1760)
6573
  }
6574
  BUS  27950, 0, 0
6575
  {
6576
   NET 7219
6577
   VTX 27947, 27949
6578
  }
6579
  VTX  27951, 0, 0
6580
  {
6581
   COORD (2080,1660)
6582
  }
6583
  BUS  27952, 0, 0
6584
  {
6585
   NET 7219
6586
   VTX 27949, 27951
6587
  }
6588
  VTX  27953, 0, 0
6589
  {
6590
   COORD (1840,1660)
6591
  }
6592
  BUS  27954, 0, 0
6593
  {
6594
   NET 7219
6595
   VTX 27951, 27953
6596
  }
6597
  VTX  27955, 0, 0
6598
  {
6599
   COORD (1840,880)
6600
  }
6601
  BUS  27956, 0, 0
6602
  {
6603
   NET 7219
6604
   VTX 27953, 27955
6605
  }
6606
  BUS  27957, 0, 0
6607
  {
6608
   NET 7219
6609
   VTX 27955, 27944
6610
  }
6611
  VTX  27959, 0, 0
6612
  {
6613
   COORD (920,1200)
6614
  }
6615
  VTX  27960, 0, 0
6616
  {
6617
   COORD (1420,760)
6618
  }
6619
  BUS  27961, 0, 0
6620
  {
6621
   NET 22353
6622
   VTX 23950, 27960
6623
  }
6624
  VTX  27962, 0, 0
6625
  {
6626
   COORD (1420,1080)
6627
  }
6628
  BUS  27963, 0, 0
6629
  {
6630
   NET 22353
6631
   VTX 27960, 27962
6632
  }
6633
  VTX  27964, 0, 0
6634
  {
6635
   COORD (1360,1080)
6636
  }
6637
  BUS  27965, 0, 0
6638
  {
6639
   NET 22353
6640
   VTX 27962, 27964
6641
  }
6642
  VTX  27966, 0, 0
6643
  {
6644
   COORD (1360,1680)
6645
  }
6646
  BUS  27967, 0, 0
6647
  {
6648
   NET 22353
6649
   VTX 27964, 27966
6650
  }
6651
  VTX  27968, 0, 0
6652
  {
6653
   COORD (900,1680)
6654
  }
6655
  BUS  27969, 0, 0
6656
  {
6657
   NET 22353
6658
   VTX 27966, 27968
6659
  }
6660
  VTX  27970, 0, 0
6661
  {
6662
   COORD (900,1200)
6663
  }
6664
  BUS  27971, 0, 0
6665
  {
6666
   NET 22353
6667
   VTX 27968, 27970
6668
  }
6669
  BUS  27972, 0, 0
6670
  {
6671
   NET 22353
6672
   VTX 27970, 27959
6673
  }
6674
  INSTANCE  28001, 0, 0
6675
  {
6676
   VARIABLES
6677
   {
6678
    #COMPONENT="exec_stage1"
6679
    #LIBRARY="#default"
6680
    #REFERENCE="U3"
6681
    #SYMBOL="exec_stage1"
6682
   }
6683
   COORD (2000,860)
6684
   VERTEXES ( (2,29630), (6,29632), (10,29635), (14,29639), (16,29640), (18,29641), (20,29643), (22,29645), (24,29647), (26,29649), (28,29650), (30,29652), (32,29653), (34,29655), (36,29657), (4,29631), (8,29633), (12,29637) )
6685
  }
6686
  TEXT  28002, 0, 0
6687
  {
6688
   TEXT "$#REFERENCE"
6689
   RECT (2000,824,2036,859)
6690
   ALIGN 8
6691
   MARGINS (1,1)
6692
   PARENT 28001
6693
  }
6694
  TEXT  28006, 0, 0
6695
  {
6696
   TEXT "$#COMPONENT"
6697
   RECT (2000,1500,2189,1535)
6698
   MARGINS (1,1)
6699
   PARENT 28001
6700
  }
6701
  NET BUS  28013, 0, 0
6702
  VTX  28063, 0, 0
6703
  {
6704
   COORD (2180,670)
6705
  }
6706
  WIRE  28064, 0, 0
6707
  {
6708
   NET 26196
6709
   VTX 23932, 28063
6710
  }
6711
  VTX  29629, 0, 0
6712
  {
6713
   COORD (700,280)
6714
  }
6715
  VTX  29630, 0, 0
6716
  {
6717
   COORD (2000,900)
6718
  }
6719
  VTX  29631, 0, 0
6720
  {
6721
   COORD (2400,900)
6722
  }
6723
  VTX  29632, 0, 0
6724
  {
6725
   COORD (2000,940)
6726
  }
6727
  VTX  29633, 0, 0
6728
  {
6729
   COORD (2400,940)
6730
  }
6731
  VTX  29634, 0, 0
6732
  {
6733
   COORD (2020,1920)
6734
  }
6735
  VTX  29635, 0, 0
6736
  {
6737
   COORD (2000,980)
6738
  }
6739
  VTX  29636, 0, 0
6740
  {
6741
   COORD (920,1600)
6742
  }
6743
  VTX  29637, 0, 0
6744
  {
6745
   COORD (2400,980)
6746
  }
6747
  VTX  29638, 0, 0
6748
  {
6749
   COORD (2740,1700)
6750
  }
6751
  VTX  29639, 0, 0
6752
  {
6753
   COORD (2000,1020)
6754
  }
6755
  VTX  29640, 0, 0
6756
  {
6757
   COORD (2000,1060)
6758
  }
6759
  VTX  29641, 0, 0
6760
  {
6761
   COORD (2000,1100)
6762
  }
6763
  VTX  29642, 0, 0
6764
  {
6765
   COORD (700,560)
6766
  }
6767
  VTX  29643, 0, 0
6768
  {
6769
   COORD (2000,1140)
6770
  }
6771
  VTX  29644, 0, 0
6772
  {
6773
   COORD (2020,1760)
6774
  }
6775
  VTX  29645, 0, 0
6776
  {
6777
   COORD (2000,1180)
6778
  }
6779
  VTX  29646, 0, 0
6780
  {
6781
   COORD (700,600)
6782
  }
6783
  VTX  29647, 0, 0
6784
  {
6785
   COORD (2000,1220)
6786
  }
6787
  VTX  29648, 0, 0
6788
  {
6789
   COORD (2020,1800)
6790
  }
6791
  VTX  29649, 0, 0
6792
  {
6793
   COORD (2000,1260)
6794
  }
6795
  VTX  29650, 0, 0
6796
  {
6797
   COORD (2000,1300)
6798
  }
6799
  VTX  29651, 0, 0
6800
  {
6801
   COORD (2740,1300)
6802
  }
6803
  VTX  29652, 0, 0
6804
  {
6805
   COORD (2000,1340)
6806
  }
6807
  VTX  29653, 0, 0
6808
  {
6809
   COORD (2000,1380)
6810
  }
6811
  VTX  29654, 0, 0
6812
  {
6813
   COORD (2740,1480)
6814
  }
6815
  VTX  29655, 0, 0
6816
  {
6817
   COORD (2000,1420)
6818
  }
6819
  VTX  29656, 0, 0
6820
  {
6821
   COORD (2340,1700)
6822
  }
6823
  VTX  29657, 0, 0
6824
  {
6825
   COORD (2000,1460)
6826
  }
6827
  VTX  29658, 0, 0
6828
  {
6829
   COORD (1640,280)
6830
  }
6831
  BUS  29659, 0, 0
6832
  {
6833
   NET 6275
6834
   VTX 29629, 29658
6835
  }
6836
  VTX  29660, 0, 0
6837
  {
6838
   COORD (1640,820)
6839
  }
6840
  BUS  29661, 0, 0
6841
  {
6842
   NET 6275
6843
   VTX 29658, 29660
6844
  }
6845
  VTX  29662, 0, 0
6846
  {
6847
   COORD (1960,820)
6848
  }
6849
  BUS  29663, 0, 0
6850
  {
6851
   NET 6275
6852
   VTX 29660, 29662
6853
  }
6854
  VTX  29664, 0, 0
6855
  {
6856
   COORD (1960,900)
6857
  }
6858
  BUS  29665, 0, 0
6859
  {
6860
   NET 6275
6861
   VTX 29662, 29664
6862
  }
6863
  BUS  29666, 0, 0
6864
  {
6865
   NET 6275
6866
   VTX 29664, 29630
6867
  }
6868
  VTX  29667, 0, 0
6869
  {
6870
   COORD (2420,920)
6871
  }
6872
  BUS  29668, 0, 0
6873
  {
6874
   NET 9589
6875
   VTX 26982, 29667
6876
  }
6877
  VTX  29669, 0, 0
6878
  {
6879
   COORD (2420,900)
6880
  }
6881
  BUS  29670, 0, 0
6882
  {
6883
   NET 9589
6884
   VTX 29667, 29669
6885
  }
6886
  BUS  29671, 0, 0
6887
  {
6888
   NET 9589
6889
   VTX 29669, 29631
6890
  }
6891
  VTX  29672, 0, 0
6892
  {
6893
   COORD (2185,670)
6894
  }
6895
  WIRE  29673, 0, 0
6896
  {
6897
   NET 26196
6898
   VTX 28063, 29672
6899
  }
6900
  VTX  29674, 0, 0
6901
  {
6902
   COORD (2185,850)
6903
  }
6904
  WIRE  29675, 0, 0
6905
  {
6906
   NET 26196
6907
   VTX 29672, 29674
6908
  }
6909
  VTX  29676, 0, 0
6910
  {
6911
   COORD (1995,850)
6912
  }
6913
  WIRE  29677, 0, 0
6914
  {
6915
   NET 26196
6916
   VTX 29674, 29676
6917
  }
6918
  VTX  29678, 0, 0
6919
  {
6920
   COORD (1995,940)
6921
  }
6922
  WIRE  29679, 0, 0
6923
  {
6924
   NET 26196
6925
   VTX 29676, 29678
6926
  }
6927
  WIRE  29680, 0, 0
6928
  {
6929
   NET 26196
6930
   VTX 29678, 29632
6931
  }
6932
  VTX  29681, 0, 0
6933
  {
6934
   COORD (2460,840)
6935
  }
6936
  BUS  29682, 0, 0
6937
  {
6938
   NET 9884
6939
   VTX 26138, 29681
6940
  }
6941
  VTX  29683, 0, 0
6942
  {
6943
   COORD (2460,940)
6944
  }
6945
  BUS  29684, 0, 0
6946
  {
6947
   NET 9884
6948
   VTX 29681, 29683
6949
  }
6950
  BUS  29685, 0, 0
6951
  {
6952
   NET 9884
6953
   VTX 29683, 29633
6954
  }
6955
  VTX  29686, 0, 0
6956
  {
6957
   COORD (2100,1920)
6958
  }
6959
  BUS  29687, 0, 0
6960
  {
6961
   NET 5993
6962
   VTX 29634, 29686
6963
  }
6964
  VTX  29688, 0, 0
6965
  {
6966
   COORD (2100,1560)
6967
  }
6968
  BUS  29689, 0, 0
6969
  {
6970
   NET 5993
6971
   VTX 29686, 29688
6972
  }
6973
  VTX  29690, 0, 0
6974
  {
6975
   COORD (1640,1560)
6976
  }
6977
  BUS  29691, 0, 0
6978
  {
6979
   NET 5993
6980
   VTX 29688, 29690
6981
  }
6982
  VTX  29692, 0, 0
6983
  {
6984
   COORD (1640,1640)
6985
  }
6986
  BUS  29693, 0, 0
6987
  {
6988
   NET 5993
6989
   VTX 29690, 29692
6990
  }
6991
  VTX  29694, 0, 0
6992
  {
6993
   COORD (1580,1640)
6994
  }
6995
  BUS  29695, 0, 0
6996
  {
6997
   NET 5993
6998
   VTX 29692, 29694
6999
  }
7000
  VTX  29696, 0, 0
7001
  {
7002
   COORD (1580,1360)
7003
  }
7004
  BUS  29697, 0, 0
7005
  {
7006
   NET 5993
7007
   VTX 29694, 29696
7008
  }
7009
  VTX  29698, 0, 0
7010
  {
7011
   COORD (1760,1360)
7012
  }
7013
  BUS  29699, 0, 0
7014
  {
7015
   NET 5993
7016
   VTX 29696, 29698
7017
  }
7018
  VTX  29700, 0, 0
7019
  {
7020
   COORD (1760,980)
7021
  }
7022
  BUS  29701, 0, 0
7023
  {
7024
   NET 5993
7025
   VTX 29698, 29700
7026
  }
7027
  BUS  29702, 0, 0
7028
  {
7029
   NET 5993
7030
   VTX 29700, 29635
7031
  }
7032
  VTX  29703, 0, 0
7033
  {
7034
   COORD (820,1600)
7035
  }
7036
  BUS  29704, 0, 0
7037
  {
7038
   NET 28013
7039
   VTX 29636, 29703
7040
  }
7041
  VTX  29705, 0, 0
7042
  {
7043
   COORD (820,1700)
7044
  }
7045
  BUS  29706, 0, 0
7046
  {
7047
   NET 28013
7048
   VTX 29703, 29705
7049
  }
7050
  VTX  29707, 0, 0
7051
  {
7052
   COORD (1940,1700)
7053
  }
7054
  BUS  29708, 0, 0
7055
  {
7056
   NET 28013
7057
   VTX 29705, 29707
7058
  }
7059
  VTX  29709, 0, 0
7060
  {
7061
   COORD (1940,1680)
7062
  }
7063
  BUS  29710, 0, 0
7064
  {
7065
   NET 28013
7066
   VTX 29707, 29709
7067
  }
7068
  VTX  29711, 0, 0
7069
  {
7070
   COORD (2020,1680)
7071
  }
7072
  BUS  29712, 0, 0
7073
  {
7074
   NET 28013
7075
   VTX 29709, 29711
7076
  }
7077
  VTX  29713, 0, 0
7078
  {
7079
   COORD (2020,1520)
7080
  }
7081
  BUS  29714, 0, 0
7082
  {
7083
   NET 28013
7084
   VTX 29711, 29713
7085
  }
7086
  VTX  29715, 0, 0
7087
  {
7088
   COORD (2410,1520)
7089
  }
7090
  BUS  29716, 0, 0
7091
  {
7092
   NET 28013
7093
   VTX 29713, 29715
7094
  }
7095
  VTX  29717, 0, 0
7096
  {
7097
   COORD (2410,980)
7098
  }
7099
  BUS  29718, 0, 0
7100
  {
7101
   NET 28013
7102
   VTX 29715, 29717
7103
  }
7104
  BUS  29719, 0, 0
7105
  {
7106
   NET 28013
7107
   VTX 29717, 29637
7108
  }
7109
  VTX  29720, 0, 0
7110
  {
7111
   COORD (2780,1700)
7112
  }
7113
  BUS  29721, 0, 0
7114
  {
7115
   NET 7231
7116
   VTX 29638, 29720
7117
  }
7118
  VTX  29722, 0, 0
7119
  {
7120
   COORD (2780,1060)
7121
  }
7122
  BUS  29723, 0, 0
7123
  {
7124
   NET 7231
7125
   VTX 29720, 29722
7126
  }
7127
  VTX  29724, 0, 0
7128
  {
7129
   COORD (3020,1060)
7130
  }
7131
  BUS  29725, 0, 0
7132
  {
7133
   NET 7231
7134
   VTX 29722, 29724
7135
  }
7136
  VTX  29726, 0, 0
7137
  {
7138
   COORD (3020,820)
7139
  }
7140
  BUS  29727, 0, 0
7141
  {
7142
   NET 7231
7143
   VTX 29724, 29726
7144
  }
7145
  VTX  29728, 0, 0
7146
  {
7147
   COORD (1980,820)
7148
  }
7149
  BUS  29729, 0, 0
7150
  {
7151
   NET 7231
7152
   VTX 29726, 29728
7153
  }
7154
  VTX  29730, 0, 0
7155
  {
7156
   COORD (1980,1020)
7157
  }
7158
  BUS  29731, 0, 0
7159
  {
7160
   NET 7231
7161
   VTX 29728, 29730
7162
  }
7163
  BUS  29732, 0, 0
7164
  {
7165
   NET 7231
7166
   VTX 29730, 29639
7167
  }
7168
  VTX  29733, 0, 0
7169
  {
7170
   COORD (1920,790)
7171
  }
7172
  BUS  29734, 0, 0
7173
  {
7174
   NET 29854
7175
   VTX 26673, 29733
7176
  }
7177
  VTX  29735, 0, 0
7178
  {
7179
   COORD (1990,790)
7180
  }
7181
  BUS  29736, 0, 0
7182
  {
7183
   NET 29854
7184
   VTX 29733, 29735
7185
  }
7186
  VTX  29737, 0, 0
7187
  {
7188
   COORD (1990,1060)
7189
  }
7190
  BUS  29738, 0, 0
7191
  {
7192
   NET 29854
7193
   VTX 29735, 29737
7194
  }
7195
  BUS  29739, 0, 0
7196
  {
7197
   NET 29854
7198
   VTX 29737, 29640
7199
  }
7200
  VTX  29740, 0, 0
7201
  {
7202
   COORD (1820,1100)
7203
  }
7204
  BUS  29741, 0, 0
7205
  {
7206
   NET 15471
7207
   VTX 23939, 29740
7208
  }
7209
  BUS  29742, 0, 0
7210
  {
7211
   NET 15471
7212
   VTX 29740, 29641
7213
  }
7214
  VTX  29743, 0, 0
7215
  {
7216
   COORD (1520,560)
7217
  }
7218
  BUS  29744, 0, 0
7219
  {
7220
   NET 5832
7221
   VTX 29642, 29743
7222
  }
7223
  VTX  29745, 0, 0
7224
  {
7225
   COORD (1520,1000)
7226
  }
7227
  BUS  29746, 0, 0
7228
  {
7229
   NET 5832
7230
   VTX 29743, 29745
7231
  }
7232
  VTX  29747, 0, 0
7233
  {
7234
   COORD (1780,1000)
7235
  }
7236
  BUS  29748, 0, 0
7237
  {
7238
   NET 5832
7239
   VTX 29745, 29747
7240
  }
7241
  VTX  29749, 0, 0
7242
  {
7243
   COORD (1780,1140)
7244
  }
7245
  BUS  29750, 0, 0
7246
  {
7247
   NET 5832
7248
   VTX 29747, 29749
7249
  }
7250
  BUS  29751, 0, 0
7251
  {
7252
   NET 5832
7253
   VTX 29749, 29643
7254
  }
7255
  VTX  29752, 0, 0
7256
  {
7257
   COORD (2040,1760)
7258
  }
7259
  BUS  29753, 0, 0
7260
  {
7261
   NET 1158
7262
   VTX 29644, 29752
7263
  }
7264
  VTX  29754, 0, 0
7265
  {
7266
   COORD (2040,1540)
7267
  }
7268
  BUS  29755, 0, 0
7269
  {
7270
   NET 1158
7271
   VTX 29752, 29754
7272
  }
7273
  VTX  29756, 0, 0
7274
  {
7275
   COORD (1860,1540)
7276
  }
7277
  BUS  29757, 0, 0
7278
  {
7279
   NET 1158
7280
   VTX 29754, 29756
7281
  }
7282
  VTX  29758, 0, 0
7283
  {
7284
   COORD (1860,1180)
7285
  }
7286
  BUS  29759, 0, 0
7287
  {
7288
   NET 1158
7289
   VTX 29756, 29758
7290
  }
7291
  BUS  29760, 0, 0
7292
  {
7293
   NET 1158
7294
   VTX 29758, 29645
7295
  }
7296
  VTX  29761, 0, 0
7297
  {
7298
   COORD (1500,600)
7299
  }
7300
  BUS  29762, 0, 0
7301
  {
7302
   NET 5840
7303
   VTX 29646, 29761
7304
  }
7305
  VTX  29763, 0, 0
7306
  {
7307
   COORD (1500,900)
7308
  }
7309
  BUS  29764, 0, 0
7310
  {
7311
   NET 5840
7312
   VTX 29761, 29763
7313
  }
7314
  VTX  29765, 0, 0
7315
  {
7316
   COORD (1940,900)
7317
  }
7318
  BUS  29766, 0, 0
7319
  {
7320
   NET 5840
7321
   VTX 29763, 29765
7322
  }
7323
  VTX  29767, 0, 0
7324
  {
7325
   COORD (1940,1220)
7326
  }
7327
  BUS  29768, 0, 0
7328
  {
7329
   NET 5840
7330
   VTX 29765, 29767
7331
  }
7332
  BUS  29769, 0, 0
7333
  {
7334
   NET 5840
7335
   VTX 29767, 29647
7336
  }
7337
  VTX  29770, 0, 0
7338
  {
7339
   COORD (2140,1800)
7340
  }
7341
  BUS  29771, 0, 0
7342
  {
7343
   NET 1196
7344
   VTX 29648, 29770
7345
  }
7346
  VTX  29772, 0, 0
7347
  {
7348
   COORD (2140,1580)
7349
  }
7350
  BUS  29773, 0, 0
7351
  {
7352
   NET 1196
7353
   VTX 29770, 29772
7354
  }
7355
  VTX  29774, 0, 0
7356
  {
7357
   COORD (1920,1580)
7358
  }
7359
  BUS  29775, 0, 0
7360
  {
7361
   NET 1196
7362
   VTX 29772, 29774
7363
  }
7364
  VTX  29776, 0, 0
7365
  {
7366
   COORD (1920,1260)
7367
  }
7368
  BUS  29777, 0, 0
7369
  {
7370
   NET 1196
7371
   VTX 29774, 29776
7372
  }
7373
  BUS  29778, 0, 0
7374
  {
7375
   NET 1196
7376
   VTX 29776, 29649
7377
  }
7378
  VTX  29779, 0, 0
7379
  {
7380
   COORD (680,1760)
7381
  }
7382
  BUS  29780, 0, 0
7383
  {
7384
   NET 27031
7385
   VTX 23997, 29779
7386
  }
7387
  VTX  29781, 0, 0
7388
  {
7389
   COORD (1320,1760)
7390
  }
7391
  BUS  29782, 0, 0
7392
  {
7393
   NET 27031
7394
   VTX 29779, 29781
7395
  }
7396
  VTX  29783, 0, 0
7397
  {
7398
   COORD (1320,1640)
7399
  }
7400
  BUS  29784, 0, 0
7401
  {
7402
   NET 27031
7403
   VTX 29781, 29783
7404
  }
7405
  VTX  29785, 0, 0
7406
  {
7407
   COORD (1420,1640)
7408
  }
7409
  BUS  29786, 0, 0
7410
  {
7411
   NET 27031
7412
   VTX 29783, 29785
7413
  }
7414
  VTX  29787, 0, 0
7415
  {
7416
   COORD (1420,1560)
7417
  }
7418
  BUS  29788, 0, 0
7419
  {
7420
   NET 27031
7421
   VTX 29785, 29787
7422
  }
7423
  VTX  29789, 0, 0
7424
  {
7425
   COORD (1460,1560)
7426
  }
7427
  BUS  29790, 0, 0
7428
  {
7429
   NET 27031
7430
   VTX 29787, 29789
7431
  }
7432
  VTX  29791, 0, 0
7433
  {
7434
   COORD (1460,1340)
7435
  }
7436
  BUS  29792, 0, 0
7437
  {
7438
   NET 27031
7439
   VTX 29789, 29791
7440
  }
7441
  VTX  29793, 0, 0
7442
  {
7443
   COORD (1940,1340)
7444
  }
7445
  BUS  29794, 0, 0
7446
  {
7447
   NET 27031
7448
   VTX 29791, 29793
7449
  }
7450
  VTX  29795, 0, 0
7451
  {
7452
   COORD (1940,1320)
7453
  }
7454
  BUS  29796, 0, 0
7455
  {
7456
   NET 27031
7457
   VTX 29793, 29795
7458
  }
7459
  VTX  29797, 0, 0
7460
  {
7461
   COORD (1980,1320)
7462
  }
7463
  BUS  29798, 0, 0
7464
  {
7465
   NET 27031
7466
   VTX 29795, 29797
7467
  }
7468
  VTX  29799, 0, 0
7469
  {
7470
   COORD (1980,1300)
7471
  }
7472
  BUS  29800, 0, 0
7473
  {
7474
   NET 27031
7475
   VTX 29797, 29799
7476
  }
7477
  BUS  29801, 0, 0
7478
  {
7479
   NET 27031
7480
   VTX 29799, 29650
7481
  }
7482
  VTX  29802, 0, 0
7483
  {
7484
   COORD (2760,1300)
7485
  }
7486
  BUS  29803, 0, 0
7487
  {
7488
   NET 7101
7489
   VTX 29651, 29802
7490
  }
7491
  VTX  29804, 0, 0
7492
  {
7493
   COORD (2760,1600)
7494
  }
7495
  BUS  29805, 0, 0
7496
  {
7497
   NET 7101
7498
   VTX 29802, 29804
7499
  }
7500
  VTX  29806, 0, 0
7501
  {
7502
   COORD (1940,1600)
7503
  }
7504
  BUS  29807, 0, 0
7505
  {
7506
   NET 7101
7507
   VTX 29804, 29806
7508
  }
7509
  VTX  29808, 0, 0
7510
  {
7511
   COORD (1940,1360)
7512
  }
7513
  BUS  29809, 0, 0
7514
  {
7515
   NET 7101
7516
   VTX 29806, 29808
7517
  }
7518
  VTX  29810, 0, 0
7519
  {
7520
   COORD (1980,1360)
7521
  }
7522
  BUS  29811, 0, 0
7523
  {
7524
   NET 7101
7525
   VTX 29808, 29810
7526
  }
7527
  VTX  29812, 0, 0
7528
  {
7529
   COORD (1980,1340)
7530
  }
7531
  BUS  29813, 0, 0
7532
  {
7533
   NET 7101
7534
   VTX 29810, 29812
7535
  }
7536
  BUS  29814, 0, 0
7537
  {
7538
   NET 7101
7539
   VTX 29812, 29652
7540
  }
7541
  VTX  29815, 0, 0
7542
  {
7543
   COORD (1340,1660)
7544
  }
7545
  WIRE  29816, 0, 0
7546
  {
7547
   NET 7555
7548
   VTX 23947, 29815
7549
  }
7550
  VTX  29817, 0, 0
7551
  {
7552
   COORD (1340,1580)
7553
  }
7554
  WIRE  29818, 0, 0
7555
  {
7556
   NET 7555
7557
   VTX 29815, 29817
7558
  }
7559
  VTX  29819, 0, 0
7560
  {
7561
   COORD (1900,1580)
7562
  }
7563
  WIRE  29820, 0, 0
7564
  {
7565
   NET 7555
7566
   VTX 29817, 29819
7567
  }
7568
  VTX  29821, 0, 0
7569
  {
7570
   COORD (1900,1400)
7571
  }
7572
  WIRE  29822, 0, 0
7573
  {
7574
   NET 7555
7575
   VTX 29819, 29821
7576
  }
7577
  VTX  29823, 0, 0
7578
  {
7579
   COORD (1980,1400)
7580
  }
7581
  WIRE  29824, 0, 0
7582
  {
7583
   NET 7555
7584
   VTX 29821, 29823
7585
  }
7586
  VTX  29825, 0, 0
7587
  {
7588
   COORD (1980,1380)
7589
  }
7590
  WIRE  29826, 0, 0
7591
  {
7592
   NET 7555
7593
   VTX 29823, 29825
7594
  }
7595
  WIRE  29827, 0, 0
7596
  {
7597
   NET 7555
7598
   VTX 29825, 29653
7599
  }
7600
  VTX  29828, 0, 0
7601
  {
7602
   COORD (3000,1480)
7603
  }
7604
  BUS  29829, 0, 0
7605
  {
7606
   NET 7117
7607
   VTX 29654, 29828
7608
  }
7609
  VTX  29830, 0, 0
7610
  {
7611
   COORD (3000,800)
7612
  }
7613
  BUS  29831, 0, 0
7614
  {
7615
   NET 7117
7616
   VTX 29828, 29830
7617
  }
7618
  VTX  29832, 0, 0
7619
  {
7620
   COORD (1880,800)
7621
  }
7622
  BUS  29833, 0, 0
7623
  {
7624
   NET 7117
7625
   VTX 29830, 29832
7626
  }
7627
  VTX  29834, 0, 0
7628
  {
7629
   COORD (1880,1420)
7630
  }
7631
  BUS  29835, 0, 0
7632
  {
7633
   NET 7117
7634
   VTX 29832, 29834
7635
  }
7636
  BUS  29836, 0, 0
7637
  {
7638
   NET 7117
7639
   VTX 29834, 29655
7640
  }
7641
  VTX  29837, 0, 0
7642
  {
7643
   COORD (2360,1700)
7644
  }
7645
  WIRE  29838, 0, 0
7646
  {
7647
   NET 21531
7648
   VTX 29656, 29837
7649
  }
7650
  VTX  29839, 0, 0
7651
  {
7652
   COORD (2360,2060)
7653
  }
7654
  WIRE  29840, 0, 0
7655
  {
7656
   NET 21531
7657
   VTX 29837, 29839
7658
  }
7659
  VTX  29841, 0, 0
7660
  {
7661
   COORD (1460,2060)
7662
  }
7663
  WIRE  29842, 0, 0
7664
  {
7665
   NET 21531
7666
   VTX 29839, 29841
7667
  }
7668
  VTX  29843, 0, 0
7669
  {
7670
   COORD (1460,1600)
7671
  }
7672
  WIRE  29844, 0, 0
7673
  {
7674
   NET 21531
7675
   VTX 29841, 29843
7676
  }
7677
  VTX  29845, 0, 0
7678
  {
7679
   COORD (1880,1600)
7680
  }
7681
  WIRE  29846, 0, 0
7682
  {
7683
   NET 21531
7684
   VTX 29843, 29845
7685
  }
7686
  VTX  29847, 0, 0
7687
  {
7688
   COORD (1880,1480)
7689
  }
7690
  WIRE  29848, 0, 0
7691
  {
7692
   NET 21531
7693
   VTX 29845, 29847
7694
  }
7695
  VTX  29849, 0, 0
7696
  {
7697
   COORD (1980,1480)
7698
  }
7699
  WIRE  29850, 0, 0
7700
  {
7701
   NET 21531
7702
   VTX 29847, 29849
7703
  }
7704
  VTX  29851, 0, 0
7705
  {
7706
   COORD (1980,1460)
7707
  }
7708
  WIRE  29852, 0, 0
7709
  {
7710
   NET 21531
7711
   VTX 29849, 29851
7712
  }
7713
  WIRE  29853, 0, 0
7714
  {
7715
   NET 21531
7716
   VTX 29851, 29657
7717
  }
7718
  NET BUS  29854, 0, 0
7719
 }
7720
 
7721
}
7722
 
7723
PAGE ""
7724
{
7725
 PAGEHEADER
7726
 {
7727
  PAGESIZE (3307,2338)
7728
  MARGINS (200,200,200,200)
7729
  RECT (0,0,0,0)
7730
  VARIABLES
7731
  {
7732
   #ARCHITECTURE="\\#TABLE\\"
7733
   #BLOCKTABLE_PAGE="1"
7734
   #BLOCKTABLE_TEMPL="1"
7735
   #BLOCKTABLE_VISIBLE="0"
7736
   #ENTITY="\\#TABLE\\"
7737
   #MODIFIED="1140746926"
7738
  }
7739
 }
7740
 
7741
 BODY
7742
 {
7743
  TEXT  29855, 0, 0
7744
  {
7745
   PAGEALIGN 10
7746
   OUTLINE 5,1, (0,0,0)
7747
   TEXT "Created:"
7748
   RECT (2247,2024,2364,2077)
7749
   ALIGN 4
7750
   MARGINS (1,10)
7751
   COLOR (0,0,0)
7752
   FONT (12,0,0,700,0,0,0,"Arial")
7753
  }
7754
  TEXT  29856, 0, 0
7755
  {
7756
   PAGEALIGN 10
7757
   TEXT "$CREATIONDATE"
7758
   RECT (2417,2018,3087,2078)
7759
   ALIGN 4
7760
   MARGINS (1,1)
7761
   COLOR (0,0,0)
7762
   FONT (12,0,0,700,0,128,0,"Arial")
7763
   UPDATE 0
7764
  }
7765
  TEXT  29857, 0, 0
7766
  {
7767
   PAGEALIGN 10
7768
   TEXT "Title:"
7769
   RECT (2248,2082,2319,2135)
7770
   ALIGN 4
7771
   MARGINS (1,10)
7772
   COLOR (0,0,0)
7773
   FONT (12,0,0,700,0,0,0,"Arial")
7774
  }
7775
  TEXT  29858, 0, 0
7776
  {
7777
   PAGEALIGN 10
7778
   OUTLINE 5,1, (0,0,0)
7779
   TEXT "$TITLE"
7780
   RECT (2417,2078,3087,2138)
7781
   ALIGN 4
7782
   MARGINS (1,1)
7783
   COLOR (0,0,0)
7784
   FONT (12,0,0,700,0,128,0,"Arial")
7785
   UPDATE 0
7786
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7789
   PAGEALIGN 10
7790
   OUTLINE 0,1, (128,128,128)
7791
   POINTS ( (2237,2018), (3107,2018) )
7792
   FILL (1,(0,0,0),0)
7793
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7794
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  {
7796
   PAGEALIGN 10
7797
   OUTLINE 0,1, (128,128,128)
7798
   POINTS ( (2237,2078), (3107,2078) )
7799
   FILL (1,(0,0,0),0)
7800
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7801
  LINE  29861, 0, 0
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7803
   PAGEALIGN 10
7804
   OUTLINE 0,1, (128,128,128)
7805
   POINTS ( (2407,2018), (2407,2138) )
7806
  }
7807
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7809
   PAGEALIGN 10
7810
   OUTLINE 0,1, (128,128,128)
7811
   POINTS ( (3107,2138), (3107,1878), (2237,1878), (2237,2138), (3107,2138) )
7812
   FILL (1,(0,0,0),0)
7813
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7814
  TEXT  29863, 0, 0
7815
  {
7816
   PAGEALIGN 10
7817
   TEXT
7818
"(C)ALDEC. Inc\n"+
7819
"2260 Corporate Circle\n"+
7820
"Henderson, NV 89074"
7821
   RECT (2247,1898,2542,1999)
7822
   MARGINS (1,1)
7823
   COLOR (0,0,0)
7824
   FONT (12,0,0,700,0,0,0,"Arial")
7825
   MULTILINE
7826
  }
7827
  LINE  29864, 0, 0
7828
  {
7829
   PAGEALIGN 10
7830
   OUTLINE 0,1, (128,128,128)
7831
   POINTS ( (2547,1878), (2547,2018) )
7832
  }
7833
  LINE  29865, 0, 0
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  {
7835
   PAGEALIGN 10
7836
   OUTLINE 0,4, (0,4,255)
7837
   POINTS ( (2723,1942), (2789,1942) )
7838
   FILL (0,(0,4,255),0)
7839
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7840
  LINE  29866, 0, 0
7841
  {
7842
   PAGEALIGN 10
7843
   OUTLINE 0,1, (0,4,255)
7844
   POINTS ( (2692,1938), (2692,1938) )
7845
   FILL (0,(0,4,255),0)
7846
  }
7847
  LINE  29867, 0, 0
7848
  {
7849
   PAGEALIGN 10
7850
   OUTLINE 0,3, (0,4,255)
7851
   POINTS ( (2741,1942), (2757,1902) )
7852
   FILL (0,(0,4,255),0)
7853
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7854
  TEXT  29868, -4, 0
7855
  {
7856
   PAGEALIGN 10
7857
   OUTLINE 5,0, (49,101,255)
7858
   TEXT "ALDEC"
7859
   RECT (2770,1884,3068,1986)
7860
   MARGINS (1,1)
7861
   COLOR (0,4,255)
7862
   FONT (36,0,0,700,0,0,0,"Arial")
7863
  }
7864
  LINE  29869, 0, 0
7865
  {
7866
   PAGEALIGN 10
7867
   OUTLINE 0,3, (0,4,255)
7868
   POINTS ( (2683,1902), (2658,1965) )
7869
   FILL (0,(0,4,255),0)
7870
  }
7871
  BEZIER  29870, 0, 0
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7873
   PAGEALIGN 10
7874
   OUTLINE 0,3, (0,4,255)
7875
   FILL (0,(0,4,255),0)
7876
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7877
   CONTROLS (( (2714,1928), (2722,1927)),( (2720,1953), (2717,1953)),( (2690,1945), (2690,1940)) )
7878
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7880
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7881
   PAGEALIGN 10
7882
   OUTLINE 0,4, (0,4,255)
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   POINTS ( (2602,1949), (2690,1949) )
7884
   FILL (0,(0,4,255),0)
7885
  }
7886
  LINE  29872, 0, 0
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  {
7888
   PAGEALIGN 10
7889
   OUTLINE 0,4, (0,4,255)
7890
   POINTS ( (2609,1932), (2690,1932) )
7891
   FILL (0,(0,4,255),0)
7892
  }
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7894
  {
7895
   PAGEALIGN 10
7896
   OUTLINE 0,1, (0,4,255)
7897
   POINTS ( (2795,1909), (2618,1909) )
7898
   FILL (0,(0,4,255),0)
7899
  }
7900
  LINE  29874, 0, 0
7901
  {
7902
   PAGEALIGN 10
7903
   OUTLINE 0,1, (0,4,255)
7904
   POINTS ( (2793,1916), (2615,1916) )
7905
   FILL (0,(0,4,255),0)
7906
  }
7907
  LINE  29875, 0, 0
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  {
7909
   PAGEALIGN 10
7910
   OUTLINE 0,1, (0,4,255)
7911
   POINTS ( (2807,1924), (2613,1924) )
7912
   FILL (0,(0,4,255),0)
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   OUTLINE 0,1, (0,4,255)
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   POINTS ( (2809,1932), (2617,1932) )
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   FILL (0,(0,4,255),0)
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  {
7923
   PAGEALIGN 10
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   OUTLINE 0,1, (0,4,255)
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   POINTS ( (2722,1940), (2606,1940) )
7926
   FILL (0,(0,4,255),0)
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  {
7930
   PAGEALIGN 10
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   OUTLINE 0,1, (0,4,255)
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   POINTS ( (2787,1949), (2602,1949) )
7933
   FILL (0,(0,4,255),0)
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  }
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  LINE  29879, 0, 0
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7937
   PAGEALIGN 10
7938
   OUTLINE 0,1, (0,4,255)
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   POINTS ( (2780,1957), (2599,1957) )
7940
   FILL (0,(0,4,255),0)
7941
  }
7942
  TEXT  29880, 0, 0
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  {
7944
   PAGEALIGN 10
7945
   TEXT "The Design Verification Company"
7946
   RECT (2589,1974,3041,2008)
7947
   MARGINS (1,1)
7948
   COLOR (0,4,255)
7949
   FONT (12,0,0,700,1,0,0,"Arial")
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  LINE  29881, 0, 0
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7953
   PAGEALIGN 10
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   OUTLINE 0,1, (0,4,255)
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   POINTS ( (2774,1965), (2596,1965) )
7956
   FILL (0,(0,4,255),0)
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  {
7960
   PAGEALIGN 10
7961
   OUTLINE 0,1, (0,4,255)
7962
   POINTS ( (2797,1902), (2621,1902) )
7963
   FILL (0,(0,4,255),0)
7964
  }
7965
 }
7966
 
7967
}
7968
 

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