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URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [dbe/] [decode_pipe.BDE] - Blame information for rev 55

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 6022
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="decode_pipe3"
12 
  AUTHOR="liwei"
13 
  COMPANY="PKU"
14 
  CREATIONDATE="2007-8-4"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "pipelinedregs" "pipelinedregs"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #GENERIC0="DANGLING_INPUT_CONSTANT:integer:=1'bZ"
25 
    #LANGUAGE="VERILOG"
26 
    #MODIFIED="1194442907"
27 
   }
28 
  }
29 
  PAGE ""
30 
  {
31 
   PAGEHEADER
32 
   {
33 
    RECT (0,0,400,640)
34 
    FREEID 57
35 
   }
36 
 
37 
   BODY
38 
   {
39 
    RECT  1, -1, 0
40 
    {
41 
     VARIABLES
42 
     {
43 
      #OUTLINE_FILLING="1"
44 
     }
45 
     AREA (20,0,380,640)
46 
    }
47 
    TEXT  3, 0, 0
48 
    {
49 
     TEXT "$#NAME"
50 
     RECT (25,30,192,54)
51 
     ALIGN 4
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     MARGINS (1,1)
53 
     PARENT 2
54 
    }
55 
    TEXT  5, 0, 0
56 
    {
57 
     TEXT "$#NAME"
58 
     RECT (208,30,375,54)
59 
     ALIGN 6
60 
     MARGINS (1,1)
61 
     PARENT 4
62 
    }
63 
    TEXT  7, 0, 0
64 
    {
65 
     TEXT "$#NAME"
66 
     RECT (25,70,170,94)
67 
     ALIGN 4
68 
     MARGINS (1,1)
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     PARENT 6
70 
    }
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    TEXT  9, 0, 0
72 
    {
73 
     TEXT "$#NAME"
74 
     RECT (230,70,375,94)
75 
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76 
     MARGINS (1,1)
77 
     PARENT 8
78 
    }
79 
    TEXT  11, 0, 0
80 
    {
81 
     TEXT "$#NAME"
82 
     RECT (25,110,60,134)
83 
     ALIGN 4
84 
     MARGINS (1,1)
85 
     PARENT 10
86 
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87 
    TEXT  13, 0, 0
88 
    {
89 
     TEXT "$#NAME"
90 
     RECT (219,110,375,134)
91 
     ALIGN 6
92 
     MARGINS (1,1)
93 
     PARENT 12
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95 
    TEXT  15, 0, 0
96 
    {
97 
     TEXT "$#NAME"
98 
     RECT (25,150,181,174)
99 
     ALIGN 4
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     MARGINS (1,1)
101 
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103 
    TEXT  17, 0, 0
104 
    {
105 
     TEXT "$#NAME"
106 
     RECT (208,150,375,174)
107 
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    TEXT  19, 0, 0
112 
    {
113 
     TEXT "$#NAME"
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     RECT (25,190,192,214)
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    TEXT  21, 0, 0
120 
    {
121 
     TEXT "$#NAME"
122 
     RECT (175,190,375,214)
123 
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    TEXT  23, 0, 0
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    {
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     TEXT "$#NAME"
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     RECT (25,230,181,254)
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    TEXT  25, 0, 0
136 
    {
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     TEXT "$#NAME"
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     RECT (241,230,375,254)
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    TEXT  27, 0, 0
144 
    {
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     TEXT "$#NAME"
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    TEXT  29, 0, 0
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    {
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     TEXT "$#NAME"
154 
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155 
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160 
    {
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     TEXT "$#NAME"
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    TEXT  33, 0, 0
168 
    {
169 
     TEXT "$#NAME"
170 
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    }
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    TEXT  35, 0, 0
176 
    {
177 
     TEXT "$#NAME"
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     RECT (25,350,192,374)
179 
     ALIGN 4
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     MARGINS (1,1)
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    }
183 
    TEXT  37, 0, 0
184 
    {
185 
     TEXT "$#NAME"
186 
     RECT (186,350,375,374)
187 
     ALIGN 6
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     MARGINS (1,1)
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     PARENT 36
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    }
191 
    TEXT  39, 0, 0
192 
    {
193 
     TEXT "$#NAME"
194 
     RECT (25,390,192,414)
195 
     ALIGN 4
196 
     MARGINS (1,1)
197 
     PARENT 38
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    }
199 
    TEXT  41, 0, 0
200 
    {
201 
     TEXT "$#NAME"
202 
     RECT (230,390,375,414)
203 
     ALIGN 6
204 
     MARGINS (1,1)
205 
     PARENT 40
206 
    }
207 
    TEXT  43, 0, 0
208 
    {
209 
     TEXT "$#NAME"
210 
     RECT (25,430,214,454)
211 
     ALIGN 4
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     MARGINS (1,1)
213 
     PARENT 42
214 
    }
215 
    TEXT  45, 0, 0
216 
    {
217 
     TEXT "$#NAME"
218 
     RECT (186,430,375,454)
219 
     ALIGN 6
220 
     MARGINS (1,1)
221 
     PARENT 44
222 
    }
223 
    TEXT  47, 0, 0
224 
    {
225 
     TEXT "$#NAME"
226 
     RECT (25,470,170,494)
227 
     ALIGN 4
228 
     MARGINS (1,1)
229 
     PARENT 46
230 
    }
231 
    TEXT  49, 0, 0
232 
    {
233 
     TEXT "$#NAME"
234 
     RECT (241,470,375,494)
235 
     ALIGN 6
236 
     MARGINS (1,1)
237 
     PARENT 48
238 
    }
239 
    TEXT  51, 0, 0
240 
    {
241 
     TEXT "$#NAME"
242 
     RECT (25,510,170,534)
243 
     ALIGN 4
244 
     MARGINS (1,1)
245 
     PARENT 50
246 
    }
247 
    TEXT  53, 0, 0
248 
    {
249 
     TEXT "$#NAME"
250 
     RECT (25,550,214,574)
251 
     ALIGN 4
252 
     MARGINS (1,1)
253 
     PARENT 52
254 
    }
255 
    TEXT  55, 0, 0
256 
    {
257 
     TEXT "$#NAME"
258 
     RECT (25,590,159,614)
259 
     ALIGN 4
260 
     MARGINS (1,1)
261 
     PARENT 54
262 
    }
263 
    PIN  2, 0, 0
264 
    {
265 
     COORD (0,40)
266 
     VARIABLES
267 
     {
268 
      #DIRECTION="IN"
269 
      #DOWNTO="1"
270 
      #LENGTH="20"
271 
      #MDA_RECORD_TOKEN="OTHER"
272 
      #NAME="alu_func_i(4:0)"
273 
      #NUMBER="0"
274 
      #VERILOG_TYPE="wire"
275 
     }
276 
     LINE  2, 0, 0
277 
     {
278 
      POINTS ( (0,0), (20,0) )
279 
     }
280 
    }
281 
    PIN  4, 0, 0
282 
    {
283 
     COORD (400,40)
284 
     VARIABLES
285 
     {
286 
      #DIRECTION="OUT"
287 
      #DOWNTO="1"
288 
      #LENGTH="20"
289 
      #MDA_RECORD_TOKEN="OTHER"
290 
      #NAME="alu_func_o(4:0)"
291 
      #NUMBER="0"
292 
      #VERILOG_TYPE="wire"
293 
     }
294 
     LINE  2, 0, 0
295 
     {
296 
      POINTS ( (-20,0), (0,0) )
297 
     }
298 
    }
299 
    PIN  6, 0, 0
300 
    {
301 
     COORD (0,80)
302 
     VARIABLES
303 
     {
304 
      #DIRECTION="IN"
305 
      #DOWNTO="1"
306 
      #LENGTH="20"
307 
      #MDA_RECORD_TOKEN="OTHER"
308 
      #NAME="alu_we_i(0:0)"
309 
      #NUMBER="0"
310 
      #VERILOG_TYPE="wire"
311 
     }
312 
     LINE  2, 0, 0
313 
     {
314 
      POINTS ( (0,0), (20,0) )
315 
     }
316 
    }
317 
    PIN  8, 0, 0
318 
    {
319 
     COORD (400,80)
320 
     VARIABLES
321 
     {
322 
      #DIRECTION="OUT"
323 
      #DOWNTO="1"
324 
      #LENGTH="20"
325 
      #MDA_RECORD_TOKEN="OTHER"
326 
      #NAME="alu_we_o(0:0)"
327 
      #NUMBER="0"
328 
      #VERILOG_TYPE="wire"
329 
     }
330 
     LINE  2, 0, 0
331 
     {
332 
      POINTS ( (-20,0), (0,0) )
333 
     }
334 
    }
335 
    PIN  10, 0, 0
336 
    {
337 
     COORD (0,120)
338 
     VARIABLES
339 
     {
340 
      #DIRECTION="IN"
341 
      #LENGTH="20"
342 
      #MDA_RECORD_TOKEN="OTHER"
343 
      #NAME="clk"
344 
      #NUMBER="0"
345 
      #VERILOG_TYPE="wire"
346 
     }
347 
     LINE  2, 0, 0
348 
     {
349 
      POINTS ( (0,0), (20,0) )
350 
     }
351 
    }
352 
    PIN  12, 0, 0
353 
    {
354 
     COORD (400,120)
355 
     VARIABLES
356 
     {
357 
      #DIRECTION="OUT"
358 
      #DOWNTO="1"
359 
      #LENGTH="20"
360 
      #MDA_RECORD_TOKEN="OTHER"
361 
      #NAME="cmp_ctl_o(2:0)"
362 
      #NUMBER="0"
363 
      #VERILOG_TYPE="wire"
364 
     }
365 
     LINE  2, 0, 0
366 
     {
367 
      POINTS ( (-20,0), (0,0) )
368 
     }
369 
    }
370 
    PIN  14, 0, 0
371 
    {
372 
     COORD (0,160)
373 
     VARIABLES
374 
     {
375 
      #DIRECTION="IN"
376 
      #DOWNTO="1"
377 
      #LENGTH="20"
378 
      #MDA_RECORD_TOKEN="OTHER"
379 
      #NAME="cmp_ctl_i(2:0)"
380 
      #NUMBER="0"
381 
      #VERILOG_TYPE="wire"
382 
     }
383 
     LINE  2, 0, 0
384 
     {
385 
      POINTS ( (0,0), (20,0) )
386 
     }
387 
    }
388 
    PIN  16, 0, 0
389 
    {
390 
     COORD (400,160)
391 
     VARIABLES
392 
     {
393 
      #DIRECTION="OUT"
394 
      #DOWNTO="1"
395 
      #LENGTH="20"
396 
      #MDA_RECORD_TOKEN="OTHER"
397 
      #NAME="dmem_ctl_o(3:0)"
398 
      #NUMBER="0"
399 
      #VERILOG_TYPE="wire"
400 
     }
401 
     LINE  2, 0, 0
402 
     {
403 
      POINTS ( (-20,0), (0,0) )
404 
     }
405 
    }
406 
    PIN  18, 0, 0
407 
    {
408 
     COORD (0,200)
409 
     VARIABLES
410 
     {
411 
      #DIRECTION="IN"
412 
      #DOWNTO="1"
413 
      #LENGTH="20"
414 
      #MDA_RECORD_TOKEN="OTHER"
415 
      #NAME="dmem_ctl_i(3:0)"
416 
      #NUMBER="0"
417 
      #VERILOG_TYPE="wire"
418 
     }
419 
     LINE  2, 0, 0
420 
     {
421 
      POINTS ( (0,0), (20,0) )
422 
     }
423 
    }
424 
    PIN  20, 0, 0
425 
    {
426 
     COORD (400,200)
427 
     VARIABLES
428 
     {
429 
      #DIRECTION="OUT"
430 
      #DOWNTO="1"
431 
      #LENGTH="20"
432 
      #MDA_RECORD_TOKEN="OTHER"
433 
      #NAME="dmem_ctl_ur_o(3:0)"
434 
      #NUMBER="0"
435 
      #VERILOG_TYPE="wire"
436 
     }
437 
     LINE  2, 0, 0
438 
     {
439 
      POINTS ( (-20,0), (0,0) )
440 
     }
441 
    }
442 
    PIN  22, 0, 0
443 
    {
444 
     COORD (0,240)
445 
     VARIABLES
446 
     {
447 
      #DIRECTION="IN"
448 
      #DOWNTO="1"
449 
      #LENGTH="20"
450 
      #MDA_RECORD_TOKEN="OTHER"
451 
      #NAME="ext_ctl_i(2:0)"
452 
      #NUMBER="0"
453 
      #VERILOG_TYPE="wire"
454 
     }
455 
     LINE  2, 0, 0
456 
     {
457 
      POINTS ( (0,0), (20,0) )
458 
     }
459 
    }
460 
    PIN  24, 0, 0
461 
    {
462 
     COORD (400,240)
463 
     VARIABLES
464 
     {
465 
      #DIRECTION="OUT"
466 
      #DOWNTO="1"
467 
      #LENGTH="20"
468 
      #MDA_RECORD_TOKEN="OTHER"
469 
      #NAME="ext_ctl(2:0)"
470 
      #NUMBER="0"
471 
      #VERILOG_TYPE="wire"
472 
     }
473 
     LINE  2, 0, 0
474 
     {
475 
      POINTS ( (-20,0), (0,0) )
476 
     }
477 
    }
478 
    PIN  26, 0, 0
479 
    {
480 
     COORD (0,280)
481 
     VARIABLES
482 
     {
483 
      #DIRECTION="IN"
484 
      #LENGTH="20"
485 
      #MDA_RECORD_TOKEN="OTHER"
486 
      #NAME="id2ra_ctl_clr"
487 
      #NUMBER="0"
488 
      #VERILOG_TYPE="wire"
489 
     }
490 
     LINE  2, 0, 0
491 
     {
492 
      POINTS ( (0,0), (20,0) )
493 
     }
494 
    }
495 
    PIN  28, 0, 0
496 
    {
497 
     COORD (400,280)
498 
     VARIABLES
499 
     {
500 
      #DIRECTION="OUT"
501 
      #DOWNTO="1"
502 
      #LENGTH="20"
503 
      #MDA_RECORD_TOKEN="OTHER"
504 
      #NAME="muxa_ctl_o(1:0)"
505 
      #NUMBER="0"
506 
      #VERILOG_TYPE="wire"
507 
     }
508 
     LINE  2, 0, 0
509 
     {
510 
      POINTS ( (-20,0), (0,0) )
511 
     }
512 
    }
513 
    PIN  30, 0, 0
514 
    {
515 
     COORD (0,320)
516 
     VARIABLES
517 
     {
518 
      #DIRECTION="IN"
519 
      #LENGTH="20"
520 
      #MDA_RECORD_TOKEN="OTHER"
521 
      #NAME="id2ra_ctl_cls"
522 
      #NUMBER="0"
523 
      #VERILOG_TYPE="wire"
524 
     }
525 
     LINE  2, 0, 0
526 
     {
527 
      POINTS ( (0,0), (20,0) )
528 
     }
529 
    }
530 
    PIN  32, 0, 0
531 
    {
532 
     COORD (400,320)
533 
     VARIABLES
534 
     {
535 
      #DIRECTION="OUT"
536 
      #DOWNTO="1"
537 
      #LENGTH="20"
538 
      #MDA_RECORD_TOKEN="OTHER"
539 
      #NAME="muxb_ctl_o(1:0)"
540 
      #NUMBER="0"
541 
      #VERILOG_TYPE="wire"
542 
     }
543 
     LINE  2, 0, 0
544 
     {
545 
      POINTS ( (-20,0), (0,0) )
546 
     }
547 
    }
548 
    PIN  34, 0, 0
549 
    {
550 
     COORD (0,360)
551 
     VARIABLES
552 
     {
553 
      #DIRECTION="IN"
554 
      #DOWNTO="1"
555 
      #LENGTH="20"
556 
      #MDA_RECORD_TOKEN="OTHER"
557 
      #NAME="muxa_ctl_i(1:0)"
558 
      #NUMBER="0"
559 
      #VERILOG_TYPE="wire"
560 
     }
561 
     LINE  2, 0, 0
562 
     {
563 
      POINTS ( (0,0), (20,0) )
564 
     }
565 
    }
566 
    PIN  36, 0, 0
567 
    {
568 
     COORD (400,360)
569 
     VARIABLES
570 
     {
571 
      #DIRECTION="OUT"
572 
      #DOWNTO="1"
573 
      #LENGTH="20"
574 
      #MDA_RECORD_TOKEN="OTHER"
575 
      #NAME="pc_gen_ctl_o(2:0)"
576 
      #NUMBER="0"
577 
      #VERILOG_TYPE="wire"
578 
     }
579 
     LINE  2, 0, 0
580 
     {
581 
      POINTS ( (-20,0), (0,0) )
582 
     }
583 
    }
584 
    PIN  38, 0, 0
585 
    {
586 
     COORD (0,400)
587 
     VARIABLES
588 
     {
589 
      #DIRECTION="IN"
590 
      #DOWNTO="1"
591 
      #LENGTH="20"
592 
      #MDA_RECORD_TOKEN="OTHER"
593 
      #NAME="muxb_ctl_i(1:0)"
594 
      #NUMBER="0"
595 
      #VERILOG_TYPE="wire"
596 
     }
597 
     LINE  2, 0, 0
598 
     {
599 
      POINTS ( (0,0), (20,0) )
600 
     }
601 
    }
602 
    PIN  40, 0, 0
603 
    {
604 
     COORD (400,400)
605 
     VARIABLES
606 
     {
607 
      #DIRECTION="OUT"
608 
      #DOWNTO="1"
609 
      #LENGTH="20"
610 
      #MDA_RECORD_TOKEN="OTHER"
611 
      #NAME="rd_sel_o(1:0)"
612 
      #NUMBER="0"
613 
      #VERILOG_TYPE="wire"
614 
     }
615 
     LINE  2, 0, 0
616 
     {
617 
      POINTS ( (-20,0), (0,0) )
618 
     }
619 
    }
620 
    PIN  42, 0, 0
621 
    {
622 
     COORD (0,440)
623 
     VARIABLES
624 
     {
625 
      #DIRECTION="IN"
626 
      #DOWNTO="1"
627 
      #LENGTH="20"
628 
      #MDA_RECORD_TOKEN="OTHER"
629 
      #NAME="pc_gen_ctl_i(2:0)"
630 
      #NUMBER="0"
631 
      #VERILOG_TYPE="wire"
632 
     }
633 
     LINE  2, 0, 0
634 
     {
635 
      POINTS ( (0,0), (20,0) )
636 
     }
637 
    }
638 
    PIN  44, 0, 0
639 
    {
640 
     COORD (400,440)
641 
     VARIABLES
642 
     {
643 
      #DIRECTION="OUT"
644 
      #DOWNTO="1"
645 
      #LENGTH="20"
646 
      #MDA_RECORD_TOKEN="OTHER"
647 
      #NAME="wb_mux_ctl_o(0:0)"
648 
      #NUMBER="0"
649 
      #VERILOG_TYPE="wire"
650 
     }
651 
     LINE  2, 0, 0
652 
     {
653 
      POINTS ( (-20,0), (0,0) )
654 
     }
655 
    }
656 
    PIN  46, 0, 0
657 
    {
658 
     COORD (0,480)
659 
     VARIABLES
660 
     {
661 
      #DIRECTION="IN"
662 
      #LENGTH="20"
663 
      #MDA_RECORD_TOKEN="OTHER"
664 
      #NAME="ra2ex_ctl_clr"
665 
      #NUMBER="0"
666 
      #VERILOG_TYPE="wire"
667 
     }
668 
     LINE  2, 0, 0
669 
     {
670 
      POINTS ( (0,0), (20,0) )
671 
     }
672 
    }
673 
    PIN  48, 0, 0
674 
    {
675 
     COORD (400,480)
676 
     VARIABLES
677 
     {
678 
      #DIRECTION="OUT"
679 
      #DOWNTO="1"
680 
      #LENGTH="20"
681 
      #MDA_RECORD_TOKEN="OTHER"
682 
      #NAME="wb_we_o(0:0)"
683 
      #NUMBER="0"
684 
      #VERILOG_TYPE="wire"
685 
     }
686 
     LINE  2, 0, 0
687 
     {
688 
      POINTS ( (-20,0), (0,0) )
689 
     }
690 
    }
691 
    PIN  50, 0, 0
692 
    {
693 
     COORD (0,520)
694 
     VARIABLES
695 
     {
696 
      #DIRECTION="IN"
697 
      #DOWNTO="1"
698 
      #LENGTH="20"
699 
      #MDA_RECORD_TOKEN="OTHER"
700 
      #NAME="rd_sel_i(1:0)"
701 
      #NUMBER="0"
702 
      #VERILOG_TYPE="wire"
703 
     }
704 
     LINE  2, 0, 0
705 
     {
706 
      POINTS ( (0,0), (20,0) )
707 
     }
708 
    }
709 
    PIN  52, 0, 0
710 
    {
711 
     COORD (0,560)
712 
     VARIABLES
713 
     {
714 
      #DIRECTION="IN"
715 
      #DOWNTO="1"
716 
      #LENGTH="20"
717 
      #MDA_RECORD_TOKEN="OTHER"
718 
      #NAME="wb_mux_ctl_i(0:0)"
719 
      #NUMBER="0"
720 
      #VERILOG_TYPE="wire"
721 
     }
722 
     LINE  2, 0, 0
723 
     {
724 
      POINTS ( (0,0), (20,0) )
725 
     }
726 
    }
727 
    PIN  54, 0, 0
728 
    {
729 
     COORD (0,600)
730 
     VARIABLES
731 
     {
732 
      #DIRECTION="IN"
733 
      #DOWNTO="1"
734 
      #LENGTH="20"
735 
      #MDA_RECORD_TOKEN="OTHER"
736 
      #NAME="wb_we_i(0:0)"
737 
      #NUMBER="0"
738 
      #VERILOG_TYPE="wire"
739 
     }
740 
     LINE  2, 0, 0
741 
     {
742 
      POINTS ( (0,0), (20,0) )
743 
     }
744 
    }
745 
   }
746 
  }
747 
 }
748 
 SYMBOL "#default" "decoder3" "decoder3"
749 
 {
750 
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751 
  {
752 
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753 
   {
754 
    #DESCRIPTION=""
755 
    #LANGUAGE="VERILOG"
756 
    #MODIFIED="1218402908"
757 
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758 
  }
759 
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760 
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761 
   PAGEHEADER
762 
   {
763 
    RECT (0,0,280,520)
764 
    FREEID 28
765 
   }
766 
 
767 
   BODY
768 
   {
769 
    RECT  1, -1, 0
770 
    {
771 
     VARIABLES
772 
     {
773 
      #OUTLINE_FILLING="1"
774 
     }
775 
     AREA (20,0,260,520)
776 
    }
777 
    TEXT  3, 0, 0
778 
    {
779 
     TEXT "$#NAME"
780 
     RECT (25,30,148,54)
781 
     ALIGN 4
782 
     MARGINS (1,1)
783 
     PARENT 2
784 
    }
785 
    TEXT  5, 0, 0
786 
    {
787 
     TEXT "$#NAME"
788 
     RECT (110,30,255,54)
789 
     ALIGN 6
790 
     MARGINS (1,1)
791 
     PARENT 4
792 
    }
793 
    TEXT  7, 0, 0
794 
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795 
     TEXT "$#NAME"
796 
     RECT (132,70,255,94)
797 
     ALIGN 6
798 
     MARGINS (1,1)
799 
     PARENT 6
800 
    }
801 
    TEXT  9, 0, 0
802 
    {
803 
     TEXT "$#NAME"
804 
     RECT (121,110,255,134)
805 
     ALIGN 6
806 
     MARGINS (1,1)
807 
     PARENT 8
808 
    }
809 
    TEXT  11, 0, 0
810 
    {
811 
     TEXT "$#NAME"
812 
     RECT (110,150,255,174)
813 
     ALIGN 6
814 
     MARGINS (1,1)
815 
     PARENT 10
816 
    }
817 
    TEXT  13, 0, 0
818 
    {
819 
     TEXT "$#NAME"
820 
     RECT (121,190,255,214)
821 
     ALIGN 6
822 
     MARGINS (1,1)
823 
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824 
    }
825 
    TEXT  15, 0, 0
826 
    {
827 
     TEXT "$#NAME"
828 
     RECT (121,230,255,254)
829 
     ALIGN 6
830 
     MARGINS (1,1)
831 
     PARENT 14
832 
    }
833 
    TEXT  17, 0, 0
834 
    {
835 
     TEXT "$#NAME"
836 
     RECT (110,270,255,294)
837 
     ALIGN 6
838 
     MARGINS (1,1)
839 
     PARENT 16
840 
    }
841 
    TEXT  19, 0, 0
842 
    {
843 
     TEXT "$#NAME"
844 
     RECT (110,310,255,334)
845 
     ALIGN 6
846 
     MARGINS (1,1)
847 
     PARENT 18
848 
    }
849 
    TEXT  21, 0, 0
850 
    {
851 
     TEXT "$#NAME"
852 
     RECT (88,350,255,374)
853 
     ALIGN 6
854 
     MARGINS (1,1)
855 
     PARENT 20
856 
    }
857 
    TEXT  23, 0, 0
858 
    {
859 
     TEXT "$#NAME"
860 
     RECT (132,390,255,414)
861 
     ALIGN 6
862 
     MARGINS (1,1)
863 
     PARENT 22
864 
    }
865 
    TEXT  25, 0, 0
866 
    {
867 
     TEXT "$#NAME"
868 
     RECT (132,430,255,454)
869 
     ALIGN 6
870 
     MARGINS (1,1)
871 
     PARENT 24
872 
    }
873 
    TEXT  27, 0, 0
874 
    {
875 
     TEXT "$#NAME"
876 
     RECT (143,470,255,494)
877 
     ALIGN 6
878 
     MARGINS (1,1)
879 
     PARENT 26
880 
    }
881 
    PIN  2, 0, 0
882 
    {
883 
     COORD (0,40)
884 
     VARIABLES
885 
     {
886 
      #DIRECTION="IN"
887 
      #DOWNTO="1"
888 
      #LENGTH="20"
889 
      #MDA_RECORD_TOKEN="OTHER"
890 
      #NAME="ins_i(31:0)"
891 
      #NUMBER="0"
892 
      #VERILOG_TYPE="wire"
893 
     }
894 
     LINE  2, 0, 0
895 
     {
896 
      POINTS ( (0,0), (20,0) )
897 
     }
898 
    }
899 
    PIN  4, 0, 0
900 
    {
901 
     COORD (280,40)
902 
     VARIABLES
903 
     {
904 
      #DIRECTION="OUT"
905 
      #DOWNTO="1"
906 
      #LENGTH="20"
907 
      #MDA_RECORD_TOKEN="OTHER"
908 
      #NAME="alu_func(4:0)"
909 
      #NUMBER="0"
910 
      #VERILOG_TYPE="reg"
911 
     }
912 
     LINE  2, 0, 0
913 
     {
914 
      POINTS ( (-20,0), (0,0) )
915 
     }
916 
    }
917 
    PIN  6, 0, 0
918 
    {
919 
     COORD (280,80)
920 
     VARIABLES
921 
     {
922 
      #DIRECTION="OUT"
923 
      #DOWNTO="1"
924 
      #LENGTH="20"
925 
      #MDA_RECORD_TOKEN="OTHER"
926 
      #NAME="alu_we(0:0)"
927 
      #NUMBER="0"
928 
      #VERILOG_TYPE="reg"
929 
     }
930 
     LINE  2, 0, 0
931 
     {
932 
      POINTS ( (-20,0), (0,0) )
933 
     }
934 
    }
935 
    PIN  8, 0, 0
936 
    {
937 
     COORD (280,120)
938 
     VARIABLES
939 
     {
940 
      #DIRECTION="OUT"
941 
      #DOWNTO="1"
942 
      #LENGTH="20"
943 
      #MDA_RECORD_TOKEN="OTHER"
944 
      #NAME="cmp_ctl(2:0)"
945 
      #NUMBER="0"
946 
      #VERILOG_TYPE="reg"
947 
     }
948 
     LINE  2, 0, 0
949 
     {
950 
      POINTS ( (-20,0), (0,0) )
951 
     }
952 
    }
953 
    PIN  10, 0, 0
954 
    {
955 
     COORD (280,160)
956 
     VARIABLES
957 
     {
958 
      #DIRECTION="OUT"
959 
      #DOWNTO="1"
960 
      #LENGTH="20"
961 
      #MDA_RECORD_TOKEN="OTHER"
962 
      #NAME="dmem_ctl(3:0)"
963 
      #NUMBER="0"
964 
      #VERILOG_TYPE="reg"
965 
     }
966 
     LINE  2, 0, 0
967 
     {
968 
      POINTS ( (-20,0), (0,0) )
969 
     }
970 
    }
971 
    PIN  12, 0, 0
972 
    {
973 
     COORD (280,200)
974 
     VARIABLES
975 
     {
976 
      #DIRECTION="OUT"
977 
      #DOWNTO="1"
978 
      #LENGTH="20"
979 
      #MDA_RECORD_TOKEN="OTHER"
980 
      #NAME="ext_ctl(2:0)"
981 
      #NUMBER="0"
982 
      #VERILOG_TYPE="reg"
983 
     }
984 
     LINE  2, 0, 0
985 
     {
986 
      POINTS ( (-20,0), (0,0) )
987 
     }
988 
    }
989 
    PIN  14, 0, 0
990 
    {
991 
     COORD (280,240)
992 
     VARIABLES
993 
     {
994 
      #DIRECTION="OUT"
995 
      #DOWNTO="1"
996 
      #LENGTH="20"
997 
      #MDA_RECORD_TOKEN="OTHER"
998 
      #NAME="fsm_dly(2:0)"
999 
      #NUMBER="0"
1000 
      #VERILOG_TYPE="reg"
1001 
     }
1002 
     LINE  2, 0, 0
1003 
     {
1004 
      POINTS ( (-20,0), (0,0) )
1005 
     }
1006 
    }
1007 
    PIN  16, 0, 0
1008 
    {
1009 
     COORD (280,280)
1010 
     VARIABLES
1011 
     {
1012 
      #DIRECTION="OUT"
1013 
      #DOWNTO="1"
1014 
      #LENGTH="20"
1015 
      #MDA_RECORD_TOKEN="OTHER"
1016 
      #NAME="muxa_ctl(1:0)"
1017 
      #NUMBER="0"
1018 
      #VERILOG_TYPE="reg"
1019 
     }
1020 
     LINE  2, 0, 0
1021 
     {
1022 
      POINTS ( (-20,0), (0,0) )
1023 
     }
1024 
    }
1025 
    PIN  18, 0, 0
1026 
    {
1027 
     COORD (280,320)
1028 
     VARIABLES
1029 
     {
1030 
      #DIRECTION="OUT"
1031 
      #DOWNTO="1"
1032 
      #LENGTH="20"
1033 
      #MDA_RECORD_TOKEN="OTHER"
1034 
      #NAME="muxb_ctl(1:0)"
1035 
      #NUMBER="0"
1036 
      #VERILOG_TYPE="reg"
1037 
     }
1038 
     LINE  2, 0, 0
1039 
     {
1040 
      POINTS ( (-20,0), (0,0) )
1041 
     }
1042 
    }
1043 
    PIN  20, 0, 0
1044 
    {
1045 
     COORD (280,360)
1046 
     VARIABLES
1047 
     {
1048 
      #DIRECTION="OUT"
1049 
      #DOWNTO="1"
1050 
      #LENGTH="20"
1051 
      #MDA_RECORD_TOKEN="OTHER"
1052 
      #NAME="pc_gen_ctl(2:0)"
1053 
      #NUMBER="0"
1054 
      #VERILOG_TYPE="reg"
1055 
     }
1056 
     LINE  2, 0, 0
1057 
     {
1058 
      POINTS ( (-20,0), (0,0) )
1059 
     }
1060 
    }
1061 
    PIN  22, 0, 0
1062 
    {
1063 
     COORD (280,400)
1064 
     VARIABLES
1065 
     {
1066 
      #DIRECTION="OUT"
1067 
      #DOWNTO="1"
1068 
      #LENGTH="20"
1069 
      #MDA_RECORD_TOKEN="OTHER"
1070 
      #NAME="rd_sel(1:0)"
1071 
      #NUMBER="0"
1072 
      #VERILOG_TYPE="reg"
1073 
     }
1074 
     LINE  2, 0, 0
1075 
     {
1076 
      POINTS ( (-20,0), (0,0) )
1077 
     }
1078 
    }
1079 
    PIN  24, 0, 0
1080 
    {
1081 
     COORD (280,440)
1082 
     VARIABLES
1083 
     {
1084 
      #DIRECTION="OUT"
1085 
      #DOWNTO="1"
1086 
      #LENGTH="20"
1087 
      #MDA_RECORD_TOKEN="OTHER"
1088 
      #NAME="wb_mux(0:0)"
1089 
      #NUMBER="0"
1090 
      #VERILOG_TYPE="reg"
1091 
     }
1092 
     LINE  2, 0, 0
1093 
     {
1094 
      POINTS ( (-20,0), (0,0) )
1095 
     }
1096 
    }
1097 
    PIN  26, 0, 0
1098 
    {
1099 
     COORD (280,480)
1100 
     VARIABLES
1101 
     {
1102 
      #DIRECTION="OUT"
1103 
      #DOWNTO="1"
1104 
      #LENGTH="20"
1105 
      #MDA_RECORD_TOKEN="OTHER"
1106 
      #NAME="wb_we(0:0)"
1107 
      #NUMBER="0"
1108 
      #VERILOG_TYPE="reg"
1109 
     }
1110 
     LINE  2, 0, 0
1111 
     {
1112 
      POINTS ( (-20,0), (0,0) )
1113 
     }
1114 
    }
1115 
   }
1116 
  }
1117 
 }
1118 
}
1119 
 
1120 
PAGE ""
1121 
{
1122 
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1123 
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1124 
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1125 
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1126 
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1127 
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1128 
 
1129 
 BODY
1130 
 {
1131 
  INSTANCE  99, 0, 0
1132 
  {
1133 
   VARIABLES
1134 
   {
1135 
    #COMPONENT="BusInput"
1136 
    #LIBRARY="#terminals"
1137 
    #REFERENCE="ins_i(31:0)"
1138 
    #SYMBOL="BusInput"
1139 
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1140 
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1141 
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1142 
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1143 
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1144 
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1145 
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1146 
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1147 
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1148 
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1149 
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1150 
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1151 
  INSTANCE  566, 0, 0
1152 
  {
1153 
   VARIABLES
1154 
   {
1155 
    #COMPONENT="Input"
1156 
    #LIBRARY="#terminals"
1157 
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1158 
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1159 
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1160 
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1161 
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1162 
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1163 
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1164 
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1165 
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1166 
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1167 
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1168 
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1169 
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1170 
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1171 
  INSTANCE  632, 0, 0
1172 
  {
1173 
   VARIABLES
1174 
   {
1175 
    #COMPONENT="BusOutput"
1176 
    #LIBRARY="#terminals"
1177 
    #REFERENCE="alu_func_o(4:0)"
1178 
    #SYMBOL="BusOutput"
1179 
    #VERILOG_TYPE="wire"
1180 
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1181 
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1182 
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1183 
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1184 
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1185 
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1186 
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1187 
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1188 
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1189 
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1190 
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1191 
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1192 
  INSTANCE  637, 0, 0
1193 
  {
1194 
   VARIABLES
1195 
   {
1196 
    #COMPONENT="BusOutput"
1197 
    #LIBRARY="#terminals"
1198 
    #REFERENCE="alu_we_o(0:0)"
1199 
    #SYMBOL="BusOutput"
1200 
    #VERILOG_TYPE="wire"
1201 
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1202 
   COORD (1600,460)
1203 
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1204 
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1205 
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1206 
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1207 
   TEXT "$#REFERENCE"
1208 
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1209 
   ALIGN 4
1210 
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1211 
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1212 
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1213 
  INSTANCE  642, 0, 0
1214 
  {
1215 
   VARIABLES
1216 
   {
1217 
    #COMPONENT="BusOutput"
1218 
    #LIBRARY="#terminals"
1219 
    #REFERENCE="cmp_ctl_o(2:0)"
1220 
    #SYMBOL="BusOutput"
1221 
    #VERILOG_TYPE="wire"
1222 
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1223 
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1224 
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1225 
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1226 
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1227 
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1228 
   TEXT "$#REFERENCE"
1229 
   RECT (1652,483,1892,518)
1230 
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1231 
   MARGINS (1,1)
1232 
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1233 
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1234 
  INSTANCE  647, 0, 0
1235 
  {
1236 
   VARIABLES
1237 
   {
1238 
    #COMPONENT="BusOutput"
1239 
    #LIBRARY="#terminals"
1240 
    #REFERENCE="dmem_ctl_o(3:0)"
1241 
    #SYMBOL="BusOutput"
1242 
    #VERILOG_TYPE="wire"
1243 
   }
1244 
   COORD (1600,540)
1245 
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1246 
  }
1247 
  TEXT  648, 0, 0
1248 
  {
1249 
   TEXT "$#REFERENCE"
1250 
   RECT (1652,523,1909,558)
1251 
   ALIGN 4
1252 
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1253 
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1254 
  }
1255 
  INSTANCE  652, 0, 0
1256 
  {
1257 
   VARIABLES
1258 
   {
1259 
    #COMPONENT="BusOutput"
1260 
    #LIBRARY="#terminals"
1261 
    #REFERENCE="dmem_ctl_ur_o(3:0)"
1262 
    #SYMBOL="BusOutput"
1263 
    #VERILOG_TYPE="wire"
1264 
   }
1265 
   COORD (1600,580)
1266 
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1267 
  }
1268 
  TEXT  653, 0, 0
1269 
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1270 
   TEXT "$#REFERENCE"
1271 
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1272 
   ALIGN 4
1273 
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1274 
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1275 
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1276 
  INSTANCE  657, 0, 0
1277 
  {
1278 
   VARIABLES
1279 
   {
1280 
    #COMPONENT="BusOutput"
1281 
    #LIBRARY="#terminals"
1282 
    #REFERENCE="ext_ctl_o(2:0)"
1283 
    #SYMBOL="BusOutput"
1284 
    #VERILOG_TYPE="wire"
1285 
   }
1286 
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1287 
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1288 
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1289 
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1290 
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1291 
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1292 
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1293 
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1294 
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1295 
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1296 
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1297 
  INSTANCE  662, 0, 0
1298 
  {
1299 
   VARIABLES
1300 
   {
1301 
    #COMPONENT="BusOutput"
1302 
    #LIBRARY="#terminals"
1303 
    #REFERENCE="muxa_ctl_o(1:0)"
1304 
    #SYMBOL="BusOutput"
1305 
    #VERILOG_TYPE="wire"
1306 
   }
1307 
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1308 
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1309 
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1310 
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1311 
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1312 
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1313 
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1314 
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1315 
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1316 
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1317 
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1318 
  INSTANCE  667, 0, 0
1319 
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1320 
   VARIABLES
1321 
   {
1322 
    #COMPONENT="BusOutput"
1323 
    #LIBRARY="#terminals"
1324 
    #REFERENCE="muxb_ctl_o(1:0)"
1325 
    #SYMBOL="BusOutput"
1326 
    #VERILOG_TYPE="wire"
1327 
   }
1328 
   COORD (1600,700)
1329 
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1330 
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1331 
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1332 
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1333 
   TEXT "$#REFERENCE"
1334 
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1335 
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1336 
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1337 
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1338 
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1339 
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1340 
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1341 
   VARIABLES
1342 
   {
1343 
    #COMPONENT="BusOutput"
1344 
    #LIBRARY="#terminals"
1345 
    #REFERENCE="pc_gen_ctl_o(2:0)"
1346 
    #SYMBOL="BusOutput"
1347 
    #VERILOG_TYPE="wire"
1348 
   }
1349 
   COORD (1600,740)
1350 
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1351 
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1352 
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1353 
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1354 
   TEXT "$#REFERENCE"
1355 
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1356 
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1357 
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1358 
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1359 
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1360 
  INSTANCE  677, 0, 0
1361 
  {
1362 
   VARIABLES
1363 
   {
1364 
    #COMPONENT="BusOutput"
1365 
    #LIBRARY="#terminals"
1366 
    #REFERENCE="rd_sel_o(1:0)"
1367 
    #SYMBOL="BusOutput"
1368 
    #VERILOG_TYPE="wire"
1369 
   }
1370 
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1371 
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1372 
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1373 
  TEXT  678, 0, 0
1374 
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1375 
   TEXT "$#REFERENCE"
1376 
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1377 
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1378 
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1379 
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1380 
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1381 
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1382 
  {
1383 
   VARIABLES
1384 
   {
1385 
    #COMPONENT="BusOutput"
1386 
    #LIBRARY="#terminals"
1387 
    #REFERENCE="wb_mux_ctl_o(0:0)"
1388 
    #SYMBOL="BusOutput"
1389 
   }
1390 
   COORD (1600,820)
1391 
   VERTEXES ( (2,4078) )
1392 
  }
1393 
  TEXT  683, 0, 0
1394 
  {
1395 
   TEXT "$#REFERENCE"
1396 
   RECT (1652,803,1943,838)
1397 
   ALIGN 4
1398 
   MARGINS (1,1)
1399 
   PARENT 682
1400 
  }
1401 
  INSTANCE  687, 0, 0
1402 
  {
1403 
   VARIABLES
1404 
   {
1405 
    #COMPONENT="BusOutput"
1406 
    #LIBRARY="#terminals"
1407 
    #REFERENCE="wb_we_o(0:0)"
1408 
    #SYMBOL="BusOutput"
1409 
   }
1410 
   COORD (1600,860)
1411 
   VERTEXES ( (2,4080) )
1412 
  }
1413 
  TEXT  688, 0, 0
1414 
  {
1415 
   TEXT "$#REFERENCE"
1416 
   RECT (1652,843,1858,878)
1417 
   ALIGN 4
1418 
   MARGINS (1,1)
1419 
   PARENT 687
1420 
  }
1421 
  NET BUS  694, 0, 0
1422 
  NET BUS  698, 0, 0
1423 
  NET BUS  702, 0, 0
1424 
  NET BUS  714, 0, 0
1425 
  NET BUS  718, 0, 0
1426 
  NET BUS  722, 0, 0
1427 
  NET BUS  726, 0, 0
1428 
  NET BUS  730, 0, 0
1429 
  NET BUS  734, 0, 0
1430 
  NET BUS  738, 0, 0
1431 
  NET BUS  742, 0, 0
1432 
  NET BUS  750, 0, 0
1433 
  INSTANCE  1260, 0, 0
1434 
  {
1435 
   VARIABLES
1436 
   {
1437 
    #COMPONENT="BusOutput"
1438 
    #LIBRARY="#terminals"
1439 
    #REFERENCE="fsm_dly(2:0)"
1440 
    #SYMBOL="BusOutput"
1441 
   }
1442 
   COORD (1600,1060)
1443 
   VERTEXES ( (2,5812) )
1444 
  }
1445 
  TEXT  1261, 0, 0
1446 
  {
1447 
   TEXT "$#REFERENCE"
1448 
   RECT (1652,1043,1858,1078)
1449 
   ALIGN 4
1450 
   MARGINS (1,1)
1451 
   PARENT 1260
1452 
  }
1453 
  NET BUS  1391, 0, 0
1454 
  NET WIRE  2028, 0, 0
1455 
  NET BUS  2040, 0, 0
1456 
  NET BUS  2048, 0, 0
1457 
  NET BUS  2056, 0, 0
1458 
  NET BUS  2064, 0, 0
1459 
  NET BUS  2072, 0, 0
1460 
  NET BUS  2086, 0, 0
1461 
  NET BUS  2094, 0, 0
1462 
  NET BUS  2102, 0, 0
1463 
  NET BUS  2110, 0, 0
1464 
  NET BUS  2118, 0, 0
1465 
  NET BUS  2126, 0, 0
1466 
  INSTANCE  2216, 0, 0
1467 
  {
1468 
   VARIABLES
1469 
   {
1470 
    #COMPONENT="pipelinedregs"
1471 
    #LIBRARY="#default"
1472 
    #REFERENCE="pipereg"
1473 
    #SYMBOL="pipelinedregs"
1474 
   }
1475 
   COORD (1160,380)
1476 
   VERTEXES ( (26,4054), (30,4055), (46,4036), (4,4057), (8,4059), (12,4061), (16,4063), (20,4065), (24,4067), (28,4069), (32,4071), (36,4073), (40,4075), (44,4077), (48,4079), (10,5361), (2,5802), (6,5804), (18,5808), (22,5810), (34,5814), (38,5816), (42,5919), (50,5927), (52,5948), (54,5976), (14,5983) )
1477 
  }
1478 
  TEXT  2217, 0, 0
1479 
  {
1480 
   TEXT "$#REFERENCE"
1481 
   RECT (1160,344,1281,379)
1482 
   ALIGN 8
1483 
   MARGINS (1,1)
1484 
   PARENT 2216
1485 
  }
1486 
  TEXT  2221, 0, 0
1487 
  {
1488 
   TEXT "$#COMPONENT"
1489 
   RECT (1160,1020,1383,1055)
1490 
   MARGINS (1,1)
1491 
   PARENT 2216
1492 
  }
1493 
  INSTANCE  2281, 0, 0
1494 
  {
1495 
   VARIABLES
1496 
   {
1497 
    #COMPONENT="Input"
1498 
    #LIBRARY="#terminals"
1499 
    #REFERENCE="id2ra_ctl_clr"
1500 
    #SYMBOL="Input"
1501 
   }
1502 
   COORD (740,1000)
1503 
   VERTEXES ( (2,4053) )
1504 
  }
1505 
  TEXT  2282, 0, 0
1506 
  {
1507 
   TEXT "$#REFERENCE"
1508 
   RECT (466,983,689,1018)
1509 
   ALIGN 6
1510 
   MARGINS (1,1)
1511 
   PARENT 2281
1512 
  }
1513 
  INSTANCE  2286, 0, 0
1514 
  {
1515 
   VARIABLES
1516 
   {
1517 
    #COMPONENT="Input"
1518 
    #LIBRARY="#terminals"
1519 
    #REFERENCE="id2ra_ctl_cls"
1520 
    #SYMBOL="Input"
1521 
   }
1522 
   COORD (740,1040)
1523 
   VERTEXES ( (2,4056) )
1524 
  }
1525 
  TEXT  2287, 0, 0
1526 
  {
1527 
   TEXT "$#REFERENCE"
1528 
   RECT (466,1023,689,1058)
1529 
   ALIGN 6
1530 
   MARGINS (1,1)
1531 
   PARENT 2286
1532 
  }
1533 
  INSTANCE  2291, 0, 0
1534 
  {
1535 
   VARIABLES
1536 
   {
1537 
    #COMPONENT="Input"
1538 
    #LIBRARY="#terminals"
1539 
    #REFERENCE="ra2ex_ctl_clr"
1540 
    #SYMBOL="Input"
1541 
   }
1542 
   COORD (740,1080)
1543 
   VERTEXES ( (2,4035) )
1544 
  }
1545 
  TEXT  2292, 0, 0
1546 
  {
1547 
   TEXT "$#REFERENCE"
1548 
   RECT (466,1063,689,1098)
1549 
   ALIGN 6
1550 
   MARGINS (1,1)
1551 
   PARENT 2291
1552 
  }
1553 
  NET WIRE  2298, 0, 0
1554 
  NET WIRE  2306, 0, 0
1555 
  NET WIRE  2314, 0, 0
1556 
  NET BUS  2344, 0, 0
1557 
  VTX  4035, 0, 0
1558 
  {
1559 
   COORD (740,1080)
1560 
  }
1561 
  VTX  4036, 0, 0
1562 
  {
1563 
   COORD (1160,860)
1564 
  }
1565 
  VTX  4053, 0, 0
1566 
  {
1567 
   COORD (740,1000)
1568 
  }
1569 
  VTX  4054, 0, 0
1570 
  {
1571 
   COORD (1160,660)
1572 
  }
1573 
  VTX  4055, 0, 0
1574 
  {
1575 
   COORD (1160,700)
1576 
  }
1577 
  VTX  4056, 0, 0
1578 
  {
1579 
   COORD (740,1040)
1580 
  }
1581 
  VTX  4057, 0, 0
1582 
  {
1583 
   COORD (1560,420)
1584 
  }
1585 
  VTX  4058, 0, 0
1586 
  {
1587 
   COORD (1600,420)
1588 
  }
1589 
  VTX  4059, 0, 0
1590 
  {
1591 
   COORD (1560,460)
1592 
  }
1593 
  VTX  4060, 0, 0
1594 
  {
1595 
   COORD (1600,460)
1596 
  }
1597 
  VTX  4061, 0, 0
1598 
  {
1599 
   COORD (1560,500)
1600 
  }
1601 
  VTX  4062, 0, 0
1602 
  {
1603 
   COORD (1600,500)
1604 
  }
1605 
  VTX  4063, 0, 0
1606 
  {
1607 
   COORD (1560,540)
1608 
  }
1609 
  VTX  4064, 0, 0
1610 
  {
1611 
   COORD (1600,540)
1612 
  }
1613 
  VTX  4065, 0, 0
1614 
  {
1615 
   COORD (1560,580)
1616 
  }
1617 
  VTX  4066, 0, 0
1618 
  {
1619 
   COORD (1600,580)
1620 
  }
1621 
  VTX  4067, 0, 0
1622 
  {
1623 
   COORD (1560,620)
1624 
  }
1625 
  VTX  4068, 0, 0
1626 
  {
1627 
   COORD (1600,620)
1628 
  }
1629 
  VTX  4069, 0, 0
1630 
  {
1631 
   COORD (1560,660)
1632 
  }
1633 
  VTX  4070, 0, 0
1634 
  {
1635 
   COORD (1600,660)
1636 
  }
1637 
  VTX  4071, 0, 0
1638 
  {
1639 
   COORD (1560,700)
1640 
  }
1641 
  VTX  4072, 0, 0
1642 
  {
1643 
   COORD (1600,700)
1644 
  }
1645 
  VTX  4073, 0, 0
1646 
  {
1647 
   COORD (1560,740)
1648 
  }
1649 
  VTX  4074, 0, 0
1650 
  {
1651 
   COORD (1600,740)
1652 
  }
1653 
  VTX  4075, 0, 0
1654 
  {
1655 
   COORD (1560,780)
1656 
  }
1657 
  VTX  4076, 0, 0
1658 
  {
1659 
   COORD (1600,780)
1660 
  }
1661 
  VTX  4077, 0, 0
1662 
  {
1663 
   COORD (1560,820)
1664 
  }
1665 
  VTX  4078, 0, 0
1666 
  {
1667 
   COORD (1600,820)
1668 
  }
1669 
  VTX  4079, 0, 0
1670 
  {
1671 
   COORD (1560,860)
1672 
  }
1673 
  VTX  4080, 0, 0
1674 
  {
1675 
   COORD (1600,860)
1676 
  }
1677 
  VTX  4090, 0, 0
1678 
  {
1679 
   COORD (980,1080)
1680 
  }
1681 
  WIRE  4091, 0, 0
1682 
  {
1683 
   NET 2314
1684 
   VTX 4035, 4090
1685 
  }
1686 
  VTX  4092, 0, 0
1687 
  {
1688 
   COORD (980,880)
1689 
  }
1690 
  WIRE  4093, 0, 0
1691 
  {
1692 
   NET 2314
1693 
   VTX 4090, 4092
1694 
  }
1695 
  VTX  4094, 0, 0
1696 
  {
1697 
   COORD (1140,880)
1698 
  }
1699 
  WIRE  4095, 0, 0
1700 
  {
1701 
   NET 2314
1702 
   VTX 4092, 4094
1703 
  }
1704 
  VTX  4096, 0, 0
1705 
  {
1706 
   COORD (1140,860)
1707 
  }
1708 
  WIRE  4097, 0, 0
1709 
  {
1710 
   NET 2314
1711 
   VTX 4094, 4096
1712 
  }
1713 
  WIRE  4098, 0, 0
1714 
  {
1715 
   NET 2314
1716 
   VTX 4096, 4036
1717 
  }
1718 
  VTX  4139, 0, 0
1719 
  {
1720 
   COORD (940,1000)
1721 
  }
1722 
  WIRE  4140, 0, 0
1723 
  {
1724 
   NET 2298
1725 
   VTX 4053, 4139
1726 
  }
1727 
  VTX  4141, 0, 0
1728 
  {
1729 
   COORD (940,660)
1730 
  }
1731 
  WIRE  4142, 0, 0
1732 
  {
1733 
   NET 2298
1734 
   VTX 4139, 4141
1735 
  }
1736 
  WIRE  4143, 0, 0
1737 
  {
1738 
   NET 2298
1739 
   VTX 4141, 4054
1740 
  }
1741 
  VTX  4144, 0, 0
1742 
  {
1743 
   COORD (1120,700)
1744 
  }
1745 
  WIRE  4145, 0, 0
1746 
  {
1747 
   NET 2306
1748 
   VTX 4055, 4144
1749 
  }
1750 
  VTX  4146, 0, 0
1751 
  {
1752 
   COORD (1120,720)
1753 
  }
1754 
  WIRE  4147, 0, 0
1755 
  {
1756 
   NET 2306
1757 
   VTX 4144, 4146
1758 
  }
1759 
  VTX  4148, 0, 0
1760 
  {
1761 
   COORD (960,720)
1762 
  }
1763 
  WIRE  4149, 0, 0
1764 
  {
1765 
   NET 2306
1766 
   VTX 4146, 4148
1767 
  }
1768 
  VTX  4150, 0, 0
1769 
  {
1770 
   COORD (960,1040)
1771 
  }
1772 
  WIRE  4151, 0, 0
1773 
  {
1774 
   NET 2306
1775 
   VTX 4148, 4150
1776 
  }
1777 
  WIRE  4152, 0, 0
1778 
  {
1779 
   NET 2306
1780 
   VTX 4150, 4056
1781 
  }
1782 
  BUS  4153, 0, 0
1783 
  {
1784 
   NET 694
1785 
   VTX 4057, 4058
1786 
  }
1787 
  BUS  4154, 0, 0
1788 
  {
1789 
   NET 698
1790 
   VTX 4059, 4060
1791 
  }
1792 
  BUS  4155, 0, 0
1793 
  {
1794 
   NET 702
1795 
   VTX 4061, 4062
1796 
  }
1797 
  BUS  4156, 0, 0
1798 
  {
1799 
   NET 714
1800 
   VTX 4063, 4064
1801 
  }
1802 
  BUS  4157, 0, 0
1803 
  {
1804 
   NET 718
1805 
   VTX 4065, 4066
1806 
  }
1807 
  BUS  4158, 0, 0
1808 
  {
1809 
   NET 722
1810 
   VTX 4067, 4068
1811 
  }
1812 
  BUS  4159, 0, 0
1813 
  {
1814 
   NET 726
1815 
   VTX 4069, 4070
1816 
  }
1817 
  BUS  4160, 0, 0
1818 
  {
1819 
   NET 730
1820 
   VTX 4071, 4072
1821 
  }
1822 
  BUS  4161, 0, 0
1823 
  {
1824 
   NET 734
1825 
   VTX 4073, 4074
1826 
  }
1827 
  BUS  4162, 0, 0
1828 
  {
1829 
   NET 738
1830 
   VTX 4075, 4076
1831 
  }
1832 
  BUS  4163, 0, 0
1833 
  {
1834 
   NET 742
1835 
   VTX 4077, 4078
1836 
  }
1837 
  BUS  4164, 0, 0
1838 
  {
1839 
   NET 750
1840 
   VTX 4079, 4080
1841 
  }
1842 
  VTX  5361, 0, 0
1843 
  {
1844 
   COORD (1160,500)
1845 
  }
1846 
  VTX  5362, 0, 0
1847 
  {
1848 
   COORD (480,360)
1849 
  }
1850 
  VTX  5363, 0, 0
1851 
  {
1852 
   COORD (1040,500)
1853 
  }
1854 
  WIRE  5364, 0, 0
1855 
  {
1856 
   NET 2028
1857 
   VTX 5361, 5363
1858 
  }
1859 
  VTX  5365, 0, 0
1860 
  {
1861 
   COORD (1040,360)
1862 
  }
1863 
  WIRE  5366, 0, 0
1864 
  {
1865 
   NET 2028
1866 
   VTX 5363, 5365
1867 
  }
1868 
  WIRE  5367, 0, 0
1869 
  {
1870 
   NET 2028
1871 
   VTX 5365, 5362
1872 
  }
1873 
  INSTANCE  5632, 0, 0
1874 
  {
1875 
   VARIABLES
1876 
   {
1877 
    #COMPONENT="decoder3"
1878 
    #LIBRARY="#default"
1879 
    #REFERENCE="decoder"
1880 
    #SYMBOL="decoder3"
1881 
   }
1882 
   COORD (500,380)
1883 
   VERTEXES ( (2,5801), (4,5803), (6,5805), (10,5809), (12,5811), (14,5813), (16,5815), (18,5817), (20,5920), (22,5926), (24,5950), (26,5977), (8,5985) )
1884 
  }
1885 
  TEXT  5633, 0, 0
1886 
  {
1887 
   TEXT "$#REFERENCE"
1888 
   RECT (500,344,621,379)
1889 
   ALIGN 8
1890 
   MARGINS (1,1)
1891 
   PARENT 5632
1892 
  }
1893 
  TEXT  5637, 0, 0
1894 
  {
1895 
   TEXT "$#COMPONENT"
1896 
   RECT (500,900,638,935)
1897 
   MARGINS (1,1)
1898 
   PARENT 5632
1899 
  }
1900 
  VTX  5800, 0, 0
1901 
  {
1902 
   COORD (460,460)
1903 
  }
1904 
  VTX  5801, 0, 0
1905 
  {
1906 
   COORD (500,420)
1907 
  }
1908 
  VTX  5802, 0, 0
1909 
  {
1910 
   COORD (1160,420)
1911 
  }
1912 
  VTX  5803, 0, 0
1913 
  {
1914 
   COORD (780,420)
1915 
  }
1916 
  VTX  5804, 0, 0
1917 
  {
1918 
   COORD (1160,460)
1919 
  }
1920 
  VTX  5805, 0, 0
1921 
  {
1922 
   COORD (780,460)
1923 
  }
1924 
  VTX  5808, 0, 0
1925 
  {
1926 
   COORD (1160,580)
1927 
  }
1928 
  VTX  5809, 0, 0
1929 
  {
1930 
   COORD (780,540)
1931 
  }
1932 
  VTX  5810, 0, 0
1933 
  {
1934 
   COORD (1160,620)
1935 
  }
1936 
  VTX  5811, 0, 0
1937 
  {
1938 
   COORD (780,580)
1939 
  }
1940 
  VTX  5812, 0, 0
1941 
  {
1942 
   COORD (1600,1060)
1943 
  }
1944 
  VTX  5813, 0, 0
1945 
  {
1946 
   COORD (780,620)
1947 
  }
1948 
  VTX  5814, 0, 0
1949 
  {
1950 
   COORD (1160,740)
1951 
  }
1952 
  VTX  5815, 0, 0
1953 
  {
1954 
   COORD (780,660)
1955 
  }
1956 
  VTX  5816, 0, 0
1957 
  {
1958 
   COORD (1160,780)
1959 
  }
1960 
  VTX  5817, 0, 0
1961 
  {
1962 
   COORD (780,700)
1963 
  }
1964 
  VTX  5826, 0, 0
1965 
  {
1966 
   COORD (480,460)
1967 
  }
1968 
  BUS  5827, 0, 0
1969 
  {
1970 
   NET 2344
1971 
   VTX 5800, 5826
1972 
  }
1973 
  VTX  5828, 0, 0
1974 
  {
1975 
   COORD (480,420)
1976 
  }
1977 
  BUS  5829, 0, 0
1978 
  {
1979 
   NET 2344
1980 
   VTX 5826, 5828
1981 
  }
1982 
  BUS  5830, 0, 0
1983 
  {
1984 
   NET 2344
1985 
   VTX 5828, 5801
1986 
  }
1987 
  BUS  5831, 0, 0
1988 
  {
1989 
   NET 2040
1990 
   VTX 5802, 5803
1991 
  }
1992 
  BUS  5832, 0, 0
1993 
  {
1994 
   NET 2048
1995 
   VTX 5804, 5805
1996 
  }
1997 
  VTX  5842, 0, 0
1998 
  {
1999 
   COORD (1060,580)
2000 
  }
2001 
  BUS  5843, 0, 0
2002 
  {
2003 
   NET 2064
2004 
   VTX 5808, 5842
2005 
  }
2006 
  VTX  5844, 0, 0
2007 
  {
2008 
   COORD (1060,540)
2009 
  }
2010 
  BUS  5845, 0, 0
2011 
  {
2012 
   NET 2064
2013 
   VTX 5842, 5844
2014 
  }
2015 
  BUS  5846, 0, 0
2016 
  {
2017 
   NET 2064
2018 
   VTX 5844, 5809
2019 
  }
2020 
  VTX  5847, 0, 0
2021 
  {
2022 
   COORD (1040,620)
2023 
  }
2024 
  BUS  5848, 0, 0
2025 
  {
2026 
   NET 2072
2027 
   VTX 5810, 5847
2028 
  }
2029 
  VTX  5849, 0, 0
2030 
  {
2031 
   COORD (1040,580)
2032 
  }
2033 
  BUS  5850, 0, 0
2034 
  {
2035 
   NET 2072
2036 
   VTX 5847, 5849
2037 
  }
2038 
  BUS  5851, 0, 0
2039 
  {
2040 
   NET 2072
2041 
   VTX 5849, 5811
2042 
  }
2043 
  VTX  5852, 0, 0
2044 
  {
2045 
   COORD (1020,1060)
2046 
  }
2047 
  BUS  5853, 0, 0
2048 
  {
2049 
   NET 1391
2050 
   VTX 5812, 5852
2051 
  }
2052 
  VTX  5854, 0, 0
2053 
  {
2054 
   COORD (1020,620)
2055 
  }
2056 
  BUS  5855, 0, 0
2057 
  {
2058 
   NET 1391
2059 
   VTX 5852, 5854
2060 
  }
2061 
  BUS  5856, 0, 0
2062 
  {
2063 
   NET 1391
2064 
   VTX 5854, 5813
2065 
  }
2066 
  VTX  5857, 0, 0
2067 
  {
2068 
   COORD (920,740)
2069 
  }
2070 
  BUS  5858, 0, 0
2071 
  {
2072 
   NET 2086
2073 
   VTX 5814, 5857
2074 
  }
2075 
  VTX  5859, 0, 0
2076 
  {
2077 
   COORD (920,660)
2078 
  }
2079 
  BUS  5860, 0, 0
2080 
  {
2081 
   NET 2086
2082 
   VTX 5857, 5859
2083 
  }
2084 
  BUS  5861, 0, 0
2085 
  {
2086 
   NET 2086
2087 
   VTX 5859, 5815
2088 
  }
2089 
  VTX  5862, 0, 0
2090 
  {
2091 
   COORD (900,780)
2092 
  }
2093 
  BUS  5863, 0, 0
2094 
  {
2095 
   NET 2094
2096 
   VTX 5816, 5862
2097 
  }
2098 
  VTX  5864, 0, 0
2099 
  {
2100 
   COORD (900,700)
2101 
  }
2102 
  BUS  5865, 0, 0
2103 
  {
2104 
   NET 2094
2105 
   VTX 5862, 5864
2106 
  }
2107 
  BUS  5866, 0, 0
2108 
  {
2109 
   NET 2094
2110 
   VTX 5864, 5817
2111 
  }
2112 
  VTX  5919, 0, 0
2113 
  {
2114 
   COORD (1160,820)
2115 
  }
2116 
  VTX  5920, 0, 0
2117 
  {
2118 
   COORD (780,740)
2119 
  }
2120 
  VTX  5921, 0, 0
2121 
  {
2122 
   COORD (880,820)
2123 
  }
2124 
  BUS  5922, 0, 0
2125 
  {
2126 
   NET 2102
2127 
   VTX 5919, 5921
2128 
  }
2129 
  VTX  5923, 0, 0
2130 
  {
2131 
   COORD (880,740)
2132 
  }
2133 
  BUS  5924, 0, 0
2134 
  {
2135 
   NET 2102
2136 
   VTX 5921, 5923
2137 
  }
2138 
  BUS  5925, 0, 0
2139 
  {
2140 
   NET 2102
2141 
   VTX 5923, 5920
2142 
  }
2143 
  VTX  5926, 0, 0
2144 
  {
2145 
   COORD (780,780)
2146 
  }
2147 
  VTX  5927, 0, 0
2148 
  {
2149 
   COORD (1160,900)
2150 
  }
2151 
  VTX  5928, 0, 0
2152 
  {
2153 
   COORD (840,780)
2154 
  }
2155 
  BUS  5929, 0, 0
2156 
  {
2157 
   NET 2110
2158 
   VTX 5926, 5928
2159 
  }
2160 
  VTX  5930, 0, 0
2161 
  {
2162 
   COORD (840,840)
2163 
  }
2164 
  BUS  5931, 0, 0
2165 
  {
2166 
   NET 2110
2167 
   VTX 5928, 5930
2168 
  }
2169 
  VTX  5932, 0, 0
2170 
  {
2171 
   COORD (1120,840)
2172 
  }
2173 
  BUS  5933, 0, 0
2174 
  {
2175 
   NET 2110
2176 
   VTX 5930, 5932
2177 
  }
2178 
  VTX  5934, 0, 0
2179 
  {
2180 
   COORD (1120,900)
2181 
  }
2182 
  BUS  5935, 0, 0
2183 
  {
2184 
   NET 2110
2185 
   VTX 5932, 5934
2186 
  }
2187 
  BUS  5936, 0, 0
2188 
  {
2189 
   NET 2110
2190 
   VTX 5934, 5927
2191 
  }
2192 
  VTX  5948, 0, 0
2193 
  {
2194 
   COORD (1160,940)
2195 
  }
2196 
  VTX  5950, 0, 0
2197 
  {
2198 
   COORD (780,820)
2199 
  }
2200 
  VTX  5951, 0, 0
2201 
  {
2202 
   COORD (860,940)
2203 
  }
2204 
  BUS  5952, 0, 0
2205 
  {
2206 
   NET 2118
2207 
   VTX 5948, 5951
2208 
  }
2209 
  VTX  5953, 0, 0
2210 
  {
2211 
   COORD (860,860)
2212 
  }
2213 
  BUS  5954, 0, 0
2214 
  {
2215 
   NET 2118
2216 
   VTX 5951, 5953
2217 
  }
2218 
  VTX  5956, 0, 0
2219 
  {
2220 
   COORD (820,820)
2221 
  }
2222 
  BUS  5957, 0, 0
2223 
  {
2224 
   NET 2118
2225 
   VTX 5950, 5956
2226 
  }
2227 
  VTX  5958, 0, 0
2228 
  {
2229 
   COORD (820,860)
2230 
  }
2231 
  BUS  5959, 0, 0
2232 
  {
2233 
   NET 2118
2234 
   VTX 5956, 5958
2235 
  }
2236 
  BUS  5961, 0, 0
2237 
  {
2238 
   NET 2118
2239 
   VTX 5953, 5958
2240 
  }
2241 
  VTX  5976, 0, 0
2242 
  {
2243 
   COORD (1160,980)
2244 
  }
2245 
  VTX  5977, 0, 0
2246 
  {
2247 
   COORD (780,860)
2248 
  }
2249 
  VTX  5978, 0, 0
2250 
  {
2251 
   COORD (800,980)
2252 
  }
2253 
  BUS  5979, 0, 0
2254 
  {
2255 
   NET 2126
2256 
   VTX 5976, 5978
2257 
  }
2258 
  VTX  5980, 0, 0
2259 
  {
2260 
   COORD (800,860)
2261 
  }
2262 
  BUS  5981, 0, 0
2263 
  {
2264 
   NET 2126
2265 
   VTX 5978, 5980
2266 
  }
2267 
  BUS  5982, 0, 0
2268 
  {
2269 
   NET 2126
2270 
   VTX 5980, 5977
2271 
  }
2272 
  VTX  5983, 0, 0
2273 
  {
2274 
   COORD (1160,540)
2275 
  }
2276 
  VTX  5984, 0, 0
2277 
  {
2278 
   COORD (900,500)
2279 
  }
2280 
  VTX  5985, 0, 0
2281 
  {
2282 
   COORD (780,500)
2283 
  }
2284 
  VTX  5986, 0, 0
2285 
  {
2286 
   COORD (1080,540)
2287 
  }
2288 
  BUS  5987, 0, 0
2289 
  {
2290 
   NET 2056
2291 
   VTX 5983, 5986
2292 
  }
2293 
  VTX  5988, 0, 0
2294 
  {
2295 
   COORD (1080,520)
2296 
  }
2297 
  BUS  5989, 0, 0
2298 
  {
2299 
   NET 2056
2300 
   VTX 5986, 5988
2301 
  }
2302 
  VTX  5990, 0, 0
2303 
  {
2304 
   COORD (900,520)
2305 
  }
2306 
  BUS  5991, 0, 0
2307 
  {
2308 
   NET 2056
2309 
   VTX 5988, 5990
2310 
  }
2311 
  BUS  5992, 0, 0
2312 
  {
2313 
   NET 2056
2314 
   VTX 5990, 5984
2315 
  }
2316 
  BUS  5993, 0, 0
2317 
  {
2318 
   NET 2056
2319 
   VTX 5985, 5984
2320 
  }
2321 
 }
2322 
 
2323 
}
2324 
 
2325 
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2570 
 

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