OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [dbe/] [exec_stage.BDE] - Blame information for rev 59

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 3044
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="exec_stage1"
12 
  AUTHOR="liwei"
13 
  COMPANY="PKU"
14 
  CREATIONDATE="2007-8-4"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "big_alu" "big_alu"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1186224868"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,360,380)
33 
    FREEID 17
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,340,380)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,30,104,54)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (289,30,335,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (25,70,104,94)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    TEXT  9, 0, 0
71 
    {
72 
     TEXT "$#NAME"
73 
     RECT (256,70,335,94)
74 
     ALIGN 6
75 
     MARGINS (1,1)
76 
     PARENT 8
77 
    }
78 
    TEXT  11, 0, 0
79 
    {
80 
     TEXT "$#NAME"
81 
     RECT (25,110,60,134)
82 
     ALIGN 4
83 
     MARGINS (1,1)
84 
     PARENT 10
85 
    }
86 
    TEXT  13, 0, 0
87 
    {
88 
     TEXT "$#NAME"
89 
     RECT (25,150,115,174)
90 
     ALIGN 4
91 
     MARGINS (1,1)
92 
     PARENT 12
93 
    }
94 
    TEXT  15, 0, 0
95 
    {
96 
     TEXT "$#NAME"
97 
     RECT (25,190,60,214)
98 
     ALIGN 4
99 
     MARGINS (1,1)
100 
     PARENT 14
101 
    }
102 
    PIN  2, 0, 0
103 
    {
104 
     COORD (0,40)
105 
     VARIABLES
106 
     {
107 
      #DIRECTION="IN"
108 
      #DOWNTO="1"
109 
      #LENGTH="20"
110 
      #MDA_RECORD_TOKEN="OTHER"
111 
      #NAME="a(31:0)"
112 
      #NUMBER="0"
113 
      #VERILOG_TYPE="wire"
114 
     }
115 
     LINE  2, 0, 0
116 
     {
117 
      POINTS ( (0,0), (20,0) )
118 
     }
119 
    }
120 
    PIN  4, 0, 0
121 
    {
122 
     COORD (360,40)
123 
     VARIABLES
124 
     {
125 
      #DIRECTION="OUT"
126 
      #LENGTH="20"
127 
      #MDA_RECORD_TOKEN="OTHER"
128 
      #NAME="busy"
129 
      #NUMBER="0"
130 
      #VERILOG_TYPE="wire"
131 
     }
132 
     LINE  2, 0, 0
133 
     {
134 
      POINTS ( (-20,0), (0,0) )
135 
     }
136 
    }
137 
    PIN  6, 0, 0
138 
    {
139 
     COORD (0,80)
140 
     VARIABLES
141 
     {
142 
      #DIRECTION="IN"
143 
      #DOWNTO="1"
144 
      #LENGTH="20"
145 
      #MDA_RECORD_TOKEN="OTHER"
146 
      #NAME="b(31:0)"
147 
      #NUMBER="0"
148 
      #VERILOG_TYPE="wire"
149 
     }
150 
     LINE  2, 0, 0
151 
     {
152 
      POINTS ( (0,0), (20,0) )
153 
     }
154 
    }
155 
    PIN  8, 0, 0
156 
    {
157 
     COORD (360,80)
158 
     VARIABLES
159 
     {
160 
      #DIRECTION="OUT"
161 
      #DOWNTO="1"
162 
      #LENGTH="20"
163 
      #MDA_RECORD_TOKEN="OTHER"
164 
      #NAME="c(31:0)"
165 
      #NUMBER="0"
166 
      #VERILOG_TYPE="wire"
167 
     }
168 
     LINE  2, 0, 0
169 
     {
170 
      POINTS ( (-20,0), (0,0) )
171 
     }
172 
    }
173 
    PIN  10, 0, 0
174 
    {
175 
     COORD (0,120)
176 
     VARIABLES
177 
     {
178 
      #DIRECTION="IN"
179 
      #LENGTH="20"
180 
      #MDA_RECORD_TOKEN="OTHER"
181 
      #NAME="clk"
182 
      #NUMBER="0"
183 
      #VERILOG_TYPE="wire"
184 
     }
185 
     LINE  2, 0, 0
186 
     {
187 
      POINTS ( (0,0), (20,0) )
188 
     }
189 
    }
190 
    PIN  12, 0, 0
191 
    {
192 
     COORD (0,160)
193 
     VARIABLES
194 
     {
195 
      #DIRECTION="IN"
196 
      #DOWNTO="1"
197 
      #LENGTH="20"
198 
      #MDA_RECORD_TOKEN="OTHER"
199 
      #NAME="ctl(4:0)"
200 
      #NUMBER="0"
201 
      #VERILOG_TYPE="wire"
202 
     }
203 
     LINE  2, 0, 0
204 
     {
205 
      POINTS ( (0,0), (20,0) )
206 
     }
207 
    }
208 
    PIN  14, 0, 0
209 
    {
210 
     COORD (0,200)
211 
     VARIABLES
212 
     {
213 
      #DIRECTION="IN"
214 
      #LENGTH="20"
215 
      #MDA_RECORD_TOKEN="OTHER"
216 
      #NAME="rst"
217 
      #NUMBER="0"
218 
      #VERILOG_TYPE="wire"
219 
     }
220 
     LINE  2, 0, 0
221 
     {
222 
      POINTS ( (0,0), (20,0) )
223 
     }
224 
    }
225 
   }
226 
  }
227 
 }
228 
 SYMBOL "#default" "alu_muxa" "alu_muxa"
229 
 {
230 
  HEADER
231 
  {
232 
   VARIABLES
233 
   {
234 
    #DESCRIPTION=""
235 
    #LANGUAGE="VERILOG"
236 
    #MODIFIED="1186224887"
237 
   }
238 
  }
239 
  PAGE ""
240 
  {
241 
   PAGEHEADER
242 
   {
243 
    RECT (0,0,280,360)
244 
    FREEID 21
245 
   }
246 
 
247 
   BODY
248 
   {
249 
    RECT  1, -1, 0
250 
    {
251 
     VARIABLES
252 
     {
253 
      #OUTLINE_FILLING="1"
254 
     }
255 
     AREA (20,0,260,360)
256 
    }
257 
    TEXT  3, 0, 0
258 
    {
259 
     TEXT "$#NAME"
260 
     RECT (25,30,115,54)
261 
     ALIGN 4
262 
     MARGINS (1,1)
263 
     PARENT 2
264 
    }
265 
    TEXT  5, 0, 0
266 
    {
267 
     TEXT "$#NAME"
268 
     RECT (154,30,255,54)
269 
     ALIGN 6
270 
     MARGINS (1,1)
271 
     PARENT 4
272 
    }
273 
    TEXT  7, 0, 0
274 
    {
275 
     TEXT "$#NAME"
276 
     RECT (25,70,126,94)
277 
     ALIGN 4
278 
     MARGINS (1,1)
279 
     PARENT 6
280 
    }
281 
    TEXT  9, 0, 0
282 
    {
283 
     TEXT "$#NAME"
284 
     RECT (25,110,159,134)
285 
     ALIGN 4
286 
     MARGINS (1,1)
287 
     PARENT 8
288 
    }
289 
    TEXT  11, 0, 0
290 
    {
291 
     TEXT "$#NAME"
292 
     RECT (25,150,148,174)
293 
     ALIGN 4
294 
     MARGINS (1,1)
295 
     PARENT 10
296 
    }
297 
    TEXT  13, 0, 0
298 
    {
299 
     TEXT "$#NAME"
300 
     RECT (25,190,159,214)
301 
     ALIGN 4
302 
     MARGINS (1,1)
303 
     PARENT 12
304 
    }
305 
    TEXT  15, 0, 0
306 
    {
307 
     TEXT "$#NAME"
308 
     RECT (25,230,115,254)
309 
     ALIGN 4
310 
     MARGINS (1,1)
311 
     PARENT 14
312 
    }
313 
    TEXT  17, 0, 0
314 
    {
315 
     TEXT "$#NAME"
316 
     RECT (25,270,115,294)
317 
     ALIGN 4
318 
     MARGINS (1,1)
319 
     PARENT 16
320 
    }
321 
    TEXT  19, 0, 0
322 
    {
323 
     TEXT "$#NAME"
324 
     RECT (25,310,126,334)
325 
     ALIGN 4
326 
     MARGINS (1,1)
327 
     PARENT 18
328 
    }
329 
    PIN  2, 0, 0
330 
    {
331 
     COORD (0,40)
332 
     VARIABLES
333 
     {
334 
      #DIRECTION="IN"
335 
      #DOWNTO="1"
336 
      #LENGTH="20"
337 
      #MDA_RECORD_TOKEN="OTHER"
338 
      #NAME="ctl(1:0)"
339 
      #NUMBER="0"
340 
      #VERILOG_TYPE="wire"
341 
     }
342 
     LINE  2, 0, 0
343 
     {
344 
      POINTS ( (0,0), (20,0) )
345 
     }
346 
    }
347 
    PIN  4, 0, 0
348 
    {
349 
     COORD (280,40)
350 
     VARIABLES
351 
     {
352 
      #DIRECTION="OUT"
353 
      #DOWNTO="1"
354 
      #LENGTH="20"
355 
      #MDA_RECORD_TOKEN="OTHER"
356 
      #NAME="a_o(31:0)"
357 
      #NUMBER="0"
358 
      #VERILOG_TYPE="reg"
359 
     }
360 
     LINE  2, 0, 0
361 
     {
362 
      POINTS ( (-20,0), (0,0) )
363 
     }
364 
    }
365 
    PIN  6, 0, 0
366 
    {
367 
     COORD (0,80)
368 
     VARIABLES
369 
     {
370 
      #DIRECTION="IN"
371 
      #DOWNTO="1"
372 
      #LENGTH="20"
373 
      #MDA_RECORD_TOKEN="OTHER"
374 
      #NAME="ext(31:0)"
375 
      #NUMBER="0"
376 
      #VERILOG_TYPE="wire"
377 
     }
378 
     LINE  2, 0, 0
379 
     {
380 
      POINTS ( (0,0), (20,0) )
381 
     }
382 
    }
383 
    PIN  8, 0, 0
384 
    {
385 
     COORD (0,120)
386 
     VARIABLES
387 
     {
388 
      #DIRECTION="IN"
389 
      #DOWNTO="1"
390 
      #LENGTH="20"
391 
      #MDA_RECORD_TOKEN="OTHER"
392 
      #NAME="fw_alu(31:0)"
393 
      #NUMBER="0"
394 
      #VERILOG_TYPE="wire"
395 
     }
396 
     LINE  2, 0, 0
397 
     {
398 
      POINTS ( (0,0), (20,0) )
399 
     }
400 
    }
401 
    PIN  10, 0, 0
402 
    {
403 
     COORD (0,160)
404 
     VARIABLES
405 
     {
406 
      #DIRECTION="IN"
407 
      #DOWNTO="1"
408 
      #LENGTH="20"
409 
      #MDA_RECORD_TOKEN="OTHER"
410 
      #NAME="fw_ctl(2:0)"
411 
      #NUMBER="0"
412 
      #VERILOG_TYPE="wire"
413 
     }
414 
     LINE  2, 0, 0
415 
     {
416 
      POINTS ( (0,0), (20,0) )
417 
     }
418 
    }
419 
    PIN  12, 0, 0
420 
    {
421 
     COORD (0,200)
422 
     VARIABLES
423 
     {
424 
      #DIRECTION="IN"
425 
      #DOWNTO="1"
426 
      #LENGTH="20"
427 
      #MDA_RECORD_TOKEN="OTHER"
428 
      #NAME="fw_mem(31:0)"
429 
      #NUMBER="0"
430 
      #VERILOG_TYPE="wire"
431 
     }
432 
     LINE  2, 0, 0
433 
     {
434 
      POINTS ( (0,0), (20,0) )
435 
     }
436 
    }
437 
    PIN  14, 0, 0
438 
    {
439 
     COORD (0,240)
440 
     VARIABLES
441 
     {
442 
      #DIRECTION="IN"
443 
      #DOWNTO="1"
444 
      #LENGTH="20"
445 
      #MDA_RECORD_TOKEN="OTHER"
446 
      #NAME="pc(31:0)"
447 
      #NUMBER="0"
448 
      #VERILOG_TYPE="wire"
449 
     }
450 
     LINE  2, 0, 0
451 
     {
452 
      POINTS ( (0,0), (20,0) )
453 
     }
454 
    }
455 
    PIN  16, 0, 0
456 
    {
457 
     COORD (0,280)
458 
     VARIABLES
459 
     {
460 
      #DIRECTION="IN"
461 
      #DOWNTO="1"
462 
      #LENGTH="20"
463 
      #MDA_RECORD_TOKEN="OTHER"
464 
      #NAME="rs(31:0)"
465 
      #NUMBER="0"
466 
      #VERILOG_TYPE="wire"
467 
     }
468 
     LINE  2, 0, 0
469 
     {
470 
      POINTS ( (0,0), (20,0) )
471 
     }
472 
    }
473 
    PIN  18, 0, 0
474 
    {
475 
     COORD (0,320)
476 
     VARIABLES
477 
     {
478 
      #DIRECTION="IN"
479 
      #DOWNTO="1"
480 
      #LENGTH="20"
481 
      #MDA_RECORD_TOKEN="OTHER"
482 
      #NAME="spc(31:0)"
483 
      #NUMBER="0"
484 
      #VERILOG_TYPE="wire"
485 
     }
486 
     LINE  2, 0, 0
487 
     {
488 
      POINTS ( (0,0), (20,0) )
489 
     }
490 
    }
491 
   }
492 
  }
493 
 }
494 
 SYMBOL "#default" "alu_muxb" "alu_muxb"
495 
 {
496 
  HEADER
497 
  {
498 
   VARIABLES
499 
   {
500 
    #DESCRIPTION=""
501 
    #LANGUAGE="VERILOG"
502 
    #MODIFIED="1186224897"
503 
   }
504 
  }
505 
  PAGE ""
506 
  {
507 
   PAGEHEADER
508 
   {
509 
    RECT (0,0,280,280)
510 
    FREEID 17
511 
   }
512 
 
513 
   BODY
514 
   {
515 
    RECT  1, -1, 0
516 
    {
517 
     VARIABLES
518 
     {
519 
      #OUTLINE_FILLING="1"
520 
     }
521 
     AREA (20,0,260,280)
522 
    }
523 
    TEXT  3, 0, 0
524 
    {
525 
     TEXT "$#NAME"
526 
     RECT (25,30,115,54)
527 
     ALIGN 4
528 
     MARGINS (1,1)
529 
     PARENT 2
530 
    }
531 
    TEXT  5, 0, 0
532 
    {
533 
     TEXT "$#NAME"
534 
     RECT (154,30,255,54)
535 
     ALIGN 6
536 
     MARGINS (1,1)
537 
     PARENT 4
538 
    }
539 
    TEXT  7, 0, 0
540 
    {
541 
     TEXT "$#NAME"
542 
     RECT (25,70,126,94)
543 
     ALIGN 4
544 
     MARGINS (1,1)
545 
     PARENT 6
546 
    }
547 
    TEXT  9, 0, 0
548 
    {
549 
     TEXT "$#NAME"
550 
     RECT (25,110,159,134)
551 
     ALIGN 4
552 
     MARGINS (1,1)
553 
     PARENT 8
554 
    }
555 
    TEXT  11, 0, 0
556 
    {
557 
     TEXT "$#NAME"
558 
     RECT (25,150,148,174)
559 
     ALIGN 4
560 
     MARGINS (1,1)
561 
     PARENT 10
562 
    }
563 
    TEXT  13, 0, 0
564 
    {
565 
     TEXT "$#NAME"
566 
     RECT (25,190,159,214)
567 
     ALIGN 4
568 
     MARGINS (1,1)
569 
     PARENT 12
570 
    }
571 
    TEXT  15, 0, 0
572 
    {
573 
     TEXT "$#NAME"
574 
     RECT (25,230,115,254)
575 
     ALIGN 4
576 
     MARGINS (1,1)
577 
     PARENT 14
578 
    }
579 
    PIN  2, 0, 0
580 
    {
581 
     COORD (0,40)
582 
     VARIABLES
583 
     {
584 
      #DIRECTION="IN"
585 
      #DOWNTO="1"
586 
      #LENGTH="20"
587 
      #MDA_RECORD_TOKEN="OTHER"
588 
      #NAME="ctl(1:0)"
589 
      #NUMBER="0"
590 
      #VERILOG_TYPE="wire"
591 
     }
592 
     LINE  2, 0, 0
593 
     {
594 
      POINTS ( (0,0), (20,0) )
595 
     }
596 
    }
597 
    PIN  4, 0, 0
598 
    {
599 
     COORD (280,40)
600 
     VARIABLES
601 
     {
602 
      #DIRECTION="OUT"
603 
      #DOWNTO="1"
604 
      #LENGTH="20"
605 
      #MDA_RECORD_TOKEN="OTHER"
606 
      #NAME="b_o(31:0)"
607 
      #NUMBER="0"
608 
      #VERILOG_TYPE="reg"
609 
     }
610 
     LINE  2, 0, 0
611 
     {
612 
      POINTS ( (-20,0), (0,0) )
613 
     }
614 
    }
615 
    PIN  6, 0, 0
616 
    {
617 
     COORD (0,80)
618 
     VARIABLES
619 
     {
620 
      #DIRECTION="IN"
621 
      #DOWNTO="1"
622 
      #LENGTH="20"
623 
      #MDA_RECORD_TOKEN="OTHER"
624 
      #NAME="ext(31:0)"
625 
      #NUMBER="0"
626 
      #VERILOG_TYPE="wire"
627 
     }
628 
     LINE  2, 0, 0
629 
     {
630 
      POINTS ( (0,0), (20,0) )
631 
     }
632 
    }
633 
    PIN  8, 0, 0
634 
    {
635 
     COORD (0,120)
636 
     VARIABLES
637 
     {
638 
      #DIRECTION="IN"
639 
      #DOWNTO="1"
640 
      #LENGTH="20"
641 
      #MDA_RECORD_TOKEN="OTHER"
642 
      #NAME="fw_alu(31:0)"
643 
      #NUMBER="0"
644 
      #VERILOG_TYPE="wire"
645 
     }
646 
     LINE  2, 0, 0
647 
     {
648 
      POINTS ( (0,0), (20,0) )
649 
     }
650 
    }
651 
    PIN  10, 0, 0
652 
    {
653 
     COORD (0,160)
654 
     VARIABLES
655 
     {
656 
      #DIRECTION="IN"
657 
      #DOWNTO="1"
658 
      #LENGTH="20"
659 
      #MDA_RECORD_TOKEN="OTHER"
660 
      #NAME="fw_ctl(2:0)"
661 
      #NUMBER="0"
662 
      #VERILOG_TYPE="wire"
663 
     }
664 
     LINE  2, 0, 0
665 
     {
666 
      POINTS ( (0,0), (20,0) )
667 
     }
668 
    }
669 
    PIN  12, 0, 0
670 
    {
671 
     COORD (0,200)
672 
     VARIABLES
673 
     {
674 
      #DIRECTION="IN"
675 
      #DOWNTO="1"
676 
      #LENGTH="20"
677 
      #MDA_RECORD_TOKEN="OTHER"
678 
      #NAME="fw_mem(31:0)"
679 
      #NUMBER="0"
680 
      #VERILOG_TYPE="wire"
681 
     }
682 
     LINE  2, 0, 0
683 
     {
684 
      POINTS ( (0,0), (20,0) )
685 
     }
686 
    }
687 
    PIN  14, 0, 0
688 
    {
689 
     COORD (0,240)
690 
     VARIABLES
691 
     {
692 
      #DIRECTION="IN"
693 
      #DOWNTO="1"
694 
      #LENGTH="20"
695 
      #MDA_RECORD_TOKEN="OTHER"
696 
      #NAME="rt(31:0)"
697 
      #NUMBER="0"
698 
      #VERILOG_TYPE="wire"
699 
     }
700 
     LINE  2, 0, 0
701 
     {
702 
      POINTS ( (0,0), (20,0) )
703 
     }
704 
    }
705 
   }
706 
  }
707 
 }
708 
 SYMBOL "#default" "dmem_data_mux" "dmem_data_mux"
709 
 {
710 
  HEADER
711 
  {
712 
   VARIABLES
713 
   {
714 
    #DESCRIPTION=""
715 
    #LANGUAGE="VERILOG"
716 
    #MODIFIED="1186224822"
717 
   }
718 
  }
719 
  PAGE ""
720 
  {
721 
   PAGEHEADER
722 
   {
723 
    RECT (0,0,280,200)
724 
    FREEID 12
725 
   }
726 
 
727 
   BODY
728 
   {
729 
    RECT  1, -1, 0
730 
    {
731 
     VARIABLES
732 
     {
733 
      #OUTLINE_FILLING="1"
734 
     }
735 
     AREA (20,0,260,200)
736 
    }
737 
    TEXT  3, 0, 0
738 
    {
739 
     TEXT "$#NAME"
740 
     RECT (25,30,159,54)
741 
     ALIGN 4
742 
     MARGINS (1,1)
743 
     PARENT 2
744 
    }
745 
    TEXT  5, 0, 0
746 
    {
747 
     TEXT "$#NAME"
748 
     RECT (121,30,255,54)
749 
     ALIGN 6
750 
     MARGINS (1,1)
751 
     PARENT 4
752 
    }
753 
    TEXT  7, 0, 0
754 
    {
755 
     TEXT "$#NAME"
756 
     RECT (25,70,148,94)
757 
     ALIGN 4
758 
     MARGINS (1,1)
759 
     PARENT 6
760 
    }
761 
    TEXT  9, 0, 0
762 
    {
763 
     TEXT "$#NAME"
764 
     RECT (25,110,170,134)
765 
     ALIGN 4
766 
     MARGINS (1,1)
767 
     PARENT 8
768 
    }
769 
    TEXT  11, 0, 0
770 
    {
771 
     TEXT "$#NAME"
772 
     RECT (25,150,115,174)
773 
     ALIGN 4
774 
     MARGINS (1,1)
775 
     PARENT 10
776 
    }
777 
    PIN  2, 0, 0
778 
    {
779 
     COORD (0,40)
780 
     VARIABLES
781 
     {
782 
      #DIRECTION="IN"
783 
      #DOWNTO="1"
784 
      #LENGTH="20"
785 
      #MDA_RECORD_TOKEN="OTHER"
786 
      #NAME="fw_alu(31:0)"
787 
      #NUMBER="0"
788 
      #VERILOG_TYPE="wire"
789 
     }
790 
     LINE  2, 0, 0
791 
     {
792 
      POINTS ( (0,0), (20,0) )
793 
     }
794 
    }
795 
    PIN  4, 0, 0
796 
    {
797 
     COORD (280,40)
798 
     VARIABLES
799 
     {
800 
      #DIRECTION="OUT"
801 
      #DOWNTO="1"
802 
      #LENGTH="20"
803 
      #MDA_RECORD_TOKEN="OTHER"
804 
      #NAME="data_o(31:0)"
805 
      #NUMBER="0"
806 
      #VERILOG_TYPE="reg"
807 
     }
808 
     LINE  2, 0, 0
809 
     {
810 
      POINTS ( (-20,0), (0,0) )
811 
     }
812 
    }
813 
    PIN  6, 0, 0
814 
    {
815 
     COORD (0,80)
816 
     VARIABLES
817 
     {
818 
      #DIRECTION="IN"
819 
      #DOWNTO="1"
820 
      #LENGTH="20"
821 
      #MDA_RECORD_TOKEN="OTHER"
822 
      #NAME="fw_ctl(2:0)"
823 
      #NUMBER="0"
824 
      #VERILOG_TYPE="wire"
825 
     }
826 
     LINE  2, 0, 0
827 
     {
828 
      POINTS ( (0,0), (20,0) )
829 
     }
830 
    }
831 
    PIN  8, 0, 0
832 
    {
833 
     COORD (0,120)
834 
     VARIABLES
835 
     {
836 
      #DIRECTION="IN"
837 
      #DOWNTO="1"
838 
      #LENGTH="20"
839 
      #MDA_RECORD_TOKEN="OTHER"
840 
      #NAME="fw_dmem(31:0)"
841 
      #NUMBER="0"
842 
      #VERILOG_TYPE="wire"
843 
     }
844 
     LINE  2, 0, 0
845 
     {
846 
      POINTS ( (0,0), (20,0) )
847 
     }
848 
    }
849 
    PIN  10, 0, 0
850 
    {
851 
     COORD (0,160)
852 
     VARIABLES
853 
     {
854 
      #DIRECTION="IN"
855 
      #DOWNTO="1"
856 
      #LENGTH="20"
857 
      #MDA_RECORD_TOKEN="OTHER"
858 
      #NAME="rt(31:0)"
859 
      #NUMBER="0"
860 
      #VERILOG_TYPE="wire"
861 
     }
862 
     LINE  2, 0, 0
863 
     {
864 
      POINTS ( (0,0), (20,0) )
865 
     }
866 
    }
867 
   }
868 
  }
869 
 }
870 
 SYMBOL "#default" "r32_reg_cls" "r32_reg_cls"
871 
 {
872 
  HEADER
873 
  {
874 
   VARIABLES
875 
   {
876 
    #DESCRIPTION=""
877 
    #LANGUAGE="VERILOG"
878 
    #MODIFIED="1194394294"
879 
   }
880 
  }
881 
  PAGE ""
882 
  {
883 
   PAGEHEADER
884 
   {
885 
    RECT (0,0,240,160)
886 
    FREEID 11
887 
   }
888 
 
889 
   BODY
890 
   {
891 
    RECT  1, -1, 0
892 
    {
893 
     VARIABLES
894 
     {
895 
      #OUTLINE_FILLING="1"
896 
     }
897 
     AREA (20,0,220,160)
898 
    }
899 
    TEXT  3, 0, 0
900 
    {
901 
     TEXT "$#NAME"
902 
     RECT (25,30,60,54)
903 
     ALIGN 4
904 
     MARGINS (1,1)
905 
     PARENT 2
906 
    }
907 
    TEXT  5, 0, 0
908 
    {
909 
     TEXT "$#NAME"
910 
     RECT (92,30,215,54)
911 
     ALIGN 6
912 
     MARGINS (1,1)
913 
     PARENT 4
914 
    }
915 
    TEXT  7, 0, 0
916 
    {
917 
     TEXT "$#NAME"
918 
     RECT (25,70,60,94)
919 
     ALIGN 4
920 
     MARGINS (1,1)
921 
     PARENT 6
922 
    }
923 
    TEXT  9, 0, 0
924 
    {
925 
     TEXT "$#NAME"
926 
     RECT (25,110,148,134)
927 
     ALIGN 4
928 
     MARGINS (1,1)
929 
     PARENT 8
930 
    }
931 
    PIN  2, 0, 0
932 
    {
933 
     COORD (0,40)
934 
     VARIABLES
935 
     {
936 
      #DIRECTION="IN"
937 
      #LENGTH="20"
938 
      #MDA_RECORD_TOKEN="OTHER"
939 
      #NAME="clk"
940 
      #NUMBER="0"
941 
      #VERILOG_TYPE="wire"
942 
     }
943 
     LINE  2, 0, 0
944 
     {
945 
      POINTS ( (0,0), (20,0) )
946 
     }
947 
    }
948 
    PIN  4, 0, 0
949 
    {
950 
     COORD (240,40)
951 
     VARIABLES
952 
     {
953 
      #DIRECTION="OUT"
954 
      #DOWNTO="1"
955 
      #LENGTH="20"
956 
      #MDA_RECORD_TOKEN="OTHER"
957 
      #NAME="r32_o(31:0)"
958 
      #NUMBER="0"
959 
      #VERILOG_TYPE="reg"
960 
     }
961 
     LINE  2, 0, 0
962 
     {
963 
      POINTS ( (-20,0), (0,0) )
964 
     }
965 
    }
966 
    PIN  6, 0, 0
967 
    {
968 
     COORD (0,80)
969 
     VARIABLES
970 
     {
971 
      #DIRECTION="IN"
972 
      #LENGTH="20"
973 
      #MDA_RECORD_TOKEN="OTHER"
974 
      #NAME="cls"
975 
      #NUMBER="0"
976 
      #VERILOG_TYPE="wire"
977 
     }
978 
     LINE  2, 0, 0
979 
     {
980 
      POINTS ( (0,0), (20,0) )
981 
     }
982 
    }
983 
    PIN  8, 0, 0
984 
    {
985 
     COORD (0,120)
986 
     VARIABLES
987 
     {
988 
      #DIRECTION="IN"
989 
      #DOWNTO="1"
990 
      #LENGTH="20"
991 
      #MDA_RECORD_TOKEN="OTHER"
992 
      #NAME="r32_i(31:0)"
993 
      #NUMBER="0"
994 
      #VERILOG_TYPE="wire"
995 
     }
996 
     LINE  2, 0, 0
997 
     {
998 
      POINTS ( (0,0), (20,0) )
999 
     }
1000 
    }
1001 
   }
1002 
  }
1003 
 }
1004 
 SYMBOL "#default" "r32_reg" "r32_reg"
1005 
 {
1006 
  HEADER
1007 
  {
1008 
   VARIABLES
1009 
   {
1010 
    #DESCRIPTION=""
1011 
    #LANGUAGE="VERILOG"
1012 
    #MODIFIED="1219001703"
1013 
   }
1014 
  }
1015 
  PAGE ""
1016 
  {
1017 
   PAGEHEADER
1018 
   {
1019 
    RECT (120,0,340,60)
1020 
    FREEID 9
1021 
   }
1022 
 
1023 
   BODY
1024 
   {
1025 
    RECT  1, -1, 0
1026 
    {
1027 
     VARIABLES
1028 
     {
1029 
      #OUTLINE_FILLING="1"
1030 
     }
1031 
     AREA (140,0,320,60)
1032 
    }
1033 
    TEXT  3, 0, 0
1034 
    {
1035 
     TEXT "$#NAME"
1036 
     RECT (145,30,180,54)
1037 
     ALIGN 4
1038 
     MARGINS (1,1)
1039 
     PARENT 2
1040 
    }
1041 
    TEXT  5, 0, 0
1042 
    {
1043 
     TEXT "$#NAME"
1044 
     RECT (192,10,315,34)
1045 
     ALIGN 6
1046 
     MARGINS (1,1)
1047 
     PARENT 4
1048 
    }
1049 
    TEXT  7, 0, 0
1050 
    {
1051 
     TEXT "$#NAME"
1052 
     RECT (145,10,268,34)
1053 
     ALIGN 4
1054 
     MARGINS (1,1)
1055 
     PARENT 6
1056 
    }
1057 
    PIN  2, 0, 0
1058 
    {
1059 
     COORD (120,40)
1060 
     VARIABLES
1061 
     {
1062 
      #DIRECTION="IN"
1063 
      #LENGTH="20"
1064 
      #MDA_RECORD_TOKEN="OTHER"
1065 
      #NAME="clk"
1066 
      #NUMBER="0"
1067 
      #SIDE="left"
1068 
      #VERILOG_TYPE="wire"
1069 
     }
1070 
     LINE  2, 0, 0
1071 
     {
1072 
      POINTS ( (0,0), (20,0) )
1073 
     }
1074 
    }
1075 
    PIN  4, 0, 0
1076 
    {
1077 
     COORD (340,20)
1078 
     VARIABLES
1079 
     {
1080 
      #DIRECTION="OUT"
1081 
      #DOWNTO="1"
1082 
      #LENGTH="20"
1083 
      #MDA_RECORD_TOKEN="OTHER"
1084 
      #NAME="r32_o(31:0)"
1085 
      #NUMBER="0"
1086 
      #SIDE="right"
1087 
      #VERILOG_TYPE="reg"
1088 
     }
1089 
     LINE  2, 0, 0
1090 
     {
1091 
      POINTS ( (-20,0), (0,0) )
1092 
     }
1093 
    }
1094 
    PIN  6, 0, 0
1095 
    {
1096 
     COORD (120,20)
1097 
     VARIABLES
1098 
     {
1099 
      #DIRECTION="IN"
1100 
      #DOWNTO="1"
1101 
      #LENGTH="20"
1102 
      #MDA_RECORD_TOKEN="OTHER"
1103 
      #NAME="r32_i(31:0)"
1104 
      #NUMBER="0"
1105 
      #SIDE="left"
1106 
      #VERILOG_TYPE="wire"
1107 
     }
1108 
     LINE  2, 0, 0
1109 
     {
1110 
      POINTS ( (0,0), (20,0) )
1111 
     }
1112 
    }
1113 
   }
1114 
  }
1115 
 }
1116 
 SYMBOL "#default" "add32" "add32"
1117 
 {
1118 
  HEADER
1119 
  {
1120 
   VARIABLES
1121 
   {
1122 
    #DESCRIPTION=""
1123 
    #LANGUAGE="VERILOG"
1124 
    #MODIFIED="1194488763"
1125 
   }
1126 
  }
1127 
  PAGE ""
1128 
  {
1129 
   PAGEHEADER
1130 
   {
1131 
    RECT (0,0,200,80)
1132 
    FREEID 7
1133 
   }
1134 
 
1135 
   BODY
1136 
   {
1137 
    RECT  1, -1, 0
1138 
    {
1139 
     VARIABLES
1140 
     {
1141 
      #OUTLINE_FILLING="1"
1142 
     }
1143 
     AREA (20,0,180,80)
1144 
    }
1145 
    TEXT  3, 0, 0
1146 
    {
1147 
     TEXT "$#NAME"
1148 
     RECT (25,30,126,54)
1149 
     ALIGN 4
1150 
     MARGINS (1,1)
1151 
     PARENT 2
1152 
    }
1153 
    TEXT  5, 0, 0
1154 
    {
1155 
     TEXT "$#NAME"
1156 
     RECT (74,30,175,54)
1157 
     ALIGN 6
1158 
     MARGINS (1,1)
1159 
     PARENT 4
1160 
    }
1161 
    PIN  2, 0, 0
1162 
    {
1163 
     COORD (0,40)
1164 
     VARIABLES
1165 
     {
1166 
      #DIRECTION="IN"
1167 
      #DOWNTO="1"
1168 
      #LENGTH="20"
1169 
      #MDA_RECORD_TOKEN="OTHER"
1170 
      #NAME="d_i(31:0)"
1171 
      #NUMBER="0"
1172 
      #VERILOG_TYPE="wire"
1173 
     }
1174 
     LINE  2, 0, 0
1175 
     {
1176 
      POINTS ( (0,0), (20,0) )
1177 
     }
1178 
    }
1179 
    PIN  4, 0, 0
1180 
    {
1181 
     COORD (200,40)
1182 
     VARIABLES
1183 
     {
1184 
      #DIRECTION="OUT"
1185 
      #DOWNTO="1"
1186 
      #LENGTH="20"
1187 
      #MDA_RECORD_TOKEN="OTHER"
1188 
      #NAME="d_o(31:0)"
1189 
      #NUMBER="0"
1190 
      #VERILOG_TYPE="wire"
1191 
     }
1192 
     LINE  2, 0, 0
1193 
     {
1194 
      POINTS ( (-20,0), (0,0) )
1195 
     }
1196 
    }
1197 
   }
1198 
  }
1199 
 }
1200 
}
1201 
 
1202 
PAGE ""
1203 
{
1204 
 PAGEHEADER
1205 
 {
1206 
  PAGESIZE (2338,1653)
1207 
  MARGINS (200,200,200,200)
1208 
  RECT (0,0,100,200)
1209 
 }
1210 
 
1211 
 BODY
1212 
 {
1213 
  INSTANCE  103, 0, 0
1214 
  {
1215 
   VARIABLES
1216 
   {
1217 
    #COMPONENT="big_alu"
1218 
    #LIBRARY="#default"
1219 
    #REFERENCE="MIPS_alu"
1220 
    #SYMBOL="big_alu"
1221 
   }
1222 
   COORD (1320,620)
1223 
   VERTEXES ( (14,595), (12,557), (6,521), (2,528), (10,579), (8,2626) )
1224 
  }
1225 
  TEXT  104, 0, 0
1226 
  {
1227 
   TEXT "$#REFERENCE"
1228 
   RECT (1320,584,1458,619)
1229 
   ALIGN 8
1230 
   MARGINS (1,1)
1231 
   PARENT 103
1232 
  }
1233 
  TEXT  108, 0, 0
1234 
  {
1235 
   TEXT "$#COMPONENT"
1236 
   RECT (1320,1000,1441,1035)
1237 
   MARGINS (1,1)
1238 
   PARENT 103
1239 
  }
1240 
  INSTANCE  112, 0, 0
1241 
  {
1242 
   VARIABLES
1243 
   {
1244 
    #COMPONENT="alu_muxa"
1245 
    #LIBRARY="#default"
1246 
    #REFERENCE="i_alu_muxa"
1247 
    #SYMBOL="alu_muxa"
1248 
   }
1249 
   COORD (900,360)
1250 
   VERTEXES ( (8,257), (12,273), (6,406), (4,527), (10,265), (2,438), (18,2410), (16,2813), (14,2978) )
1251 
  }
1252 
  TEXT  113, 0, 0
1253 
  {
1254 
   TEXT "$#REFERENCE"
1255 
   RECT (900,324,1072,359)
1256 
   ALIGN 8
1257 
   MARGINS (1,1)
1258 
   PARENT 112
1259 
  }
1260 
  TEXT  117, 0, 0
1261 
  {
1262 
   TEXT "$#COMPONENT"
1263 
   RECT (900,720,1038,755)
1264 
   MARGINS (1,1)
1265 
   PARENT 112
1266 
  }
1267 
  INSTANCE  121, 0, 0
1268 
  {
1269 
   VARIABLES
1270 
   {
1271 
    #COMPONENT="alu_muxb"
1272 
    #LIBRARY="#default"
1273 
    #REFERENCE="i_alu_muxb"
1274 
    #SYMBOL="alu_muxb"
1275 
   }
1276 
   COORD (880,820)
1277 
   VERTEXES ( (8,281), (12,289), (2,380), (6,413), (10,671), (14,738), (4,520) )
1278 
  }
1279 
  TEXT  122, 0, 0
1280 
  {
1281 
   TEXT "$#REFERENCE"
1282 
   RECT (880,785,1052,820)
1283 
   ALIGN 8
1284 
   MARGINS (1,1)
1285 
   PARENT 121
1286 
  }
1287 
  TEXT  126, 0, 0
1288 
  {
1289 
   TEXT "$#COMPONENT"
1290 
   RECT (880,1100,1018,1135)
1291 
   MARGINS (1,1)
1292 
   PARENT 121
1293 
  }
1294 
  INSTANCE  130, 0, 0
1295 
  {
1296 
   VARIABLES
1297 
   {
1298 
    #COMPONENT="dmem_data_mux"
1299 
    #LIBRARY="#default"
1300 
    #REFERENCE="dmem_data_mux"
1301 
    #SYMBOL="dmem_data_mux"
1302 
   }
1303 
   COORD (1820,800)
1304 
   VERTEXES ( (2,953), (6,955), (8,956), (10,957), (4,2615) )
1305 
  }
1306 
  TEXT  131, 0, 0
1307 
  {
1308 
   TEXT "$#REFERENCE"
1309 
   RECT (1820,764,2043,799)
1310 
   ALIGN 8
1311 
   MARGINS (1,1)
1312 
   PARENT 130
1313 
  }
1314 
  TEXT  135, 0, 0
1315 
  {
1316 
   TEXT "$#COMPONENT"
1317 
   RECT (1820,1000,2043,1035)
1318 
   MARGINS (1,1)
1319 
   PARENT 130
1320 
  }
1321 
  NET BUS  146, 0, 0
1322 
  INSTANCE  165, 0, 0
1323 
  {
1324 
   VARIABLES
1325 
   {
1326 
    #COMPONENT="BusInput"
1327 
    #LIBRARY="#terminals"
1328 
    #REFERENCE="fw_alu(31:0)"
1329 
    #SYMBOL="BusInput"
1330 
   }
1331 
   COORD (300,320)
1332 
   VERTEXES ( (2,1477) )
1333 
  }
1334 
  TEXT  166, 0, 0
1335 
  {
1336 
   TEXT "$#REFERENCE"
1337 
   RECT (43,303,249,338)
1338 
   ALIGN 6
1339 
   MARGINS (1,1)
1340 
   PARENT 165
1341 
  }
1342 
  INSTANCE  170, 0, 0
1343 
  {
1344 
   VARIABLES
1345 
   {
1346 
    #COMPONENT="BusInput"
1347 
    #LIBRARY="#terminals"
1348 
    #REFERENCE="fw_dmem(31:0)"
1349 
    #SYMBOL="BusInput"
1350 
   }
1351 
   COORD (300,360)
1352 
   VERTEXES ( (2,436) )
1353 
  }
1354 
  TEXT  171, 0, 0
1355 
  {
1356 
   TEXT "$#REFERENCE"
1357 
   RECT (26,343,249,378)
1358 
   ALIGN 6
1359 
   MARGINS (1,1)
1360 
   PARENT 170
1361 
  }
1362 
  INSTANCE  175, 0, 0
1363 
  {
1364 
   VARIABLES
1365 
   {
1366 
    #COMPONENT="BusInput"
1367 
    #LIBRARY="#terminals"
1368 
    #REFERENCE="muxa_fw_ctl(2:0)"
1369 
    #SYMBOL="BusInput"
1370 
    #VERILOG_TYPE="wire"
1371 
   }
1372 
   COORD (300,400)
1373 
   VERTEXES ( (2,437) )
1374 
  }
1375 
  TEXT  176, 0, 0
1376 
  {
1377 
   TEXT "$#REFERENCE"
1378 
   RECT (-34,383,240,418)
1379 
   ALIGN 6
1380 
   MARGINS (1,1)
1381 
   PARENT 175
1382 
  }
1383 
  VTX  257, 0, 0
1384 
  {
1385 
   COORD (900,480)
1386 
  }
1387 
  NET BUS  259, 0, 0
1388 
  VTX  260, 0, 0
1389 
  {
1390 
   COORD (800,480)
1391 
  }
1392 
  BUS  261, 0, 0
1393 
  {
1394 
   NET 259
1395 
   VTX 257, 260
1396 
  }
1397 
  VTX  265, 0, 0
1398 
  {
1399 
   COORD (900,520)
1400 
  }
1401 
  NET BUS  267, 0, 0
1402 
  VTX  268, 0, 0
1403 
  {
1404 
   COORD (820,520)
1405 
  }
1406 
  BUS  269, 0, 0
1407 
  {
1408 
   NET 267
1409 
   VTX 265, 268
1410 
  }
1411 
  VTX  273, 0, 0
1412 
  {
1413 
   COORD (900,560)
1414 
  }
1415 
  NET BUS  275, 0, 0
1416 
  VTX  276, 0, 0
1417 
  {
1418 
   COORD (840,560)
1419 
  }
1420 
  BUS  277, 0, 0
1421 
  {
1422 
   NET 275
1423 
   VTX 273, 276
1424 
  }
1425 
  VTX  281, 0, 0
1426 
  {
1427 
   COORD (880,940)
1428 
  }
1429 
  VTX  282, 0, 0
1430 
  {
1431 
   COORD (800,940)
1432 
  }
1433 
  BUS  283, 0, 0
1434 
  {
1435 
   NET 259
1436 
   VTX 281, 282
1437 
  }
1438 
  BUS  284, 0, 0
1439 
  {
1440 
   NET 259
1441 
   VTX 282, 260
1442 
  }
1443 
  VTX  289, 0, 0
1444 
  {
1445 
   COORD (880,1020)
1446 
  }
1447 
  VTX  290, 0, 0
1448 
  {
1449 
   COORD (840,1020)
1450 
  }
1451 
  BUS  291, 0, 0
1452 
  {
1453 
   NET 275
1454 
   VTX 276, 290
1455 
  }
1456 
  BUS  292, 0, 0
1457 
  {
1458 
   NET 275
1459 
   VTX 290, 289
1460 
  }
1461 
  INSTANCE  293, 0, 0
1462 
  {
1463 
   VARIABLES
1464 
   {
1465 
    #COMPONENT="BusInput"
1466 
    #LIBRARY="#terminals"
1467 
    #REFERENCE="rt_i(31:0)"
1468 
    #SYMBOL="BusInput"
1469 
    #VERILOG_TYPE="wire"
1470 
   }
1471 
   COORD (300,1060)
1472 
   VERTEXES ( (2,736) )
1473 
  }
1474 
  TEXT  294, 0, 0
1475 
  {
1476 
   TEXT "$#REFERENCE"
1477 
   RECT (77,1043,249,1078)
1478 
   ALIGN 6
1479 
   MARGINS (1,1)
1480 
   PARENT 293
1481 
  }
1482 
  INSTANCE  298, 0, 0
1483 
  {
1484 
   VARIABLES
1485 
   {
1486 
    #COMPONENT="BusInput"
1487 
    #LIBRARY="#terminals"
1488 
    #REFERENCE="pc_i(31:0)"
1489 
    #SYMBOL="BusInput"
1490 
    #VERILOG_TYPE="wire"
1491 
   }
1492 
   COORD (300,780)
1493 
   VERTEXES ( (2,2441) )
1494 
  }
1495 
  TEXT  299, 0, 0
1496 
  {
1497 
   TEXT "$#REFERENCE"
1498 
   RECT (77,763,249,798)
1499 
   ALIGN 6
1500 
   MARGINS (1,1)
1501 
   PARENT 298
1502 
  }
1503 
  NET BUS  340, 0, 0
1504 
  INSTANCE  341, 0, 0
1505 
  {
1506 
   VARIABLES
1507 
   {
1508 
    #COMPONENT="BusInput"
1509 
    #LIBRARY="#terminals"
1510 
    #REFERENCE="muxa_ctl_i(1:0)"
1511 
    #SYMBOL="BusInput"
1512 
   }
1513 
   COORD (300,280)
1514 
   VERTEXES ( (2,439) )
1515 
  }
1516 
  TEXT  342, 0, 0
1517 
  {
1518 
   TEXT "$#REFERENCE"
1519 
   RECT (-8,263,249,298)
1520 
   ALIGN 6
1521 
   MARGINS (1,1)
1522 
   PARENT 341
1523 
  }
1524 
  INSTANCE  346, 0, 0
1525 
  {
1526 
   VARIABLES
1527 
   {
1528 
    #COMPONENT="BusInput"
1529 
    #LIBRARY="#terminals"
1530 
    #REFERENCE="rs_i(31:0)"
1531 
    #SYMBOL="BusInput"
1532 
    #VERILOG_TYPE="wire"
1533 
   }
1534 
   COORD (300,440)
1535 
   VERTEXES ( (2,2814) )
1536 
  }
1537 
  TEXT  347, 0, 0
1538 
  {
1539 
   TEXT "$#REFERENCE"
1540 
   RECT (77,423,249,458)
1541 
   ALIGN 6
1542 
   MARGINS (1,1)
1543 
   PARENT 346
1544 
  }
1545 
  INSTANCE  351, 0, 0
1546 
  {
1547 
   VARIABLES
1548 
   {
1549 
    #COMPONENT="BusInput"
1550 
    #LIBRARY="#terminals"
1551 
    #REFERENCE="ext_i(31:0)"
1552 
    #SYMBOL="BusInput"
1553 
    #VERILOG_TYPE="wire"
1554 
   }
1555 
   COORD (300,240)
1556 
   VERTEXES ( (2,442) )
1557 
  }
1558 
  TEXT  352, 0, 0
1559 
  {
1560 
   TEXT "$#REFERENCE"
1561 
   RECT (60,223,249,258)
1562 
   ALIGN 6
1563 
   MARGINS (1,1)
1564 
   PARENT 351
1565 
  }
1566 
  INSTANCE  361, 0, 0
1567 
  {
1568 
   VARIABLES
1569 
   {
1570 
    #COMPONENT="BusInput"
1571 
    #LIBRARY="#terminals"
1572 
    #REFERENCE="muxb_ctl_i(1:0)"
1573 
    #SYMBOL="BusInput"
1574 
    #VERILOG_TYPE="wire"
1575 
   }
1576 
   COORD (300,860)
1577 
   VERTEXES ( (2,381) )
1578 
  }
1579 
  TEXT  362, 0, 0
1580 
  {
1581 
   TEXT "$#REFERENCE"
1582 
   RECT (-8,843,249,878)
1583 
   ALIGN 6
1584 
   MARGINS (1,1)
1585 
   PARENT 361
1586 
  }
1587 
  NET BUS  367, 0, 0
1588 
  VTX  380, 0, 0
1589 
  {
1590 
   COORD (880,860)
1591 
  }
1592 
  VTX  381, 0, 0
1593 
  {
1594 
   COORD (300,860)
1595 
  }
1596 
  BUS  382, 0, 0
1597 
  {
1598 
   NET 367
1599 
   VTX 380, 381
1600 
  }
1601 
  NET BUS  385, 0, 0
1602 
  NET BUS  400, 0, 0
1603 
  VTX  406, 0, 0
1604 
  {
1605 
   COORD (900,440)
1606 
  }
1607 
  VTX  408, 0, 0
1608 
  {
1609 
   COORD (880,440)
1610 
  }
1611 
  BUS  409, 0, 0
1612 
  {
1613 
   NET 400
1614 
   VTX 406, 408
1615 
  }
1616 
  VTX  413, 0, 0
1617 
  {
1618 
   COORD (880,900)
1619 
  }
1620 
  VTX  414, 0, 0
1621 
  {
1622 
   COORD (860,440)
1623 
  }
1624 
  BUS  415, 0, 0
1625 
  {
1626 
   NET 400
1627 
   VTX 408, 414
1628 
  }
1629 
  VTX  416, 0, 0
1630 
  {
1631 
   COORD (860,900)
1632 
  }
1633 
  BUS  417, 0, 0
1634 
  {
1635 
   NET 400
1636 
   VTX 414, 416
1637 
  }
1638 
  BUS  418, 0, 0
1639 
  {
1640 
   NET 400
1641 
   VTX 416, 413
1642 
  }
1643 
  NET BUS  421, 0, 0
1644 
  VTX  436, 0, 0
1645 
  {
1646 
   COORD (300,360)
1647 
  }
1648 
  VTX  437, 0, 0
1649 
  {
1650 
   COORD (300,400)
1651 
  }
1652 
  VTX  438, 0, 0
1653 
  {
1654 
   COORD (900,400)
1655 
  }
1656 
  VTX  439, 0, 0
1657 
  {
1658 
   COORD (300,280)
1659 
  }
1660 
  VTX  442, 0, 0
1661 
  {
1662 
   COORD (300,240)
1663 
  }
1664 
  VTX  447, 0, 0
1665 
  {
1666 
   COORD (840,360)
1667 
  }
1668 
  BUS  448, 0, 0
1669 
  {
1670 
   NET 275
1671 
   VTX 276, 447
1672 
  }
1673 
  BUS  449, 0, 0
1674 
  {
1675 
   NET 275
1676 
   VTX 447, 436
1677 
  }
1678 
  VTX  450, 0, 0
1679 
  {
1680 
   COORD (820,400)
1681 
  }
1682 
  BUS  451, 0, 0
1683 
  {
1684 
   NET 267
1685 
   VTX 268, 450
1686 
  }
1687 
  BUS  452, 0, 0
1688 
  {
1689 
   NET 267
1690 
   VTX 450, 437
1691 
  }
1692 
  VTX  453, 0, 0
1693 
  {
1694 
   COORD (860,400)
1695 
  }
1696 
  BUS  454, 0, 0
1697 
  {
1698 
   NET 385
1699 
   VTX 438, 453
1700 
  }
1701 
  VTX  455, 0, 0
1702 
  {
1703 
   COORD (860,280)
1704 
  }
1705 
  BUS  456, 0, 0
1706 
  {
1707 
   NET 385
1708 
   VTX 453, 455
1709 
  }
1710 
  BUS  457, 0, 0
1711 
  {
1712 
   NET 385
1713 
   VTX 455, 439
1714 
  }
1715 
  VTX  463, 0, 0
1716 
  {
1717 
   COORD (880,240)
1718 
  }
1719 
  BUS  464, 0, 0
1720 
  {
1721 
   NET 400
1722 
   VTX 408, 463
1723 
  }
1724 
  BUS  465, 0, 0
1725 
  {
1726 
   NET 400
1727 
   VTX 463, 442
1728 
  }
1729 
  NET BUS  468, 0, 0
1730 
  NET BUS  476, 0, 0
1731 
  VTX  520, 0, 0
1732 
  {
1733 
   COORD (1160,860)
1734 
  }
1735 
  VTX  521, 0, 0
1736 
  {
1737 
   COORD (1320,700)
1738 
  }
1739 
  VTX  522, 0, 0
1740 
  {
1741 
   COORD (1200,860)
1742 
  }
1743 
  BUS  523, 0, 0
1744 
  {
1745 
   NET 468
1746 
   VTX 520, 522
1747 
  }
1748 
  VTX  524, 0, 0
1749 
  {
1750 
   COORD (1200,700)
1751 
  }
1752 
  BUS  525, 0, 0
1753 
  {
1754 
   NET 468
1755 
   VTX 522, 524
1756 
  }
1757 
  BUS  526, 0, 0
1758 
  {
1759 
   NET 468
1760 
   VTX 524, 521
1761 
  }
1762 
  VTX  527, 0, 0
1763 
  {
1764 
   COORD (1180,400)
1765 
  }
1766 
  VTX  528, 0, 0
1767 
  {
1768 
   COORD (1320,660)
1769 
  }
1770 
  VTX  529, 0, 0
1771 
  {
1772 
   COORD (1200,400)
1773 
  }
1774 
  BUS  530, 0, 0
1775 
  {
1776 
   NET 476
1777 
   VTX 527, 529
1778 
  }
1779 
  VTX  531, 0, 0
1780 
  {
1781 
   COORD (1200,660)
1782 
  }
1783 
  BUS  532, 0, 0
1784 
  {
1785 
   NET 476
1786 
   VTX 529, 531
1787 
  }
1788 
  BUS  533, 0, 0
1789 
  {
1790 
   NET 476
1791 
   VTX 531, 528
1792 
  }
1793 
  INSTANCE  534, 0, 0
1794 
  {
1795 
   VARIABLES
1796 
   {
1797 
    #COMPONENT="Input"
1798 
    #LIBRARY="#terminals"
1799 
    #REFERENCE="clk"
1800 
    #SYMBOL="Input"
1801 
   }
1802 
   COORD (1220,220)
1803 
   VERTEXES ( (2,578) )
1804 
  }
1805 
  TEXT  535, 0, 0
1806 
  {
1807 
   TEXT "$#REFERENCE"
1808 
   RECT (1116,203,1169,238)
1809 
   ALIGN 6
1810 
   MARGINS (1,1)
1811 
   PARENT 534
1812 
  }
1813 
  INSTANCE  539, 0, 0
1814 
  {
1815 
   VARIABLES
1816 
   {
1817 
    #COMPONENT="Input"
1818 
    #LIBRARY="#terminals"
1819 
    #REFERENCE="rst"
1820 
    #SYMBOL="Input"
1821 
   }
1822 
   COORD (1220,260)
1823 
   VERTEXES ( (2,594) )
1824 
  }
1825 
  TEXT  540, 0, 0
1826 
  {
1827 
   TEXT "$#REFERENCE"
1828 
   RECT (1116,243,1169,278)
1829 
   ALIGN 6
1830 
   MARGINS (1,1)
1831 
   PARENT 539
1832 
  }
1833 
  INSTANCE  544, 0, 0
1834 
  {
1835 
   VARIABLES
1836 
   {
1837 
    #COMPONENT="BusInput"
1838 
    #LIBRARY="#terminals"
1839 
    #REFERENCE="alu_func(4:0)"
1840 
    #SYMBOL="BusInput"
1841 
    #VERILOG_TYPE="wire"
1842 
   }
1843 
   COORD (1220,300)
1844 
   VERTEXES ( (2,558) )
1845 
  }
1846 
  TEXT  545, 0, 0
1847 
  {
1848 
   TEXT "$#REFERENCE"
1849 
   RECT (946,283,1169,318)
1850 
   ALIGN 6
1851 
   MARGINS (1,1)
1852 
   PARENT 544
1853 
  }
1854 
  NET BUS  551, 0, 0
1855 
  VTX  557, 0, 0
1856 
  {
1857 
   COORD (1320,780)
1858 
  }
1859 
  VTX  558, 0, 0
1860 
  {
1861 
   COORD (1220,300)
1862 
  }
1863 
  VTX  559, 0, 0
1864 
  {
1865 
   COORD (1300,780)
1866 
  }
1867 
  BUS  560, 0, 0
1868 
  {
1869 
   NET 551
1870 
   VTX 557, 559
1871 
  }
1872 
  VTX  561, 0, 0
1873 
  {
1874 
   COORD (1300,300)
1875 
  }
1876 
  BUS  562, 0, 0
1877 
  {
1878 
   NET 551
1879 
   VTX 559, 561
1880 
  }
1881 
  BUS  563, 0, 0
1882 
  {
1883 
   NET 551
1884 
   VTX 561, 558
1885 
  }
1886 
  VTX  578, 0, 0
1887 
  {
1888 
   COORD (1220,220)
1889 
  }
1890 
  VTX  579, 0, 0
1891 
  {
1892 
   COORD (1320,740)
1893 
  }
1894 
  VTX  581, 0, 0
1895 
  {
1896 
   COORD (1280,220)
1897 
  }
1898 
  WIRE  582, 0, 0
1899 
  {
1900 
   NET 2987
1901 
   VTX 578, 581
1902 
  }
1903 
  VTX  583, 0, 0
1904 
  {
1905 
   COORD (1280,740)
1906 
  }
1907 
  WIRE  584, 0, 0
1908 
  {
1909 
   NET 2987
1910 
   VTX 581, 583
1911 
  }
1912 
  WIRE  585, 0, 0
1913 
  {
1914 
   NET 2987
1915 
   VTX 583, 579
1916 
  }
1917 
  VTX  594, 0, 0
1918 
  {
1919 
   COORD (1220,260)
1920 
  }
1921 
  VTX  595, 0, 0
1922 
  {
1923 
   COORD (1320,820)
1924 
  }
1925 
  NET WIRE  596, 0, 0
1926 
  VTX  597, 0, 0
1927 
  {
1928 
   COORD (1260,260)
1929 
  }
1930 
  WIRE  598, 0, 0
1931 
  {
1932 
   NET 596
1933 
   VTX 594, 597
1934 
  }
1935 
  VTX  599, 0, 0
1936 
  {
1937 
   COORD (1260,820)
1938 
  }
1939 
  WIRE  600, 0, 0
1940 
  {
1941 
   NET 596
1942 
   VTX 597, 599
1943 
  }
1944 
  WIRE  601, 0, 0
1945 
  {
1946 
   NET 596
1947 
   VTX 599, 595
1948 
  }
1949 
  INSTANCE  602, 0, 0
1950 
  {
1951 
   VARIABLES
1952 
   {
1953 
    #COMPONENT="BusOutput"
1954 
    #LIBRARY="#terminals"
1955 
    #REFERENCE="alu_ur_o(31:0)"
1956 
    #SYMBOL="BusOutput"
1957 
    #VERILOG_TYPE="wire"
1958 
   }
1959 
   COORD (1860,220)
1960 
   VERTEXES ( (2,2627) )
1961 
  }
1962 
  TEXT  603, 0, 0
1963 
  {
1964 
   TEXT "$#REFERENCE"
1965 
   RECT (1912,203,2152,238)
1966 
   ALIGN 4
1967 
   MARGINS (1,1)
1968 
   PARENT 602
1969 
  }
1970 
  NET BUS  609, 0, 0
1971 
  INSTANCE  644, 0, 0
1972 
  {
1973 
   VARIABLES
1974 
   {
1975 
    #COMPONENT="BusInput"
1976 
    #LIBRARY="#terminals"
1977 
    #REFERENCE="muxb_fw_ctl(2:0)"
1978 
    #SYMBOL="BusInput"
1979 
    #VERILOG_TYPE="wire"
1980 
   }
1981 
   COORD (300,980)
1982 
   VERTEXES ( (2,670) )
1983 
  }
1984 
  TEXT  645, 0, 0
1985 
  {
1986 
   TEXT "$#REFERENCE"
1987 
   RECT (-25,963,249,998)
1988 
   ALIGN 6
1989 
   MARGINS (1,1)
1990 
   PARENT 644
1991 
  }
1992 
  VTX  670, 0, 0
1993 
  {
1994 
   COORD (300,980)
1995 
  }
1996 
  VTX  671, 0, 0
1997 
  {
1998 
   COORD (880,980)
1999 
  }
2000 
  NET BUS  672, 0, 0
2001 
  BUS  673, 0, 0
2002 
  {
2003 
   NET 672
2004 
   VTX 670, 671
2005 
  }
2006 
  VTX  736, 0, 0
2007 
  {
2008 
   COORD (300,1060)
2009 
  }
2010 
  VTX  737, 0, 0
2011 
  {
2012 
   COORD (860,1060)
2013 
  }
2014 
  VTX  738, 0, 0
2015 
  {
2016 
   COORD (880,1060)
2017 
  }
2018 
  BUS  740, 0, 0
2019 
  {
2020 
   NET 340
2021 
   VTX 736, 737
2022 
  }
2023 
  BUS  741, 0, 0
2024 
  {
2025 
   NET 340
2026 
   VTX 738, 737
2027 
  }
2028 
  INSTANCE  765, 0, 0
2029 
  {
2030 
   VARIABLES
2031 
   {
2032 
    #COMPONENT="BusInput"
2033 
    #LIBRARY="#terminals"
2034 
    #REFERENCE="dmem_fw_ctl(2:0)"
2035 
    #SYMBOL="BusInput"
2036 
    #VERILOG_TYPE="wire"
2037 
   }
2038 
   COORD (300,1180)
2039 
   VERTEXES ( (2,954) )
2040 
  }
2041 
  TEXT  766, 0, 0
2042 
  {
2043 
   TEXT "$#REFERENCE"
2044 
   RECT (-25,1163,249,1198)
2045 
   ALIGN 6
2046 
   MARGINS (1,1)
2047 
   PARENT 765
2048 
  }
2049 
  NET BUS  772, 0, 0
2050 
  VTX  953, 0, 0
2051 
  {
2052 
   COORD (1820,840)
2053 
  }
2054 
  VTX  954, 0, 0
2055 
  {
2056 
   COORD (300,1180)
2057 
  }
2058 
  VTX  955, 0, 0
2059 
  {
2060 
   COORD (1820,880)
2061 
  }
2062 
  VTX  956, 0, 0
2063 
  {
2064 
   COORD (1820,920)
2065 
  }
2066 
  VTX  957, 0, 0
2067 
  {
2068 
   COORD (1820,960)
2069 
  }
2070 
  VTX  958, 0, 0
2071 
  {
2072 
   COORD (800,1160)
2073 
  }
2074 
  BUS  959, 0, 0
2075 
  {
2076 
   NET 259
2077 
   VTX 282, 958
2078 
  }
2079 
  VTX  960, 0, 0
2080 
  {
2081 
   COORD (1720,1160)
2082 
  }
2083 
  BUS  961, 0, 0
2084 
  {
2085 
   NET 259
2086 
   VTX 958, 960
2087 
  }
2088 
  VTX  962, 0, 0
2089 
  {
2090 
   COORD (1720,840)
2091 
  }
2092 
  BUS  963, 0, 0
2093 
  {
2094 
   NET 259
2095 
   VTX 960, 962
2096 
  }
2097 
  BUS  964, 0, 0
2098 
  {
2099 
   NET 259
2100 
   VTX 962, 953
2101 
  }
2102 
  VTX  965, 0, 0
2103 
  {
2104 
   COORD (1700,1180)
2105 
  }
2106 
  BUS  966, 0, 0
2107 
  {
2108 
   NET 772
2109 
   VTX 954, 965
2110 
  }
2111 
  VTX  967, 0, 0
2112 
  {
2113 
   COORD (1700,880)
2114 
  }
2115 
  BUS  968, 0, 0
2116 
  {
2117 
   NET 772
2118 
   VTX 965, 967
2119 
  }
2120 
  BUS  969, 0, 0
2121 
  {
2122 
   NET 772
2123 
   VTX 967, 955
2124 
  }
2125 
  VTX  970, 0, 0
2126 
  {
2127 
   COORD (840,1140)
2128 
  }
2129 
  BUS  971, 0, 0
2130 
  {
2131 
   NET 275
2132 
   VTX 290, 970
2133 
  }
2134 
  VTX  972, 0, 0
2135 
  {
2136 
   COORD (1760,1140)
2137 
  }
2138 
  BUS  973, 0, 0
2139 
  {
2140 
   NET 275
2141 
   VTX 970, 972
2142 
  }
2143 
  VTX  974, 0, 0
2144 
  {
2145 
   COORD (1760,920)
2146 
  }
2147 
  BUS  975, 0, 0
2148 
  {
2149 
   NET 275
2150 
   VTX 972, 974
2151 
  }
2152 
  BUS  976, 0, 0
2153 
  {
2154 
   NET 275
2155 
   VTX 974, 956
2156 
  }
2157 
  VTX  977, 0, 0
2158 
  {
2159 
   COORD (860,1120)
2160 
  }
2161 
  BUS  978, 0, 0
2162 
  {
2163 
   NET 340
2164 
   VTX 737, 977
2165 
  }
2166 
  VTX  979, 0, 0
2167 
  {
2168 
   COORD (1740,1120)
2169 
  }
2170 
  BUS  980, 0, 0
2171 
  {
2172 
   NET 340
2173 
   VTX 977, 979
2174 
  }
2175 
  VTX  981, 0, 0
2176 
  {
2177 
   COORD (1740,960)
2178 
  }
2179 
  BUS  982, 0, 0
2180 
  {
2181 
   NET 340
2182 
   VTX 979, 981
2183 
  }
2184 
  BUS  983, 0, 0
2185 
  {
2186 
   NET 340
2187 
   VTX 981, 957
2188 
  }
2189 
  INSTANCE  991, 0, 0
2190 
  {
2191 
   VARIABLES
2192 
   {
2193 
    #COMPONENT="BusOutput"
2194 
    #LIBRARY="#terminals"
2195 
    #REFERENCE="dmem_data_ur_o(31:0)"
2196 
    #SYMBOL="BusOutput"
2197 
   }
2198 
   COORD (1860,300)
2199 
   VERTEXES ( (2,2616) )
2200 
  }
2201 
  TEXT  992, 0, 0
2202 
  {
2203 
   TEXT "$#REFERENCE"
2204 
   RECT (1900,283,2242,318)
2205 
   ALIGN 4
2206 
   MARGINS (1,1)
2207 
   PARENT 991
2208 
  }
2209 
  NET BUS  1015, 0, 0
2210 
  INSTANCE  1138, 0, 0
2211 
  {
2212 
   VARIABLES
2213 
   {
2214 
    #COMPONENT="Input"
2215 
    #LIBRARY="#terminals"
2216 
    #REFERENCE="spc_cls_i"
2217 
    #SYMBOL="Input"
2218 
   }
2219 
   COORD (300,740)
2220 
   VERTEXES ( (2,2444) )
2221 
  }
2222 
  TEXT  1139, 0, 0
2223 
  {
2224 
   TEXT "$#REFERENCE"
2225 
   RECT (94,723,249,758)
2226 
   ALIGN 6
2227 
   MARGINS (1,1)
2228 
   PARENT 1138
2229 
  }
2230 
  NET WIRE  1145, 0, 0
2231 
  VTX  1477, 0, 0
2232 
  {
2233 
   COORD (300,320)
2234 
  }
2235 
  VTX  1478, 0, 0
2236 
  {
2237 
   COORD (800,320)
2238 
  }
2239 
  BUS  1479, 0, 0
2240 
  {
2241 
   NET 259
2242 
   VTX 1477, 1478
2243 
  }
2244 
  BUS  1480, 0, 0
2245 
  {
2246 
   NET 259
2247 
   VTX 1478, 260
2248 
  }
2249 
  INSTANCE  1882, 0, 0
2250 
  {
2251 
   VARIABLES
2252 
   {
2253 
    #COMPONENT="r32_reg_cls"
2254 
    #LIBRARY="#default"
2255 
    #REFERENCE="spc"
2256 
    #SYMBOL="r32_reg_cls"
2257 
   }
2258 
   COORD (480,660)
2259 
   VERTEXES ( (2,2409), (4,2411), (8,2440), (6,2443) )
2260 
  }
2261 
  TEXT  1883, 0, 0
2262 
  {
2263 
   TEXT "$#REFERENCE"
2264 
   RECT (440,665,493,700)
2265 
   ALIGN 8
2266 
   MARGINS (1,1)
2267 
   PARENT 1882
2268 
  }
2269 
  TEXT  1887, 0, 0
2270 
  {
2271 
   TEXT "$#COMPONENT"
2272 
   RECT (480,820,669,855)
2273 
   MARGINS (1,1)
2274 
   PARENT 1882
2275 
  }
2276 
  NET BUS  2332, 0, 0
2277 
  INSTANCE  2338, 0, 0
2278 
  {
2279 
   VARIABLES
2280 
   {
2281 
    #COMPONENT="r32_reg"
2282 
    #LIBRARY="#default"
2283 
    #REFERENCE="pc_nxt"
2284 
    #SYMBOL="r32_reg"
2285 
   }
2286 
   COORD (380,580)
2287 
   VERTEXES ( (6,2981), (2,2977), (4,2979) )
2288 
  }
2289 
  TEXT  2339, 0, 0
2290 
  {
2291 
   TEXT "$#REFERENCE"
2292 
   RECT (500,544,604,579)
2293 
   ALIGN 8
2294 
   MARGINS (1,1)
2295 
   PARENT 2338
2296 
  }
2297 
  TEXT  2343, 0, 0
2298 
  {
2299 
   TEXT "$#COMPONENT"
2300 
   RECT (500,640,621,675)
2301 
   MARGINS (1,1)
2302 
   PARENT 2338
2303 
  }
2304 
  INSTANCE  2375, 0, 0
2305 
  {
2306 
   VARIABLES
2307 
   {
2308 
    #COMPONENT="add32"
2309 
    #LIBRARY="#default"
2310 
    #REFERENCE="add4"
2311 
    #SYMBOL="add32"
2312 
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2313 
   COORD (280,560)
2314 
   VERTEXES ( (2,2672), (4,2980) )
2315 
  }
2316 
  TEXT  2376, 0, 0
2317 
  {
2318 
   TEXT "$#REFERENCE"
2319 
   RECT (280,524,350,559)
2320 
   ALIGN 8
2321 
   MARGINS (1,1)
2322 
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2323 
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2324 
  TEXT  2380, 0, 0
2325 
  {
2326 
   TEXT "$#COMPONENT"
2327 
   RECT (280,640,367,675)
2328 
   MARGINS (1,1)
2329 
   PARENT 2375
2330 
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2331 
  VTX  2409, 0, 0
2332 
  {
2333 
   COORD (480,700)
2334 
  }
2335 
  VTX  2410, 0, 0
2336 
  {
2337 
   COORD (900,680)
2338 
  }
2339 
  VTX  2411, 0, 0
2340 
  {
2341 
   COORD (720,700)
2342 
  }
2343 
  VTX  2416, 0, 0
2344 
  {
2345 
   COORD (740,740)
2346 
  }
2347 
  WIRE  2417, 0, 0
2348 
  {
2349 
   NET 2987
2350 
   VTX 583, 2416
2351 
  }
2352 
  VTX  2418, 0, 0
2353 
  {
2354 
   COORD (740,840)
2355 
  }
2356 
  WIRE  2419, 0, 0
2357 
  {
2358 
   NET 2987
2359 
   VTX 2416, 2418
2360 
  }
2361 
  VTX  2420, 0, 0
2362 
  {
2363 
   COORD (420,840)
2364 
  }
2365 
  WIRE  2421, 0, 0
2366 
  {
2367 
   NET 2987
2368 
   VTX 2418, 2420
2369 
  }
2370 
  VTX  2422, 0, 0
2371 
  {
2372 
   COORD (420,700)
2373 
  }
2374 
  WIRE  2423, 0, 0
2375 
  {
2376 
   NET 2987
2377 
   VTX 2420, 2422
2378 
  }
2379 
  WIRE  2424, 0, 0
2380 
  {
2381 
   NET 2987
2382 
   VTX 2422, 2409
2383 
  }
2384 
  VTX  2425, 0, 0
2385 
  {
2386 
   COORD (740,680)
2387 
  }
2388 
  BUS  2426, 0, 0
2389 
  {
2390 
   NET 146
2391 
   VTX 2410, 2425
2392 
  }
2393 
  VTX  2427, 0, 0
2394 
  {
2395 
   COORD (740,700)
2396 
  }
2397 
  BUS  2428, 0, 0
2398 
  {
2399 
   NET 146
2400 
   VTX 2425, 2427
2401 
  }
2402 
  BUS  2429, 0, 0
2403 
  {
2404 
   NET 146
2405 
   VTX 2427, 2411
2406 
  }
2407 
  VTX  2440, 0, 0
2408 
  {
2409 
   COORD (480,780)
2410 
  }
2411 
  VTX  2441, 0, 0
2412 
  {
2413 
   COORD (300,780)
2414 
  }
2415 
  VTX  2443, 0, 0
2416 
  {
2417 
   COORD (480,740)
2418 
  }
2419 
  VTX  2444, 0, 0
2420 
  {
2421 
   COORD (300,740)
2422 
  }
2423 
  WIRE  2445, 0, 0
2424 
  {
2425 
   NET 1145
2426 
   VTX 2443, 2444
2427 
  }
2428 
  NET BUS  2446, 0, 0
2429 
  VTX  2454, 0, 0
2430 
  {
2431 
   COORD (400,780)
2432 
  }
2433 
  BUS  2455, 0, 0
2434 
  {
2435 
   NET 2465
2436 
   VTX 2440, 2454
2437 
  }
2438 
  BUS  2456, 0, 0
2439 
  {
2440 
   NET 2465
2441 
   VTX 2454, 2441
2442 
  }
2443 
  NET BUS  2465, 0, 0
2444 
  VTX  2615, 0, 0
2445 
  {
2446 
   COORD (2100,840)
2447 
  }
2448 
  VTX  2616, 0, 0
2449 
  {
2450 
   COORD (1860,300)
2451 
  }
2452 
  VTX  2617, 0, 0
2453 
  {
2454 
   COORD (2110,840)
2455 
  }
2456 
  BUS  2618, 0, 0
2457 
  {
2458 
   NET 1015
2459 
   VTX 2615, 2617
2460 
  }
2461 
  VTX  2619, 0, 0
2462 
  {
2463 
   COORD (2110,740)
2464 
  }
2465 
  BUS  2620, 0, 0
2466 
  {
2467 
   NET 1015
2468 
   VTX 2617, 2619
2469 
  }
2470 
  VTX  2621, 0, 0
2471 
  {
2472 
   COORD (1800,740)
2473 
  }
2474 
  BUS  2622, 0, 0
2475 
  {
2476 
   NET 1015
2477 
   VTX 2619, 2621
2478 
  }
2479 
  VTX  2623, 0, 0
2480 
  {
2481 
   COORD (1800,300)
2482 
  }
2483 
  BUS  2624, 0, 0
2484 
  {
2485 
   NET 1015
2486 
   VTX 2621, 2623
2487 
  }
2488 
  BUS  2625, 0, 0
2489 
  {
2490 
   NET 1015
2491 
   VTX 2623, 2616
2492 
  }
2493 
  VTX  2626, 0, 0
2494 
  {
2495 
   COORD (1680,700)
2496 
  }
2497 
  VTX  2627, 0, 0
2498 
  {
2499 
   COORD (1860,220)
2500 
  }
2501 
  VTX  2628, 0, 0
2502 
  {
2503 
   COORD (1700,700)
2504 
  }
2505 
  BUS  2629, 0, 0
2506 
  {
2507 
   NET 609
2508 
   VTX 2626, 2628
2509 
  }
2510 
  VTX  2630, 0, 0
2511 
  {
2512 
   COORD (1700,220)
2513 
  }
2514 
  BUS  2631, 0, 0
2515 
  {
2516 
   NET 609
2517 
   VTX 2628, 2630
2518 
  }
2519 
  BUS  2632, 0, 0
2520 
  {
2521 
   NET 609
2522 
   VTX 2630, 2627
2523 
  }
2524 
  VTX  2672, 0, 0
2525 
  {
2526 
   COORD (280,600)
2527 
  }
2528 
  VTX  2673, 0, 0
2529 
  {
2530 
   COORD (400,680)
2531 
  }
2532 
  BUS  2674, 0, 0
2533 
  {
2534 
   NET 2465
2535 
   VTX 2454, 2673
2536 
  }
2537 
  VTX  2675, 0, 0
2538 
  {
2539 
   COORD (270,680)
2540 
  }
2541 
  BUS  2676, 0, 0
2542 
  {
2543 
   NET 2465
2544 
   VTX 2673, 2675
2545 
  }
2546 
  VTX  2677, 0, 0
2547 
  {
2548 
   COORD (270,600)
2549 
  }
2550 
  BUS  2678, 0, 0
2551 
  {
2552 
   NET 2465
2553 
   VTX 2675, 2677
2554 
  }
2555 
  BUS  2679, 0, 0
2556 
  {
2557 
   NET 2465
2558 
   VTX 2677, 2672
2559 
  }
2560 
  VTX  2813, 0, 0
2561 
  {
2562 
   COORD (900,640)
2563 
  }
2564 
  VTX  2814, 0, 0
2565 
  {
2566 
   COORD (300,440)
2567 
  }
2568 
  VTX  2815, 0, 0
2569 
  {
2570 
   COORD (780,640)
2571 
  }
2572 
  BUS  2816, 0, 0
2573 
  {
2574 
   NET 421
2575 
   VTX 2813, 2815
2576 
  }
2577 
  VTX  2817, 0, 0
2578 
  {
2579 
   COORD (780,440)
2580 
  }
2581 
  BUS  2818, 0, 0
2582 
  {
2583 
   NET 421
2584 
   VTX 2815, 2817
2585 
  }
2586 
  BUS  2819, 0, 0
2587 
  {
2588 
   NET 421
2589 
   VTX 2817, 2814
2590 
  }
2591 
  VTX  2820, 0, 0
2592 
  {
2593 
   COORD (280,500)
2594 
  }
2595 
  VTX  2821, 0, 0
2596 
  {
2597 
   COORD (740,500)
2598 
  }
2599 
  BUS  2822, 0, 0
2600 
  {
2601 
   NET 146
2602 
   VTX 2425, 2821
2603 
  }
2604 
  BUS  2823, 0, 0
2605 
  {
2606 
   NET 146
2607 
   VTX 2821, 2820
2608 
  }
2609 
  INSTANCE  2824, 0, 0
2610 
  {
2611 
   VARIABLES
2612 
   {
2613 
    #COMPONENT="BusOutput"
2614 
    #LIBRARY="#terminals"
2615 
    #REFERENCE="zz_spc_o(31:0)"
2616 
    #SYMBOL="BusOutput"
2617 
   }
2618 
   COORD (280,500)
2619 
   ORIENTATION 2
2620 
   VERTEXES ( (2,2820) )
2621 
  }
2622 
  TEXT  2825, 0, 0
2623 
  {
2624 
   TEXT "$#REFERENCE"
2625 
   RECT (-12,483,228,518)
2626 
   ALIGN 6
2627 
   MARGINS (1,1)
2628 
   PARENT 2824
2629 
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2630 
  VTX  2977, 0, 0
2631 
  {
2632 
   COORD (500,620)
2633 
  }
2634 
  VTX  2978, 0, 0
2635 
  {
2636 
   COORD (900,600)
2637 
  }
2638 
  VTX  2979, 0, 0
2639 
  {
2640 
   COORD (720,600)
2641 
  }
2642 
  VTX  2980, 0, 0
2643 
  {
2644 
   COORD (480,600)
2645 
  }
2646 
  VTX  2981, 0, 0
2647 
  {
2648 
   COORD (500,600)
2649 
  }
2650 
  VTX  2982, 0, 0
2651 
  {
2652 
   COORD (480,620)
2653 
  }
2654 
  WIRE  2983, 0, 0
2655 
  {
2656 
   NET 2987
2657 
   VTX 2409, 2982
2658 
  }
2659 
  WIRE  2984, 0, 0
2660 
  {
2661 
   NET 2987
2662 
   VTX 2982, 2977
2663 
  }
2664 
  BUS  2985, 0, 0
2665 
  {
2666 
   NET 2332
2667 
   VTX 2978, 2979
2668 
  }
2669 
  BUS  2986, 0, 0
2670 
  {
2671 
   NET 2446
2672 
   VTX 2980, 2981
2673 
  }
2674 
  NET WIRE  2987, 0, 0
2675 
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2676 
 
2677 
}
2678 
 
2679 
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2683 
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2684 
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2689 
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2691 
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2692 
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2693 
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