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URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [dbe/] [forward.BDE] - Blame information for rev 59

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 1671
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="forward2"
12 
  AUTHOR="YlmF"
13 
  COMPANY="WwW.YlmF.CoM"
14 
  CREATIONDATE="2008-8-10"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "forward_node" "forward_node"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1218305310"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,320,240)
33 
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34 
   }
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36 
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   {
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    RECT  1, -1, 0
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    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
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    TEXT  3, 0, 0
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     TEXT "$#NAME"
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     RECT (25,30,93,54)
50 
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    {
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     TEXT "$#NAME"
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     RECT (172,30,295,54)
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    {
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     TEXT "$#NAME"
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     RECT (25,70,181,94)
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     ALIGN 4
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    TEXT  9, 0, 0
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    {
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     TEXT "$#NAME"
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     RECT (25,110,93,134)
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     ALIGN 4
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     MARGINS (1,1)
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     PARENT 8
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    }
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    TEXT  11, 0, 0
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    {
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     TEXT "$#NAME"
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    TEXT  13, 0, 0
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    {
88 
     TEXT "$#NAME"
89 
     RECT (25,190,104,214)
90 
     ALIGN 4
91 
     MARGINS (1,1)
92 
     PARENT 12
93 
    }
94 
    PIN  2, 0, 0
95 
    {
96 
     COORD (0,40)
97 
     VARIABLES
98 
     {
99 
      #DIRECTION="IN"
100 
      #LENGTH="20"
101 
      #MDA_RECORD_TOKEN="OTHER"
102 
      #NAME="alu_we"
103 
      #NUMBER="0"
104 
      #VERILOG_TYPE="wire"
105 
     }
106 
     LINE  2, 0, 0
107 
     {
108 
      POINTS ( (0,0), (20,0) )
109 
     }
110 
    }
111 
    PIN  4, 0, 0
112 
    {
113 
     COORD (320,40)
114 
     VARIABLES
115 
     {
116 
      #DIRECTION="OUT"
117 
      #DOWNTO="1"
118 
      #LENGTH="20"
119 
      #MDA_RECORD_TOKEN="OTHER"
120 
      #NAME="mux_fw(2:0)"
121 
      #NUMBER="0"
122 
      #VERILOG_TYPE="wire"
123 
     }
124 
     LINE  2, 0, 0
125 
     {
126 
      POINTS ( (-20,0), (0,0) )
127 
     }
128 
    }
129 
    PIN  6, 0, 0
130 
    {
131 
     COORD (0,80)
132 
     VARIABLES
133 
     {
134 
      #DIRECTION="IN"
135 
      #DOWNTO="1"
136 
      #LENGTH="20"
137 
      #MDA_RECORD_TOKEN="OTHER"
138 
      #NAME="alu_wr_rn(4:0)"
139 
      #NUMBER="0"
140 
      #VERILOG_TYPE="wire"
141 
     }
142 
     LINE  2, 0, 0
143 
     {
144 
      POINTS ( (0,0), (20,0) )
145 
     }
146 
    }
147 
    PIN  8, 0, 0
148 
    {
149 
     COORD (0,120)
150 
     VARIABLES
151 
     {
152 
      #DIRECTION="IN"
153 
      #LENGTH="20"
154 
      #MDA_RECORD_TOKEN="OTHER"
155 
      #NAME="mem_we"
156 
      #NUMBER="0"
157 
      #VERILOG_TYPE="wire"
158 
     }
159 
     LINE  2, 0, 0
160 
     {
161 
      POINTS ( (0,0), (20,0) )
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     }
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    }
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    PIN  10, 0, 0
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    {
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     COORD (0,160)
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     VARIABLES
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     {
169 
      #DIRECTION="IN"
170 
      #DOWNTO="1"
171 
      #LENGTH="20"
172 
      #MDA_RECORD_TOKEN="OTHER"
173 
      #NAME="mem_wr_rn(4:0)"
174 
      #NUMBER="0"
175 
      #VERILOG_TYPE="wire"
176 
     }
177 
     LINE  2, 0, 0
178 
     {
179 
      POINTS ( (0,0), (20,0) )
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     }
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    }
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    PIN  12, 0, 0
183 
    {
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     COORD (0,200)
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     VARIABLES
186 
     {
187 
      #DIRECTION="IN"
188 
      #DOWNTO="1"
189 
      #LENGTH="20"
190 
      #MDA_RECORD_TOKEN="OTHER"
191 
      #NAME="rn(4:0)"
192 
      #NUMBER="0"
193 
      #VERILOG_TYPE="wire"
194 
     }
195 
     LINE  2, 0, 0
196 
     {
197 
      POINTS ( (0,0), (20,0) )
198 
     }
199 
    }
200 
   }
201 
  }
202 
 }
203 
 SYMBOL "#default" "fw_latch5" "fw_latch5"
204 
 {
205 
  HEADER
206 
  {
207 
   VARIABLES
208 
   {
209 
    #DESCRIPTION=""
210 
    #LANGUAGE="VERILOG"
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    {
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     VARIABLES
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     {
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     TEXT "$#NAME"
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     ALIGN 4
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     PARENT 6
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    }
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    PIN  2, 0, 0
257 
    {
258 
     COORD (0,40)
259 
     VARIABLES
260 
     {
261 
      #DIRECTION="IN"
262 
      #LENGTH="20"
263 
      #MDA_RECORD_TOKEN="OTHER"
264 
      #NAME="clk"
265 
      #NUMBER="0"
266 
      #VERILOG_TYPE="wire"
267 
     }
268 
     LINE  2, 0, 0
269 
     {
270 
      POINTS ( (0,0), (20,0) )
271 
     }
272 
    }
273 
    PIN  4, 0, 0
274 
    {
275 
     COORD (160,40)
276 
     VARIABLES
277 
     {
278 
      #DIRECTION="OUT"
279 
      #DOWNTO="1"
280 
      #LENGTH="20"
281 
      #MDA_RECORD_TOKEN="OTHER"
282 
      #NAME="q(4:0)"
283 
      #NUMBER="0"
284 
      #VERILOG_TYPE="reg"
285 
     }
286 
     LINE  2, 0, 0
287 
     {
288 
      POINTS ( (-20,0), (0,0) )
289 
     }
290 
    }
291 
    PIN  6, 0, 0
292 
    {
293 
     COORD (0,80)
294 
     VARIABLES
295 
     {
296 
      #DIRECTION="IN"
297 
      #DOWNTO="1"
298 
      #LENGTH="20"
299 
      #MDA_RECORD_TOKEN="OTHER"
300 
      #NAME="d(4:0)"
301 
      #NUMBER="0"
302 
      #VERILOG_TYPE="wire"
303 
     }
304 
     LINE  2, 0, 0
305 
     {
306 
      POINTS ( (0,0), (20,0) )
307 
     }
308 
    }
309 
   }
310 
  }
311 
 }
312 
}
313 
 
314 
PAGE ""
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323 
 BODY
324 
 {
325 
  INSTANCE  56, 0, 0
326 
  {
327 
   VARIABLES
328 
   {
329 
    #COMPONENT="Input"
330 
    #LIBRARY="#terminals"
331 
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332 
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333 
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346 
  {
347 
   VARIABLES
348 
   {
349 
    #COMPONENT="forward_node"
350 
    #LIBRARY="#default"
351 
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352 
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353 
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  INSTANCE  78, 0, 0
373 
  {
374 
   VARIABLES
375 
   {
376 
    #COMPONENT="fw_latch5"
377 
    #LIBRARY="#default"
378 
    #REFERENCE="fw_reg_rns"
379 
    #SYMBOL="fw_latch5"
380 
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   COORD (1360,560)
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   RECT (1360,680,1515,715)
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398 
  }
399 
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400 
  INSTANCE  94, 0, 0
401 
  {
402 
   VARIABLES
403 
   {
404 
    #COMPONENT="forward_node"
405 
    #LIBRARY="#default"
406 
    #REFERENCE="fw_cmp_rs"
407 
    #SYMBOL="forward_node"
408 
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  {
429 
   VARIABLES
430 
   {
431 
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432 
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433 
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434 
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435 
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456 
   VARIABLES
457 
   {
458 
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459 
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461 
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462 
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483 
   VARIABLES
484 
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485 
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486 
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487 
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488 
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489 
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507 
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510 
   VARIABLES
511 
   {
512 
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513 
    #LIBRARY="#terminals"
514 
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515 
    #SYMBOL="BusInput"
516 
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517 
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531 
   VARIABLES
532 
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533 
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534 
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535 
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536 
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537 
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573 
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593 
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594 
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596 
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597 
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612 
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613 
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614 
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615 
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616 
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617 
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639 
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640 
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641 
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642 
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643 
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644 
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   VARIABLES
660 
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661 
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662 
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663 
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664 
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665 
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666 
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682 
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683 
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684 
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685 
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686 
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687 
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701 
  {
702 
   VARIABLES
703 
   {
704 
    #COMPONENT="BusOutput"
705 
    #LIBRARY="#terminals"
706 
    #REFERENCE="dmem_fw(2:0)"
707 
    #SYMBOL="BusOutput"
708 
    #VERILOG_TYPE="wire"
709 
   }
710 
   COORD (2060,1200)
711 
   VERTEXES ( (2,1541) )
712 
  }
713 
  TEXT  625, 0, 0
714 
  {
715 
   TEXT "$#REFERENCE"
716 
   RECT (2112,1183,2318,1218)
717 
   ALIGN 4
718 
   MARGINS (1,1)
719 
   PARENT 624
720 
  }
721 
  INSTANCE  633, 0, 0
722 
  {
723 
   VARIABLES
724 
   {
725 
    #COMPONENT="BusOutput"
726 
    #LIBRARY="#terminals"
727 
    #REFERENCE="alu_rs_fw(2:0)"
728 
    #SYMBOL="BusOutput"
729 
    #VERILOG_TYPE="wire"
730 
   }
731 
   COORD (2040,440)
732 
   VERTEXES ( (2,1519) )
733 
  }
734 
  TEXT  634, 0, 0
735 
  {
736 
   TEXT "$#REFERENCE"
737 
   RECT (2092,423,2332,458)
738 
   ALIGN 4
739 
   MARGINS (1,1)
740 
   PARENT 633
741 
  }
742 
  NET BUS  635, 0, 0
743 
  NET BUS  937, 0, 0
744 
  NET BUS  1100, 0, 0
745 
  NET BUS  1163, 0, 0
746 
  NET WIRE  1175, 0, 0
747 
  NET BUS  1345, 0, 0
748 
  VTX  1486, 0, 0
749 
  {
750 
   COORD (1640,600)
751 
  }
752 
  VTX  1487, 0, 0
753 
  {
754 
   COORD (1520,600)
755 
  }
756 
  VTX  1488, 0, 0
757 
  {
758 
   COORD (1340,1120)
759 
  }
760 
  VTX  1489, 0, 0
761 
  {
762 
   COORD (1360,600)
763 
  }
764 
  VTX  1490, 0, 0
765 
  {
766 
   COORD (1360,1220)
767 
  }
768 
  VTX  1491, 0, 0
769 
  {
770 
   COORD (1640,440)
771 
  }
772 
  VTX  1492, 0, 0
773 
  {
774 
   COORD (1300,740)
775 
  }
776 
  VTX  1493, 0, 0
777 
  {
778 
   COORD (1640,740)
779 
  }
780 
  VTX  1494, 0, 0
781 
  {
782 
   COORD (1460,740)
783 
  }
784 
  VTX  1495, 0, 0
785 
  {
786 
   COORD (1580,1060)
787 
  }
788 
  VTX  1496, 0, 0
789 
  {
790 
   COORD (1640,1060)
791 
  }
792 
  VTX  1497, 0, 0
793 
  {
794 
   COORD (1640,1380)
795 
  }
796 
  VTX  1498, 0, 0
797 
  {
798 
   COORD (1560,780)
799 
  }
800 
  VTX  1499, 0, 0
801 
  {
802 
   COORD (1640,780)
803 
  }
804 
  VTX  1500, 0, 0
805 
  {
806 
   COORD (1640,480)
807 
  }
808 
  VTX  1501, 0, 0
809 
  {
810 
   COORD (1640,1100)
811 
  }
812 
  VTX  1502, 0, 0
813 
  {
814 
   COORD (1560,1100)
815 
  }
816 
  VTX  1503, 0, 0
817 
  {
818 
   COORD (1640,1420)
819 
  }
820 
  VTX  1504, 0, 0
821 
  {
822 
   COORD (1600,820)
823 
  }
824 
  VTX  1505, 0, 0
825 
  {
826 
   COORD (1640,820)
827 
  }
828 
  VTX  1506, 0, 0
829 
  {
830 
   COORD (1640,520)
831 
  }
832 
  VTX  1507, 0, 0
833 
  {
834 
   COORD (1640,1140)
835 
  }
836 
  VTX  1508, 0, 0
837 
  {
838 
   COORD (1600,1140)
839 
  }
840 
  VTX  1509, 0, 0
841 
  {
842 
   COORD (1640,1460)
843 
  }
844 
  VTX  1510, 0, 0
845 
  {
846 
   COORD (1640,560)
847 
  }
848 
  VTX  1511, 0, 0
849 
  {
850 
   COORD (1540,860)
851 
  }
852 
  VTX  1512, 0, 0
853 
  {
854 
   COORD (1640,860)
855 
  }
856 
  VTX  1513, 0, 0
857 
  {
858 
   COORD (1360,640)
859 
  }
860 
  VTX  1514, 0, 0
861 
  {
862 
   COORD (1320,640)
863 
  }
864 
  VTX  1515, 0, 0
865 
  {
866 
   COORD (1360,1260)
867 
  }
868 
  VTX  1516, 0, 0
869 
  {
870 
   COORD (1340,1260)
871 
  }
872 
  VTX  1517, 0, 0
873 
  {
874 
   COORD (1640,1540)
875 
  }
876 
  VTX  1518, 0, 0
877 
  {
878 
   COORD (1960,440)
879 
  }
880 
  VTX  1519, 0, 0
881 
  {
882 
   COORD (2040,440)
883 
  }
884 
  VTX  1520, 0, 0
885 
  {
886 
   COORD (1960,1380)
887 
  }
888 
  VTX  1521, 0, 0
889 
  {
890 
   COORD (2040,1380)
891 
  }
892 
  VTX  1522, 0, 0
893 
  {
894 
   COORD (1180,640)
895 
  }
896 
  VTX  1523, 0, 0
897 
  {
898 
   COORD (1180,740)
899 
  }
900 
  VTX  1524, 0, 0
901 
  {
902 
   COORD (1180,1260)
903 
  }
904 
  VTX  1525, 0, 0
905 
  {
906 
   COORD (1540,980)
907 
  }
908 
  VTX  1526, 0, 0
909 
  {
910 
   COORD (1640,1180)
911 
  }
912 
  VTX  1527, 0, 0
913 
  {
914 
   COORD (1180,820)
915 
  }
916 
  VTX  1528, 0, 0
917 
  {
918 
   COORD (1180,780)
919 
  }
920 
  VTX  1529, 0, 0
921 
  {
922 
   COORD (1180,980)
923 
  }
924 
  VTX  1530, 0, 0
925 
  {
926 
   COORD (1300,980)
927 
  }
928 
  VTX  1531, 0, 0
929 
  {
930 
   COORD (1640,1500)
931 
  }
932 
  VTX  1532, 0, 0
933 
  {
934 
   COORD (1640,900)
935 
  }
936 
  VTX  1533, 0, 0
937 
  {
938 
   COORD (2060,740)
939 
  }
940 
  VTX  1534, 0, 0
941 
  {
942 
   COORD (1960,740)
943 
  }
944 
  VTX  1535, 0, 0
945 
  {
946 
   COORD (1180,1120)
947 
  }
948 
  VTX  1536, 0, 0
949 
  {
950 
   COORD (1640,1220)
951 
  }
952 
  VTX  1537, 0, 0
953 
  {
954 
   COORD (1520,1220)
955 
  }
956 
  VTX  1538, 0, 0
957 
  {
958 
   COORD (2060,1060)
959 
  }
960 
  VTX  1539, 0, 0
961 
  {
962 
   COORD (2020,1060)
963 
  }
964 
  VTX  1540, 0, 0
965 
  {
966 
   COORD (1960,1060)
967 
  }
968 
  VTX  1541, 0, 0
969 
  {
970 
   COORD (2060,1200)
971 
  }
972 
  BUS  1542, 0, 0
973 
  {
974 
   NET 82
975 
   VTX 1486, 1487
976 
  }
977 
  VTX  1543, 0, 0
978 
  {
979 
   COORD (1340,600)
980 
  }
981 
  WIRE  1544, 0, 0
982 
  {
983 
   NET 1175
984 
   VTX 1488, 1543
985 
  }
986 
  WIRE  1545, 0, 0
987 
  {
988 
   NET 1175
989 
   VTX 1543, 1489
990 
  }
991 
  VTX  1546, 0, 0
992 
  {
993 
   COORD (1340,1220)
994 
  }
995 
  WIRE  1547, 0, 0
996 
  {
997 
   NET 1175
998 
   VTX 1488, 1546
999 
  }
1000 
  WIRE  1548, 0, 0
1001 
  {
1002 
   NET 1175
1003 
   VTX 1546, 1490
1004 
  }
1005 
  VTX  1549, 0, 0
1006 
  {
1007 
   COORD (1300,440)
1008 
  }
1009 
  WIRE  1550, 0, 0
1010 
  {
1011 
   NET 410
1012 
   VTX 1491, 1549
1013 
  }
1014 
  WIRE  1551, 0, 0
1015 
  {
1016 
   NET 410
1017 
   VTX 1549, 1492
1018 
  }
1019 
  WIRE  1552, 0, 0
1020 
  {
1021 
   NET 410
1022 
   VTX 1493, 1494
1023 
  }
1024 
  WIRE  1553, 0, 0
1025 
  {
1026 
   NET 410
1027 
   VTX 1494, 1492
1028 
  }
1029 
  VTX  1554, 0, 0
1030 
  {
1031 
   COORD (1460,1060)
1032 
  }
1033 
  WIRE  1555, 0, 0
1034 
  {
1035 
   NET 410
1036 
   VTX 1494, 1554
1037 
  }
1038 
  WIRE  1556, 0, 0
1039 
  {
1040 
   NET 410
1041 
   VTX 1554, 1495
1042 
  }
1043 
  WIRE  1557, 0, 0
1044 
  {
1045 
   NET 410
1046 
   VTX 1495, 1496
1047 
  }
1048 
  VTX  1558, 0, 0
1049 
  {
1050 
   COORD (1580,1380)
1051 
  }
1052 
  WIRE  1559, 0, 0
1053 
  {
1054 
   NET 410
1055 
   VTX 1495, 1558
1056 
  }
1057 
  WIRE  1560, 0, 0
1058 
  {
1059 
   NET 410
1060 
   VTX 1558, 1497
1061 
  }
1062 
  BUS  1561, 0, 0
1063 
  {
1064 
   NET 447
1065 
   VTX 1498, 1499
1066 
  }
1067 
  VTX  1562, 0, 0
1068 
  {
1069 
   COORD (1560,480)
1070 
  }
1071 
  BUS  1563, 0, 0
1072 
  {
1073 
   NET 447
1074 
   VTX 1500, 1562
1075 
  }
1076 
  BUS  1564, 0, 0
1077 
  {
1078 
   NET 447
1079 
   VTX 1562, 1498
1080 
  }
1081 
  BUS  1565, 0, 0
1082 
  {
1083 
   NET 447
1084 
   VTX 1501, 1502
1085 
  }
1086 
  BUS  1566, 0, 0
1087 
  {
1088 
   NET 447
1089 
   VTX 1502, 1498
1090 
  }
1091 
  VTX  1567, 0, 0
1092 
  {
1093 
   COORD (1560,1420)
1094 
  }
1095 
  BUS  1568, 0, 0
1096 
  {
1097 
   NET 447
1098 
   VTX 1503, 1567
1099 
  }
1100 
  BUS  1569, 0, 0
1101 
  {
1102 
   NET 447
1103 
   VTX 1567, 1502
1104 
  }
1105 
  WIRE  1570, 0, 0
1106 
  {
1107 
   NET 472
1108 
   VTX 1504, 1505
1109 
  }
1110 
  VTX  1571, 0, 0
1111 
  {
1112 
   COORD (1600,520)
1113 
  }
1114 
  WIRE  1572, 0, 0
1115 
  {
1116 
   NET 472
1117 
   VTX 1506, 1571
1118 
  }
1119 
  WIRE  1573, 0, 0
1120 
  {
1121 
   NET 472
1122 
   VTX 1571, 1504
1123 
  }
1124 
  WIRE  1574, 0, 0
1125 
  {
1126 
   NET 472
1127 
   VTX 1507, 1508
1128 
  }
1129 
  WIRE  1575, 0, 0
1130 
  {
1131 
   NET 472
1132 
   VTX 1508, 1504
1133 
  }
1134 
  VTX  1576, 0, 0
1135 
  {
1136 
   COORD (1600,1460)
1137 
  }
1138 
  WIRE  1577, 0, 0
1139 
  {
1140 
   NET 472
1141 
   VTX 1508, 1576
1142 
  }
1143 
  WIRE  1578, 0, 0
1144 
  {
1145 
   NET 472
1146 
   VTX 1576, 1509
1147 
  }
1148 
  VTX  1579, 0, 0
1149 
  {
1150 
   COORD (1540,560)
1151 
  }
1152 
  BUS  1580, 0, 0
1153 
  {
1154 
   NET 1100
1155 
   VTX 1510, 1579
1156 
  }
1157 
  BUS  1581, 0, 0
1158 
  {
1159 
   NET 1100
1160 
   VTX 1579, 1511
1161 
  }
1162 
  BUS  1582, 0, 0
1163 
  {
1164 
   NET 1100
1165 
   VTX 1512, 1511
1166 
  }
1167 
  BUS  1583, 0, 0
1168 
  {
1169 
   NET 550
1170 
   VTX 1513, 1514
1171 
  }
1172 
  BUS  1584, 0, 0
1173 
  {
1174 
   NET 559
1175 
   VTX 1515, 1516
1176 
  }
1177 
  VTX  1585, 0, 0
1178 
  {
1179 
   COORD (1340,1540)
1180 
  }
1181 
  BUS  1586, 0, 0
1182 
  {
1183 
   NET 559
1184 
   VTX 1516, 1585
1185 
  }
1186 
  BUS  1587, 0, 0
1187 
  {
1188 
   NET 559
1189 
   VTX 1585, 1517
1190 
  }
1191 
  BUS  1588, 0, 0
1192 
  {
1193 
   NET 635
1194 
   VTX 1518, 1519
1195 
  }
1196 
  BUS  1589, 0, 0
1197 
  {
1198 
   NET 620
1199 
   VTX 1520, 1521
1200 
  }
1201 
  BUS  1590, 0, 0
1202 
  {
1203 
   NET 550
1204 
   VTX 1514, 1522
1205 
  }
1206 
  WIRE  1591, 0, 0
1207 
  {
1208 
   NET 410
1209 
   VTX 1492, 1523
1210 
  }
1211 
  BUS  1592, 0, 0
1212 
  {
1213 
   NET 559
1214 
   VTX 1516, 1524
1215 
  }
1216 
  VTX  1593, 0, 0
1217 
  {
1218 
   COORD (1540,1180)
1219 
  }
1220 
  BUS  1594, 0, 0
1221 
  {
1222 
   NET 1100
1223 
   VTX 1525, 1593
1224 
  }
1225 
  BUS  1595, 0, 0
1226 
  {
1227 
   NET 1100
1228 
   VTX 1593, 1526
1229 
  }
1230 
  WIRE  1596, 0, 0
1231 
  {
1232 
   NET 472
1233 
   VTX 1504, 1527
1234 
  }
1235 
  BUS  1597, 0, 0
1236 
  {
1237 
   NET 447
1238 
   VTX 1498, 1528
1239 
  }
1240 
  BUS  1598, 0, 0
1241 
  {
1242 
   NET 1100
1243 
   VTX 1525, 1511
1244 
  }
1245 
  BUS  1599, 0, 0
1246 
  {
1247 
   NET 1100
1248 
   VTX 1529, 1530
1249 
  }
1250 
  BUS  1600, 0, 0
1251 
  {
1252 
   NET 1100
1253 
   VTX 1530, 1525
1254 
  }
1255 
  VTX  1601, 0, 0
1256 
  {
1257 
   COORD (1300,1500)
1258 
  }
1259 
  BUS  1602, 0, 0
1260 
  {
1261 
   NET 1100
1262 
   VTX 1531, 1601
1263 
  }
1264 
  BUS  1603, 0, 0
1265 
  {
1266 
   NET 1100
1267 
   VTX 1601, 1530
1268 
  }
1269 
  VTX  1604, 0, 0
1270 
  {
1271 
   COORD (1320,900)
1272 
  }
1273 
  BUS  1605, 0, 0
1274 
  {
1275 
   NET 550
1276 
   VTX 1514, 1604
1277 
  }
1278 
  BUS  1606, 0, 0
1279 
  {
1280 
   NET 550
1281 
   VTX 1604, 1532
1282 
  }
1283 
  BUS  1607, 0, 0
1284 
  {
1285 
   NET 1163
1286 
   VTX 1533, 1534
1287 
  }
1288 
  WIRE  1608, 0, 0
1289 
  {
1290 
   NET 1175
1291 
   VTX 1488, 1535
1292 
  }
1293 
  BUS  1609, 0, 0
1294 
  {
1295 
   NET 937
1296 
   VTX 1536, 1537
1297 
  }
1298 
  BUS  1610, 0, 0
1299 
  {
1300 
   NET 1345
1301 
   VTX 1538, 1539
1302 
  }
1303 
  BUS  1611, 0, 0
1304 
  {
1305 
   NET 1345
1306 
   VTX 1539, 1540
1307 
  }
1308 
  VTX  1612, 0, 0
1309 
  {
1310 
   COORD (2020,1200)
1311 
  }
1312 
  BUS  1613, 0, 0
1313 
  {
1314 
   NET 1345
1315 
   VTX 1539, 1612
1316 
  }
1317 
  BUS  1614, 0, 0
1318 
  {
1319 
   NET 1345
1320 
   VTX 1612, 1541
1321 
  }
1322 
 }
1323 
 
1324 
}
1325 
 
1326 
PAGE ""
1327 
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1329 
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   TEXT "Created:"
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1359 
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1361 
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