OpenCores
URL https://opencores.org/ocsvn/mips789/mips789/trunk

Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [dbe/] [mips_led.BDE] - Blame information for rev 53

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Line No. Rev Author Line
1 2 mcupro 
SCHM0103
2 
 
3 
HEADER
4 
{
5 
 FREEID 3011
6 
 VARIABLES
7 
 {
8 
  #BLOCKTABLE_FILE="#table.bde"
9 
  #BLOCKTABLE_INCLUDED="1"
10 
  #LANGUAGE="VERILOG"
11 
  #MODULE="mips_top123"
12 
  AUTHOR="YlmF"
13 
  COMPANY="WwW.YlmF.CoM"
14 
  CREATIONDATE="2008-8-13"
15 
  TITLE="No Title"
16 
 }
17 
 SYMBOL "#default" "mem_array" "mem_array"
18 
 {
19 
  HEADER
20 
  {
21 
   VARIABLES
22 
   {
23 
    #DESCRIPTION=""
24 
    #LANGUAGE="VERILOG"
25 
    #MODIFIED="1218631627"
26 
   }
27 
  }
28 
  PAGE ""
29 
  {
30 
   PAGEHEADER
31 
   {
32 
    RECT (0,0,300,280)
33 
    FREEID 19
34 
   }
35 
 
36 
   BODY
37 
   {
38 
    RECT  1, -1, 0
39 
    {
40 
     VARIABLES
41 
     {
42 
      #OUTLINE_FILLING="1"
43 
     }
44 
     AREA (20,0,280,280)
45 
    }
46 
    TEXT  3, 0, 0
47 
    {
48 
     TEXT "$#NAME"
49 
     RECT (25,30,60,54)
50 
     ALIGN 4
51 
     MARGINS (1,1)
52 
     PARENT 2
53 
    }
54 
    TEXT  5, 0, 0
55 
    {
56 
     TEXT "$#NAME"
57 
     RECT (163,30,275,54)
58 
     ALIGN 6
59 
     MARGINS (1,1)
60 
     PARENT 4
61 
    }
62 
    TEXT  7, 0, 0
63 
    {
64 
     TEXT "$#NAME"
65 
     RECT (25,70,126,94)
66 
     ALIGN 4
67 
     MARGINS (1,1)
68 
     PARENT 6
69 
    }
70 
    TEXT  9, 0, 0
71 
    {
72 
     TEXT "$#NAME"
73 
     RECT (152,70,275,94)
74 
     ALIGN 6
75 
     MARGINS (1,1)
76 
     PARENT 8
77 
    }
78 
    TEXT  11, 0, 0
79 
    {
80 
     TEXT "$#NAME"
81 
     RECT (25,110,137,134)
82 
     ALIGN 4
83 
     MARGINS (1,1)
84 
     PARENT 10
85 
    }
86 
    TEXT  13, 0, 0
87 
    {
88 
     TEXT "$#NAME"
89 
     RECT (25,150,192,174)
90 
     ALIGN 4
91 
     MARGINS (1,1)
92 
     PARENT 12
93 
    }
94 
    TEXT  15, 0, 0
95 
    {
96 
     TEXT "$#NAME"
97 
     RECT (25,190,192,214)
98 
     ALIGN 4
99 
     MARGINS (1,1)
100 
     PARENT 14
101 
    }
102 
    TEXT  17, 0, 0
103 
    {
104 
     TEXT "$#NAME"
105 
     RECT (25,230,126,254)
106 
     ALIGN 4
107 
     MARGINS (1,1)
108 
     PARENT 16
109 
    }
110 
    PIN  2, 0, 0
111 
    {
112 
     COORD (0,40)
113 
     VARIABLES
114 
     {
115 
      #DIRECTION="IN"
116 
      #LENGTH="20"
117 
      #MDA_RECORD_TOKEN="OTHER"
118 
      #NAME="clk"
119 
      #NUMBER="0"
120 
      #VERILOG_TYPE="wire"
121 
     }
122 
     LINE  2, 0, 0
123 
     {
124 
      POINTS ( (0,0), (20,0) )
125 
     }
126 
    }
127 
    PIN  4, 0, 0
128 
    {
129 
     COORD (300,40)
130 
     VARIABLES
131 
     {
132 
      #DIRECTION="OUT"
133 
      #DOWNTO="1"
134 
      #LENGTH="20"
135 
      #MDA_RECORD_TOKEN="OTHER"
136 
      #NAME="dout(31:0)"
137 
      #NUMBER="0"
138 
      #VERILOG_TYPE="wire"
139 
     }
140 
     LINE  2, 0, 0
141 
     {
142 
      POINTS ( (-20,0), (0,0) )
143 
     }
144 
    }
145 
    PIN  6, 0, 0
146 
    {
147 
     COORD (0,80)
148 
     VARIABLES
149 
     {
150 
      #DIRECTION="IN"
151 
      #DOWNTO="1"
152 
      #LENGTH="20"
153 
      #MDA_RECORD_TOKEN="OTHER"
154 
      #NAME="din(31:0)"
155 
      #NUMBER="0"
156 
      #VERILOG_TYPE="wire"
157 
     }
158 
     LINE  2, 0, 0
159 
     {
160 
      POINTS ( (0,0), (20,0) )
161 
     }
162 
    }
163 
    PIN  8, 0, 0
164 
    {
165 
     COORD (300,80)
166 
     VARIABLES
167 
     {
168 
      #DIRECTION="OUT"
169 
      #DOWNTO="1"
170 
      #LENGTH="20"
171 
      #MDA_RECORD_TOKEN="OTHER"
172 
      #NAME="ins_o(31:0)"
173 
      #NUMBER="0"
174 
      #VERILOG_TYPE="wire"
175 
     }
176 
     LINE  2, 0, 0
177 
     {
178 
      POINTS ( (-20,0), (0,0) )
179 
     }
180 
    }
181 
    PIN  10, 0, 0
182 
    {
183 
     COORD (0,120)
184 
     VARIABLES
185 
     {
186 
      #DIRECTION="IN"
187 
      #DOWNTO="1"
188 
      #LENGTH="20"
189 
      #MDA_RECORD_TOKEN="OTHER"
190 
      #NAME="pc_i(31:0)"
191 
      #NUMBER="0"
192 
      #VERILOG_TYPE="wire"
193 
     }
194 
     LINE  2, 0, 0
195 
     {
196 
      POINTS ( (0,0), (20,0) )
197 
     }
198 
    }
199 
    PIN  12, 0, 0
200 
    {
201 
     COORD (0,160)
202 
     VARIABLES
203 
     {
204 
      #DIRECTION="IN"
205 
      #DOWNTO="1"
206 
      #LENGTH="20"
207 
      #MDA_RECORD_TOKEN="OTHER"
208 
      #NAME="rd_addr_i(31:0)"
209 
      #NUMBER="0"
210 
      #VERILOG_TYPE="wire"
211 
     }
212 
     LINE  2, 0, 0
213 
     {
214 
      POINTS ( (0,0), (20,0) )
215 
     }
216 
    }
217 
    PIN  14, 0, 0
218 
    {
219 
     COORD (0,200)
220 
     VARIABLES
221 
     {
222 
      #DIRECTION="IN"
223 
      #DOWNTO="1"
224 
      #LENGTH="20"
225 
      #MDA_RECORD_TOKEN="OTHER"
226 
      #NAME="wr_addr_i(31:0)"
227 
      #NUMBER="0"
228 
      #VERILOG_TYPE="wire"
229 
     }
230 
     LINE  2, 0, 0
231 
     {
232 
      POINTS ( (0,0), (20,0) )
233 
     }
234 
    }
235 
    PIN  16, 0, 0
236 
    {
237 
     COORD (0,240)
238 
     VARIABLES
239 
     {
240 
      #DIRECTION="IN"
241 
      #DOWNTO="1"
242 
      #LENGTH="20"
243 
      #MDA_RECORD_TOKEN="OTHER"
244 
      #NAME="wren(3:0)"
245 
      #NUMBER="0"
246 
      #VERILOG_TYPE="wire"
247 
     }
248 
     LINE  2, 0, 0
249 
     {
250 
      POINTS ( (0,0), (20,0) )
251 
     }
252 
    }
253 
   }
254 
  }
255 
 }
256 
 SYMBOL "#default" "mips_seg7led" "mips_seg7led"
257 
 {
258 
  HEADER
259 
  {
260 
   VARIABLES
261 
   {
262 
    #DESCRIPTION=""
263 
    #LANGUAGE="VERILOG"
264 
    #MODIFIED="1218632224"
265 
   }
266 
  }
267 
  PAGE ""
268 
  {
269 
   PAGEHEADER
270 
   {
271 
    RECT (0,0,400,240)
272 
    FREEID 17
273 
   }
274 
 
275 
   BODY
276 
   {
277 
    RECT  1, -1, 0
278 
    {
279 
     VARIABLES
280 
     {
281 
      #OUTLINE_FILLING="1"
282 
     }
283 
     AREA (20,0,380,240)
284 
    }
285 
    TEXT  3, 0, 0
286 
    {
287 
     TEXT "$#NAME"
288 
     RECT (25,30,159,54)
289 
     ALIGN 4
290 
     MARGINS (1,1)
291 
     PARENT 2
292 
    }
293 
    TEXT  5, 0, 0
294 
    {
295 
     TEXT "$#NAME"
296 
     RECT (230,30,375,54)
297 
     ALIGN 6
298 
     MARGINS (1,1)
299 
     PARENT 4
300 
    }
301 
    TEXT  7, 0, 0
302 
    {
303 
     TEXT "$#NAME"
304 
     RECT (25,70,60,94)
305 
     ALIGN 4
306 
     MARGINS (1,1)
307 
     PARENT 6
308 
    }
309 
    TEXT  9, 0, 0
310 
    {
311 
     TEXT "$#NAME"
312 
     RECT (230,70,375,94)
313 
     ALIGN 6
314 
     MARGINS (1,1)
315 
     PARENT 8
316 
    }
317 
    TEXT  11, 0, 0
318 
    {
319 
     TEXT "$#NAME"
320 
     RECT (25,110,126,134)
321 
     ALIGN 4
322 
     MARGINS (1,1)
323 
     PARENT 10
324 
    }
325 
    TEXT  13, 0, 0
326 
    {
327 
     TEXT "$#NAME"
328 
     RECT (25,150,192,174)
329 
     ALIGN 4
330 
     MARGINS (1,1)
331 
     PARENT 12
332 
    }
333 
    TEXT  15, 0, 0
334 
    {
335 
     TEXT "$#NAME"
336 
     RECT (25,190,60,214)
337 
     ALIGN 4
338 
     MARGINS (1,1)
339 
     PARENT 14
340 
    }
341 
    PIN  2, 0, 0
342 
    {
343 
     COORD (0,40)
344 
     VARIABLES
345 
     {
346 
      #DIRECTION="IN"
347 
      #DOWNTO="1"
348 
      #LENGTH="20"
349 
      #MDA_RECORD_TOKEN="OTHER"
350 
      #NAME="addr_i(31:0)"
351 
      #NUMBER="0"
352 
      #VERILOG_TYPE="wire"
353 
     }
354 
     LINE  2, 0, 0
355 
     {
356 
      POINTS ( (0,0), (20,0) )
357 
     }
358 
    }
359 
    PIN  4, 0, 0
360 
    {
361 
     COORD (400,40)
362 
     VARIABLES
363 
     {
364 
      #DIRECTION="OUT"
365 
      #DOWNTO="1"
366 
      #LENGTH="20"
367 
      #MDA_RECORD_TOKEN="OTHER"
368 
      #NAME="seg7led1(6:0)"
369 
      #NUMBER="0"
370 
      #VERILOG_TYPE="wire"
371 
     }
372 
     LINE  2, 0, 0
373 
     {
374 
      POINTS ( (-20,0), (0,0) )
375 
     }
376 
    }
377 
    PIN  6, 0, 0
378 
    {
379 
     COORD (0,80)
380 
     VARIABLES
381 
     {
382 
      #DIRECTION="IN"
383 
      #LENGTH="20"
384 
      #MDA_RECORD_TOKEN="OTHER"
385 
      #NAME="clk"
386 
      #NUMBER="0"
387 
      #VERILOG_TYPE="wire"
388 
     }
389 
     LINE  2, 0, 0
390 
     {
391 
      POINTS ( (0,0), (20,0) )
392 
     }
393 
    }
394 
    PIN  8, 0, 0
395 
    {
396 
     COORD (400,80)
397 
     VARIABLES
398 
     {
399 
      #DIRECTION="OUT"
400 
      #DOWNTO="1"
401 
      #LENGTH="20"
402 
      #MDA_RECORD_TOKEN="OTHER"
403 
      #NAME="seg7led2(6:0)"
404 
      #NUMBER="0"
405 
      #VERILOG_TYPE="wire"
406 
     }
407 
     LINE  2, 0, 0
408 
     {
409 
      POINTS ( (-20,0), (0,0) )
410 
     }
411 
    }
412 
    PIN  10, 0, 0
413 
    {
414 
     COORD (0,120)
415 
     VARIABLES
416 
     {
417 
      #DIRECTION="IN"
418 
      #DOWNTO="1"
419 
      #LENGTH="20"
420 
      #MDA_RECORD_TOKEN="OTHER"
421 
      #NAME="din(31:0)"
422 
      #NUMBER="0"
423 
      #VERILOG_TYPE="wire"
424 
     }
425 
     LINE  2, 0, 0
426 
     {
427 
      POINTS ( (0,0), (20,0) )
428 
     }
429 
    }
430 
    PIN  12, 0, 0
431 
    {
432 
     COORD (0,160)
433 
     VARIABLES
434 
     {
435 
      #DIRECTION="IN"
436 
      #DOWNTO="1"
437 
      #LENGTH="20"
438 
      #MDA_RECORD_TOKEN="OTHER"
439 
      #NAME="dmem_ctl_i(3:0)"
440 
      #NUMBER="0"
441 
      #VERILOG_TYPE="wire"
442 
     }
443 
     LINE  2, 0, 0
444 
     {
445 
      POINTS ( (0,0), (20,0) )
446 
     }
447 
    }
448 
    PIN  14, 0, 0
449 
    {
450 
     COORD (0,200)
451 
     VARIABLES
452 
     {
453 
      #DIRECTION="IN"
454 
      #LENGTH="20"
455 
      #MDA_RECORD_TOKEN="OTHER"
456 
      #NAME="rst"
457 
      #NUMBER="0"
458 
      #VERILOG_TYPE="wire"
459 
     }
460 
     LINE  2, 0, 0
461 
     {
462 
      POINTS ( (0,0), (20,0) )
463 
     }
464 
    }
465 
   }
466 
  }
467 
 }
468 
 SYMBOL "#default" "mips_core1" "mips_core1"
469 
 {
470 
  HEADER
471 
  {
472 
   VARIABLES
473 
   {
474 
    #DESCRIPTION=""
475 
    #LANGUAGE="VERILOG"
476 
    #MODIFIED="1218631794"
477 
   }
478 
  }
479 
  PAGE ""
480 
  {
481 
   PAGEHEADER
482 
   {
483 
    RECT (0,0,440,360)
484 
    FREEID 33
485 
   }
486 
 
487 
   BODY
488 
   {
489 
    RECT  1, -1, 0
490 
    {
491 
     VARIABLES
492 
     {
493 
      #OUTLINE_FILLING="1"
494 
     }
495 
     AREA (20,0,420,360)
496 
    }
497 
    TEXT  3, 0, 0
498 
    {
499 
     TEXT "$#NAME"
500 
     RECT (25,30,60,54)
501 
     ALIGN 4
502 
     MARGINS (1,1)
503 
     PARENT 2
504 
    }
505 
    TEXT  5, 0, 0
506 
    {
507 
     TEXT "$#NAME"
508 
     RECT (237,30,415,54)
509 
     ALIGN 6
510 
     MARGINS (1,1)
511 
     PARENT 4
512 
    }
513 
    TEXT  7, 0, 0
514 
    {
515 
     TEXT "$#NAME"
516 
     RECT (25,70,181,94)
517 
     ALIGN 4
518 
     MARGINS (1,1)
519 
     PARENT 6
520 
    }
521 
    TEXT  9, 0, 0
522 
    {
523 
     TEXT "$#NAME"
524 
     RECT (237,70,415,94)
525 
     ALIGN 6
526 
     MARGINS (1,1)
527 
     PARENT 8
528 
    }
529 
    TEXT  11, 0, 0
530 
    {
531 
     TEXT "$#NAME"
532 
     RECT (25,110,181,134)
533 
     ALIGN 4
534 
     MARGINS (1,1)
535 
     PARENT 10
536 
    }
537 
    TEXT  13, 0, 0
538 
    {
539 
     TEXT "$#NAME"
540 
     RECT (215,110,415,134)
541 
     ALIGN 6
542 
     MARGINS (1,1)
543 
     PARENT 12
544 
    }
545 
    TEXT  15, 0, 0
546 
    {
547 
     TEXT "$#NAME"
548 
     RECT (25,150,82,174)
549 
     ALIGN 4
550 
     MARGINS (1,1)
551 
     PARENT 14
552 
    }
553 
    TEXT  17, 0, 0
554 
    {
555 
     TEXT "$#NAME"
556 
     RECT (347,150,415,174)
557 
     ALIGN 6
558 
     MARGINS (1,1)
559 
     PARENT 16
560 
    }
561 
    TEXT  19, 0, 0
562 
    {
563 
     TEXT "$#NAME"
564 
     RECT (25,190,60,214)
565 
     ALIGN 4
566 
     MARGINS (1,1)
567 
     PARENT 18
568 
    }
569 
    TEXT  21, 0, 0
570 
    {
571 
     TEXT "$#NAME"
572 
     RECT (248,190,415,214)
573 
     ALIGN 6
574 
     MARGINS (1,1)
575 
     PARENT 20
576 
    }
577 
    TEXT  23, 0, 0
578 
    {
579 
     TEXT "$#NAME"
580 
     RECT (25,230,159,254)
581 
     ALIGN 4
582 
     MARGINS (1,1)
583 
     PARENT 22
584 
    }
585 
    TEXT  25, 0, 0
586 
    {
587 
     TEXT "$#NAME"
588 
     RECT (270,230,415,254)
589 
     ALIGN 6
590 
     MARGINS (1,1)
591 
     PARENT 24
592 
    }
593 
    TEXT  27, 0, 0
594 
    {
595 
     TEXT "$#NAME"
596 
     RECT (25,270,181,294)
597 
     ALIGN 4
598 
     MARGINS (1,1)
599 
     PARENT 26
600 
    }
601 
    TEXT  29, 0, 0
602 
    {
603 
     TEXT "$#NAME"
604 
     RECT (270,270,415,294)
605 
     ALIGN 6
606 
     MARGINS (1,1)
607 
     PARENT 28
608 
    }
609 
    TEXT  31, 0, 0
610 
    {
611 
     TEXT "$#NAME"
612 
     RECT (248,310,415,334)
613 
     ALIGN 6
614 
     MARGINS (1,1)
615 
     PARENT 30
616 
    }
617 
    PIN  2, 0, 0
618 
    {
619 
     COORD (0,40)
620 
     VARIABLES
621 
     {
622 
      #DIRECTION="IN"
623 
      #LENGTH="20"
624 
      #MDA_RECORD_TOKEN="OTHER"
625 
      #NAME="clk"
626 
      #NUMBER="0"
627 
      #VERILOG_TYPE="wire"
628 
     }
629 
     LINE  2, 0, 0
630 
     {
631 
      POINTS ( (0,0), (20,0) )
632 
     }
633 
    }
634 
    PIN  4, 0, 0
635 
    {
636 
     COORD (440,40)
637 
     VARIABLES
638 
     {
639 
      #DIRECTION="OUT"
640 
      #DOWNTO="1"
641 
      #LENGTH="20"
642 
      #MDA_RECORD_TOKEN="OTHER"
643 
      #NAME="cop_addr_o(31:0)"
644 
      #NUMBER="0"
645 
      #VERILOG_TYPE="wire"
646 
     }
647 
     LINE  2, 0, 0
648 
     {
649 
      POINTS ( (-20,0), (0,0) )
650 
     }
651 
    }
652 
    PIN  6, 0, 0
653 
    {
654 
     COORD (0,80)
655 
     VARIABLES
656 
     {
657 
      #DIRECTION="IN"
658 
      #DOWNTO="1"
659 
      #LENGTH="20"
660 
      #MDA_RECORD_TOKEN="OTHER"
661 
      #NAME="cop_dout(31:0)"
662 
      #NUMBER="0"
663 
      #VERILOG_TYPE="wire"
664 
     }
665 
     LINE  2, 0, 0
666 
     {
667 
      POINTS ( (0,0), (20,0) )
668 
     }
669 
    }
670 
    PIN  8, 0, 0
671 
    {
672 
     COORD (440,80)
673 
     VARIABLES
674 
     {
675 
      #DIRECTION="OUT"
676 
      #DOWNTO="1"
677 
      #LENGTH="20"
678 
      #MDA_RECORD_TOKEN="OTHER"
679 
      #NAME="cop_data_o(31:0)"
680 
      #NUMBER="0"
681 
      #VERILOG_TYPE="wire"
682 
     }
683 
     LINE  2, 0, 0
684 
     {
685 
      POINTS ( (-20,0), (0,0) )
686 
     }
687 
    }
688 
    PIN  10, 0, 0
689 
    {
690 
     COORD (0,120)
691 
     VARIABLES
692 
     {
693 
      #DIRECTION="IN"
694 
      #DOWNTO="1"
695 
      #LENGTH="20"
696 
      #MDA_RECORD_TOKEN="OTHER"
697 
      #NAME="irq_addr(31:0)"
698 
      #NUMBER="0"
699 
      #VERILOG_TYPE="wire"
700 
     }
701 
     LINE  2, 0, 0
702 
     {
703 
      POINTS ( (0,0), (20,0) )
704 
     }
705 
    }
706 
    PIN  12, 0, 0
707 
    {
708 
     COORD (440,120)
709 
     VARIABLES
710 
     {
711 
      #DIRECTION="OUT"
712 
      #DOWNTO="1"
713 
      #LENGTH="20"
714 
      #MDA_RECORD_TOKEN="OTHER"
715 
      #NAME="cop_mem_ctl_o(3:0)"
716 
      #NUMBER="0"
717 
      #VERILOG_TYPE="wire"
718 
     }
719 
     LINE  2, 0, 0
720 
     {
721 
      POINTS ( (-20,0), (0,0) )
722 
     }
723 
    }
724 
    PIN  14, 0, 0
725 
    {
726 
     COORD (0,160)
727 
     VARIABLES
728 
     {
729 
      #DIRECTION="IN"
730 
      #LENGTH="20"
731 
      #MDA_RECORD_TOKEN="OTHER"
732 
      #NAME="irq_i"
733 
      #NUMBER="0"
734 
      #VERILOG_TYPE="wire"
735 
     }
736 
     LINE  2, 0, 0
737 
     {
738 
      POINTS ( (0,0), (20,0) )
739 
     }
740 
    }
741 
    PIN  16, 0, 0
742 
    {
743 
     COORD (440,160)
744 
     VARIABLES
745 
     {
746 
      #DIRECTION="OUT"
747 
      #LENGTH="20"
748 
      #MDA_RECORD_TOKEN="OTHER"
749 
      #NAME="iack_o"
750 
      #NUMBER="0"
751 
      #VERILOG_TYPE="wire"
752 
     }
753 
     LINE  2, 0, 0
754 
     {
755 
      POINTS ( (-20,0), (0,0) )
756 
     }
757 
    }
758 
    PIN  18, 0, 0
759 
    {
760 
     COORD (0,200)
761 
     VARIABLES
762 
     {
763 
      #DIRECTION="IN"
764 
      #LENGTH="20"
765 
      #MDA_RECORD_TOKEN="OTHER"
766 
      #NAME="rst"
767 
      #NUMBER="0"
768 
      #VERILOG_TYPE="wire"
769 
     }
770 
     LINE  2, 0, 0
771 
     {
772 
      POINTS ( (0,0), (20,0) )
773 
     }
774 
    }
775 
    PIN  20, 0, 0
776 
    {
777 
     COORD (440,200)
778 
     VARIABLES
779 
     {
780 
      #DIRECTION="OUT"
781 
      #DOWNTO="1"
782 
      #LENGTH="20"
783 
      #MDA_RECORD_TOKEN="OTHER"
784 
      #NAME="zz_addr_o(31:0)"
785 
      #NUMBER="0"
786 
      #VERILOG_TYPE="wire"
787 
     }
788 
     LINE  2, 0, 0
789 
     {
790 
      POINTS ( (-20,0), (0,0) )
791 
     }
792 
    }
793 
    PIN  22, 0, 0
794 
    {
795 
     COORD (0,240)
796 
     VARIABLES
797 
     {
798 
      #DIRECTION="IN"
799 
      #DOWNTO="1"
800 
      #LENGTH="20"
801 
      #MDA_RECORD_TOKEN="OTHER"
802 
      #NAME="zz_din(31:0)"
803 
      #NUMBER="0"
804 
      #VERILOG_TYPE="wire"
805 
     }
806 
     LINE  2, 0, 0
807 
     {
808 
      POINTS ( (0,0), (20,0) )
809 
     }
810 
    }
811 
    PIN  24, 0, 0
812 
    {
813 
     COORD (440,240)
814 
     VARIABLES
815 
     {
816 
      #DIRECTION="OUT"
817 
      #DOWNTO="1"
818 
      #LENGTH="20"
819 
      #MDA_RECORD_TOKEN="OTHER"
820 
      #NAME="zz_dout(31:0)"
821 
      #NUMBER="0"
822 
      #VERILOG_TYPE="wire"
823 
     }
824 
     LINE  2, 0, 0
825 
     {
826 
      POINTS ( (-20,0), (0,0) )
827 
     }
828 
    }
829 
    PIN  26, 0, 0
830 
    {
831 
     COORD (0,280)
832 
     VARIABLES
833 
     {
834 
      #DIRECTION="IN"
835 
      #DOWNTO="1"
836 
      #LENGTH="20"
837 
      #MDA_RECORD_TOKEN="OTHER"
838 
      #NAME="zz_ins_i(31:0)"
839 
      #NUMBER="0"
840 
      #VERILOG_TYPE="wire"
841 
     }
842 
     LINE  2, 0, 0
843 
     {
844 
      POINTS ( (0,0), (20,0) )
845 
     }
846 
    }
847 
    PIN  28, 0, 0
848 
    {
849 
     COORD (440,280)
850 
     VARIABLES
851 
     {
852 
      #DIRECTION="OUT"
853 
      #DOWNTO="1"
854 
      #LENGTH="20"
855 
      #MDA_RECORD_TOKEN="OTHER"
856 
      #NAME="zz_pc_o(31:0)"
857 
      #NUMBER="0"
858 
      #VERILOG_TYPE="wire"
859 
     }
860 
     LINE  2, 0, 0
861 
     {
862 
      POINTS ( (-20,0), (0,0) )
863 
     }
864 
    }
865 
    PIN  30, 0, 0
866 
    {
867 
     COORD (440,320)
868 
     VARIABLES
869 
     {
870 
      #DIRECTION="OUT"
871 
      #DOWNTO="1"
872 
      #LENGTH="20"
873 
      #MDA_RECORD_TOKEN="OTHER"
874 
      #NAME="zz_wr_en_o(3:0)"
875 
      #NUMBER="0"
876 
      #VERILOG_TYPE="wire"
877 
     }
878 
     LINE  2, 0, 0
879 
     {
880 
      POINTS ( (-20,0), (0,0) )
881 
     }
882 
    }
883 
   }
884 
  }
885 
 }
886 
}
887 
 
888 
PAGE ""
889 
{
890 
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892 
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897 
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898 
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900 
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901 
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902 
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903 
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904 
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905 
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906 
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907 
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924 
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925 
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928 
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929 
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930 
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931 
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932 
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933 
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934 
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948 
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949 
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950 
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951 
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952 
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953 
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954 
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963 
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965 
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966 
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967 
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968 
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969 
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970 
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971 
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973 
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974 
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987 
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989 
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990 
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991 
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992 
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993 
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994 
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995 
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997 
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1010 
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1012 
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1013 
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1014 
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1015 
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1016 
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1017 
  {
1018 
   VARIABLES
1019 
   {
1020 
    #COMPONENT="BusOutput"
1021 
    #LIBRARY="#terminals"
1022 
    #REFERENCE="seg7led1(6:0)"
1023 
    #SYMBOL="BusOutput"
1024 
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1025 
   COORD (1660,420)
1026 
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1033 
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1034 
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1035 
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1036 
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1037 
  {
1038 
   VARIABLES
1039 
   {
1040 
    #COMPONENT="BusOutput"
1041 
    #LIBRARY="#terminals"
1042 
    #REFERENCE="seg7led2(6:0)"
1043 
    #SYMBOL="BusOutput"
1044 
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1046 
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   TEXT "$#REFERENCE"
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1052 
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1053 
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1054 
   PARENT 1349
1055 
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1057 
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1058 
  INSTANCE  1698, 0, 0
1059 
  {
1060 
   VARIABLES
1061 
   {
1062 
    #COMPONENT="mips_core1"
1063 
    #LIBRARY="#default"
1064 
    #REFERENCE="mips_core_"
1065 
    #SYMBOL="mips_core1"
1066 
   }
1067 
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1068 
   VERTEXES ( (2,2129), (6,2148), (10,2150), (14,2124), (18,2130), (26,2122), (20,2156), (24,2153), (28,2155), (30,2147), (22,2335), (4,2851), (8,2886), (12,2893) )
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1072 
   TEXT "$#REFERENCE"
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1075 
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1077 
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1081 
   RECT (660,1080,832,1115)
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1084 
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1085 
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1086 
  NET BUS  2018, 0, 0
1087 
  INSTANCE  2020, 0, 0
1088 
  {
1089 
   VARIABLES
1090 
   {
1091 
    #COMPONENT="BusInput"
1092 
    #LIBRARY="#terminals"
1093 
    #REFERENCE="cop_data(31:0)"
1094 
    #SYMBOL="BusInput"
1095 
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1096 
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1097 
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1101 
   TEXT "$#REFERENCE"
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1103 
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1104 
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1105 
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1106 
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1108 
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1109 
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1110 
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1111 
    #COMPONENT="BusInput"
1112 
    #LIBRARY="#terminals"
1113 
    #REFERENCE="irq_addr(31:0)"
1114 
    #SYMBOL="BusInput"
1115 
   }
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1117 
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1121 
   TEXT "$#REFERENCE"
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1126 
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1129 
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1130 
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1132 
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1133 
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1134 
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1136 
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1137 
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1138 
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1141 
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1145 
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1148 
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1149 
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1150 
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1152 
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1153 
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1154 
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1157 
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1158 
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1160 
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1161 
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1162 
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1163 
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1164 
  {
1165 
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1166 
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1168 
  {
1169 
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1170 
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1171 
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1172 
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1173 
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1174 
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1175 
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1176 
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1177 
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1178 
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1179 
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1180 
  {
1181 
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1182 
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1183 
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1184 
  {
1185 
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1186 
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1187 
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1188 
  {
1189 
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1190 
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1191 
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1192 
  {
1193 
   COORD (1660,460)
1194 
  }
1195 
  VTX  2136, 0, 0
1196 
  {
1197 
   COORD (1600,460)
1198 
  }
1199 
  VTX  2137, 0, 0
1200 
  {
1201 
   COORD (1200,580)
1202 
  }
1203 
  VTX  2138, 0, 0
1204 
  {
1205 
   COORD (520,680)
1206 
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1207 
  VTX  2139, 0, 0
1208 
  {
1209 
   COORD (1200,460)
1210 
  }
1211 
  VTX  2146, 0, 0
1212 
  {
1213 
   COORD (1380,1040)
1214 
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1215 
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1216 
  {
1217 
   COORD (1060,1040)
1218 
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1219 
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1220 
  {
1221 
   COORD (620,800)
1222 
  }
1223 
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1224 
  {
1225 
   COORD (520,800)
1226 
  }
1227 
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1228 
  {
1229 
   COORD (620,840)
1230 
  }
1231 
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1232 
  {
1233 
   COORD (520,840)
1234 
  }
1235 
  VTX  2152, 0, 0
1236 
  {
1237 
   COORD (1380,880)
1238 
  }
1239 
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1240 
  {
1241 
   COORD (1060,960)
1242 
  }
1243 
  VTX  2154, 0, 0
1244 
  {
1245 
   COORD (1380,920)
1246 
  }
1247 
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1248 
  {
1249 
   COORD (1060,1000)
1250 
  }
1251 
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1252 
  {
1253 
   COORD (1060,920)
1254 
  }
1255 
  BUS  2157, 0, 0
1256 
  {
1257 
   NET 2557
1258 
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1259 
  }
1260 
  VTX  2158, 0, 0
1261 
  {
1262 
   COORD (1360,1000)
1263 
  }
1264 
  BUS  2159, 0, 0
1265 
  {
1266 
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1267 
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1268 
  }
1269 
  BUS  2160, 0, 0
1270 
  {
1271 
   NET 2557
1272 
   VTX 2158, 2119
1273 
  }
1274 
  VTX  2170, 0, 0
1275 
  {
1276 
   COORD (610,1000)
1277 
  }
1278 
  BUS  2171, 0, 0
1279 
  {
1280 
   NET 2560
1281 
   VTX 2122, 2170
1282 
  }
1283 
  VTX  2172, 0, 0
1284 
  {
1285 
   COORD (610,1100)
1286 
  }
1287 
  BUS  2173, 0, 0
1288 
  {
1289 
   NET 2560
1290 
   VTX 2170, 2172
1291 
  }
1292 
  VTX  2174, 0, 0
1293 
  {
1294 
   COORD (1700,1100)
1295 
  }
1296 
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1297 
  {
1298 
   NET 2560
1299 
   VTX 2172, 2174
1300 
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1301 
   {
1302 
    #NAMED="1"
1303 
   }
1304 
  }
1305 
  VTX  2176, 0, 0
1306 
  {
1307 
   COORD (1700,880)
1308 
  }
1309 
  BUS  2177, 0, 0
1310 
  {
1311 
   NET 2560
1312 
   VTX 2174, 2176
1313 
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1314 
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1315 
  {
1316 
   NET 2560
1317 
   VTX 2176, 2123
1318 
  }
1319 
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1320 
  {
1321 
   NET 945
1322 
   VTX 2124, 2125
1323 
  }
1324 
  VTX  2180, 0, 0
1325 
  {
1326 
   COORD (1340,680)
1327 
  }
1328 
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1329 
  {
1330 
   NET 1376
1331 
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1332 
  }
1333 
  VTX  2182, 0, 0
1334 
  {
1335 
   COORD (1340,840)
1336 
  }
1337 
  WIRE  2183, 0, 0
1338 
  {
1339 
   NET 1376
1340 
   VTX 2180, 2182
1341 
  }
1342 
  WIRE  2184, 0, 0
1343 
  {
1344 
   NET 1376
1345 
   VTX 2182, 2127
1346 
  }
1347 
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1348 
  {
1349 
   NET 1376
1350 
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1351 
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1352 
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1353 
  {
1354 
   NET 1367
1355 
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1356 
  }
1357 
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1358 
  {
1359 
   NET 1367
1360 
   VTX 2131, 2132
1361 
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1362 
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1363 
  {
1364 
   NET 1338
1365 
   VTX 2133, 2134
1366 
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1367 
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1368 
  {
1369 
   NET 1342
1370 
   VTX 2135, 2136
1371 
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1372 
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1373 
  {
1374 
   COORD (600,580)
1375 
  }
1376 
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1377 
  {
1378 
   NET 1367
1379 
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1380 
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1381 
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1382 
  {
1383 
   NET 1367
1384 
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1385 
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1386 
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1387 
  {
1388 
   NET 1376
1389 
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1390 
  }
1391 
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1392 
  {
1393 
   COORD (640,460)
1394 
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1395 
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1396 
  {
1397 
   NET 1376
1398 
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1399 
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1400 
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1401 
  {
1402 
   NET 1376
1403 
   VTX 2194, 2126
1404 
  }
1405 
  WIRE  2197, 0, 0
1406 
  {
1407 
   NET 1376
1408 
   VTX 2126, 2128
1409 
  }
1410 
  BUS  2217, 0, 0
1411 
  {
1412 
   NET 2559
1413 
   VTX 2146, 2147
1414 
   VARIABLES
1415 
   {
1416 
    #NAMED="1"
1417 
   }
1418 
  }
1419 
  BUS  2218, 0, 0
1420 
  {
1421 
   NET 2014
1422 
   VTX 2148, 2149
1423 
  }
1424 
  BUS  2219, 0, 0
1425 
  {
1426 
   NET 2018
1427 
   VTX 2150, 2151
1428 
  }
1429 
  VTX  2220, 0, 0
1430 
  {
1431 
   COORD (1120,880)
1432 
  }
1433 
  BUS  2221, 0, 0
1434 
  {
1435 
   NET 2426
1436 
   VTX 2152, 2220
1437 
   VARIABLES
1438 
   {
1439 
    #NAMED="1"
1440 
   }
1441 
  }
1442 
  VTX  2222, 0, 0
1443 
  {
1444 
   COORD (1120,960)
1445 
  }
1446 
  BUS  2223, 0, 0
1447 
  {
1448 
   NET 2426
1449 
   VTX 2220, 2222
1450 
  }
1451 
  BUS  2224, 0, 0
1452 
  {
1453 
   NET 2426
1454 
   VTX 2222, 2153
1455 
  }
1456 
  VTX  2225, 0, 0
1457 
  {
1458 
   COORD (1280,920)
1459 
  }
1460 
  BUS  2226, 0, 0
1461 
  {
1462 
   NET 2558
1463 
   VTX 2154, 2225
1464 
  }
1465 
  VTX  2227, 0, 0
1466 
  {
1467 
   COORD (1280,1000)
1468 
  }
1469 
  BUS  2228, 0, 0
1470 
  {
1471 
   NET 2558
1472 
   VTX 2225, 2227
1473 
  }
1474 
  BUS  2229, 0, 0
1475 
  {
1476 
   NET 2558
1477 
   VTX 2227, 2155
1478 
   VARIABLES
1479 
   {
1480 
    #NAMED="1"
1481 
   }
1482 
  }
1483 
  VTX  2230, 0, 0
1484 
  {
1485 
   COORD (1200,960)
1486 
  }
1487 
  BUS  2231, 0, 0
1488 
  {
1489 
   NET 2557
1490 
   VTX 2117, 2230
1491 
  }
1492 
  VTX  2232, 0, 0
1493 
  {
1494 
   COORD (1200,920)
1495 
  }
1496 
  BUS  2233, 0, 0
1497 
  {
1498 
   NET 2557
1499 
   VTX 2230, 2232
1500 
  }
1501 
  BUS  2234, 0, 0
1502 
  {
1503 
   NET 2557
1504 
   VTX 2232, 2156
1505 
   VARIABLES
1506 
   {
1507 
    #NAMED="1"
1508 
   }
1509 
  }
1510 
  VTX  2335, 0, 0
1511 
  {
1512 
   COORD (620,960)
1513 
  }
1514 
  VTX  2336, 0, 0
1515 
  {
1516 
   COORD (1680,840)
1517 
  }
1518 
  VTX  2337, 0, 0
1519 
  {
1520 
   COORD (580,960)
1521 
  }
1522 
  BUS  2338, 0, 0
1523 
  {
1524 
   NET 2561
1525 
   VTX 2335, 2337
1526 
  }
1527 
  VTX  2339, 0, 0
1528 
  {
1529 
   COORD (580,1120)
1530 
  }
1531 
  BUS  2340, 0, 0
1532 
  {
1533 
   NET 2561
1534 
   VTX 2337, 2339
1535 
  }
1536 
  VTX  2341, 0, 0
1537 
  {
1538 
   COORD (1720,1120)
1539 
  }
1540 
  BUS  2342, 0, 0
1541 
  {
1542 
   NET 2561
1543 
   VTX 2339, 2341
1544 
   VARIABLES
1545 
   {
1546 
    #NAMED="1"
1547 
   }
1548 
  }
1549 
  VTX  2343, 0, 0
1550 
  {
1551 
   COORD (1720,840)
1552 
  }
1553 
  BUS  2344, 0, 0
1554 
  {
1555 
   NET 2561
1556 
   VTX 2341, 2343
1557 
  }
1558 
  BUS  2345, 0, 0
1559 
  {
1560 
   NET 2561
1561 
   VTX 2343, 2336
1562 
  }
1563 
  NET BUS  2411, 0, 0
1564 
  {
1565 
   VARIABLES
1566 
   {
1567 
    #MDA_RECORD_TOKEN="OTHER"
1568 
    #NAME="cop_addr(31:0)"
1569 
    #VERILOG_TYPE="wire"
1570 
   }
1571 
  }
1572 
  TEXT  2412, 0, 0
1573 
  {
1574 
   TEXT "$#NAME"
1575 
   RECT (980,386,1178,415)
1576 
   ALIGN 4
1577 
   MARGINS (1,1)
1578 
   PARENT 2855
1579 
  }
1580 
  NET BUS  2416, 0, 0
1581 
  {
1582 
   VARIABLES
1583 
   {
1584 
    #MDA_RECORD_TOKEN="OTHER"
1585 
    #NAME="data2cop(31:0)"
1586 
    #VERILOG_TYPE="wire"
1587 
   }
1588 
  }
1589 
  TEXT  2417, 0, 0
1590 
  {
1591 
   TEXT "$#NAME"
1592 
   RECT (900,626,1098,655)
1593 
   ALIGN 4
1594 
   MARGINS (1,1)
1595 
   PARENT 2890
1596 
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1597 
  NET BUS  2421, 0, 0
1598 
  {
1599 
   VARIABLES
1600 
   {
1601 
    #MDA_RECORD_TOKEN="OTHER"
1602 
    #NAME="cop_mem_ctl(3:0)"
1603 
    #VERILOG_TYPE="wire"
1604 
   }
1605 
  }
1606 
  TEXT  2422, 0, 0
1607 
  {
1608 
   TEXT "$#NAME"
1609 
   RECT (1167,751,1393,780)
1610 
   ALIGN 9
1611 
   MARGINS (1,1)
1612 
   PARENT 2898
1613 
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1614 
  NET BUS  2426, 0, 0
1615 
  {
1616 
   VARIABLES
1617 
   {
1618 
    #MDA_RECORD_TOKEN="OTHER"
1619 
    #NAME="data2mem(31:0)"
1620 
    #VERILOG_TYPE="wire"
1621 
   }
1622 
  }
1623 
  TEXT  2427, 0, 0
1624 
  {
1625 
   TEXT "$#NAME"
1626 
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1627 
   ALIGN 9
1628 
   MARGINS (1,1)
1629 
   PARENT 2221
1630 
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1631 
  TEXT  2432, 0, 0
1632 
  {
1633 
   TEXT "$#NAME"
1634 
   RECT (1031,890,1229,919)
1635 
   ALIGN 9
1636 
   MARGINS (1,1)
1637 
   PARENT 2234
1638 
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1639 
  TEXT  2437, 0, 0
1640 
  {
1641 
   TEXT "$#NAME"
1642 
   RECT (1113,970,1227,999)
1643 
   ALIGN 9
1644 
   MARGINS (1,1)
1645 
   PARENT 2229
1646 
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1647 
  TEXT  2442, 0, 0
1648 
  {
1649 
   TEXT "$#NAME"
1650 
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1651 
   ALIGN 9
1652 
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1653 
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1654 
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1655 
  TEXT  2456, 0, 0
1656 
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1657 
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1658 
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1659 
   ALIGN 9
1660 
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1661 
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1662 
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1663 
  TEXT  2525, 0, 0
1664 
  {
1665 
   TEXT "$#NAME"
1666 
   RECT (1101,1071,1299,1100)
1667 
   ALIGN 9
1668 
   MARGINS (1,1)
1669 
   PARENT 2175
1670 
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1671 
  NET BUS  2557, 0, 0
1672 
  {
1673 
   VARIABLES
1674 
   {
1675 
    #MDA_RECORD_TOKEN="OTHER"
1676 
    #NAME="mem_Addr(31:0)"
1677 
    #VERILOG_TYPE="wire"
1678 
   }
1679 
  }
1680 
  NET BUS  2558, 0, 0
1681 
  {
1682 
   VARIABLES
1683 
   {
1684 
    #MDA_RECORD_TOKEN="OTHER"
1685 
    #NAME="pc(31:0)"
1686 
    #VERILOG_TYPE="wire"
1687 
   }
1688 
  }
1689 
  NET BUS  2559, 0, 0
1690 
  {
1691 
   VARIABLES
1692 
   {
1693 
    #MDA_RECORD_TOKEN="OTHER"
1694 
    #NAME="wr_en(3:0)"
1695 
    #VERILOG_TYPE="wire"
1696 
   }
1697 
  }
1698 
  NET BUS  2560, 0, 0
1699 
  {
1700 
   VARIABLES
1701 
   {
1702 
    #MDA_RECORD_TOKEN="OTHER"
1703 
    #NAME="ins2core(31:0)"
1704 
    #VERILOG_TYPE="wire"
1705 
   }
1706 
  }
1707 
  NET BUS  2561, 0, 0
1708 
  {
1709 
   VARIABLES
1710 
   {
1711 
    #MDA_RECORD_TOKEN="OTHER"
1712 
    #NAME="data2core(31:0)"
1713 
    #VERILOG_TYPE="wire"
1714 
   }
1715 
  }
1716 
  VTX  2850, 0, 0
1717 
  {
1718 
   COORD (1200,420)
1719 
  }
1720 
  VTX  2851, 0, 0
1721 
  {
1722 
   COORD (1060,760)
1723 
  }
1724 
  VTX  2852, 0, 0
1725 
  {
1726 
   COORD (1120,420)
1727 
  }
1728 
  BUS  2853, 0, 0
1729 
  {
1730 
   NET 2411
1731 
   VTX 2850, 2852
1732 
  }
1733 
  VTX  2854, 0, 0
1734 
  {
1735 
   COORD (1120,760)
1736 
  }
1737 
  BUS  2855, 0, 0
1738 
  {
1739 
   NET 2411
1740 
   VTX 2852, 2854
1741 
   VARIABLES
1742 
   {
1743 
    #NAMED="1"
1744 
   }
1745 
  }
1746 
  BUS  2856, 0, 0
1747 
  {
1748 
   NET 2411
1749 
   VTX 2854, 2851
1750 
  }
1751 
  VTX  2885, 0, 0
1752 
  {
1753 
   COORD (1200,500)
1754 
  }
1755 
  VTX  2886, 0, 0
1756 
  {
1757 
   COORD (1060,800)
1758 
  }
1759 
  VTX  2887, 0, 0
1760 
  {
1761 
   COORD (1140,500)
1762 
  }
1763 
  BUS  2888, 0, 0
1764 
  {
1765 
   NET 2416
1766 
   VTX 2885, 2887
1767 
  }
1768 
  VTX  2889, 0, 0
1769 
  {
1770 
   COORD (1140,800)
1771 
  }
1772 
  BUS  2890, 0, 0
1773 
  {
1774 
   NET 2416
1775 
   VTX 2887, 2889
1776 
   VARIABLES
1777 
   {
1778 
    #NAMED="1"
1779 
   }
1780 
  }
1781 
  BUS  2891, 0, 0
1782 
  {
1783 
   NET 2416
1784 
   VTX 2889, 2886
1785 
  }
1786 
  VTX  2892, 0, 0
1787 
  {
1788 
   COORD (1200,540)
1789 
  }
1790 
  VTX  2893, 0, 0
1791 
  {
1792 
   COORD (1060,840)
1793 
  }
1794 
  VTX  2894, 0, 0
1795 
  {
1796 
   COORD (1160,540)
1797 
  }
1798 
  BUS  2895, 0, 0
1799 
  {
1800 
   NET 2421
1801 
   VTX 2892, 2894
1802 
  }
1803 
  VTX  2896, 0, 0
1804 
  {
1805 
   COORD (1160,840)
1806 
  }
1807 
  BUS  2897, 0, 0
1808 
  {
1809 
   NET 2421
1810 
   VTX 2894, 2896
1811 
  }
1812 
  BUS  2898, 0, 0
1813 
  {
1814 
   NET 2421
1815 
   VTX 2896, 2893
1816 
   VARIABLES
1817 
   {
1818 
    #NAMED="1"
1819 
   }
1820 
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1821 
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1822 
 
1823 
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1824 
 
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2069 
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2070 
 

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