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/////////////////////////////////////////////////////////////////////
////  Author: Liwei                                              ////
////                                                             ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Liwei                               ////
////                         mcupro@yahoo.com.hk                 ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2007.8.1                                  ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description:                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
module ctl_FSM8 (
        clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
        id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
        pc_prectl, ra2exec_ctl_clr, rst    ,zz_is_nop
    );
 
    parameter
        ID_CUR   = 1,
        ID_LD    = 5,
        ID_MUL   = 2,
        ID_NOI   = 6,
        ID_RET   = 4,
        ONE      = 1,
        PC_IGN   = 1,
        PC_IRQ   = 4,
        PC_KEP   = 2,
        PC_RST   = 8,
        ZERO     = 0;
    input   clk;
    input   [2:0] id_cmd;
    input   irq;
    input   rst;
    output  iack;
    output zz_is_nop;
    output  id2ra_ctl_clr;
    output  id2ra_ctl_cls;
    output  id2ra_ins_clr;
    output  id2ra_ins_cls;
    output  [3:0] pc_prectl;
    output  ra2exec_ctl_clr;
 
    wire    clk;
    reg     iack;
    reg zz_is_nop;
    reg     id2ra_ctl_clr;
    reg     id2ra_ctl_cls;
    reg     id2ra_ins_clr;
    reg     id2ra_ins_cls;
    wire    [2:0] id_cmd;
    wire    irq;
    reg     [3:0] pc_prectl;
    reg     ra2exec_ctl_clr;
    wire    rst;
 
    reg  [0:5]delay_counter_Sreg0, next_delay_counter_Sreg0;
 
`define D2_MUL_DLY 4'b0000
`define IDLE 4'b0001
`define MUL 4'b0010
`define CUR 4'b0011
`define RET 4'b0100
`define IRQ 4'b0101
`define RST 4'b0110
`define LD 4'b0111
`define NOI 4'b1000
 
    reg [3:0] CurrState_Sreg0;
    reg [3:0] NextState_Sreg0;
    reg riack;
 
    always @ (*)
    begin : Sreg0_NextState
        case (CurrState_Sreg0) // synopsys parallel_case full_case
            `IDLE:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl=PC_IGN;
                iack = riack;
                if ((irq)&&(~iack))
                    NextState_Sreg0 <= `IRQ;
                else if (id_cmd ==ID_NOI)
                    NextState_Sreg0 <= `NOI;
                else if (id_cmd==ID_CUR)
                    NextState_Sreg0 <= `CUR;
                else if (id_cmd==ID_MUL)
                    NextState_Sreg0 <= `MUL;
                else if (id_cmd==ID_LD)
                    NextState_Sreg0 <= `LD;
                else if (id_cmd==ID_RET)
                    NextState_Sreg0 <= `RET;
                else
                    NextState_Sreg0 <= `IDLE;
            end
            `MUL:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack = riack;
                NextState_Sreg0 <= `D2_MUL_DLY;
                next_delay_counter_Sreg0 <= 34 - 1;
                zz_is_nop =0;
            end
            `CUR:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ONE;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ONE;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_KEP;
                iack = riack;
                NextState_Sreg0 <= `NOI;
                zz_is_nop = 1;
            end
            `RET:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                pc_prectl =PC_IGN;
                iack =ZERO;
                riack =ZERO;
                NextState_Sreg0 <= `IDLE;
                zz_is_nop = ZERO;
            end
            `IRQ:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl =PC_IRQ;
                iack =ONE;
                riack=ONE;
                NextState_Sreg0 <= `IDLE;
                zz_is_nop = ZERO;
            end
            `RST:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                riack=ZERO;
                NextState_Sreg0 <= `IDLE;
                zz_is_nop = ONE;
            end
            `LD:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                NextState_Sreg0 <= `IDLE;
                zz_is_nop = ZERO;
            end
            `NOI:
            begin
                id2ra_ins_clr=ZERO;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ZERO;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr =ZERO;
                iack=riack;
                pc_prectl=PC_IGN;
                NextState_Sreg0 <= `IDLE;
                zz_is_nop = ZERO;
            end
            `D2_MUL_DLY:
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ZERO;
                pc_prectl =PC_KEP;
                iack=riack;
                zz_is_nop = ONE;
                if (delay_counter_Sreg0 == 0)
                    NextState_Sreg0 <= `IDLE;
                else
                begin
                    NextState_Sreg0 <= `D2_MUL_DLY;
                    if (delay_counter_Sreg0 != 0) next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
                end
            end
            default :
            begin
                id2ra_ins_clr=ONE;
                id2ra_ins_cls=ZERO;
                id2ra_ctl_clr=ONE;
                id2ra_ctl_cls=ZERO;
                ra2exec_ctl_clr=ONE;
                pc_prectl=PC_RST;
                iack=ZERO;
                riack=ZERO;
                zz_is_nop = ONE;
                NextState_Sreg0 <= `IDLE;
            end
        endcase
    end
 
    always @ (posedge clk or negedge rst)
    begin : Sreg0_CurrentState
        if (~rst)
            CurrState_Sreg0 <= `RST;
        else
            CurrState_Sreg0 <= NextState_Sreg0;
    end
 
    always @ (posedge clk or negedge rst)
    begin : Sreg0_RegOutput
        if (~rst)
        begin
            delay_counter_Sreg0 <= 0     ;       // Initialization in the reset state or default value required!!
        end
        else
        begin
            delay_counter_Sreg0 <= next_delay_counter_Sreg0;
        end
    end
 
endmodule
 
 
/*
how to modify this module
        1,add riack
        2,change the `RST action as default
        3,set `IRQ has highest pority.
*/

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Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [verilog/] [mips_core/] [CTL_FSM.v] - Blame information for rev 55

Line No.	Rev	Author	Line
1	2	mcupro	`/////////////////////////////////////////////////////////////////////`
2			`//// Author: Liwei ////`
3			`//// ////`
4			`//// ////`
5			`//// If you encountered any problem, please contact : ////`
6			`//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////`
7			`//// ////`
8			`//// Downloaded from: ////`
9			`//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2007 Liwei ////`
13			`//// mcupro@yahoo.com.hk ////`
14			`//// ////`
15			`//// ////`
16			`//// This source file may be used and distributed freely without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and any derivative work contains the ////`
19			`//// original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// Please let the author know if it is used ////`
22			`//// for commercial purpose. ////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`//// ////`
40			`//// ////`
41			`//// Date of Creation: 2007.8.1 ////`
42			`//// ////`
43			`//// Version: 0.0.1 ////`
44			`//// ////`
45			`//// Description: ////`
46			`//// ////`
47			`//// ////`
48			`/////////////////////////////////////////////////////////////////////`
49			`//// ////`
50			`//// Change log: ////`
51			`//// ////`
52			`/////////////////////////////////////////////////////////////////////`
53
54			`module ctl_FSM8 (`
55			`clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,`
56			`id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,`
57			`pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop`
58			`);`
59
60			`parameter`
61			`ID_CUR = 1,`
62			`ID_LD = 5,`
63			`ID_MUL = 2,`
64			`ID_NOI = 6,`
65			`ID_RET = 4,`
66			`ONE = 1,`
67			`PC_IGN = 1,`
68			`PC_IRQ = 4,`
69			`PC_KEP = 2,`
70			`PC_RST = 8,`
71			`ZERO = 0;`
72			`input clk;`
73			`input [2:0] id_cmd;`
74			`input irq;`
75			`input rst;`
76			`output iack;`
77			`output zz_is_nop;`
78			`output id2ra_ctl_clr;`
79			`output id2ra_ctl_cls;`
80			`output id2ra_ins_clr;`
81			`output id2ra_ins_cls;`
82			`output [3:0] pc_prectl;`
83			`output ra2exec_ctl_clr;`
84
85			`wire clk;`
86			`reg iack;`
87			`reg zz_is_nop;`
88			`reg id2ra_ctl_clr;`
89			`reg id2ra_ctl_cls;`
90			`reg id2ra_ins_clr;`
91			`reg id2ra_ins_cls;`
92			`wire [2:0] id_cmd;`
93			`wire irq;`
94			`reg [3:0] pc_prectl;`
95			`reg ra2exec_ctl_clr;`
96			`wire rst;`
97
98			`reg [0:5]delay_counter_Sreg0, next_delay_counter_Sreg0;`
99
100			`define D2_MUL_DLY 4'b0000
101			`define IDLE 4'b0001
102			`define MUL 4'b0010
103			`define CUR 4'b0011
104			`define RET 4'b0100
105			`define IRQ 4'b0101
106			`define RST 4'b0110
107			`define LD 4'b0111
108			`define NOI 4'b1000
109
110			`reg [3:0] CurrState_Sreg0;`
111			`reg [3:0] NextState_Sreg0;`
112			`reg riack;`
113
114			`always @ (*)`
115			`begin : Sreg0_NextState`
116			`case (CurrState_Sreg0) // synopsys parallel_case full_case`
117			`IDLE:
118			`begin`
119			`id2ra_ins_clr=ZERO;`
120			`id2ra_ins_cls=ZERO;`
121			`id2ra_ctl_clr=ZERO;`
122			`id2ra_ctl_cls=ZERO;`
123			`ra2exec_ctl_clr =ZERO;`
124			`pc_prectl=PC_IGN;`
125			`iack = riack;`
126			`if ((irq)&&(~iack))`
127			NextState_Sreg0 <= `IRQ;
128			`else if (id_cmd ==ID_NOI)`
129			NextState_Sreg0 <= `NOI;
130			`else if (id_cmd==ID_CUR)`
131			NextState_Sreg0 <= `CUR;
132			`else if (id_cmd==ID_MUL)`
133			NextState_Sreg0 <= `MUL;
134			`else if (id_cmd==ID_LD)`
135			NextState_Sreg0 <= `LD;
136			`else if (id_cmd==ID_RET)`
137			NextState_Sreg0 <= `RET;
138			`else`
139			NextState_Sreg0 <= `IDLE;
140			`end`
141			`MUL:
142			`begin`
143			`id2ra_ins_clr=ONE;`
144			`id2ra_ins_cls=ZERO;`
145			`id2ra_ctl_clr=ONE;`
146			`id2ra_ctl_cls=ZERO;`
147			`ra2exec_ctl_clr=ZERO;`
148			`pc_prectl =PC_KEP;`
149			`iack = riack;`
150			NextState_Sreg0 <= `D2_MUL_DLY;
151			`next_delay_counter_Sreg0 <= 34 - 1;`
152			`zz_is_nop =0;`
153			`end`
154			`CUR:
155			`begin`
156			`id2ra_ins_clr=ZERO;`
157			`id2ra_ins_cls=ONE;`
158			`id2ra_ctl_clr=ZERO;`
159			`id2ra_ctl_cls=ONE;`
160			`ra2exec_ctl_clr=ONE;`
161			`pc_prectl =PC_KEP;`
162			`iack = riack;`
163			NextState_Sreg0 <= `NOI;
164			`zz_is_nop = 1;`
165			`end`
166			`RET:
167			`begin`
168			`id2ra_ins_clr=ZERO;`
169			`id2ra_ins_cls=ZERO;`
170			`id2ra_ctl_clr=ZERO;`
171			`id2ra_ctl_cls=ZERO;`
172			`ra2exec_ctl_clr =ZERO;`
173			`pc_prectl =PC_IGN;`
174			`iack =ZERO;`
175			`riack =ZERO;`
176			NextState_Sreg0 <= `IDLE;
177			`zz_is_nop = ZERO;`
178			`end`
179			`IRQ:
180			`begin`
181			`id2ra_ins_clr=ONE;`
182			`id2ra_ins_cls=ZERO;`
183			`id2ra_ctl_clr=ONE;`
184			`id2ra_ctl_cls=ZERO;`
185			`ra2exec_ctl_clr=ONE;`
186			`pc_prectl =PC_IRQ;`
187			`iack =ONE;`
188			`riack=ONE;`
189			NextState_Sreg0 <= `IDLE;
190			`zz_is_nop = ZERO;`
191			`end`
192			`RST:
193			`begin`
194			`id2ra_ins_clr=ONE;`
195			`id2ra_ins_cls=ZERO;`
196			`id2ra_ctl_clr=ONE;`
197			`id2ra_ctl_cls=ZERO;`
198			`ra2exec_ctl_clr=ONE;`
199			`pc_prectl=PC_RST;`
200			`iack=ZERO;`
201			`riack=ZERO;`
202			NextState_Sreg0 <= `IDLE;
203			`zz_is_nop = ONE;`
204			`end`
205			`LD:
206			`begin`
207			`id2ra_ins_clr=ONE;`
208			`id2ra_ins_cls=ZERO;`
209			`id2ra_ctl_clr=ONE;`
210			`id2ra_ctl_cls=ZERO;`
211			`ra2exec_ctl_clr=ZERO;`
212			`pc_prectl =PC_KEP;`
213			`iack=riack;`
214			NextState_Sreg0 <= `IDLE;
215			`zz_is_nop = ZERO;`
216			`end`
217			`NOI:
218			`begin`
219			`id2ra_ins_clr=ZERO;`
220			`id2ra_ins_cls=ZERO;`
221			`id2ra_ctl_clr=ZERO;`
222			`id2ra_ctl_cls=ZERO;`
223			`ra2exec_ctl_clr =ZERO;`
224			`iack=riack;`
225			`pc_prectl=PC_IGN;`
226			NextState_Sreg0 <= `IDLE;
227			`zz_is_nop = ZERO;`
228			`end`
229			`D2_MUL_DLY:
230			`begin`
231			`id2ra_ins_clr=ONE;`
232			`id2ra_ins_cls=ZERO;`
233			`id2ra_ctl_clr=ONE;`
234			`id2ra_ctl_cls=ZERO;`
235			`ra2exec_ctl_clr=ZERO;`
236			`pc_prectl =PC_KEP;`
237			`iack=riack;`
238			`zz_is_nop = ONE;`
239			`if (delay_counter_Sreg0 == 0)`
240			NextState_Sreg0 <= `IDLE;
241			`else`
242			`begin`
243			NextState_Sreg0 <= `D2_MUL_DLY;
244			`if (delay_counter_Sreg0 != 0) next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;`
245			`end`
246			`end`
247			`default :`
248			`begin`
249			`id2ra_ins_clr=ONE;`
250			`id2ra_ins_cls=ZERO;`
251			`id2ra_ctl_clr=ONE;`
252			`id2ra_ctl_cls=ZERO;`
253			`ra2exec_ctl_clr=ONE;`
254			`pc_prectl=PC_RST;`
255			`iack=ZERO;`
256			`riack=ZERO;`
257			`zz_is_nop = ONE;`
258			NextState_Sreg0 <= `IDLE;
259			`end`
260			`endcase`
261			`end`
262
263			`always @ (posedge clk or negedge rst)`
264			`begin : Sreg0_CurrentState`
265			`if (~rst)`
266			CurrState_Sreg0 <= `RST;
267			`else`
268			`CurrState_Sreg0 <= NextState_Sreg0;`
269			`end`
270
271			`always @ (posedge clk or negedge rst)`
272			`begin : Sreg0_RegOutput`
273			`if (~rst)`
274			`begin`
275			`delay_counter_Sreg0 <= 0 ; // Initialization in the reset state or default value required!!`
276			`end`
277			`else`
278			`begin`
279			`delay_counter_Sreg0 <= next_delay_counter_Sreg0;`
280			`end`
281			`end`
282
283			`endmodule`
284
285
286			`/*`
287			`how to modify this module`
288			`1,add riack`
289			2,change the `RST action as default
290			3,set `IRQ has highest pority.
291			`*/`