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/////////////////////////////////////////////////////////////////////
////  Author: Liwei                                              ////
////                                                             ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Liwei                               ////
////                         mcupro@yahoo.com.hk                 ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2007.8.1                                  ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description:                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
module mips_core1 (
clk,irq_i,rst,cop_dout,irq_addr,
zz_din,zz_ins_i,iack_o,cop_addr_o,
cop_data_o,cop_mem_ctl_o,zz_addr_o,
zz_dout,zz_pc_o,zz_wr_en_o
);
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst;
wire rst;
input [31:0] cop_dout;
wire [31:0] cop_dout;
input [31:0] irq_addr;
wire [31:0] irq_addr;
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output iack_o;
wire iack_o;
output [31:0] cop_addr_o;
wire [31:0] cop_addr_o;
output [31:0] cop_data_o;
wire [31:0] cop_data_o;
output [3:0] cop_mem_ctl_o;
wire [3:0] cop_mem_ctl_o;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
 
wire NET1375;
wire NET1572;
wire NET1606;
wire NET1640;
wire NET21531;
wire NET457;
wire NET767;
wire [2:0] BUS109;
wire [2:0] BUS1158;
wire [2:0] BUS117;
wire [2:0] BUS1196;
wire [31:0] BUS15471;
wire [4:0] BUS1724;
wire [4:0] BUS1726;
wire [4:0] BUS18211;
wire [2:0] BUS197;
wire [2:0] BUS2140;
wire [2:0] BUS2156;
wire [31:0] BUS22401;
wire [31:0] BUS24839;
wire [31:0] BUS27031;
wire [2:0] BUS271;
wire [31:0] BUS28013;
wire [1:0] BUS371;
wire [31:0] BUS422;
wire [1:0] BUS5832;
wire [1:0] BUS5840;
wire [3:0] BUS5985;
wire [2:0] BUS5993;
wire [4:0] BUS6275;
wire [31:0] BUS7101;
wire [31:0] BUS7117;
wire [31:0] BUS7160;
wire [31:0] BUS7219;
wire [31:0] BUS7231;
wire [4:0] BUS748;
wire [4:0] BUS756;
wire [4:0] BUS775;
wire [31:0] BUS7772;
wire [31:0] BUS7780;
wire [31:0] BUS9589;
wire [31:0] BUS9884;
 
 
mem_module1 MEM_CTL
(
        .Zz_addr(zz_addr_o),
        .Zz_dout(zz_dout),
        .Zz_wr_en(zz_wr_en_o),
        .clk(clk),
        .din(BUS9884),
        .dmem_addr_i(BUS9589),
        .dmem_ctl(BUS5985),
        .dout(BUS22401),
        .zZ_din(zz_din)
);
 
assign NET21531 = NET1572 | iack_o;
 
rf_stage8 U2
(
        .clk(clk),
        .cmp_ctl_i(BUS109),
        .ext_ctl_i(BUS117),
        .ext_o(BUS7219),
        .fw_alu_i(cop_addr_o),
        .fw_cmp_rs(BUS2140),
        .fw_cmp_rt(BUS2156),
        .fw_mem_i(BUS15471),
        .iack_o(iack_o),
        .id2ra_ctl_clr_o(NET1606),
        .id2ra_ctl_cls_o(NET1572),
        .id_cmd(BUS197),
        .ins_i(zz_ins_i),
        .irq_addr_i(irq_addr),
        .irq_i(irq_i),
        .pc_gen_ctl(BUS271),
        .pc_i(BUS27031),
        .pc_next(zz_pc_o),
        .ra2ex_ctl_clr_o(NET1640),
        .rd_index_o(BUS775),
        .rd_sel_i(BUS371),
        .rs_n_o(BUS748),
        .rs_o(BUS24839),
        .rst_i(rst),
        .rt_n_o(BUS756),
        .rt_o(BUS7160),
        .wb_addr_i(BUS18211),
        .wb_din_i(BUS15471),
        .wb_we_i(NET1375),
        .zz_spc_i(BUS28013)
);
 
 
 
exec_stage1 U3
(
        .alu_func(BUS6275),
        .alu_ur_o(BUS9589),
        .clk(clk),
        .dmem_data_ur_o(BUS9884),
        .dmem_fw_ctl(BUS5993),
        .ext_i(BUS7231),
        .fw_alu(cop_addr_o),
        .fw_dmem(BUS15471),
        .muxa_ctl_i(BUS5832),
        .muxa_fw_ctl(BUS1158),
        .muxb_ctl_i(BUS5840),
        .muxb_fw_ctl(BUS1196),
        .pc_i(BUS27031),
        .rs_i(BUS7101),
        .rst(rst),
        .rt_i(BUS7117),
        .spc_cls_i(NET21531),
        .zz_spc_o(BUS28013)
);
 
 
 
r32_reg alu_pass0
(
        .clk(clk),
        .r32_i(BUS9589),
        .r32_o(cop_addr_o)
);
 
 
 
r32_reg alu_pass1
(
        .clk(clk),
        .r32_i(cop_addr_o),
        .r32_o(BUS422)
);
 
 
 
or32 cop_data_or
(
        .a(cop_dout),
        .b(BUS7772),
        .c(BUS7780)
);
 
 
 
r32_reg cop_data_reg
(
        .clk(clk),
        .r32_i(BUS9884),
        .r32_o(cop_data_o)
);
 
 
 
r32_reg cop_dout_reg
(
        .clk(clk),
        .r32_i(BUS22401),
        .r32_o(BUS7772)
);
 
 
 
decode_pipe3 decoder_pipe
(
        .alu_func_o(BUS6275),
        .alu_we_o(NET767),
        .clk(clk),
        .cmp_ctl_o(BUS109),
        .dmem_ctl_o(cop_mem_ctl_o),
        .dmem_ctl_ur_o(BUS5985),
        .ext_ctl_o(BUS117),
        .fsm_dly(BUS197),
        .id2ra_ctl_clr(NET1606),
        .id2ra_ctl_cls(NET1572),
        .ins_i(zz_ins_i),
        .muxa_ctl_o(BUS5832),
        .muxb_ctl_o(BUS5840),
        .pc_gen_ctl_o(BUS271),
        .ra2ex_ctl_clr(NET1640),
        .rd_sel_o(BUS371),
        .wb_mux_ctl_o(NET457),
        .wb_we_o(NET1375)
);
 
 
 
r32_reg ext_reg
(
        .clk(clk),
        .r32_i(BUS7219),
        .r32_o(BUS7231)
);
 
 
 
forward2 forward
(
        .alu_rs_fw(BUS1158),
        .alu_rt_fw(BUS1196),
        .alu_we(NET767),
        .clk(clk),
        .cmp_rs_fw(BUS2140),
        .cmp_rt_fw(BUS2156),
        .dmem_fw(BUS5993),
        .fw_alu_rn(BUS1724),
        .fw_mem_rn(BUS18211),
        .mem_We(NET1375),
        .rns_i(BUS748),
        .rnt_i(BUS756)
);
 
 
 
r32_reg pc
(
        .clk(clk),
        .r32_i(zz_pc_o),
        .r32_o(BUS27031)
);
 
 
 
r5_reg rnd_pass0
(
        .clk(clk),
        .r5_i(BUS775),
        .r5_o(BUS1726)
);
 
 
 
r5_reg rnd_pass1
(
        .clk(clk),
        .r5_i(BUS1726),
        .r5_o(BUS1724)
);
 
 
 
r5_reg rnd_pass2
(
        .clk(clk),
        .r5_i(BUS1724),
        .r5_o(BUS18211)
);
 
 
 
r32_reg rs_reg
(
        .clk(clk),
        .r32_i(BUS24839),
        .r32_o(BUS7101)
);
 
 
 
r32_reg rt_reg
(
        .clk(clk),
        .r32_i(BUS7160),
        .r32_o(BUS7117)
);
 
 
 
wb_mux wb_mux
(
        .alu_i(BUS422),
        .dmem_i(BUS7780),
        .sel(NET457),
        .wb_o(BUS15471)
);
 
endmodule

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Subversion Repositories mips789

[/] [mips789/] [branches/] [mcupro/] [verilog/] [mips_core/] [mips_core.v] - Blame information for rev 55

Line No.	Rev	Author	Line
1	2	mcupro	`/////////////////////////////////////////////////////////////////////`
2			`//// Author: Liwei ////`
3			`//// ////`
4			`//// ////`
5			`//// If you encountered any problem, please contact : ////`
6			`//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////`
7			`//// ////`
8			`//// Downloaded from: ////`
9			`//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2007 Liwei ////`
13			`//// mcupro@yahoo.com.hk ////`
14			`//// ////`
15			`//// ////`
16			`//// This source file may be used and distributed freely without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and any derivative work contains the ////`
19			`//// original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// Please let the author know if it is used ////`
22			`//// for commercial purpose. ////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`//// ////`
40			`//// ////`
41			`//// Date of Creation: 2007.8.1 ////`
42			`//// ////`
43			`//// Version: 0.0.1 ////`
44			`//// ////`
45			`//// Description: ////`
46			`//// ////`
47			`//// ////`
48			`/////////////////////////////////////////////////////////////////////`
49			`//// ////`
50			`//// Change log: ////`
51			`//// ////`
52			`/////////////////////////////////////////////////////////////////////`
53			`module mips_core1 (`
54			`clk,irq_i,rst,cop_dout,irq_addr,`
55			`zz_din,zz_ins_i,iack_o,cop_addr_o,`
56			`cop_data_o,cop_mem_ctl_o,zz_addr_o,`
57			`zz_dout,zz_pc_o,zz_wr_en_o`
58			`);`
59
60			`input clk;`
61			`wire clk;`
62			`input irq_i;`
63			`wire irq_i;`
64			`input rst;`
65			`wire rst;`
66			`input [31:0] cop_dout;`
67			`wire [31:0] cop_dout;`
68			`input [31:0] irq_addr;`
69			`wire [31:0] irq_addr;`
70			`input [31:0] zz_din;`
71			`wire [31:0] zz_din;`
72			`input [31:0] zz_ins_i;`
73			`wire [31:0] zz_ins_i;`
74			`output iack_o;`
75			`wire iack_o;`
76			`output [31:0] cop_addr_o;`
77			`wire [31:0] cop_addr_o;`
78			`output [31:0] cop_data_o;`
79			`wire [31:0] cop_data_o;`
80			`output [3:0] cop_mem_ctl_o;`
81			`wire [3:0] cop_mem_ctl_o;`
82			`output [31:0] zz_addr_o;`
83			`wire [31:0] zz_addr_o;`
84			`output [31:0] zz_dout;`
85			`wire [31:0] zz_dout;`
86			`output [31:0] zz_pc_o;`
87			`wire [31:0] zz_pc_o;`
88			`output [3:0] zz_wr_en_o;`
89			`wire [3:0] zz_wr_en_o;`
90
91			`wire NET1375;`
92			`wire NET1572;`
93			`wire NET1606;`
94			`wire NET1640;`
95			`wire NET21531;`
96			`wire NET457;`
97			`wire NET767;`
98			`wire [2:0] BUS109;`
99			`wire [2:0] BUS1158;`
100			`wire [2:0] BUS117;`
101			`wire [2:0] BUS1196;`
102			`wire [31:0] BUS15471;`
103			`wire [4:0] BUS1724;`
104			`wire [4:0] BUS1726;`
105			`wire [4:0] BUS18211;`
106			`wire [2:0] BUS197;`
107			`wire [2:0] BUS2140;`
108			`wire [2:0] BUS2156;`
109			`wire [31:0] BUS22401;`
110			`wire [31:0] BUS24839;`
111			`wire [31:0] BUS27031;`
112			`wire [2:0] BUS271;`
113			`wire [31:0] BUS28013;`
114			`wire [1:0] BUS371;`
115			`wire [31:0] BUS422;`
116			`wire [1:0] BUS5832;`
117			`wire [1:0] BUS5840;`
118			`wire [3:0] BUS5985;`
119			`wire [2:0] BUS5993;`
120			`wire [4:0] BUS6275;`
121			`wire [31:0] BUS7101;`
122			`wire [31:0] BUS7117;`
123			`wire [31:0] BUS7160;`
124			`wire [31:0] BUS7219;`
125			`wire [31:0] BUS7231;`
126			`wire [4:0] BUS748;`
127			`wire [4:0] BUS756;`
128			`wire [4:0] BUS775;`
129			`wire [31:0] BUS7772;`
130			`wire [31:0] BUS7780;`
131			`wire [31:0] BUS9589;`
132			`wire [31:0] BUS9884;`
133
134
135			`mem_module1 MEM_CTL`
136			`(`
137			`.Zz_addr(zz_addr_o),`
138			`.Zz_dout(zz_dout),`
139			`.Zz_wr_en(zz_wr_en_o),`
140			`.clk(clk),`
141			`.din(BUS9884),`
142			`.dmem_addr_i(BUS9589),`
143			`.dmem_ctl(BUS5985),`
144			`.dout(BUS22401),`
145			`.zZ_din(zz_din)`
146			`);`
147
148			`assign NET21531 = NET1572 \| iack_o;`
149
150			`rf_stage8 U2`
151			`(`
152			`.clk(clk),`
153			`.cmp_ctl_i(BUS109),`
154			`.ext_ctl_i(BUS117),`
155			`.ext_o(BUS7219),`
156			`.fw_alu_i(cop_addr_o),`
157			`.fw_cmp_rs(BUS2140),`
158			`.fw_cmp_rt(BUS2156),`
159			`.fw_mem_i(BUS15471),`
160			`.iack_o(iack_o),`
161			`.id2ra_ctl_clr_o(NET1606),`
162			`.id2ra_ctl_cls_o(NET1572),`
163			`.id_cmd(BUS197),`
164			`.ins_i(zz_ins_i),`
165			`.irq_addr_i(irq_addr),`
166			`.irq_i(irq_i),`
167			`.pc_gen_ctl(BUS271),`
168			`.pc_i(BUS27031),`
169			`.pc_next(zz_pc_o),`
170			`.ra2ex_ctl_clr_o(NET1640),`
171			`.rd_index_o(BUS775),`
172			`.rd_sel_i(BUS371),`
173			`.rs_n_o(BUS748),`
174			`.rs_o(BUS24839),`
175			`.rst_i(rst),`
176			`.rt_n_o(BUS756),`
177			`.rt_o(BUS7160),`
178			`.wb_addr_i(BUS18211),`
179			`.wb_din_i(BUS15471),`
180			`.wb_we_i(NET1375),`
181			`.zz_spc_i(BUS28013)`
182			`);`
183
184
185
186			`exec_stage1 U3`
187			`(`
188			`.alu_func(BUS6275),`
189			`.alu_ur_o(BUS9589),`
190			`.clk(clk),`
191			`.dmem_data_ur_o(BUS9884),`
192			`.dmem_fw_ctl(BUS5993),`
193			`.ext_i(BUS7231),`
194			`.fw_alu(cop_addr_o),`
195			`.fw_dmem(BUS15471),`
196			`.muxa_ctl_i(BUS5832),`
197			`.muxa_fw_ctl(BUS1158),`
198			`.muxb_ctl_i(BUS5840),`
199			`.muxb_fw_ctl(BUS1196),`
200			`.pc_i(BUS27031),`
201			`.rs_i(BUS7101),`
202			`.rst(rst),`
203			`.rt_i(BUS7117),`
204			`.spc_cls_i(NET21531),`
205			`.zz_spc_o(BUS28013)`
206			`);`
207
208
209
210			`r32_reg alu_pass0`
211			`(`
212			`.clk(clk),`
213			`.r32_i(BUS9589),`
214			`.r32_o(cop_addr_o)`
215			`);`
216
217
218
219			`r32_reg alu_pass1`
220			`(`
221			`.clk(clk),`
222			`.r32_i(cop_addr_o),`
223			`.r32_o(BUS422)`
224			`);`
225
226
227
228			`or32 cop_data_or`
229			`(`
230			`.a(cop_dout),`
231			`.b(BUS7772),`
232			`.c(BUS7780)`
233			`);`
234
235
236
237			`r32_reg cop_data_reg`
238			`(`
239			`.clk(clk),`
240			`.r32_i(BUS9884),`
241			`.r32_o(cop_data_o)`
242			`);`
243
244
245
246			`r32_reg cop_dout_reg`
247			`(`
248			`.clk(clk),`
249			`.r32_i(BUS22401),`
250			`.r32_o(BUS7772)`
251			`);`
252
253
254
255			`decode_pipe3 decoder_pipe`
256			`(`
257			`.alu_func_o(BUS6275),`
258			`.alu_we_o(NET767),`
259			`.clk(clk),`
260			`.cmp_ctl_o(BUS109),`
261			`.dmem_ctl_o(cop_mem_ctl_o),`
262			`.dmem_ctl_ur_o(BUS5985),`
263			`.ext_ctl_o(BUS117),`
264			`.fsm_dly(BUS197),`
265			`.id2ra_ctl_clr(NET1606),`
266			`.id2ra_ctl_cls(NET1572),`
267			`.ins_i(zz_ins_i),`
268			`.muxa_ctl_o(BUS5832),`
269			`.muxb_ctl_o(BUS5840),`
270			`.pc_gen_ctl_o(BUS271),`
271			`.ra2ex_ctl_clr(NET1640),`
272			`.rd_sel_o(BUS371),`
273			`.wb_mux_ctl_o(NET457),`
274			`.wb_we_o(NET1375)`
275			`);`
276
277
278
279			`r32_reg ext_reg`
280			`(`
281			`.clk(clk),`
282			`.r32_i(BUS7219),`
283			`.r32_o(BUS7231)`
284			`);`
285
286
287
288			`forward2 forward`
289			`(`
290			`.alu_rs_fw(BUS1158),`
291			`.alu_rt_fw(BUS1196),`
292			`.alu_we(NET767),`
293			`.clk(clk),`
294			`.cmp_rs_fw(BUS2140),`
295			`.cmp_rt_fw(BUS2156),`
296			`.dmem_fw(BUS5993),`
297			`.fw_alu_rn(BUS1724),`
298			`.fw_mem_rn(BUS18211),`
299			`.mem_We(NET1375),`
300			`.rns_i(BUS748),`
301			`.rnt_i(BUS756)`
302			`);`
303
304
305
306			`r32_reg pc`
307			`(`
308			`.clk(clk),`
309			`.r32_i(zz_pc_o),`
310			`.r32_o(BUS27031)`
311			`);`
312
313
314
315			`r5_reg rnd_pass0`
316			`(`
317			`.clk(clk),`
318			`.r5_i(BUS775),`
319			`.r5_o(BUS1726)`
320			`);`
321
322
323
324			`r5_reg rnd_pass1`
325			`(`
326			`.clk(clk),`
327			`.r5_i(BUS1726),`
328			`.r5_o(BUS1724)`
329			`);`
330
331
332
333			`r5_reg rnd_pass2`
334			`(`
335			`.clk(clk),`
336			`.r5_i(BUS1724),`
337			`.r5_o(BUS18211)`
338			`);`
339
340
341
342			`r32_reg rs_reg`
343			`(`
344			`.clk(clk),`
345			`.r32_i(BUS24839),`
346			`.r32_o(BUS7101)`
347			`);`
348
349
350
351			`r32_reg rt_reg`
352			`(`
353			`.clk(clk),`
354			`.r32_i(BUS7160),`
355			`.r32_o(BUS7117)`
356			`);`
357
358
359
360			`wb_mux wb_mux`
361			`(`
362			`.alu_i(BUS422),`
363			`.dmem_i(BUS7780),`
364			`.sel(NET457),`
365			`.wb_o(BUS15471)`
366			`);`
367
368			`endmodule`