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/////////////////////////////////////////////////////////////////////
////  Author: Liwei                                              ////
////                                                             ////
////                                                             ////
////  If you encountered any problem, please contact :           ////
////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Liwei                               ////
////                         mcupro@yahoo.com.hk                 ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// Please let the author know if it is used                    ////
//// for commercial purpose.                                     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Date of Creation: 2007.8.1                                  ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
//// Description:                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
`define   PC_IGN              1
`define   PC_KEP              2
`define   PC_IRQ              4
`define   PC_RST              8
 
`define PC_J     1
`define PC_JR    2
`define PC_BC    4
`define PC_NEXT  5
`define PC_SPC   6
`define PC_RET   6
`define PC_NOP   0
 
module pc_gen2 (
        input [2:0]ctl,
        output reg   [31:0]pc_next,
        input [3:0] pc_prectl,
        input check,
        input [31:0]s,
        input [31:0]pc,
        input [31:0]zz_spc,
        input [31:0]imm,
        input [31:0]irq
    );
 
    wire [32:0] br_addr = pc + imm ;
 
    always @ (*)
        if(pc_prectl == `PC_IGN )
        begin
            case (ctl)
                `PC_RET :                 pc_next = zz_spc ;
                `PC_J:pc_next ={pc[31:28],imm[27:0]};
                `PC_JR: pc_next = s;
                `PC_BC: pc_next = (check)?({br_addr[31:0]}):(pc+4);
                `PC_NEXT:pc_next = pc+ 4 ;
                default pc_next = pc + 4;
            endcase
        end
        else
        begin
            case (pc_prectl)
                `PC_KEP : pc_next=pc;
                `PC_IRQ : pc_next=irq;
                `PC_RST : pc_next='d0;
                default:pc_next =0;
            endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	mcupro	`/////////////////////////////////////////////////////////////////////`
2			`//// Author: Liwei ////`
3			`//// ////`
4			`//// ////`
5			`//// If you encountered any problem, please contact : ////`
6			`//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////`
7			`//// ////`
8			`//// Downloaded from: ////`
9			`//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2007 Liwei ////`
13			`//// mcupro@yahoo.com.hk ////`
14			`//// ////`
15			`//// ////`
16			`//// This source file may be used and distributed freely without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and any derivative work contains the ////`
19			`//// original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// Please let the author know if it is used ////`
22			`//// for commercial purpose. ////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`//// ////`
40			`//// ////`
41			`//// Date of Creation: 2007.8.1 ////`
42			`//// ////`
43			`//// Version: 0.0.1 ////`
44			`//// ////`
45			`//// Description: ////`
46			`//// ////`
47			`//// ////`
48			`/////////////////////////////////////////////////////////////////////`
49			`//// ////`
50			`//// Change log: ////`
51			`//// ////`
52			`/////////////////////////////////////////////////////////////////////`
53			`define PC_IGN 1
54			`define PC_KEP 2
55			`define PC_IRQ 4
56			`define PC_RST 8
57
58			`define PC_J 1
59			`define PC_JR 2
60			`define PC_BC 4
61			`define PC_NEXT 5
62			`define PC_SPC 6
63			`define PC_RET 6
64			`define PC_NOP 0
65
66			`module pc_gen2 (`
67			`input [2:0]ctl,`
68			`output reg [31:0]pc_next,`
69			`input [3:0] pc_prectl,`
70			`input check,`
71			`input [31:0]s,`
72			`input [31:0]pc,`
73			`input [31:0]zz_spc,`
74			`input [31:0]imm,`
75			`input [31:0]irq`
76			`);`
77
78			`wire [32:0] br_addr = pc + imm ;`
79
80			`always @ (*)`
81			if(pc_prectl == `PC_IGN )
82			`begin`
83			`case (ctl)`
84			`PC_RET : pc_next = zz_spc ;
85			`PC_J:pc_next ={pc[31:28],imm[27:0]};
86			`PC_JR: pc_next = s;
87			`PC_BC: pc_next = (check)?({br_addr[31:0]}):(pc+4);
88			`PC_NEXT:pc_next = pc+ 4 ;
89			`default pc_next = pc + 4;`
90			`endcase`
91			`end`
92			`else`
93			`begin`
94			`case (pc_prectl)`
95			`PC_KEP : pc_next=pc;
96			`PC_IRQ : pc_next=irq;
97			`PC_RST : pc_next='d0;
98			`default:pc_next =0;`
99			`endcase`
100			`end`
101
102			`endmodule`

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[/] [mips789/] [branches/] [mcupro/] [verilog/] [mips_core/] [pc_gen.v] - Blame information for rev 51