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[/] [mips789/] [branches/] [mcupro/] [verilog/] [mips_core/] [pc_gen.v] - Blame information for rev 55

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1 2 mcupro
/////////////////////////////////////////////////////////////////////
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////  Author: Liwei                                              ////
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////                                                             ////
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////                                                             ////
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////  If you encountered any problem, please contact :           ////
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////  Email: mcupro@yahoo.com.hk or mcupro@opencores.org         ////
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////                                                             ////
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////  Downloaded from:                                           ////
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////     http://www.opencores.org/pdownloads.cgi/list/mips789    ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2006-2007 Liwei                               ////
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////                         mcupro@yahoo.com.hk                 ////
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////                                                             ////
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////                                                             ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and any derivative work contains the  ////
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//// original copyright notice and the associated disclaimer.    ////
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////                                                             ////
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//// Please let the author know if it is used                    ////
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//// for commercial purpose.                                     ////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////                                                             ////
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//// Date of Creation: 2007.8.1                                  ////
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////                                                             ////
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//// Version: 0.0.1                                              ////
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////                                                             ////
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//// Description:                                                ////
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////                                                             ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Change log:                                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`define   PC_IGN              1
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`define   PC_KEP              2
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`define   PC_IRQ              4
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`define   PC_RST              8
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`define PC_J     1
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`define PC_JR    2
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`define PC_BC    4
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`define PC_NEXT  5
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`define PC_SPC   6
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`define PC_RET   6
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`define PC_NOP   0
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module pc_gen2 (
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        input [2:0]ctl,
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        output reg   [31:0]pc_next,
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        input [3:0] pc_prectl,
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        input check,
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        input [31:0]s,
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        input [31:0]pc,
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        input [31:0]zz_spc,
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        input [31:0]imm,
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        input [31:0]irq
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    );
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    wire [32:0] br_addr = pc + imm ;
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    always @ (*)
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        if(pc_prectl == `PC_IGN )
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        begin
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            case (ctl)
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                `PC_RET :                 pc_next = zz_spc ;
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                `PC_J:pc_next ={pc[31:28],imm[27:0]};
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                `PC_JR: pc_next = s;
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                `PC_BC: pc_next = (check)?({br_addr[31:0]}):(pc+4);
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                `PC_NEXT:pc_next = pc+ 4 ;
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                default pc_next = pc + 4;
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            endcase
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        end
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        else
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        begin
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            case (pc_prectl)
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                `PC_KEP : pc_next=pc;
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                `PC_IRQ : pc_next=irq;
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                `PC_RST : pc_next='d0;
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                default:pc_next =0;
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            endcase
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        end
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endmodule

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