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mcupro |
//This file is based YACC ->shifter.v
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/////////////////////////////////////////////////////////////////////
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//// Author: Liwei ////
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//// ////
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//// ////
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//// If you encountered any problem, please contact : ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// ////
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//// Downloaded from: ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// mcupro@yahoo.com.hk ////
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//// ////
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//// ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and any derivative work contains the ////
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//// original copyright notice and the associated disclaimer. ////
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//// ////
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//// Please let the author know if it is used ////
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//// for commercial purpose. ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Date of Creation: 2007.8.1 ////
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//// ////
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//// Version: 0.0.1 ////
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//// ////
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//// Description: ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Change log: ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`define ALU_SRL 1
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`define ALU_SLL 2
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`define ALU_SRA 4
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module
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shifter(
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input [31:0] a,
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output reg [31:0] shift_out,
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input [4:0] shift_func,//connect to alu_func_ctl
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input [31:0] shift_amount//connect to b
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);
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always @ (*)
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begin
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if( shift_func == `ALU_SLL )
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begin
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case ( shift_amount[4:0] )
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5'b00000: shift_out=a;
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5'b00001: shift_out={a[30:0],1'b0};
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5'b00010: shift_out={a[29:0],2'b0};
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5'b00011: shift_out={a[28:0],3'b0};
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5'b00100: shift_out={a[27:0],4'b0};
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5'b00101: shift_out={a[26:0],5'b0};
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5'b00110: shift_out={a[25:0],6'b0};
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5'b00111: shift_out={a[24:0],7'b0};
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5'b01000: shift_out={a[23:0],8'b0};
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5'b01001: shift_out={a[22:0],9'b0};
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5'b01010: shift_out={a[21:0],10'b0};
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5'b01011: shift_out={a[20:0],11'b0};
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5'b01100: shift_out={a[19:0],12'b0};
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5'b01101: shift_out={a[18:0],13'b0};
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5'b01110: shift_out={a[17:0],14'b0};
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5'b01111: shift_out={a[16:0],15'b0};
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5'b10000: shift_out={a[15:0],16'b0};
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5'b10001: shift_out={a[14:0],17'b0};
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5'b10010: shift_out={a[13:0],18'b0};
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5'b10011: shift_out={a[12:0],19'b0};
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5'b10100: shift_out={a[11:0],20'b0};
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5'b10101: shift_out={a[10:0],21'b0};
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5'b10110: shift_out={a[9:0],22'b0};
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5'b10111: shift_out={a[8:0],23'b0};
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5'b11000: shift_out={a[7:0],24'b0};
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5'b11001: shift_out={a[6:0],25'b0};
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5'b11010: shift_out={a[5:0],26'b0};
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5'b11011: shift_out={a[4:0],27'b0};
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5'b11100: shift_out={a[3:0],28'b0};
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5'b11101: shift_out={a[2:0],29'b0};
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5'b11110: shift_out={a[1:0],30'b0};
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5'b11111: shift_out={a[0],31'b0};
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default shift_out ='d0;
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endcase
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end else if (shift_func== `ALU_SRL) begin
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case (shift_amount[4:0])
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5'b00000: shift_out=a;
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5'b00001: shift_out={1'b0,a[31:1]};
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5'b00010: shift_out={2'b0,a[31:2]};
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5'b00011: shift_out={3'b0,a[31:3]};
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5'b00100: shift_out={4'b0,a[31:4]};
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5'b00101: shift_out={5'b0,a[31:5]};
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5'b00110: shift_out={6'b0,a[31:6]};
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5'b00111: shift_out={7'b0,a[31:7]};
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5'b01000: shift_out={8'b0,a[31:8]};
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5'b01001: shift_out={9'b0,a[31:9]};
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5'b01010: shift_out={10'b0,a[31:10]};
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5'b01011: shift_out={11'b0,a[31:11]};
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5'b01100: shift_out={12'b0,a[31:12]};
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5'b01101: shift_out={13'b0,a[31:13]};
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5'b01110: shift_out={14'b0,a[31:14]};
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5'b01111: shift_out={15'b0,a[31:15]};
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5'b10000: shift_out={16'b0,a[31:16]};
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5'b10001: shift_out={17'b0,a[31:17]};
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5'b10010: shift_out={18'b0,a[31:18]};
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5'b10011: shift_out={19'b0,a[31:19]};
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5'b10100: shift_out={20'b0,a[31:20]};
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5'b10101: shift_out={21'b0,a[31:21]};
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5'b10110: shift_out={22'b0,a[31:22]};
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5'b10111: shift_out={23'b0,a[31:23]};
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5'b11000: shift_out={24'b0,a[31:24]};
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5'b11001: shift_out={25'b0,a[31:25]};
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5'b11010: shift_out={26'b0,a[31:26]};
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5'b11011: shift_out={27'b0,a[31:27]};
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5'b11100: shift_out={28'b0,a[31:28]};
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5'b11101: shift_out={29'b0,a[31:29]};
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5'b11110: shift_out={30'b0,a[31:30]};
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5'b11111: shift_out={31'b0,a[31:31]};
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default : shift_out = 0;
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endcase
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end else
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if (shift_func==`ALU_SRA)
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begin// SHIFT_RIGHT_SIGNED
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case ( shift_amount[4:0])
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5'b00000: shift_out=a;
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5'b00001: shift_out={a[31],a[31:1]};
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5'b00010: shift_out={{2{a[31]}},a[31:2]};
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5'b00011: shift_out={{3{a[31]}},a[31:3]};
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5'b00100: shift_out={{4{a[31]}},a[31:4]};
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5'b00101: shift_out={{5{a[31]}},a[31:5]};
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5'b00110: shift_out={{6{a[31]}},a[31:6]};
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5'b00111: shift_out={{7{a[31]}},a[31:7]};
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5'b01000: shift_out={{8{a[31]}},a[31:8]};
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5'b01001: shift_out={{9{a[31]}},a[31:9]};
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5'b01010: shift_out={{10{a[31]}},a[31:10]};
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5'b01011: shift_out={{11{a[31]}},a[31:11]};
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5'b01100: shift_out={{12{a[31]}},a[31:12]};
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5'b01101: shift_out={{13{a[31]}},a[31:13]};
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5'b01110: shift_out={{14{a[31]}},a[31:14]};
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5'b01111: shift_out={{15{a[31]}},a[31:15]};
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5'b10000: shift_out={{16{a[31]}},a[31:16]};
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5'b10001: shift_out={{17{a[31]}},a[31:17]};
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5'b10010: shift_out={{18{a[31]}},a[31:18]};
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5'b10011: shift_out={{19{a[31]}},a[31:19]};
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5'b10100: shift_out={{20{a[31]}},a[31:20]};
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5'b10101: shift_out={{21{a[31]}},a[31:21]};
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5'b10110: shift_out={{22{a[31]}},a[31:22]};
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5'b10111: shift_out={{23{a[31]}},a[31:23]};
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5'b11000: shift_out={{24{a[31]}},a[31:24]};
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5'b11001: shift_out={{25{a[31]}},a[31:25]};
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5'b11010: shift_out={{26{a[31]}},a[31:26]};
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5'b11011: shift_out={{27{a[31]}},a[31:27]};
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5'b11100: shift_out={{28{a[31]}},a[31:28]};
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5'b11101: shift_out={{29{a[31]}},a[31:29]};
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5'b11110: shift_out={{30{a[31]}},a[31:30]};
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5'b11111: shift_out={{31{a[31]}},a[31:31]};
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default shift_out='d0;
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endcase
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end
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else shift_out='d0;
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end
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endmodule
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